Digital Testing with Multi-Valued Logic Signals

Abstract

The integrated circuit scaling has been following the Moore’s Law since 1965 [59, 60, 61]. Within these decades, researchers made great effort to shrink the transistor feature size and maximize the integration level. Together with the growing level of integration, the burden of testing continues to becoming heavier: the number of bits in each test pattern is larger because of increasing number of flip-flops and primary inputs; and larger number of test patterns is required to guarantee fault coverage in a large design. Both factors result in enormous test data volume. Although it is not a problem to generate a big test set by using automatic test pattern generation (ATPG) tools, it puts a higher demand on automatic test equipment (ATE) and prolongs test time, which increase testing cost rapidly. Nowadays, the testing related cost has taken about half of the total manufacturing cost. The industry urges to find a solution.

Built-in self-test (BIST) technology is investigated. It’s frequently adopted in some particular cases like memory test to reduce or remove ATE cost. However, for more general testing purpose, BIST technology cannot guarantee fault coverage because of drawbacks like the pseudo-randomness of BIST patterns, which is hard to detect random-resistant faults and these faults aren’t rare in large designs. An alternative thinking is to reduce test data volume but maintain the test information for same fault coverage. Fortunately most bits in test are don’t-cares, which makes it possible to achieve high test compression level while retaining the fault coverage. Till now, test compression technologies have been successfully utilized in industry, compressing test size by up to 100x. Currently, the test compression interface exists in most large scale designs.

Improved test planning may utilize ATE and design-for-testability (DFT) re- sources wisely to reduce testing cost. Some useful metjods are concurrent test, multi-site test, hierarchical test and reduced-pin-count test (RPCT). These techniques can shorten test time or increase test throughput. Many solutions work together to limit the test cost within a reasonable level. For example, more and more test compression tools start to support low pin count test mode, which is equivalent to RPCT. On the other hand, RPCT technology enables more chips to be tested in parallel using multi-site test.

In current RPCT implementations, the test speed has to be the test channel data rate divided by the width of deserializer interface. The width of deserializer interface can be large in large system on chip (SoC) devices that support test compression. It turns out that the test speed needs to be very slow to match the deserializer interface with the limited test channel data rate. Traditionally, ATE test channel sends and receives binary data, in which case the data rate equals to the clock frequency. In this thesis, a revolutionary approach is introduced to improve ATE test channel efficiency so that test speed can be greatly increased especially for RPCT designs. My approach is to replace the media of test channel into multi-valued logic (MVL) signal. Here I choose digital to analog converter (DAC) as the MVL generator in the ATE test channel, and analog to digital converter (ADC) as the MVL decoder in the device under test (DUT). For MVL signal, multiple bits of information are contained within one symbol. So, an MVL link can send multiple bits of information in one clock cycle. As a result, it boosts the data rate of each physical test channel by several times. This property makes it suitable for the RPCT technology. The use of MVL interface can help resolve the problem of reduced test speed.

However, the use of MVL channel comes with additional sources of error over what we have in a binary system. For example, the insufficient accuracy of MVL generator and decoder, and larger vulnerability to noise. To tackle these, a new test flow including ADC nonlinearity calibration and error detection and correction are developed. A prototype MVL test setup based on NI ELVIS II and Altera DE2 [5] FPGA is implemented to show the practicality of the MVL data transmission and to prove the concept of MVL test application. Further, I succeeded in generating the MVL signal from the available resources in the ATE system and used it to test a DUT with integrated MVL and RPCT interfaces. The experimental result shows that the use of MVL test channel greatly improves the test speed.