INITIATION AND PROGRESSION OF DAMAGE IN LEADFREE ELECTRONICS UNDER DROP-IMPACT Except where reference is made to the work of others, the work described in this thesis is my own or was done in collaboration with my advisory committee. This thesis does not include proprietary or classified information. __________________________ Deepti Raju Iyengar Certificate of Approval: __________________________ __________________________ George T. Flowers Pradeep Lall, Chair Professor Thomas Walter Professor Mechanical Engineering Mechanical Engineering __________________________ __________________________ Barton C. Prorok Joe F. Pittman Assistant Professor Interim Dean Materials Engineering Graduate School INITIATION AND PROGRESSION OF DAMAGE IN LEAD-FREE ELECTRONICS UNDER DROP IMPACT Deepti Raju Iyengar A Thesis Submitted to the Graduate Faculty of Auburn University in Partial Fulfillment of the Requirement for the Degree of Master of Science Auburn, Alabama December 19, 2008 iii INITIATION AND PROGRESSION OF DAMAGE IN LEADFREE ELECTRONICS UNDER DROP-IMPACT Deepti Raju Iyengar Permission is granted to Auburn University to make copies of this thesis at its discretion, upon the request of individuals or institutions at their expense. The author reserves all publication rights. ___________________________ Signature of Author ___________________________ Date of Graduation iv VITA Deepti Raju Iyengar, daughter of Mr. S. Raju, Senior Deputy Director, the Automotive Research Association of India (ARAI) and Mrs. Lakshmi Raju Iyengar, Senior Auditor, Central Defense Accounts (Officers) (CDAO), was born on 12th September, 1982, in Pune, Maharashtra, India. Upon graduating from high school, she earned her Bachelor of Engineering (BE) degree in Mechanical Engineering from University of Pune, India in the year 2004. She worked for the University of Pune as an instructor, teaching Machine Design from January 2005 to June 2005. In the quest to augment her academic qualifications and technical experience, she moved to Auburn, Alabama in August 2005. Since her enrollment in the M.S. program at Auburn University, she has worked for the Semiconductor Research Corporation (SRC) as a Graduate Research Assistant in the area of impact reliability of electronic packaging. She has an elder brother Vijay who received his Bachelor of Engineering degree in Electronics and Telecommunication from University of Pune. He is the co-founder and CEO of Embedded Computing Machines (ECM). v THESIS ABSTRACT INITIATION AND PROGRESSION OF DAMAGE IN LEADFREE ELECTRONICS UNDER DROP-IMPACT Deepti Raju Iyengar Master of Science, December 19, 2008 (B.E., Pune University, 2004) 131 Typed Pages Directed by Pradeep Lall Electronics may be subjected to shock, vibration, and drop impact during shipping, handling, and normal usage. Measurement of transient dynamic deformation of the electronic assemblies during shock and vibration can yield significant insight in understanding the occurrence of failure modes and the development of failure envelopes. In this work, the transient dynamics of board assemblies in the form of relative displacement, drop angle, velocity, and acceleration were measured with high-speed imaging. In addition, high-speed data acquisition systems with discrete strain gages were used for measurements of transient strain at fixed locations. A new technique called digital image correlation (DIC) using ultra high-speed cameras for full-field measurement of transient strain was investigated. Various board assemblies subjected to shock at different drop orientations were examined. Accuracy of the high-speed optical vi measurements was compared with that from discrete strain gages. Explicit finite-element models were developed and correlated with experimental data. There is a fundamental need for the development of predictive techniques for electronic failure mechanisms in shock and drop-impact. Presently, one of the primary methodologies for assessment of shock and vibration survivability of electronic packaging is the JEDEC drop test method, JESD22-B111 [JEDEC 2003] which tests board-level reliability of packaging. However, packages in electronic products may be subjected to a wide array of boundary conditions beyond those targeted in the test method. Development of damage-equivalency methodologies will be invaluable in correlating standard test conditions to widely varying design-use conditions. In this work, the development of solder-joint stress based relative damage index was investigated to establish a method for damage equivalency. In practical applications, electronics are subjected not only to drop and shock but to a combination of loads. Thus, effect of overlapping stresses on the deformation behavior of solder interconnects was investigated. The effect of different package architectures and various surface finishes including ImAg, ImSn and ENIG on impact reliability was studied. Life prediction of new lead-free alloy-systems under shock and vibration is largely unexplored. An approach to model drop and shock survivability of electronic packaging is presented for six lead-free solder alloy systems including Sn1Ag0.5Cu, Sn3Ag0.5Cu, Sn0.3Ag0.7Cu, Sn0.3Ag0.7Cu-Bi, Sn0.3Ag0.7Cu-Bi-Ni, and 96.5Sn3.5Ag. The approach is scalable to a wide variety of electronic applications. vii ACKNOWLEDGEMENTS I would like to acknowledge my deep and sincere gratitude towards my advisor, Dr. Pradeep Lall, for his immense support, motivation, patience and continuous encouragement. I am thankful to him for his invaluable guidance and sound advice provided during the course of this study. His wide knowledge and logical school of thought have been of great value to me. I am deeply grateful to my committee members, Dr. George Flowers and Dr. Barton Prorok for their valuable suggestions and their time. I owe my most sincere gratitude and gratefulness to my parents for their enduring love and immense moral support. They have been a constant source of inspiration and motivation. My special gratitude is due to my brother, Vijay, for his encouragement and loving support. I would like to express my warm and sincere thanks to a very good friend, Shashank Khandekar, for his continuous motivation and encouragement. During this work I have collaborated with many colleagues for whom I have great regard, and I wish to extend my warmest thanks to all those who have helped me with my work. I, especially, wish to acknowledge Dhananjay Panchagade and Madhura Hande for their cooperation, interest and valuable suggestions. Finally, I would like to thank all my friends and colleagues for their support and encouragement at all times during my graduate studies. The financial support of the Semiconductor Research Corporation (SRC) is also gratefully acknowledged. viii Style manual or journal used: Guide to Preparation and Submission of Theses and Dissertations Computer software used: Microsoft Office 2003, Minitab 13.1, Ansys 10.0, Matlab 7.0.1, Microsoft Visual Studio 2005, National Instrument Image Analysis Software ix TABLE OF CONTENTS LIST OF FIGURES...........................................................................................................xii LIST OF TABLES..........................................................................................................xvii 1. INTRODUCTION.........................................................................................................1 1.1 Electronic Packaging...............................................................................................1 1.2 Categorization of Electronic Packaging..................................................................4 1.3 Reliability concerns.................................................................................................8 1.4 Shock and Drop Reliability.....................................................................................9 1.5 Digital Image Correlation......................................................................................10 1.6 Thesis Organization...............................................................................................10 2. LITERATURE REVIEW............................................................................................13 2.1 Board and Package Level Testing.........................................................................14 2.2 Finite Element Models..........................................................................................16 2.3 Alloy compositions and Surface Finish................................................................17 2.4 Failure Analysis.....................................................................................................20 2.5 Digital Image Correlation (DIC)...........................................................................21 3. HIGH SPEED DIGITAL IMAGE CORRELATION AND SIMULATION TECHNIQUES FOR TRANSIENT STRAIN MEASUREMENT IN ELECTRONICS SUBJECTED TO SHOCK AND DROP....................................................................24 3.1 Introduction...........................................................................................................24 3.2 Experimental Test Vehicle....................................................................................24 x 3.3 Detection of Damage Progression.........................................................................31 3.4 Digital Image Correlation (DIC)...........................................................................39 3.5 Experimental Set-up..............................................................................................43 3.6 Correlation of DIC Technique and Strain Gage Data...........................................48 3.7 Full-Field Transient Strains for Various Lead-free Alloys...................................54 3.8 Explicit Finite Element Models.............................................................................60 3.9 Simulation Model Validation................................................................................69 4. OPTICAL FEATURE EXTRACTION TECHNIQUES FOR SURVIVABILITY OF LEADFREE PACKAGING ARCHITECTURES UNDER SHOCK AND VIBRATION...............................................................................................................73 4.1 Introduction...........................................................................................................73 4.2 Transient Mode Shapes from DIC and Strain Gage..............................................74 4.3 Leading Indicators for Damage Initiation and Progression..................................74 4.4 Statistical Pattern Recognition Techniques...........................................................78 5. SURVIVABILITY ENVELOPE BASED ON RELATIVE DAMAGE INDEX FOR LEAD FREE ALLOY COMPOSITIONS..................................................................86 5.1 Introduction...........................................................................................................86 5.2 Reliability Analysis of Lead-Free Alloy Systems.................................................86 5.3 Damage Index based Survivability Envelope.......................................................93 6. SUMMARY AND CONCLUSION............................................................................98 BIBLIOGRAPHY...........................................................................................................100 APPENDIX.....................................................................................................................112 xi LIST OF FIGURES Figure 1.1: Moore's Law.....................................................................................................3 Figure 1.2: Electronic Packaging Hierarchy [MECH 6310 Course Notes]........................5 Figure 1.3: Evolution of Chip Carriers [MECH 6310 Course Notes].................................6 Figure 1.4: Different Types of Packaging Technology.......................................................7 Figure 3.1: Test Boards A, B, C and D.............................................................................25 Figure 3.2: Test Vehicle....................................................................................................29 Figure 3.3: Interconnect Array Configuration of the 10mm-100 I/O CABGA Package..30 Figure 3.4: Strain Repeatability for Test-Board A............................................................32 Figure 3.5: Repeatability Plot at Package Location 8 on test board F..............................32 Figure 3.6: Repeatability Plot at Package Location 9 on test board F..............................33 Figure 3.7: Location of Gages and Numbering Scheme of Packages on SAC305 Alloy Specimen Board on Test Board F...............................................................................33 Figure 3.8: Experimental Set-up for Controlled JEDEC Drop of Test Board B...............34 Figure 3.9: Board B Mounted with Targets for Relative Displacement Measurement.....35 Figure 3.10: Relative Displacement of Test Board B Subjected to JEDEC Drop............36 Figure 3.11: Package Strain and Continuity History in JEDEC drop-shock Orientation, for Test board B...........................................................................................................37 Figure 3.12: Strain and continuity history at Package 12 for SAC0307 alloy system on Test Board F................................................................................................................38 xii Figure 3.13: Strain and continuity history at Package 12 for SACX alloy system on Test Board F........................................................................................................................38 Figure 3.14: DIC Principle................................................................................................40 Figure 3.15: Speckle Pattern on Four of the Test Vehicles...............................................44 Figure 3.16: Speckle Pattern on the Populated Side of the Six Alloy System Test Vehicles .....................................................................................................................................44 Figure 3.17: Speckle Coated Image of Test Board with Strain Gages (A) Package Side (B) Board Side.............................................................................................................45 Figure 3.18: Experimental Set-up for DIC in both the Drop Orientations........................47 Figure 3.19: Calibration Images........................................................................................47 Figure 3.20: Strain Correlation of Test Board-C subjected to Vertical Drop at Location A1................................................................................................................................49 Figure 3.21: Strain Correlation Test Board-C subjected to Vertical Drop at Location A3... .....................................................................................................................................49 Figure 3.22: Strain Correlation Test Board-C subjected to Vertical Drop at Location A6 .....................................................................................................................................50 Figure 3.23: Correlation of Strain from DIC and Strain Gages for SAC305 Alloy System at Gage Location S2....................................................................................................50 Figure 3.24: Correlation of Strain from DIC and Strain Gages for SAC305 Alloy System at Gage Location S3....................................................................................................51 Figure 3.25: Correlation of Strain from DIC and Strain Gages for SAC305 Alloy System at Gage Location S4....................................................................................................51 Figure 3.26: 2D Strain Contours of Boards A, B, and C Dropped in Vertical Orientation.. xiii .....................................................................................................................................52 Figure 3.27: 3D Longitudinal Strain Contours from DIC for Test-Board C subjected to 90? Vertical Drop ........................................................................................................52 Figure 3.28: 3D longitudinal strain contours from DIC for Test-Board A subjected to 0? JEDEC Drop................................................................................................................53 Figure 3.29: Comparison of DIC Strain Contour with the Actual Contour......................53 Figure 3.30: 3D Strain Contours at Successive Drops during the Transient Drop Event.54 Figure 3.31: Peak PCB Strain Values as a Function of Package Location on the SACX Solder Alloy System on Board F.................................................................................56 Figure 3.32: Peak PCB Strain Values as a Function of Package Location on the SAC0307 Solder Alloy System on Board F.................................................................................56 Figure 3.33: Comparison of Strain for the Six Alloy Systems at Package 2 Location on Board F........................................................................................................................57 Figure 3.34: Comparison of Strain for the Six Alloy Systems at Package 14 Location on Board F........................................................................................................................57 Figure 3.35: Peak Strain Values at Packages 4 and 12 Location for the Various Alloy Systems on Board F.....................................................................................................58 Figure 3.36: Failure Plot for the SACX-Plus Alloy System on Board F..........................58 Figure 3.37: Correlation of Peak Strain with Drops-to-Failure for SAC305 alloy on Board F...................................................................................................................................59 Figure 3.38: Correlation of Peak Strain with Drops-to-Failure for Sn3.5Ag alloy on Board F...................................................................................................................................59 xiv Figure 3.39: Comparison of 2D Contour Plot at Package Location 12 at Same Time Instant for Different Alloy Systems on Board F.........................................................60 Figure 3.40: Explicit-Finite Element Model for Test Board B in JEDEC Configuration .....................................................................................................................................64 Figure 3.41: Smeared Property Model..............................................................................67 Figure 3.42: PCB Strain correlation of results from experiment, finite element and DIC Technique at location A1 on Test Board C, subjected to Vertical Drop.....................70 Figure 3.43: PCB Strain correlation of results from experiment, finite element and DIC Technique at location A3 on Test Board C subjected to Vertical Drop......................70 Figure 3.44: Package Strain Correlation between DIC and Finite Element Models at the Package 13 Location on SAC305; Test Board F during 0? JEDEC Drop..................71 Figure 3.45: Correlation of DIC and FEM Full Field 3D Strain Contours of Test Board C subjected to vertical drop............................................................................................71 Figure 3.46: Correlation of DIC and FEM Full Field 3D Strain Contour of Test Board D subjected to JEDEC Drop...........................................................................................72 Figure 4.1: 2D Strain Contours at Package Location 8 Before and After Failure for the SACX-Plus Alloy System on Test Board F................................................................75 Figure 4.2: 2D Strain Contours at Package Location 13 Before and After Failure for the SACX-Plus Alloy System on Test Board F................................................................75 Figure 4.3: Strain Before and After Failure at Package 12 Location for SAC105 Alloy System on Test Board F..............................................................................................76 Figure 4.4: Strain Before and After Failure at Package 12 Location for SAC0307 Alloy System on Test Board F..............................................................................................76 xv Figure 4.5: Peak Strain Values Before and After Failure at Package 12 Location for the SAC105 Alloy System on Test Board F.....................................................................77 Figure 4.6: Peak Strain Values Before and After Failure at Package 12 Location for the SAC0307 Alloy System on Test Board F...................................................................77 Figure 4.7: Confidence Value for 6 Successive Drops at Package 8 Location for SAC305 Alloy System...............................................................................................................83 Figure 4.8: Comparison of Histograms for Successive Drops at Packages 8 Location for SAC305 Alloy System................................................................................................83 Figure 4.9: Comparison of Histograms for Successive Drops at Packages 9 Location for SAC305 Alloy System................................................................................................84 Figure 4.10: Confidence Value Degradation in the Six Alloy Systems using Wavelet Packet Energy Decomposition Approach...................................................................84 Figure 4.11: Confidence Value Degradation in the Six Alloy Systems using Mahalanobis Approach.....................................................................................................................85 Figure 4.12: Confidence Value Degradation in the Six Alloy Systems using Fast Fourier Transform Approach...................................................................................................85 Figure 5.1: Weibull Distribution of 10mm-100 I/O Components for the Various Solder Alloy Systems on Test Board F...................................................................................88 Figure 5.2: Failure Modes.................................................................................................89 Figure 5.3: Failure Modes observed in SAC105 Solder Joints.........................................90 Figure 5.4: Failure Modes observed in SAC305 Solder Joints.........................................90 Figure 5.5: Failure Modes observed in SAC0307 Solder Joints.......................................91 Figure 5.6: Failure Modes observed in SACX Solder Joints............................................91 xvi Figure 5.7: Failure Modes observed in SACX-Plus Solder Joints....................................92 Figure 5.8: Failure Modes observed in SnAg Solder Joints..............................................92 Figure 5.9: Comparison of Failure Modes in the Six Different Alloy Systems................93 Figure 5.10: Damage Index Progression for SAC105 Alloy System................................97 Figure 5.11: Damage Index Progression for SAC305 Alloy System................................97 xvii LIST OF TABLES Table 3.1: Package Architecture of 6mm, 10mm and 14mm BGAs.................................26 Table 3.2: Package Architecture of 16mm and 17mm BGAs...........................................27 Table 3.3: Package Architecture of 32 I/O and 44 I/O MLF Packages............................27 Table 3.4: CABGA Package Details.................................................................................29 Table 3.5 : Lead Free Alloy Compositions.......................................................................30 Table 3.6: Material Property for Finite Element Simulation............................................66 Table 3.7: Material Property used in the Finite Element Simulation................................68 Table 3.8: Actual and Simulated Component Masses.......................................................78 Table 5.1: Failure Mode Description................................................................................89 1 CHAPTER 1 INTRODUCTION 1.1 Electronic Packaging Electronics is the biggest, most dynamic, and rapidly evolving worldwide industry. It is an industry working under the constant pressure to improve, thus reinventing itself endlessly. Electronic systems play an important role today. They are a part of every aspect of life including simple devices like watches to complex devices such as super computers. Electronics are present in every field and are invariably used by everyone. Electronic Packaging is a major discipline of electronics that includes a wide variety of technologies like materials, design, architecture, process and manufacture. Packaging of electronic system refers to the placement and connection of various electronic and electromechanical components, which are placed in an enclosure that protects the system from the environment. Electronic packaging is conventionally defined as a process that alters bare integrated circuits (IC) into useful products. It not only acts as a bridge between the micron IC world and the macroscopic world of peripheral devices, but also provides electrical signal connections, power supply, a path for heat dissipation and environmental protection. The co-founder of Intel, Gordon E. Moore observed and stated a very important trend in the history of computer hardware [Moore 1965]. According to Moore, the transistors 2 that can be inexpensively placed on an integrated circuit were increasing exponentially and were doubling approximately every two years. The trend has been maintained for more than 40 years as shown in Figure 1.1 and is expected to continue at least for a decade more. Almost all of the factors used to gauge the capability of digital electronic systems are associated with Moore's Law, all of which have progressed at exponential rates. This progression is one of the key factors that has increased the importance of electronics. Moore's Law was especially responsible for the dynamic technological advancements in electronic packaging in the past half century. 3 Figure 1.1: Moore's Law 4 1.2 Categorization of Electronic Packaging Electronic systems are classified into several levels of packaging with characteristic types of interconnects associated with them. As per the hierarchy shown in Figure 1.2, the silicon wafer is at the zero level. The first level includes chip carriers, underfilled flip chips, chip level interconnect, and passive devices such as resistors. The second level comprises of printed circuit boards (PCB), printed wired boards (PWB) or cards. The third level incorporates the mother board and connections between PCBs and PWBs and the forth level contains connections between two subassemblies. Connections between two physically separated systems such as a computer and a printer are referred to as the fifth or final level of packaging. The two technologies for printed circuit board assemblies are plated through hole (PTH) and surface mount technology (SMT). The former is out dated as surface mount technology is far more superior. Some of the advantages of the later include more pin count on the same area and lower costs. PTH packages include Dual In Line Package (DIP), Shrink DIP (SH-DIP), Skinny DIP (SK-DIP), Slim DIP (SL-DIP), Zig-zag In Line Package (ZIP) and Pin Grid Array (PGA). The surface mount packages include Small Out-line Package (SOP), Quad Flat Package (QFP), Leadless Chip Carrier (LCC), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), Tape Automated Bonding (TAB) and Chip Scale Package (CSP). The progression of chip carriers from chip on board to package on board is shown in Figure 1.3. Some of the different types of packaging technologies are shown in Figure 1.4. 5 Zero level Figure 1.2 : Electronic Packaging Hierarchy [MECH 6310 Course Notes] 6 Figure 1.3 : Evolution of Chip Carriers [MECH 6310 Course Notes] 7 Figure 1.4 : Different Types of Packaging Technology 8 1.3 Reliability concerns The current trend in electronic packaging is strongly driven by the market?s requirement to lower costs and increase circuit density, enhanced by the necessity to have faster and multi-functional electronic products. These factors give rise to a wide range of mechanical challenges in this field such as extreme operating environments or vibration. The packaging can also be exposed to high temperature changes in high power density devices. Stresses may be induced thermally due to the large mismatch of coefficients of thermal expansion of the various materials in a package, mechanical loading due to the weight of the rest of the product such as the battery or due to shock and drop in its functional life. The challenges are further augmented by the small size of the electronic structure and new materials of interest. These concerns might be responsible for the failures in the packaging through various failure modes like solder joint fatigue, die fracture, severing of interconnects, wire bond failure, delamination, encapsulant cracking, silicon cracking and underfill cracking . Reliability of electronic packaging is classified into two categories namely thermal reliability and impact reliability. Thermo-mechanical reliability is the process of estimating useful life of electronics subjected to thermal cycling or thermal aging. Reliability studies consist of life predictions of electronics in computers which may undergo thermal cycling during working and shut down modes or in under-the-hood applications of automobiles. Impact reliability deals with the consequences of electronic packaging subjected to drop and shock or vibrations. Mechanical reliability is important in the case of hand-held devices such as cell phones, PDAs and laptops as these devices have high chances of being subjected to drop or in the case of electronics in power tools 9 which are subjected to large vibrations. This thesis essentially deals with impact reliability of electronic packaging when subjected to shock and drop. As in most of the practical situations, one is not independent of the other. The effects of overlapping stress on reliability have also been investigated. 1.4 Shock and Drop Reliability Emerging trends of portable computing and communication applications towards smaller and lighter form-factors have driven the need for robust-designs under overlapping environments of shock and vibration. Electronic products may be subjected to drop and shock due to mishandling during transportation or normal regular usage. Test methods for drop reliability can be broadly classified into board-level and product-level tests, under constrained and unconstrained or free drop. One such board-level constrained drop test is the Joint Electron Device Engineering Council (JEDEC) test method. The JEDEC test standard [JEDEC 2003] is frequently used to evaluate and compare the drop performance of surface mount electronic components for handheld electronic product applications. Correlation of the board-level tests to product level performance is often challenging. Product-level failures are often influenced by housing design, in addition to drop orientation, which may not always be perpendicular to the board surface [Lim 2002]. Factors such as drop height, mass of the product, impact orientation and the properties of the impacting surface affect the forces and the accelerations that are experienced by the product during impact. Design changes encompass an iterative process for improving the impact resistance of the electronic product. Use of experimental approach to test every possible design variation, and identify the one that 10 gives the maximum design margin is often not feasible because of product development cycle time and cost constraints. 1.5 Digital Image Correlation Earlier, the measurement of derivatives of field quantities, such as strain, was limited to specific physical locations or discrete target points in an electronic structure. It was not feasible to extract data at a very large number of locations by using discrete targets because of the time consuming process. Techniques such as Moir? Interferometry are an option to get the overall deformation contour, but it is often time consuming and involve expensive grates. Digital Image Correlation (DIC) is a state-of-the-art method which supercedes the techniques used previously as it consumes less time. This method is used by researchers mainly in the field of thermal reliability. The sample preparation is simple, quick and inexpensive since the test specimens are simply speckle painted with regular paint. The transient deformation is then recorded with the help of high-speed cameras to enable the measurement of full-field strains. This work explores the possible use of DIC to obtain full field strain and displacement contours of a PCB subjected to an impact test to get reliable results. 1.6 Thesis Organization In this work, impact reliability of electronic devices was investigated by subjecting the test boards to drop tests. An assortment of package architectures that include flex ball-grid arrays, tape array ball-grid arrays (TABGA), chip array ball grid array 11 (CABGA) and metal lead-frame (MLF) packages was examined. Various test board assemblies were drop tested in 0? JEDEC and 90? vertical drop orientations in order to study the effects of drop angle on the reliability of these packages. The performance of a wide range of alloy systems such as SAC105, SAC305, SAC405, Sn3.5Ag and alloys with impurities like nickel and bismuth were evaluated. Failure analysis was performed on the failed packages to better understand the various failure mechanisms and modes associated with the different factors that affect the reliability of the packages. Data collection was accomplished with strain gages mounted at discrete locations on the test boards in conjunction with high speed data acquisition systems. Feasibility of the DIC technique to acquire full field strain data on both the board and package side was investigated for electronic assemblies subjected to free drop and constrained drop. Simulations of the drop test were developed and correlated with the experimental data. The drop test was replicated using finite element methods. Models developed include smeared property models and Timoshenko-beam models. Statistical pattern recognition method (SPR) was implemented to quantify the relative performance based on strain histories obtained from the DIC technique. SPR was used to study the effect of damage progression for various packaging architectures and for various alloy systems. Confidence value of the transient-strain response was computed using Wavelet Packet Energy Decomposition, Mahalanobis distance and Fast Fourier Transform (FFT) approach. A methodology was developed to identify the damage progression versus number of drops by studying the transient strain history of electronic assemblies from DIC in conjunction with SPR. Manifestation of damage was studied through analysis of failure 12 modes and correlation with degradation in the confidence value. The development of a transient-strain based relative damage index was investigated to establish a method for damage equivalency for the different alloy compositions. The damage proxies developed in this work could be used on strain response from simulations or from experimental data in controlled drop or shock tests. 13 CHAPTER 2 LITERATURE REVIEW As the significance of electronics is increasing rapidly, researchers have spent enormous amounts of effort and time to understand the various aspects associated with electronic packaging. Reliability of packaging has become an imperative topic in recent times. Thermal and impact reliability are the two major classifications of this topic. Realistically, these two classifications can not be separated from each other and studies have been conducted on the effect of overlapping stresses on packaging reliability. But for most research purposes, they are investigated individually. Impact reliability at board level as well as product level is considered for applications involving shock and drop during the functional life of the products, such as hand held devices. Factors like drop orientation, surface finish and alloy systems affect drop reliability and researchers have investigated these aspects using tools like failure analysis. Full field strain contours of an electronic system under different loading conditions give important insight into several aspects affecting reliability. Various techniques for acquiring this data for example, interferometry and speckle photography were investigated in the past. Newer techniques like Digital Image Correlation are also gaining importance due to advantages of reduced cost and lower sample preparation time. These techniques are being investigated to be more applicable to this field. 14 As it is not feasible to experiment and study the influence of different combinations of factors that affect reliability simultaneously, finite element analysis is considered as a valuable instrument in understanding the different aspects causing failure in electronic packaging. Prognostic methods to predict the life of a package when subjected to different types of loading conditions has gained attention in the recent past, especially in critical areas like military applications where the functioning of the electronic devices is crucial. 2.1 Board and Package Level Testing Reliability of solder interconnects in electronic devices subjected to shock and drop impact is one of the most significant factors in hand held devices since they are more prone to experience these loading conditions. Modern portable devices are equipped with increased number of new and more powerful capabilities causing the components to dissipate more heat. This results in a considerable rise of the local temperatures of the products. As products are most likely to be dropped when they are being used, it is imperative to investigate the effect of drop testing the component boards at different temperatures as done by Mattila et. al. [Mattila 2007]. On the other hand, Lall et. al. [Lall 2006] investigated the effects of overlapping stress on packaging by subjecting them first to thermal loading followed by drop tests. To keep it simple, the two loading conditions, thermal and impact are analyzed independently. The most realistic shock tests would be product-level tests on the complete product to assess its performance under drop impact. But these tests are very expensive. Package-level tests are simplified real life impact scenarios and serve as an 15 acceptable replacement of board-level drop tests that save cost and time [Yeh 2005, 2006, Ong 2003]. A variety of tests for example, bending impact [Kim 2006], ball impact [Lai 2006], pendulum impact or Charpy [Ratchev 2007], high speed bend [Seah 2006], micro impact [Ou 2005], cold ball pull and high speed shear [Johnson 2007] were investigated as tools to study impact toughness, fracture toughness and other factors contributing to impact reliability of packaging. Results from some of these tests were compared with each other for instance, impact and cold ball pull [Zaal 2007], cold ball pull and high speed shear [Johnson 2007], shear, ball pull and monotonic bend [Geng 2004]. Amongst the mechanical tests mentioned above, the drop test is the most prominent. JEDEC established a standard [JEDEC 2003] for drop tests to specify the drop impact pulse and test board configuration. This generated a common ground for an assortment of semiconductor component manufacturers to compare the solder joint reliability under impact. This standard has been widely accepted and used by researchers to compare their reliability results. However, the JEDEC standard has some limitations. One of the limitations is that it has too many loading conditions, which may be unnecessary, and results in reduced sample sizes of each loading condition for statistical analyses. To overcome this drawback, Zhao et. al. [Zhao 2007] proposed an alternative board design with only one loading condition and a sufficiently large sample size, while Tsai et. al. [Tsai 2007] demonstrated applications of the response spectra to a JEDEC standard drop test board subjected to different JEDEC drop test conditions. In spite of its drawbacks, JEDEC is the most frequently used drop test standard. The JEDEC standard specifies that the test vehicle should be mounted with the package side facing downwards to create a more critical loading condition [Yeh 2004]. It 16 also states that the drop orientation should be horizontal or at zero degrees during the drop test. But this is not the only angle at which a product might hit the floor. Experiments conducted on cell phones by Liu et. al. [Liu 2005], Seah et. al. [Seah 2002] and Ong et. al. [Ong 2003] have shown that impact reliability is very sensitive to the impact angle of the product. Chong et. al. [Chong 2005] reported that pin-supported vertical drop of PCB generated much lower PCB flexing and impact stress damage to the solder joints compared to the horizontal orientation drop. 2.2 Finite Element Models With the continuous decrease in the size of electronic devices, it is expensive, time consuming and demanding to carry out drop tests to directly detect failure modes and identify their drop behaviors. Due to the complexities involved in direct measurement of the response variables in solder joint during drop and shock events, simulation is gaining more importance in the present times. Different types of tests such as cold ball pull test [Zaal 2007] were simulated to use it as a prognostic tool and predicted the behavior of electronic packaging subjected to various loading conditions. Several techniques to simulate electronic packaging subjected to drop test have been developed by researchers. Yeh et. al. [Yeh 2004] used an implicit solver by translating the input acceleration pulse into effective support excitation load on the test vehicle, making the method numerically efficient and accurate. Many scientists have also used the explicit finite element solver to replicate the dynamic drop event [Lall 2004, 2005, Xie 2002, 2003, Wu 1998, 2000]. Other techniques used include implicit global models [Irving 2004, Pitaressi 2004, Syed 2005], the global-local sub model [Wang 2004, Tee 17 2003, Wong 2003, Zhu 2001, 2003, 2004], smeared models [Jie 2004, Lall 2006], explicit-implicit sequential model [Zhu 2005] and models with solid elements using sub modeling [Wong 2002]. The global-local sub model has detailed models to investigate the.critica1 failure location and components and a corresponding simplified model to simulate the global response and local effects of the system. Smeared models have cluster of solder balls represented by a single column and are modeled with one 3D continual layer to represent the discrete solder joints. Tan et. al. [Tan 2005] modeled the IC package, PCB, and solder interconnects with varying levels of detail to conclude that the range of deviation in the solder stress in the three models used was as much as 40%. Zhu et. al. [Zhu 2005] examined three drop tests models namely, bare board drop, board with fixture drop or shock, and system level phone drop using the sub-modeling and explicit- implicit sequential modeling techniques. 2.3 Alloy compositions and Surface Finish Due to the implementation of Restriction of Hazardous Substances (RoHS) in electrical and electronical equipment directive, lead-free solder replaced SnPb solder alloy. This execution of banning lead in the electronics industry resulted in adopting lead- free solder in spite of SnPb, which was used as the primary solder alloy world wide in the past, out-performing lead free alloys in impact resistance. Jang et. al. [Jang 2007] reported that the reason for better performance of SnPb under impact loading conditions was due to the lesser strain rate sensitivity of the bulk solder. The most common lead free alloys used today are different compositions of the Sn-Ag-Cu (SAC) alloy. Several researchers proved that SAC alloys with lower silver(Ag) content demonstrate higher 18 resistance to impact [Kim 2006, Zhao 2006, Kim 2007, Masicat 2007, Chen 2007, Pandher 2007]. Lower Ag content implies lower modulus of elasticity which in turn implies lower stiffness giving the solder greater capability to absorb large amounts of shock [Iyer 2007]. Another lead-free alternative, eutectic Sn-Ag (Sn-3.5Ag), is gaining increased recognition as a solder alloy because it provides superior component and board level performance, while not showing the metallurgical deficiencies observed in the SAC materials. Researchers have also investigated numerous impurities which can be added to the solder alloys to improve properties such as impact resistance and fracture strength in the solder interconnect under shock loading. Addition of some of these elements in SnAgCu based solder can significantly improve the drop performance, primarily because of differences in intermetallic compound (IMC) formation and the strength of solder alloys. Nickel (Ni) [Kim 2006] is one such impurity to improve the reliability of electronic packaging by retarding the formation and growth of the Cu3Sn intermetallic layer at the pad-solder interface to minimize the potential of void formation and failure at the IMC layer [Syed 2006]. Some of the other elements which have been investigated are Cobalt (Co), Antimony (Sb), Zinc (Zn), Aluminum (Al), Germanium (Ge), Indium (In) and Bismuth (Bi). Sn-Zn-Al and other alloys were observed to be potential choices for lead-free solder alternatives [Geng 2004]. Addition of Ni softens the SnAgCu alloys to improve shock reliability [Huang 2007] and addition of copper leads to brittle fractures across the solder ball interface [Anand 2004]. Tsai et. al. [Tsai 2005] asserted that SnAg solder demonstrates the highest impact fracture strength, while BiSn solder exhibits the lowest 19 strength when compared with SAC alloys. Lee et. al. [Lee 2005] reported an improvement in impact reliability after adding Nickel and Germanium to SAC alloys. SnAgCu and SnAgCuNi interconnections with a Copper - Organic Solderability Preservative (Cu-OSP) coating prove to be equally reliable and superior to the SnAgCuBi interconnections while with the Electroless Nickel Immersion Gold (ENIG) coating the SnAgCu interconnections were the most reliable. The SnAgCuBi interconenctions were the second most reliable and the SnAgCuNi interconnections were the least reliable as reported by Mattila et. al. [Mattila 2007]. Pandher et. al. [Pandher 2007] concluded that the combination of Ni and Cr offered high drop shock reliability and excellent tarnish resistance, while the combination of Ni and Bi provided over 20% improvement in solder sphere spread on Cu-OSP. The improvement of the solder sphere spread was also maintained for the Bi, Ni, and Cr combination. Surface finish was investigated as a key player affecting the reliability of packaging. Studies revealed a strong influence of different intermetallic compound formation on soldered assemblies? drop durability. Some of the most commonly used pad finishes include Hot Air Solder Leveling (HASL), Electroless Nickel Immersion Gold (ENIG), Immersion Gold (ImAg), Immersion Tin (ImSn) and Organic Solderability Preservative (OSP). Mattila et. al. [Mattila 2007] examined the combination of surface finishes Cu- OSP and ENIG with SAC alloys doped with Ni and Bi at three different temperatures under impact loading. Results showed that interconnections with the Cu-OSP coating were more reliable than ENIG finish. Other studies [Chai 2005, Kim 2006, Zhao 2006, Zhao 2007b] also reported similar conclusions. ImSn was compared with Direct Solder on Pad (DSOP) to infer that Ball Impact Test (BIT) characteristics are greater for samples 20 with the ImSn substrate pad finish [Lai 2007]. A comparison of OSP, ENIG and ImSn was investigated to conclude that OSP supersedes the performance of the other finishes [Chong 2005]. Not only the individual effect of surface finish, but also a combination with the different solder alloys was investigated. Syed et. al. [Syed 2007] concluded that SAC125Ni solder, with much better performance for Cu-OSP finish, does not show a significant improvement over SAC305 with the ENIG finish. 2.4 Failure Analysis Failure analysis provides significant insight on mechanisms that cause deterioration in reliability of electronic packaging. Prediction of failure was investigated using fracture mechanics [Shah 2004], von-misses stress [Tee 2004], and board-strain based damage index [Lall 2005]. Failure in the interconnect occurs at the interface close to the device or board side as these are the highest stressed locations in the joint. The extent of damage and failure modes varies for different alloy systems. The impact failure modes of SnPb solder were predominated by bulk failures as the bulk solder deformation absorbs some of the impact strain and cracks through solder rather than through the interfacial intermetallic. Lead-free solder, on the other hand, exhibits a mixture of IMC and bulk failure that occur along the bond interface [Tsai 2005]. The imposed strain in the SnAgCu joints moves away from the bulk solder into the lower strength brittle IMC as the apparent strength of the solder increases at higher strain rates [Jang 2007]. Comparison of the failure modes of SAC alloys indicated that crack propagation through the bulk solder was more in SAC105, due to a lower elastic modulus, than brittle IMC layer in SAC405 [Kim 2007]. Failures at the intermetallic layer on the package side and 21 the laminate beneath the pad location on the board side were predominant in SAC305 [Iyer 2007]. The addition of impurities and different combinations of alloy systems and surface finishes cause variations in failure mechanisms. A comparison of the failure modes in SAC305 and Sn1.2Ag0.5Cu0.05Ni shows an increase in drop reliability and a shift in fracture mode from interface failure to bulk failure [Kim 2006]. Syed et. al. [Syed 2007] compared a number of solder alloys to illustrate that the interfacial failure on the package side was the primary mode of failure for SAC305 with the ENIG surface finish. The failure shifted to board side through the bulk solder for the SAC125Ni solder alloy in combination with Cu-OSP. 2.5 Digital Image Correlation (DIC) High speed photography is defined as the science of capturing an extremely fast phenomenon with the help of cameras capable of acquiring images at a very high frame rate. Some of the common applications of high speed photography include measurement of deformation and strain in sheet metal forming analysis, automotive crash testing, rail vehicle safety [Kirpatrick 2001], air-plane safety [Marzougui 1999], and modal analysis of blades and disks. Other applications are shearography using laser NDT for rapid honeycomb delamination tests, dynamic fracture phenomenon, tire tests, rotating components, exhaust manifolds, split Hopkinson bar tests and package integrity or hermiticity (MIL-STD-883) tests. High-speed cameras in high speed photography measure impact speed, force, deformation due to shock, and thermal loading. It is also used for quantitative evaluation of in-plane deformation characteristics of geo-materials 22 [Watanabe 2005] and in medical fields to assess local failure of bone by implementing mechanical compression testing of bone samples [Thurner 2005]. Measurement of full field dynamic responses of a test specimen during events such as impact and vibration was always a challenge. A range of optical methods were used in the past to measure full-field displacement and deformation gradient distributions. These non-contact methods include interferometric techniques and non-interferometric techniques, like speckle photography [Smith 1993], speckle interferometry [Cote 2001], Moir? interferometry [Ho 1997, Wang 2002], holographic interferometry [Petrov 1996], and Twyman-Green and shadow Moir? interferometry [Hartsough 2007]. Researchers have used Twyman-Green and shadow Moir? interferometry to investigate various aspects such as warpage of non-conventional packages subjected to reflow and assembly processes [Hartsough 2007] and out-of-plane deformation of the bi-material specimens during moisture absorption [Tsai 2007b]. High precision optical techniques for example, shadow moir?, moir? interferometry, reflection moir? and electronic speckle pattern interferometry were considered as efficient methods to predict warping behavior of bare substrates [Wen 2007]. Optical interferometry was used not only for strain measurement, but also for acquiring 3-D surface height maps [Braunisch 2007] and surface contours of interposer bonded in a package [Marinis 2007]. Digital Image Correlation (DIC) is a new technique based on tracking a geometric point before and after deformation that enables full field strain and displacement measurement during a transient event such as shock and impact. Tracking points on the test vehicle is done by speckle coating the surface of interest. Studies reveal that size, consistency and density of the speckle pattern affect the accuracy of the method [Zhou 23 2001, Amodio 2003, Srinivasan 2005]. This method is extremely favorable in comparison to the use of strain gage which measure strain only at localized points on the specimen. It is also advantageous over interferometry as this technique is non-contact and has reduced sample preparation time and lower costs. The DIC technique was used in the electronics industry for various applications. Investigating stresses in solder interconnects of BGA packages under thermal loading [Zhou 2001, Yogel 2001, Rajendra 2002, Zhang 2004, Zhang 2005, Xu 2006, Bieler 2006, Sun 2006], stresses and strain in flip-chip die under thermal loading [Kehoe 2006], and monitoring crack propagation and calculating Young?s modulus of the underfill at elevated temperatures during four-point bending tests [Park 2007a, Shi 2007] are some of the areas for which this technique has proven to be valuable. The DIC method applied to high resolution SEM images has also been used to study the stresses released at the component surface before and after ion milling [Vogel 2007]. In addition, DIC technique was used in the study of behavior of materials like polyurethane foams. [Jin 2007], polymer films [Park 2007b] and coating materials [Thompson 2007]. It was also used for material characterization at high strain rates [Tiwari 2005]. Although this technique has become popular in the thermal area of electronic packaging, it is fairly new in the field of dynamics. DIC systems integrated with high speed cameras are being examined as helpful tools to acquire and analyze images taken during a drop event to obtain responses such as dynamic deformation, shape and strain over the entire surface of printed circuit boards not only in the horizontal configuration [Lall 2007, Miller 2007, Park 2007c] but also in the vertical drop orientation [Scheijgrond 2005]. 24 CHAPTER 3 HIGH SPEED DIGITAL IMAGE CORRELATION AND SIMULATION TECHNIQUES FOR TRANSIENT STRAIN MEASUREMENT IN ELECTRONICS SUBJECTED TO SHOCK AND DROP 3.1 Introduction Electronic components are subjected to shock, vibration and drop-impact during shipping, handling and normal usage. Measurement of transient dynamic deformation of the electronic assemblies during shock and vibration can yield significant insight into the understanding of development of failure envelopes. In this chapter, measurement of deformation kinematics with the help of ultra high-speed data acquisition and video systems are examined. Various test board assemblies were drop tested in 00 JEDEC and 900 vertical drop orientations. Electrical continuity was measured for all the daisy chained packages during the transient event. Explicit finite element models were used to assess the reliability and performance of the electronic boards. Experimental data was correlated with the finite element results. 3.2 Experimental Test Vehicle The test vehicles used in this study included boards - A, B, C, D, and E as shown in Figure 3.1. Test board-A was a bare board which was designed to accommodate 7mm - 25 32 I/O and 7mm - 44 I/O MLF packages. Test board-B was populated with five packages which included, two 10mm - 144 I/O BGA, two 16mm - 280 I/O BGA and one 6 mm - 56 I/O BGA packages. Test board-C included, 15mm CSP, 16mm C2BGA, 27mm BGA, and PQFN packages. Test board-D was populated with ten 8mm - 0.5mm pitch 132 I/O flex-substrate chip scale packages. Each of the boards was populated only on one side of the printed circuit board. Test board-E was populated with three different packages: 17mm - 256 I/O PBGA, 18mm - 192 I/O CABGA and 6 mm - 56 I/O CABGA packages. Test boards A, B and E were FR ? 4 boards with an identical dimension of 8? x 5.5? x 0.06?. For these three test boards, lead-free solder alloy 95.5Sn4.0Ag0.5Cu (SAC 405) was used. The details of all the packages are given in Table 3.1, Table 3.2 and Table 3.3. Board A Board C Board B Board D Figure 3.1: Test Boards A, B, C and D 26 Table 3.1: Package Architecture of 6mm, 10mm and 14mm BGAs 6 mm, 56 I/O CABGA 10mm, 144 I/O BGA 14mm, 92 I/O CABGA Test Vehicle Board B, E Board B Board E Ball Count 56 144 192 Ball Pitch 0.5 mm 0.8 mm 0.8 Die Size 4 mm 7 mm 6.35 mm Substrate Thickness 0.36 mm 0.36 mm 0.36 mm Substrate Pad Diameter 0.28 mm 0.34 mm 0.34 mm Substrate Pad Type NSMD NSMD NSMD Ball Diameter 0.32 mm 0.48 mm 0.48 mm 27 Table 3.2: Package Architecture of 16mm and 17mm BGAs 16mm, 280 I/O BGA 17mm, 256 I/O PBGA Test Vehicle Board B Board E Ball Count 280 256 Ball Pitch 0.8 mm 1 mm Die Size 10 mm 6.35 mm Substrate Thickness 0.36 mm 0.36 mm Substrate Pad Diameter 0.34 mm 0.34 mm Substrate Pad Type NSMD NSMD Ball Diameter 0.48 mm 0.5 mm Table 3.3: Package Architecture of 32 I/O and 44 I/O MLF Packages 7mm, 32 I/O MLF 7mm, 44 I/O MLF Test Vehicle Board A Board A Lead Count 32 44 Pitch 0.5 mm 0.65 mm Die Size 2.5 mm 3.25 mm Substrate Thickness 0.9 mm 0.9 mm Substrate Pad Thickness 0.1 mm 0.1 mm Substrate Pad Type NSMD NSMD 28 Three different lead-free surface finishes, namely, ImAg, ENIG and ImSn for test board B were examined. All the packages used in the test configuration were daisy- chained. In all cases, multiple boards were tested in each test configuration. Test boards were exposed to sequential stresses of either thermal cycling or thermal aging, followed by shock impact to determine the effect of cumulative damage of the overlapping stresses on the interconnect reliability. Thermo-mechanical cycling included exposure from -40oC to 125oC for 100 cycles. The duration of each cycle was 90 minutes with 25 minute ramps between temperature extremes and 15 minute dwell periods at each temperature extreme. The test vehicle F used for this study is shown in Figure 3.2. The board was made up of FR-4 with dimensions of 5.2? x 3.03? x 0.04?. The test vehicles were populated only on one side. Each of the test boards had 15 Chip-Array Ball-Grid Array (CABGA) packages with an I/O count of 100 and a pitch of 0.8mm. Details of the package are shown in Table 3.4. The interconnect array configuration of the 10mm CABGA is shown in Figure 3.3. All the packages used in the test configuration were daisy chained. The surface finish of the test boards was ENIG on the populated side and Cu-OSP on the unpopulated side. Six different alloy compositions including Sn1Ag0.5Cu (SAC105), Sn3Ag0.5Cu (SAC305), Sn0.3Ag0.7Cu (SAC0307), Sn0.3Ag0.7Cu-Bi (SACX), Sn0.3Ag0.7Cu-Bi-Ni (SACX-Plus) and 96.5Sn3.5Ag (SnAg) were examined for this board. The compositions of the various alloy systems are given in Table 3.5. 29 Figure 3.2: Test Vehicle Table 3.4: CABGA Package Details Ball Count 100 Ball pitch(mm) 0.8 Die Size(mm) 5.55 Substrate Thickness(mm) 0.232 Substrate Pad Type NSMD Ball Diameter(mm) 0.48 30 Figure 3.3: Interconnect Array Configuration of the 10mm-100 I/O CABGA Package Table 3.5 : Lead Free Alloy Compositions Alloys Composition SAC105 Sn: 98.5%,Ag: 1%, Cu: 0.5% SAC305 Sn: 96.5%,Ag: 3%, Cu: 0.5% SAC0307 Sn: 99%,Ag: 0.3%, Cu: 0.7% SACX Sn: 98.9%,Ag: 0.3%, Cu: 0.7%, 0.1% Bi SACX-PLUS Sn: 98.8%,Ag: 0.3%, Cu: 0.7%, 0.1% Bi, 0.1%Ni Sn3.5Ag Sn: 96.5%,Ag: 3.5%, 31 3.3 Detection Of Damage Progression The test boards were subjected to controlled drop. Repeatability of drop orientation is critical while measuring a repeatable response. Significant effort was invested in developing a repeatable drop set-up because small variations in the drop orientation could produce significantly varying transient-dynamic board responses. Repetitive readings were taken to determine repeatability of the controlled drop orientation. Repeatability was characterized and is shown in Figure 3.4, Figure 3.5 and Figure 3.6. Tests were performed in two different drop orientations. The 0o drop was done in the JEDEC configuration, involving a 1500g, 0.5 millisecond, half-sine input pulse. The 90o drop was a free drop with a weight attached to the circuit-board assembly to simulate the weight of the battery and the components in a typical product board. For this arrangement, the test vehicle was attached to the drop table with the help of a nylon string. Weights were added to the printed circuit board F when dropped in the JEDEC drop orientation to simulate the effect of shields. Weights were in the form of two metal strips attached at equal distances from the center of the board. Strain gages were placed on the populated boards on the package side and on the board side at different locations to measure longitudinal strain on the boards. One such arrangement along with the numbering scheme of packages for test structure F has been shown in Figure 3.7. The drop tower along with a test board instrumented with strain sensors is shown in Figure 3.8. 32 Experimental Set up repeatability -800 -600 -400 -200 0 200 400 600 800 1000 0 0.01 0.02 0.03 Time (Seconds) Str ain (M icr ost ra in) Drop2 Drop3 Drop4 Drop5 Drop6 Drop7 Drop8 Drop9 Drop10 Drop11 Figure 3.4: Strain Repeatability for Test-Board A Pacakge 8 -2.E-03 -2.E-03 -1.E-03 -5.E-04 0.E+00 5.E-04 1.E-03 2.E-03 0 0.01 0.02 0.03 Time (Sec) St ra in Drop 1 Drop 2 Drop 3 Drop 4 Drop 5 Drop 6 Drop 7 Drop 8 Figure 3.5: Repeatability Plot at Package Location 8 on test board F 33 Package 9 -1.E-03 -5.E-04 0.E+00 5.E-04 1.E-03 0 0.01 0.02 0.03 Time(Sec) St ra in Drop 1 Drop 2 Drop 3 Drop 4 Drop 5 Drop 6 Figure 3.6: Repeatability Plot at Package Location 9 on test board F GND 1 42 53 10 68 79 1415 1213 11 15 CABGA100 packages 5 strain gages S2 S4 S5S3S1 Figure 3.7: Location of Gages and Numbering Scheme of Packages on SAC305 Alloy Specimen Board on Test Board F 34 Figure 3.8: Experimental Set-up for Controlled JEDEC Drop of Test Board B 35 Strain and continuity data were acquired during the drop event using a high-speed data acquisition system operating at 2.5 to 5 million samples per second. The drop-event was simultaneously monitored with an ultra high-speed video camera operating at 30,000 frames per second. Targets were mounted on the edge of the board to allow high-speed measurement of relative displacement during the drop event as shown in Figure 3.9. Responses, namely, strain, displacement, orientation angle, velocity, acceleration, and continuity data were acquired simultaneously. An image tracking software was used to quantitatively measure displacement during the drop event. Figure 3.10 shows a typical relative displacement plot measured during the drop event. The plot trace subsequent to the white scan is the relative displacement of the board targets with respect to a specified reference. In addition to relative displacement, velocity and acceleration of the board prior to impact were also measured. Figure 3.9: Board B Mounted with Targets for Relative Displacement Measurement 36 Figure 3.10: Relative Displacement of Test Board B Subjected to JEDEC Drop Figure 3.11 shows the package-strain history during the impact test of board B in the JEDEC drop orientation at the 16mm - 280 I/O package location. Failure in the device was identified as an increase in voltage drop. Similar plots, Figure 3.12 and Figure 3.13, have been shown for test structure F. Different locations on a particular test board exhibited different strain histories during the same drop. Packages at different locations on a single test vehicle failed at different cycle counts. However, the strain histories were very consistent and repeatable at the same component location on the test board for various drops. The strain history was also very repeatable for the same component location across various test boards. 37 Strain and Continuity -1000 -500 0 500 1000 1500 -0.02 -0.01 0 0.01 0.02 0.03 0.04 Time (Seconds)S tra in (M icr ost ra in) -6 -1 4 9 Vo lta ge (V olt s) Strain Continuity Figure 3.11: Package Strain and Continuity History in JEDEC drop-shock Orientation, for Test board B 38 SAC0307-Package 12 -400 -200 0 200 400 600 -0.01 0 0.01 0.02 0.03 0.04 Time(sec) Str ain (M icr ost ra ins ) -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 Co nti nu ity Transient Strain Continuity Figure 3.12: Strain and continuity history at Package 12 for SAC0307 alloy system on Test Board F SACX-Package 12 -4.E-03 -3.E-03 -2.E-03 -1.E-03 0.E+00 1.E-03 2.E-03 3.E-03 0 0.01 0.02 0.03 Time(sec) Str ain -20 -15 -10 -5 0 5 Co nti nu ity Transient Strain Continuity Figure 3.13: Strain and continuity history at Package 12 for SACX alloy system on Test Board F 39 3.4 Digital Image Correlation (DIC) Digital image correlation is an optical method to measure full field deformation on the surface of an object. The technique is based on tracking a geometric point before and after deformation and using it to calculate the displacement field. This method has been used in the past for various applications such as for acquiring stress and strain in solder interconnects and for material characterization under thermal loading. However, data is scarce for the behavior of a printed circuit board (PCB) transient dynamics in shock, which is a major reliability issue, to study the failures at the solder interconnects in portable electronics. Board-level reliability of an electronic assembly has never been studied using this technique when subjected to drop in vertical and JEDEC orientations. In this work, DIC was used for capturing the shock-deformation in electronic assemblies by tracking the speckle pattern in small regions called subsets or sub-images. High speed cameras were used to capture the motion of assemblies before and after deformation. The undeformed and deformed images are called the original image and deformed image respectively. A subset around a reference pixel O in the reference image was then compared with the corresponding subset in the deformed image using a predefined correlation function to describe the difference between the two digital sub- images. The full field displacement contour was obtained by shifting the reference pixel in the original image and applying this method to all the other pixels of the images. Figure 3.14 shows the digital images of the speckle patterns before and after deformation, obtained using high speed cameras. The relationship between the reference image I1(r) and the deformed image I2(r) is given as follows: 40 )]r(Ur[I)r(I 12 ?= (3.1) )]r(Ur[I)r(I 21 += (3.2) where U(r) is the displacement vector at pixel r = (x,y)T. An algorithm based on the mutual correlation coefficient or other statistical functions was used to correlate the change in a reference pixel in the original image and the corresponding reference pixel in the deformed image. M pixels N pixels O r Reference Image I1(r) ?x ?y Analyzed area (M x N) matrix U(r) O r Current Image I2(r) O` Before Deformation After Deformation Figure 3.14: DIC Principle Three such typical correlations are absolute difference, least square and cross correlation. They were defined as follows: Absolute difference: 41 ?? ?? ? ? ?+?= dr)r( dr)r()'rr(1)'r( I IIC 1 12 A (3.3) Least square: ?? ?? ? ? ?+?= dr)r( dr)]r()'rr([1)'r( 2 1 2 12 L I IIC (3.4) Cross-Correlation: [ ] 2/12221 21C dr)'rr(dr)r( dr)'rr(1)'r( II I)r(IC ?? ?? ?? ? ? ? + +?= (3.5) where ? (M x N) is the area of the sub-image around reference pixel r, r` is the current pixel, CA(r`) is the current absolute difference correlation function, CL(r`) is the current least square correlation function, and CC(r`) is the current cross correlation function. The cross-correlation functions provided the correspondence between matching subsets in images of the undeformed and deformed states. It was an iterative spatial domain cross- correlation method. This method maximized the cross-correlation coefficient between a subset in the reference image I1 and the deformed image I2. In practice, the absolute and least square correlation functions require less computation since constant brightness is assumed. In order to handle illumination changes, normalized cross-correlation is used, which is computationally demanding. Correlation functions determine the difference between the current pixel O? and the reference pixel O, by matching the two sub-images. To estimate sub-pixel displacements, U(r) in a sub-image corresponding to a pixel r0 = (x0, y0)T in the current image I2(r) is assumed to be constant [Davis 1998]. 42 T0000 )v,u(U)r(U)r(U === (3.6) Equations (1) and (2) can then be written as; [Zhou 2001] )Ur(I)r(I 012 ?= (3.7) )Ur(I)r(I 021 += (3.8) Taylor expansion of these two equations yields: ? ? +???+??= +?????+???= U)r(IU)r(IU)r(I)r(I)r(I UrIUrIUrIU)r(I)r(I 3 01 2 01 1 0112 3 03 12 02 11 01 10 012 (3.9) After neglecting higher order terms, 0112 U)r(I)r(I)r(I ???= (3.10) 0221 U)r(I)r(I)r(I ??+= (3.11) where )r(I1? and )r(I2? are spatial gradients of two images. Equations (3.10) and (3.11) can be rearranged as [Zhou 2001]: )]r(I)r(I[2U)]r(I)r(I[ 21021 ?=??+? (3.12) Equation (3.11) holds for M x N pixels in a sub image ? around r0 and therefore leads to M x N equations. The least squares approximate solution to these equations is then determined by [Zhou 2001]: ( ) bAAAU T1T0 ?= ? (3.13) where, 43 ???? ?? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ?+? ? ? = r,2NM 2T1T )r(I)r(IA (3.14) ???? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = r,1NM 21 )]r(I)r(I[2b (3.15) 3.5 Experimental Set-up For this study, strain was measured using two methods. The DIC technique was used to get the full field strain and displacement contours with the help of high speed cameras. Gages were also mounted at different locations on the test boards and strain was measured at these points with the help of high speed data acquisition systems. Data was acquired on the populated as well as the non-populated sides of the test specimens. In conjunction to this, continuity data was also monitored during impact. Figure 3.15 shows the speckle pattern on four of the test boards under investigation. Patterns on the six alloy system on test board F are shown in Figure 3.16. Efforts were taken to get similar and consistent speckle patterns on all the test boards since the speckle size and distribution affect the accuracy of this technique [Zhou 2001, Gu 2006]. The package side and the board side of a speckle coated specimen board mounted with strain gages are shown in Figure 3.17. 44 Test Board A Test Board B Test Board C Test Board D Figure 3.15: Speckle Pattern on Four of the Test Vehicles Figure 3.16: Speckle Pattern on the Populated Side of the Six Alloy System Test Vehicles 45 Figure 3.17: Speckle Coated Image of Test Board with Strain Gages (A) Package Side (B) Board Side The DIC experimental set up consisted of two high speed cameras mounted on two independent tripods on a rigid floor in front of the drop tower so as to make an angle of approximately 30? with the specimen. Previous research has indicated that keeping the angle between the cameras in the range of 20? to 40? gives higher accuracy [Gu 2006, Helm 1996]. The arrangement for both the drop orientations is shown in Figure 3.18. The two CCD cameras were internally synchronized and were manually triggered with an external trigger. Before recording the drop event, the cameras were calibrated. Calibration involved capturing images of the target at different orientations as shown in Figure 3.19. The target used in this study consisted of a 9 x 9 grid of black points on a white background with a 10 mm pitch. 12 to 15 such images were taken so as to get a 46 good calibration, ensuring high accuracy. The test specimen was constraint to the drop table with four screws at the four corners of the board. The drop table was dropped from a height of 9 inches, so as to achieve 1500Gs as per the JEDEC standard. A set of test vehicles were also drop tested from a height of 12 inches. In the vertical drop arrangement, the boards were attached with a nylon string to the drop table and were drop tested from a height of 3 feet. The transient event was captured by the two cameras which were triggered simultaneously and a video clip of the drop was recorded at 50,000 frames per second (fps). The clip was then sampled to get images of the event which were further analyzed using software from Correlated Solutions. The drop test was continued until all the packages on the test board failed. 47 30? CCD CCD Rigid Floor 250 CCD CCD Drop Tower Rigid Floor JEDEC Drop Orientation Vertical Drop Orientation Figure 3.18: Experimental Set-up for DIC in both the Drop Orientations Figure 3.19: Calibration Images 48 3.6 Correlation of DIC Technique and Strain Gage Data Strain from DIC technique was correlated with the strain values obtained from strain gages at various locations on the test specimens. Three such comparisons at points A1, A3, and A6 on test vehicle C subjected to drop in the vertical orientation are shown in Figure 3.20, Figure 3.21 and Figure 3.22. Comparison of strain values from DIC and strain gages at three locations on the board F with SAC305 alloy system is also shown in Figure 3.23, Figure 3.24 and Figure 3.25. DIC results obtained were accurate and consistent with the strain gage sensors. 2D strain contours of test boards A, B and C when dropped in the vertical orientation are shown in Figure 3.26. Figure 3.27 corresponds to the DIC 3-D contours of strain in the longitudinal direction at different time instants for test board C drop tested in the vertical drop direction. Although this plot represents the drop test in the vertical drop orientation, the board appears to be horizontal with the ground on the right hand side of the figure. Figure 3.28 shows the 3-D contours of strain for test board A in the 0? JEDEC configuration. Figure 3.29 shows a comparison of a DIC transient-deformation contour with the actual deformation contour of the test specimen. Figure 3.30 shows the 3D strain contours at successive drops during the transient drop event. 49 Correlation at Location A1 -2000 -1000 0 1000 2000 -0.005 0 0.005 0.01 0.015 0.02 Time (Second)St ra in (M icr os tra in) DIC Strain Gage Figure 3.20: Strain Correlation of Test Board-C subjected to Vertical Drop at Location A1 Correlation at Location A3 -3000 -2000 -1000 0 1000 2000 -0.005 0 0.005 0.01 0.015 0.02 Time (Second)Str ain (M icr os tra in) DIC Strain Gage Figure 3.21: Strain Correlation Test Board-C subjected to Vertical Drop at Location A3 50 Correlation at Location A6 -3000 -2000 -1000 0 1000 2000 -0.005 0 0.005 0.01 0.015 0.02 Time (Second)St ra in (M icr os tra in) DIC Strain Gage Figure 3.22: Strain Correlation Test Board-C subjected to Vertical Drop at Location A6 Strain Gage location - S2 -1500 -1000 -500 0 500 1000 1500 2000 0 0.005 0.01 0.015 0.02 TimeMi cro str ain Strain gage DIC Technique Figure 3.23: Correlation of Strain from DIC and Strain Gages for SAC305 Alloy System at Gage Location S2 51 Strain Gage location - S3 -1500 -1000 -500 0 500 1000 1500 2000 0 0.005 0.01 0.015 0.02 Time M icr ost ra in Strain gage DIC Technique Figure 3.24: Correlation of Strain from DIC and Strain Gages for SAC305 Alloy System at Gage Location S3 Strain Gage location - S4 -1500 -1000 -500 0 500 1000 1500 -0.005 0 0.005 0.01 0.015 0.02 Time M icr ost ra in Strain gage DIC Technique Figure 3.25: Correlation of Strain from DIC and Strain Gages for SAC305 Alloy System at Gage Location S4 52 Board A Board B Board C Figure 3.26: 2D Strain Contours of Boards A, B, and C Dropped in Vertical Orientation t=1.43ms t=2.86ms t=4.29ms t=5.0ms Figure 3.27: 3D Longitudinal Strain Contours from DIC for Test-Board C subjected to 90? Vertical Drop 53 t=4.29ms t=1.43ms t=2.86ms t=5.0ms Figure 3.28: 3D longitudinal strain contours from DIC for Test-Board A subjected to 0? JEDEC Drop Figure 3.29: Comparison of DIC Strain Contour with the Actual Contour 54 t = 1.9ms t = 10.1ms t = 13.1ms t = 14.9ms t = 3.9ms t = 5.3ms t = 9.5ms t = 19.3ms Figure 3.30: 3D Strain Contours at Successive Drops during the Transient Drop Event 3.7 Full-Field Transient Strains for Various Lead-free Alloys The full-field transient strains for six lead-free alloys, namely, SAC105, SAC305, SAC0307, SACX, SACX-Plus and Sn3.5Ag were measured. The measurements of the strain histories were compared as a function of package locations on the package-side and the board-side. Figure 3.31 and Figure 3.32 show the peak strain values as a function of package location on SACX and SAC0307 test boards. The trend was consistent for various alloy systems examined in the study. Largest PCB peak strain values were observed in the center section of the JEDEC test board, shown as maxima at package locations 2-3, 8-9, and 13-14. Strain values at two different locations, package 2 and package 14, on the PCB just below the package are shown in Figure 3.33 and Figure 3.34. The peak strain values between alloys differed greatly and are plotted in Figure 3.35. It is hypothesized that the difference in the peak strain is due to difference in the elastic modulus of the solder alloys. Figure 3.36 shows failure as a function of package 55 location. The number of drops-to-failure was strongly correlated with the magnitude of peak strain. Packages with the largest peak strain exhibited the smallest cycle count-to- failure. The negative trend between drops-to-failure and peak value of transient strain during a drop event for SAC305 and Sn3.5Ag solders is shown in Figure 3.37 and Figure 3.38. The negative trend was consistent for all the alloys. Data-analysis proved that the PCB transient strain histories were a valid potential indicator of failure progression and failure thresholds for the different lead-free alloy systems. 56 15 14 13 12 11 0 0.0002 0.0004 0.0006 0.0008 0.001 0.0012 0.0014 0.0016 0.0018 0.002 Strain SACX alloy system Figure 3.31: Peak PCB Strain Values as a Function of Package Location on the SACX Solder Alloy System on Board F 15 14 13 12 11 S1 S2 S3 0 0.0005 0.001 0.0015 0.002 0.0025 Strain SAC0307 alloy system Figure 3.32: Peak PCB Strain Values as a Function of Package Location on the SAC0307 Solder Alloy System on Board F 57 Package 2 -2.00E-03 -1.50E-03 -1.00E-03 -5.00E-04 0.00E+00 5.00E-04 1.00E-03 1.50E-03 2.00E-03 0 0.002 0.004 0.006 0.008 0.01 Time (Seconds) Str ain SAC105 SAC305 SAC0307 SACX SACX-plus Sn3.5Ag Figure 3.33: Comparison of Strain for the Six Alloy Systems at Package 2 Location on Board F Package 14 -2.00E-03 -1.50E-03 -1.00E-03 -5.00E-04 0.00E+00 5.00E-04 1.00E-03 1.50E-03 2.00E-03 0 0.002 0.004 0.006 0.008 0.01 Time (Seconds) Str ain SAC105 SAC305 SAC0307 SACX SACX-plus Sn3.5Ag Figure 3.34: Comparison of Strain for the Six Alloy Systems at Package 14 Location on Board F 58 Peak Strain Values 0 0.0005 0.001 0.0015 0.002 SAC 105 SAC 030 7 SAC 305 SACX SAC X-p lus Sn3 .5A g Alloy system St ra in Package 4 Package 12 Figure 3.35: Peak Strain Values at Packages 4 and 12 Location for the Various Alloy Systems on Board F SACX-Plus Alloy System 0 50 100 150 200 250 1 2 3 4 5 Package Location Fa ilu re Cy cle Figure 3.36: Failure Plot for the SACX-Plus Alloy System on Board F 59 Figure 3.37: Correlation of Peak Strain with Drops-to-Failure for SAC305 alloy on Board F Figure 3.38: Correlation of Peak Strain with Drops-to-Failure for Sn3.5Ag alloy on Board F 60 The 2D strain state was measured on the top surface of the package during the transient deformation experienced by the board assembly during the shock-impact. The measurements of full-field package strain at various package locations were compared for the various lead-free alloys. Comparison of strain contours for the six alloys at package 12 location has been shown at the same time instant after impact in Figure 3.39. Strain distributions varied with solder alloys at the same location and same instant after impact. Figure 3.39: Comparison of 2D Contour Plot at Package Location 12 at Same Time Instant for Different Alloy Systems on Board F 3.8 Explicit Finite Element Models Explicit finite element methods are well suited to simulate high-speed dynamic events which require small increments in order to obtain high resolution solutions. Transient dynamic deformation of the test boards was treated as a wave propagation problem and 61 was modeled using explicit finite element models. Prediction of the response of the test specimen subjected to 0? JEDEC and 90? vertical drop orientations were simulated and results from the simulation were correlated with the DIC measurements. Previously, the JEDEC JESD22-B111 condition was modeled using the input-G method [Tee 2004]. In this thesis, the use of explicit finite elements has been investigated. The use of this method enables the calculation of response history using step-by-step integration in time without changing the form of dynamic equations as done in modal methods. The modeling effort was focused on the predictions of transient dynamic drop response variables using explicit finite-element theory with reduced integration elements. An explicit algorithm uses a difference expression of the general form, (3.16) where {D} is the degree of freedom vector, the ?.? on top of the variable represents time differentiation, and subscript ?n? represents the time-step. The equation contains only historical information on the right hand side. The difference expression is combined with the equation of motion at time step ?n? for the simulation and is given as, [ ] [ ] { } { } { } [ ]{ } [ ] [ ] { } 2 1 int 2 2 1 1 1 2 2 1 1 2 n ext n nn n M C Dt t R R M D M C Dt t t + ? ? ?+? ? ? ?? ? ? ?= ? + ? ?? ? ? ? ?? ? (3.17) If [C] in equation (3.16) was either zero or diagonal, each time step was executed very quickly because the solution of simultaneous equations is not required. But [C]= ? [M] + ? [K], 62 such that diagonal [C] corresponds to mass-proportional damping ? [M] with diagonal [M], which damps lower modes most heavily. Mass damping was used for the PCB material in the simulation. Hence, there was a small time-lag which was unavoidable since the implementation was to be fully explicit, i.e. the solution of any of the equations was not required. In order to have equation (3.16) to be conditionally stable, we need to have, max 2=?