A Linear CMOS Tunable Active Resistor
Except where reference is made to the work of others, the work described in this thesis is
my own or was done in collaboration with my advisory committee. This thesis does not
include proprietary or classified information.
Bradford K. Hill
Certificate of Approval:
Fa Foster Dai
Associate Professor
Electrical and Computer Engineering
Michael E. Greene, Chair
Professor Emeritus
Electrical and Computer Engineering
Bogdan M. Wilamowski
Professor
Electrical and Computer Engineering
Joe Pittman
Interim Dean
Graduate School
A Linear CMOS Tunable Active Resistor
Bradford K. Hill
A Thesis
Submitted to
the Graduate Faculty of
Auburn University
in Partial Fulfillment of the
Requirements for the
Degree of
Master of Science
Auburn, Alabama
May 10, 2008
A Linear CMOS Tunable Active Resistor
Bradford K. Hill
Permission is granted to Auburn University to make copies of this thesis at its
discretion, upon the request of individuals or institutions and at
their expense. The author reserves all publication rights.
Signature of Author
Date of Graduation
iii
Vita
Bradford Keith Hill, son of Keith and Brenda Hill, was born on May 11, 1982 in Mont-
gomery, Alabama. He started his collegiate career at Samford University in Birmingham,
Alabama in August 2000. He subsequently transferred to Auburn University to study elec-
trical engineering in May 2001. He graduated with a Bachelor?s of Electrical Engineering
Degree from Auburn University in December 2004. He started graduate school at Auburn
University in January 2005. He entered the workforce at Archangel Systems Incorporated
in May 2005 and worked as an engineer while attending graduate school.
iv
Thesis Abstract
A Linear CMOS Tunable Active Resistor
Bradford K. Hill
Master of Science, May 10, 2008
(B.E.E., Auburn University, 2004)
64 Typed Pages
Directed by Michael E. Greene
The demand for fast, inexpensive, and accurate sensors is increasing at a staggering
rate. Deciding whether to use analog of digital signal processing for these sensors has become
a challenge. Even though digital systems have become very fast, often the delay associated
with digital signal processing cause stability issues in the systems. Analog circuitry is still
needed for these types of systems. The challenges of using on-chip passive components
are described as well as so techniques of overcoming the issue. A Linear Tunable Active
resistor, proposed by Dr. Bogdan M. Wilamowski, is described in this thesis that attempts
to overcome some of the shortcomings that on-chip passive components have. The design,
operation, and simulation results of the active resistor are presented, as well as the use of
the active resistor as replacements for passive resistors in simple filters and a Proportional-
Integral-Derivative controller.
v
Acknowledgments
I would like to thank the members of my advisory committee for providing much help
and having much patience with me during my graduate studies. I would like to thank in
particular Dr. Bogdan M. Wilamowski for providing the circuits described in this thesis. I
would also like to thank Dr. Michael E. Greene for giving me a job at Archangel Systems
and being flexible to work around my class schedule.
vi
Style manual or journal used Bibliograpy follows van Leunen?s A Handbook for Scholars.
Computer software used The document preparation package TEX (specifically LATEX)
together with the departmental style-file aums.sty. PSPICE
vii
Table of Contents
List of Figures ix
List of Tables xi
1 Introduction 1
1.1 Increasing Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.1 Increasing Electrode Area . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.2 Increasing the Permativity of the Dielectric . . . . . . . . . . . . . . 7
1.1.3 Decreasing the Distance Between the Electrodes . . . . . . . . . . . 9
1.2 Active Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Design and Simulation of Active CMOS Resistor(ACR) 11
2.1 Design of CMOS Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.1 Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.2 Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 DC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 AC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4 Transient Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5 Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3 Resistor Substitution 25
3.1 Single Pole Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1 Low-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.2 High-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2 PID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2.1 Proportional Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2.2 Integral Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2.3 Differential Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4 Conclusion 46
Bibliography 47
Appendices 49
A Transistor Models 50
viii
List of Figures
1.1 Architecture of a double stacked MIM capacitor . . . . . . . . . . . . . . . . 5
1.2 VPP capacitor layout diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 High Density Trench Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Separate Die Integration Platform . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Schematic of ACR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Small Signal Model for ACR . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Output Current vs Output Voltage . . . . . . . . . . . . . . . . . . . . . . . 17
2.4 Resistance vs Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5 Resistance vs Tuning current . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.6 Output Current vs Input Voltage Frequency . . . . . . . . . . . . . . . . . . 20
2.7 Phase of Output Current vs Input Voltage Frequency . . . . . . . . . . . . 21
2.8 Resistance vs Input Frequency . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.9 Output Current with Sinusoidal Input Voltage . . . . . . . . . . . . . . . . 22
2.10 Resistance vs Sinusoidal Input Voltage . . . . . . . . . . . . . . . . . . . . . 23
3.1 Single Pole Low-Pass Filter Configuration . . . . . . . . . . . . . . . . . . . 27
3.2 Low-Pass Filter Output Magnitude vs Frequency . . . . . . . . . . . . . . . 28
3.3 Low-Pass Filter Output Phase vs Frequency . . . . . . . . . . . . . . . . . . 29
3.4 Low-Pass Filter Transient with Stepped Tuning Current . . . . . . . . . . . 30
3.5 Low-Pass Filter With 9723 Hz Input Signal . . . . . . . . . . . . . . . . . . 30
ix
3.6 Single Pole High-Pass Filter Configuration . . . . . . . . . . . . . . . . . . . 32
3.7 High-pass Filter Output Magnitude vs Frequency . . . . . . . . . . . . . . . 33
3.8 High-pass Filter Output Phase vs Frequency . . . . . . . . . . . . . . . . . 34
3.9 High-Pass Filter Transient with Stepped Tuning Current . . . . . . . . . . . 34
3.10 High-Pass Filter Transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.11 Proportional Stage of Controller . . . . . . . . . . . . . . . . . . . . . . . . 38
3.12 Proportional Stage Output Magnitude vs Input Voltage Frequency . . . . . 38
3.13 Proportional Stage Output Phase vs Input Voltage Frequency . . . . . . . . 39
3.14 Integral Stage of Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.15 Integral Stage Output Magnitude vs Input Voltage Frequency . . . . . . . . 41
3.16 Integral Stage Output Phase vs Frequency . . . . . . . . . . . . . . . . . . . 42
3.17 Derivative Stage of Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.18 Differential Stage Output Magnitude vs Input Voltage Frequency . . . . . . 44
3.19 Differential Stage Output Phase vs Input Voltage Frequency . . . . . . . . . 45
x
List of Tables
1.1 Capacitance Parameters for AMIS C5 process . . . . . . . . . . . . . . . . . 2
1.2 Resistor Parameters for AMIS C5 process . . . . . . . . . . . . . . . . . . . 3
2.1 Noise Sources of ACR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 Total Harmonic Distortion Low-Pass Filter . . . . . . . . . . . . . . . . . . 31
3.2 Total Harmonic Distortion high-pass Filter . . . . . . . . . . . . . . . . . . 36
xi
Chapter 1
Introduction
With the demand for inexpensive, fast, and accurate sensors, the need to integrate
multiple systems on one chip while reducing costs is increasing. The pros and cons of analog
versus digital signal processing must be weighed against one another to determine the type
of ASIC to be produced. The main performance advantage that analog signal processing
has over digital signal processing for these sensors is less delay and high dynamic ranges
for high frequency signals [1]. Making devices smaller has lead to the ability to increase
the speed of these devices and fit more dies per wafer, which lowers the manufacturing cost
per device. Using on-chip passive components avoids the parasitic inductance of leads and
decreases printed circuit board area, while lowering the cost of the system. While processing
technology has been able to decrease the minimum feature size of active devices, on-chip
passive components have not been able to keep up with their active device counterparts.
However, when dealing with analog signals active components would be nothing without
these passive components, so finding ways to overcome the challenges of creating high quality
and high density on-chip passive components is the obvious objective.
In order to understand the impact the limitations of on-chip passive components have
on the design of circuits, the design constraints of the circuit must be considered. In equation
(1.1), fc represents the corner frequency of an RC circuit, e.g., low-pass filter or high-pass
filter.
1
fc = 12?pi ?R?C (1.1)
With a corner frequency of 1000Hz the RC time constant of the circuit would be 1ms.
Table (1.1) shows the capacitance between each layer of the AMIS C5 process provided by
MOSIS Integrated Circuit Fabrication Service [2].
CAPACITANCE PARAMETERS N+ P+ POLY POLY2 M1 UNITS
AREA (substrate) 439 752 101 aF?2
AREA (N+active) 2411 aF?2
AREA (P+active) 2328 aF?2
AREA (poly) 929 61 aF?2
Table 1.1: Capacitance Parameters for AMIS C5 process
The most commonly used capacitor is the polysilicon to polysilicon capacitor because of
its manufacturability. The capacitance value for a poly-poly capacitor in this process is
? 1 fF?m2. Allowing a maximum of 1000?m2 for a capacitor yields a capacitor value of 1pF.
Substituting 1pF for C and 1000Hz for fc back into equation (1.1) and solving for R gives
R = 12?pi ?1000?10?12 ? 160M? (1.2)
Table (1.2) shows the resistor value of each layer per unit area.
2
PROCESS PARAMETERS N+ P+ POLY PLY2HR M1 UNITS
Sheet Resistance 80.7 103.8 22.8 949 0.09 ?/square
Contact Resistance 61.6 158.8 19.3 ?
Gate Oxide Thickness 143 angstroms
Table 1.2: Resistor Parameters for AMIS C5 process
Due to cost constraints, resistors are made of either low doped polysilicon or source
drain diffusion areas, which are susceptible to circuit coupled noise [3]. High resistance
polysilicon provides ? 1000?square. Equation (1.3) calculates the area of high resistance polysil-
icon needed to realize a resistance of 160M?, with one square = 1?m2 then
Area = 160e6?? 1?m
2
103? = 160000?m
2 (1.3)
The resulting calculation produces an area 160 times the maximum allowable size, and
therefore impractical.
Not only is a resistor of this magnitude not practical due to the area it will consume,
but also the noise generated by large resistances starts to be a concern. The Johnson noise
generated from a resistor is defined by equation (1.4). Substituting the correct values for
the variables gives
Vt =
?
4?k ?T ?R =
?
4?1.38?10?23 ?300?160?106 = 1.62?V?Hz (1.4)
A resistor with this magnitude will generate noise of 1.62?V?Hz . In sensors, since accuracy
is the key objective, any source of noise must be eliminated. Since this thermal noise is
3
proportional to the resistance value, a way to lower the resistance value must be found [4].
Fortunately, some clever techniques have been developed in order to ease the limitations of
on-chip passive components.
1.1 Increasing Capacitance
The only way to lower the resistance needed, while maintaining the same RC time
constant is to increase the capacitance. The parallel plate capacitance, equation (1.5) is
used. There are three methods to increase capacitance in parallel plate capacitors,
1. Increase area of electrodes
2. Increase the permativity, epsilon1, of the dielectric between electrodes
3. Decrease distance between electrodes
C = epsilon1Ad (1.5)
1.1.1 Increasing Electrode Area
Increasing electrode area is a subject well documented. There are several methods of
increasing electrode area and all are equally clever in their approaches. The first that is
discussed in detail, in [5] as well as [6], is using three dimensional capacitors utilizing not
only plates stacked on top of one another but also those adjacent to each other. In [5], a
method of using vertical parallel plates is discussed. This method uses metal plates in a
parallel fashion by stacking metal levels. Vertical parallel plates are also discussed in [6].
4
Figure 1.1 from [6] shows in more detail what is suggested, using multiple metal layers with
oxide between them as a dielectric, in a Metal Insulator Metal (MIM) configuration. These
parallel plates stacked vertically are wired in parallel to effectively double the electrode
area.
Figure 1.1: Architecture of a double stacked MIM capacitor
Another means of making three dimensional capacitors is discussed in [7]. This method
uses the sides of interdigitated metal lines and interlayer vias maximize capacitor density.
Figure 1.2 shows a clear illustration of the three dimensional capacitor in [7].
The authors of [7] claim capacitive densities of 2.18 fF?m2 while the authors of [6] claim
densities of 30 fF?m2.
In [8], yet another method of increasing capacitance is discussed. This method utilizes
deep trenches etched into the silicon to create capacitors. Locally doped substrate provides a
connection to the bottom electrode. Chemical Vapor Deposition (CVD) is used to deposit a
nitride or oxide to serve as the dielectric and finally the pores are filled in with poly-silicon to
complete the top electrode. Aluminum is used as an interconnect for the capacitor. Figure
1.3 shows a detailed drawing of the high density trench capacitors. The authors have found
5
Figure 1.2: VPP capacitor layout diagram.
that using trenches to make high density capacitors can yield densities of ? 25 fF?m2. Not
only do the trenches serve to increase the surface area, but the paper also suggests using a
separate die to include the passives for a circuit. Vias are etched through the passive die to
form the interconnects. Figure 1.4 shows a detailed drawing of the proposed configuration.
The separate die integration platform alleviates some of the physical size restraints that are
put on passive components.
With capacitive densities of 2.18 fF?m2, 25 fF?m2, and 30 fF?m2 the resistance needed for
an RC time constant of 1mS would be decreased significantly and thus the area would
also. Equation (1.6) gives the area needed for passive resistors with capacitive densities
of 2.18 fF?m2, 25 fF?m2, and 30 fF?m2 respectfully. Unfortunately, with complex techniques for
constructing these three dimensional structures the cost of processing increases, which may
make these methods impractical.
6
Figure 1.3: High Density Trench Capacitor
Resistor Area = 12pi ?1000?2.18e?12 ? 1?m
2
1000? ? 73000?m
2
Resistor Area = 12pi ?1000?25e?12 ? 1?m
2
1000? ? 6400?m
2 (1.6)
Resistor Area = 12pi ?1000?30e?12 ? 1?m
2
1000? ? 5300?m
2
1.1.2 Increasing the Permativity of the Dielectric
Increasing capacitance, by means of a higher permativity dielectric, is as easy as using a
different material between the electrodes. This method of increasing capacitance is discussed
in [9], [20], and [14]. The authors in [9] suggest that using Hafnium Oxide (HfOx) or
Tantalum Oxide (TaOx) capacitor densities of 5 fF?m2 can be achieved. While the authors of
7
Figure 1.4: Separate Die Integration Platform
[20] suggest that by using Aluminum Oxide (Al2O3) as a dielectric the capacitive density
can be increased to ? 10 fF?m2. However, the most impressive is in [14], where the authors
claim that they have developed a capacitor film deposited on a silicon substrate that has
a dielectric constant of 1000 which is roughly 250 times higher than SiO2 and would yield
a density of ? 250 fF?m2. As impressive as these numbers seem, the fact is that they do not
make up for the orders of magnitude that must be overcome in order to have an achievable
on-chip passive resistor. With capacitive densities of 5 fF?m2, 10 fF?m2, and 250 fF?m2 this method
can also achieve a significant reduction in resistance needed for a 1mS RC time constant.
Equation (1.7) gives the area needed for a passive resistor with 1000 ??m2. The special
techniques for achieving these densities may not be cost effective enough for use in a low
cost application.
Resistor Area = 12pi ?1000?5e?12 ? 1?m
2
1000? ? 32000?m
2
Resistor Area = 12pi ?1000?10e?12 ? 1?m
2
1000? ? 16000?m
2 (1.7)
8
Resistor Area = 12pi ?1000?250e?12 ? 1?m
2
1000? ? 636?m
2
1.1.3 Decreasing the Distance Between the Electrodes
In an attempt to increase capacitive density by decreasing the thickness of the dielectric,
undesirable traits form in the capacitors. As the dielectric becomes thinner, the leakage
current of the capacitor increases largely, because of direct tunneling through the dielectric
[9]. This increase of leakage current no longer meets the requirement for the voltage levels
that will be used and thus other solutions to the problem must be found.
1.2 Active Resistors
Although significant strides have been made in increasing capacitive densities, these
are still not large enough to offset the need for very large value resistors. Since traditional
poly-silicon and diffused resistors can not meet the performance needs, different techniques
have been used to synthetically produce active devices that fulfill the need of a large value
resistor. These active resistors yield many advantages over traditional resistors. First,
although they do introduce noise into the system, it is not caused directly by the value of
resistance that they represent. Second, they take up much less silicon area versus regular
resistors. Finally, they are not a fixed resistance value, so they can be tuned to compensate
for variations in capacitance values in the circuit.
The simplest of these active resistors used for tuning and consists of using a MOS
transistorinparallelwitharegularpoly-siliconresistor. This allowstheparallelcombination
of the resistors to be varied based on the value of the resistance of the transistor. However,
9
this will only allow for a resistance value from 400??1600? which is quite small but shows
how easily it is to implement a tunable resistor [10]. There are several different approaches
to making an active resistor. In [12], a highly linear CMOS floating gate resistor is proposed.
This active resistor is a single MOS transistor with programming circuitry around it. It
utilizes a voltage feedback to the well in order to overcome the nonlinear nature MOS
transistor. This provides tunable resistance values from ? 1400k??660k?.
Another approach of creating high value controlled floating resistors is to use two
current controlled conveyors. The current is transferred from port X to port Z in the
current conveyor. The system uses two current conveyors coupled together with current
divider circuits in order to create the proper resistance. The authors suggest that an active
resistor with this configuration can create resistances from 93??60k? with a bandwidth of
100MHz [17]. Although these examples do drastically increase resistance values, the ability
to make active resistors with values on the order of megaohms to overcome the limitations
of on-chip capacitors, is still not achievable by these methods.
Described in this thesis is a linear active CMOS resistor, proposed by Dr. Bogdan
M. Wilamowski, for use in a control system for a MEMS gyroscope. The Active CMOS
Resistor(ACR) can achieve values up to 600M? with a bandwidth over 100KHz. The
ACR uses ?2.5V supply rails and has an input voltage swing of ?1.5V and an output
voltage swing of ?2V. It can serve as a drop in replacement for a passive resistor in most
applications as long as the input and output voltage and bandwidth of the system are within
its range.
10
Chapter 2
Design and Simulation of Active CMOS Resistor(ACR)
2.1 Design of CMOS Resistor
The described ACR is implemented using the AMIS C5 process. Being that this is a
5V process, and the desired use for the resistor is in a PID controller working with positive
and negative error voltages the resistor uses ?2.5V supply rails for operation. The input
voltage swing is ?1.5V and the output voltage swing is ?2V.
The ACR can be viewed as two separate yet interrelated parts, the input amplifier
stage and output stage. The input amplifier stage feeds the output stage while utilizing the
output for feedback to remain balanced. Figure 2.1 is a schematic of the ACR showing the
relationship between the input and output stages. The small signal model for the ACR is
given in Figure 2.2.
2.1.1 Input Stage
The input stage is a five transistor differential amplifier. There is a simple long tailed
differential pair with a NMOS current mirror providing bias current and a PMOS current
mirror serving as the load. For ease of calculations the source voltage of the differential pair
transistors, M1 and M2, is assumed to be constant, as well as the drain current of the bias
current mirror transistor ID12, IS1.
The purpose of the input amplifier stage is to translate the input voltage to the output
stage in order to adjust the output current by using feedback from the output stage. It
11
+ -
V31
-2.5
+ -
V2
2.5 + -
V4
-1
+ -
V3
1
+ -
VInp
ut
M7
CMO
SP
M3CMOSP
M5
CMO
SP
CMO
SN
M9
CMO
SN
M1
CMO
SN
M2
CMO
SP M4
M6
CMO
SP CMOS
N
M8
+ -
0V
V1
+ -
idc 5u
Is2
+ -
idc
Is1
10u
vdd
v 1 v2
vdd
vdd
vss
v s s
v s s
v s s
v2
v1
vdd
vdd
vdd
v s s
v s s
E
In
B
D
C
outp
ut
G
F
Figure 2.1: Schematic of ACR
12
Figure 2.2: Small Signal Model for ACR
takes the difference between the input and feedback voltages, and applies gain. The gain of
the input stage is found using equation (2.1).
A = gm1(ro1||ro3) = ?f11+ ro1
ro3
?= ?f1
2 (2.1)
Where,
?f1
2 =
gm1 ?ro1
2 (2.2)
gm1 = 2ID1V
GS ?VTN
?=radicalbig2KnID (2.3)
13
ro1 = 1+?VDS?I
D
?= 1
?ID (2.4)
The voltage change of the output of the amplifier stage, node C, can be written as
?VC = ?(VInput ?VB)?A
= ?(VInput ?VB)?
?2K
nID1
2?ID1
= ?(VInput ?VB)?
?K
n
??2ID1 (2.5)
= ?(VInput ?VB)?
?K
n
??IS1
2.1.2 Output Stage
The output current is controlled by the difference between the voltage on node B and
the voltage on the output node. When node B is lower than the output node the VDS of M8
is larger than the VDS for M9, so the drain current of M8 is larger than the drain current
for M9. Also, the VDS of M7 is larger than the VDS for M6, so the drain current of M7 is
larger than the drain current for M6. If ID8 > ID7 > ID6, then IOutput will be negative.
Likewise, when node B is greater than the output node the VDS of M8 is smaller than the
VDS for M9, so the drain current of M8 is smaller than the drain current for M9. Also, the
VDS of M7 is smaller than the VDS of M6, so the drain current of M7 is smaller than the
drain current for M6. If ID8 < ID7 < ID6, then IOutput will be positive.
The output stage contains six transistors. The top PMOS, M5, translates the difference
between the input and feedback voltages in to a current that keeps the input amplifier stage
in balance. Since M5 has to source twice the current as the others in this stage, it has a
14
width to length ratio that is twice that of the other transistors in order to accommodate the
extra current. The biasing current is provided by a NMOS current mirror, M10. For ease
of calculations the source voltage of the source of M8 and M9 will be considered constant,
as well as, the bias current ID10, IS2.
The output current is the difference between ID5 and IS2.
IOutput = IS2 ?ID5 (2.6)
The change in the drain current of M5, ?ID5, can be written as
?ID5 = ?VC ?gm5 (2.7)
where,
gm5 =radicalbig2KpID (2.8)
Substituting equations (2.5) and (2.8) into equation (2.7) and making IS1 = 2?IS2 yields
? = ?ID5 = ?(VInput ?VB)
?K
n
??IS1 ?
radicalbig2K
pID
= ?(VInput ?VB)
?2K
1K5IS2
??IS1 (2.9)
= ?(VInput ?VB)
?K
1K5
?
15
Equation (2.9) is not dependent on the bias current, IS2, so it is considered a constant. The
drain current of M5 can also be thought of as
ID5 = IS2 +?IS2 (2.10)
where ?IS2 is the output current and ? is defined as equation (2.9). The equivalent resis-
tance of the ACR can be written as
R = VInput ?VOutputI
Output
(2.11)
Setting VInput ?VOutput equal to one and substituting for IOutput yields
R = 1?I
S2
(2.12)
Equation (2.12) shows that the resistance value is inversely proportional to the tuning
current IS2. With this current, the resistance can be tuned to achieve the value that is
desired.
2.2 DC Analysis
A DC analysis was performed on the ACR to determine the maximum input and
output voltage swings and to determine resistance value for any given tuning current. The
DC analysis was performed using ?2.5V supply rails, the input voltage was fixed at zero
volts with an voltage source, and the current through the output voltage source was plotted.
16
Figure 2.3 shows the output current as the output voltage is swept from ?500mV and
the tuning current is stepped from 1?A to 5?A in steps of 1?A. As shown in Figure 2.3,
the output current is positive when the input voltage is higher than the output voltage and
negative when it is lower than the output voltage, passing through zero amperes when the
input and output voltages are equal.
Figure 2.3: Output Current vs Output Voltage
Figure 2.4 shows a plot of R = VInput?VOutputIOutput . The plot shows the resistance value as a
function of voltage difference and tuning current. The resistance is flat across the range.
The most important information can be gathered from a plot of resistance versus the
tuning current. A sweep of the tuning current shows how the resistance changes with tuning
current directly. The input voltage was set at a constant 250mV, while the output voltage
was set at a constant?250mV. With these two voltages fixed, the tuning current of the ACR
was swept from 10nA to 10?A. The same calculation R = VInput?VOutputIOutput was performed and
17
Figure 2.4: Resistance vs Output Voltage
plotted. The a curve was fit to the data from Figure 2.5 in order to find an equation that
describes the relationship between the tuning current and the resistance. Equation (2.13)
can be used in order to find the proper tuning current for a chosen resistance.
R = 25.774(I
S2)0.909
(2.13)
IS2 =
parenleftBigg
25.774
R
parenrightBigg( 1
0.909)
The curve fit equation (2.13) shows that the resistance is inversely proportional to the
tuning current and fairly linear through the range.
18
Figure 2.5: Resistance vs Tuning current
2.3 AC Analysis
The AC analysis will show the frequency response of the ACR and show the operational
bandwidth. An AC voltage source, swept from 10Hz to 10MHz, drives the input of the
circuit while the output voltage is kept at zero volts. The tuning current is stepped from
50nA to 3.2?A doubling with each step. The current through the output voltage source is
plotted versus the frequency of the input signal. Figure 2.6 shows how tuning current effects
the bandwidth of the circuit. As the frequency increases so does the output current, which
effectively lowers the resistance of the circuit. The bandwidth of the circuit is 200KHz
with a tuning current of 50nA and 10MHz with a tuning current of 3.2?A. The phase of
the output current is plotted in Figure 2.7. In the operational bandwidth of the ACR the
19
phase is 0?. The resistance versus frequency is plotted in Figure 2.8. It is clear that the
bandwidth of the resistor is a function of tuning current.
Figure 2.6: Output Current vs Input Voltage Frequency
2.4 Transient Analysis
A transient analysis was performed on the circuit to determine its real time response
to an input. For the simulation, a sinusoidal voltage source was used to drive the input of
the circuit. This sinusoidal signal was run at a frequency well below that of the bandwidth
of the ACR, 3KHz. The output of the circuit is held at zero volts and the output current
through the output voltage source is plotted. The tuning current was stepped from 50nA
and 3.2?A doubling with each step. Figure 2.9 how shows the current follows the sinusoidal
input. Figure 2.10 shows the resistance of the circuit versus the sinusoidal input voltage.
20
Figure 2.7: Phase of Output Current vs Input Voltage Frequency
Figure 2.8: Resistance vs Input Frequency
21
As with the other simulations, the equivalent resistance increased as the tuning current
decreased.
Figure 2.9: Output Current with Sinusoidal Input Voltage
2.5 Noise Analysis
Because of its unpredictable nature, noise is a main contributor to the inaccuracy of a
sensor. The main source of noise in a MOSFET is thermal noise due to thermal agitation of
electrons in the resistive channel [21]. Equation (2.14) gives the current noise of a MOSFET
where k = 1.38e?23, T = 300, and gm is the transconductance of the transistor.
i2 = 83 ?k ?T ?gm A
2
Hz (2.14)
22
Figure 2.10: Resistance vs Sinusoidal Input Voltage
In order to obtain the voltage noise, V 2, equation (2.14) is multiplied by the output
resistance of the transistor, ro.
V 2 = 83 ?k ?T ?gm ?r2o V
2
Hz (2.15)
Equation (2.15) clearly shows the relationship between the voltage noise of a MOSFET
and its output resistance. The output resistance is proportional to the drain current of the
transistor, therefore, the noise is proportional to the tuning current of the ACR.
A noise analysis was performed on the ACR in SPICE. In order to obtain the voltage
noise, the ACR is connected to a grounded passive resistor of equal value. The noise
contribution of the passive resistor will be subtracted off the noise voltage to yield that
23
which is contributed by the ACR. Table 2.1 gives the noise contributions of each transistor
to the total output voltage noise. At 167.778M? the total output noise for the ACR is
13.8 ?V?Hz. The main contributors to the total output noise are the four output transistors
M6, M7, M8, and M9, due to the fact that any fluctuation of their output current will
directly affect the output current and output voltage.
The square root of equation (2.15) must be taken in order to compare the noise result of
the simulation to the noise calculation of equation (2.16). Comparing the simulation results
for the thermal noise of an ACR tuned to 167.778M?, 13.8 ?V?Hz, and a passive resistor with
a value of 167.778M?, 1.667 ?V?Hz, the ACR has approximately and a factor of 8 greater
noise.
Vt =
?
4?k ?T ?R =
?
4?1.38?10?23 ?300?167.778?106 = 1.667?V?Hz (2.16)
M1 M2 M3 M4 M5 M6
ID 5.773E-16 5.658E-16 4.987E-16 4.744E-16 5.964E-19 4.372E-11
M7 M8 M9 M10 M11 M12
ID 4.373E-11 5.147E-11 5.146E-11 1.437E-19 1.519E-18 6.497E-20
Total 1.904E-10 V 2Hz
Total 13.8 ?V?Hz
Table 2.1: Noise Sources of ACR
24
Chapter 3
Resistor Substitution
The beauty behind the ACR circuit is its simplicity and the way it can replace a
passive resistor in complex applications. Because the output node is allowed to float to the
necessary voltage, the circuit performs just as a high value resistor would as it interacts
with other passive components. All the previous simulations were performed with specified
output and input voltages. However, to truly gage whether the circuit will perform like
a passive resistor, the circuit must be put in actual applications that allow the output to
drive something other than an ideal voltage source.
3.1 Single Pole Filter
The simplest application for the resistor circuit is a single pole low-pass or high-pass
filter. These filters involve one resistor either driving or being driven by a capacitor. As
stated before the main challenge with using on-chip capacitors for filtering functions is their
inherently low values. A capacitor with just one picofarad of capacitance has a significant
footprint and is as large as the proposed ACR itself. The maximum on-chip capacitance
that will be used in any of these applications will be approximately one picofarad.
3.1.1 Low-Pass Filter
Figure 3.1 shows the configuration of a simple one pole RC low-pass filter. The input
of the ACR is driven by a sinusoidal voltage source while the output node of the ACR serves
25
as the output of the filter. A one picofarad grounded capacitor is connected to the output
node to form the filter. The transfer function for this single pole low-pass filter is
H(s) = 1sRC +1 (3.1)
with the pole located at
fc = 12piRC (3.2)
The frequency response of the low-pass filter can seen in Figures 3.2 and 3.3. The tuning
current is stepped from 50nA to 3.2?A doubling with each step. The plot of the magnitude
starts at 0dB and continues flat until reaching the pole of the filter where it decreases with
a slop of ?20dB per decade, while the phase starts at 0? in the passband and turns down
toward ?90? beyond the pole. It is clearly shown in the plots that as the tuning current
of the ACR is increased the resistance is decreased, thereby increasing the frequency of the
filter?s pole. The plots also show that the filter behaves just as a passive resistor low-pass
filter would, which demonstrates the ease at which a tunable single pole low-pass filter can
be implemented on chip. Because there is very little offset, this configuration can easily be
daisy chained in order to form higher order low-pass filters.
From Figure 3.2, the pole of the low-pass can be found. For the middle trace, corre-
sponding to a tuning current of 400nA, the pole of the low-pass filter, read from the plot,
26
+ -
V31
-2.5
+ -
V2
2.5 + -
V4
-1
+ -
V3
1
CMO
SN
M1
CMO
SN
M2
CMO
SP M4
CMO
SNM11
M3CMOSP CMOSN
M12
M7
CMO
SP
+ -
{Ipro
}
idc
Tun
e
CMO
SN
M9
CMO
SNM10M5
CMO
SP M6
CMO
SP CMOS
N
M8
+ -
Inpu
t
C26
1p
vdd
v 1 v2
vdd
vdd
vss
v s s
v s s
v s s
v2
v1
vdd
v s s
vss
vdd
v s s
vdd
vdd
D
G
C
Inpu
t
B
E
F
Outp
ut
Figure 3.1: Single Pole Low-Pass Filter Configuration
27
is located at 9723Hz. Substituting 9723Hz for the cutoff frequency and one picofarad for
C in equation 3.2 and solving for R yields equation (3.3).
R = 12?pi ?9723?1e?12 = 16,368,913.2? (3.3)
Figure 3.2: Low-Pass Filter Output Magnitude vs Frequency
To see how well the circuit will perform with an actual sinusoidal signal, a transient
analysis was performed on the circuit in the low-pass filter configuration. The input is driven
by a sine wave voltage source at the frequency that is the ?3dB point of the filter with a
tuning current of 400nA, 9723Hz, to see if the filter will perform as it should, attenuating
and phase shifting the signal more as the tuning current is decreased. The tuning current
is stepped through the same range, 50nA to 3.2?A doubling with each step. Figure 3.4 is a
28
Figure 3.3: Low-Pass Filter Output Phase vs Frequency
plot of the output voltage of the filter with an input frequency of 9723Hz and magnitude
of 1V. Clearly from the plot it can be seen that the filter is functioning properly. If a closer
look is taken at the filter tuned with its fc = 9723Hz, Figure 3.5, the output is 70.7% of
the input and is phase shifted 45? with a very small DC offset. These output results are
very similar to a passive resistor filter with the same resistance value.
The total harmonic distortion is defined as the
THD =
radicalbigsummationtext?
n=2 V 2n
V1 (3.4)
29
Figure 3.4: Low-Pass Filter Transient with Stepped Tuning Current
Figure 3.5: Low-Pass Filter With 9723 Hz Input Signal
30
Harmonic Frequency Fourier Normalized Phase Normalized
NO (Hz) Component Component (deg) Phase (deg)
1 9.72E3 2.48E-1 1.000 -7.71E1 0.00
2 1.95E4 1.59E-5 6.41E-5 -4.53E1 1.09E2
3 2.92E4 3.55E-5 1.43E-4 3.12E+1 2.63E2
4 3.89E4 1.38E-5 5.56E-5 -8.80E1 2.21E2
5 4.86E4 1.21E-5 4.89E-5 -1.38E2 2.48E2
Table 3.1: Total Harmonic Distortion Low-Pass Filter
3.1.2 High-Pass Filter
The other single pole filter that can be designed using this ACR is a single pole high-
pass filter. Figure 3.6 shows the configuration of the single pole RC high-pass filter. The
input of the ACR is grounded while the output is connected to a one picofarad capacitor.
A sinusoidal voltage source drives the capacitor and the output of the ACR is the output
of the filter. The transfer function of the filter is given in equation (3.5).
H(s) = sRCsRC +1 (3.5)
The pole of the filter is located at
fc = 12piRC (3.6)
The frequency response of the high-pass filter is shown in Figures 3.7 and 3.8, as with
the low-pass filter, the tuning current was stepped from 50nA to 3.2?A doubling with each
step. The plot of the magnitude increases with a slop of 20dB per decade until reaching
31
+ -
V31
-2.5
+ -
V2
2.5 + -
V4
-1
+ -
V3
1
CMO
SN
M1
CMO
SN
M2
CMO
SP M4
CMO
SNM11
M3CMOSP CMOSN
M12
M7
CMO
SP
+ -
{Ipro
}
idc
Tun
e
CMO
SN
M9
CMO
SNM10M5
CMO
SP M6
CMO
SP CMOS
N
M8
+ -
Inpu
t
C26
1p
vdd
v 1 v2
vdd
vdd
vss
v s s
v s s
v s s
v2
v1
vdd
v s s
vss
vdd
v s s
vdd
vdd
D
G
C
B
E
F
Outp
ut
Figure 3.6: Single Pole High-Pass Filter Configuration
32
the pole of the filter and turning over to be flat, while the phase starts at 90? and goes
down to 0? in the pass band of the filter. Figure 3.7 also clearly shows the pole of the filter
moving toward dc as the tuning current decreases. The fc of the high-pass filter with a
tuning current of 400nA is 9723Hz, and the phase at that point is 45?.
Figure 3.7: High-pass Filter Output Magnitude vs Frequency
Good performance in the time domain is the main objective, thus a transient analysis is
performed to determine the performance of the filter with sinusoidal a sinusoidal input. The
sinusoidal input voltage source drives the capacitor with a 1V sine wave at the ?3dB point
of the filter which has a 400nA tuning current, 9723Hz. Figure 3.9 shows the sinusoidal
output of the filter as the tuning current is stepped from 50nA to 3.2?A doubling with each
step. With each step it is clear there is more attenuation of the signal, as well as, a much
larger phase shift.
33
Figure 3.8: High-pass Filter Output Phase vs Frequency
Figure 3.9: High-Pass Filter Transient with Stepped Tuning Current
34
To show in more detail the operation of the filter, the tuning current is set to 400nA.
The output voltage is shown in Figure 3.10. The output amplitude is only 70.7% of the input
and phase shifted by 45? with a small dc offset. Just as it was predicted in the frequency
plot, the time domain simulation of the circuit indicates that the ACR filter circuit performs
similarly to a passive resistor filter circuit. As long as the input and output voltage ranges
and frequencies are within the operating range of the ACR, it can replace a passive resistor
and have still have a very similar performance.
Figure 3.10: High-Pass Filter Transient
3.2 PID
The intended use for the ACR is in an analog control ASIC. The control ASIC contains
a traditional Proportional-Integral-Derivative (PID) controller. The ACR is a great solution
35
Harmonic Frequency Fourier Normalized Phase Normalized
NO (Hz) Component Component (deg) Phase (deg)
1 1.00E5 2E-1 1.00 -1.46E2 0.00
2 2.00E5 1.25E-3 6.25E-3 -8.29E1 2.08E2
3 3.00E5 1.01E-3 5.03E-3 -8.41E1 3.53E2
4 4.00E5 9.74E-4 4.87E-3 -8.63E1 4.96E2
5 5.00E5 9.29E-4 4.65E-3 -8.84E1 6.39E2
Table 3.2: Total Harmonic Distortion high-pass Filter
for this application, not only does it provide the high resistance needed for the desired RC
time constant, it also allows the controller gains to be adjusted to meet the demands of the
system. The error, Verr, is the input to all stages. A folded cascode amplifier was used in
conjunction with the ACR in all the stages of the PID controller. The power supply rails
of the op amp are the same as the ACR, ?2.5V.
3.2.1 Proportional Stage
The proportional stage is an inverting gain stage utilizing two resistors and an oper-
ational amplifier. More than having a large value, the main attraction of using the ACR
in this application is its adjustability. An ACR with a fixed value is included as the in-
put resistor, while another ACR with variable resistance is used as the feedback resistor
so the gain of the stage can be adjusted. The mathematical operation performed by the
proportional stage is given by equation (3.7).
VP = KP ?Verr (3.7)
36
The gain of the proportional stage is like that of any inverting gain stage given by
equation (3.8).
VP = ?RfR
i
?Verr (3.8)
Figure 3.11 shows the proportional stage of the controller. To see how the gain responds
to input voltage frequency and tuning current of the feedback resistor, an AC simulation
was performed. The feedback resistor tuning current was stepped from 50nA to 3.2?A,
doubling with each step, while the tuning current of the input resistor was held constant at
3.2?A. Figure 3.12 shows the magnitude of the output voltage as the frequency of the input
voltage was swept from 10Hz to 100MHz. The magnitude stays the same across frequencies
until the frequency limitations of the resistor are met. The plot shows the circuit working
properly with the gain increasing as the tuning current of the feedback resistor is decreased.
Figure 3.13 shows how the phase of the output is affected by the frequency of the input
voltage and the tuning current of the feedback resistor. The phase starts at 180? because
of the inverting configuration of the op amp, while at higher frequencies the internal poles
and zeros of the ACR and op amp change the phase.
The simulations have shown the ACR can replace a passive resistor in an inverting gain
stage in order to increase the flexibility of the circuit by allowing the gains to be changed
with an adjustment to the tuning current of the feedback resistor.
37
Figure 3.11: Proportional Stage of Controller
Figure 3.12: Proportional Stage Output Magnitude vs Input Voltage Frequency
38
Figure 3.13: Proportional Stage Output Phase vs Input Voltage Frequency
3.2.2 Integral Stage
The integral stage uses a resistor connected between the input and inverting terminal of
the op-amp and a feedback capacitor connected between the output and inverting terminal
of the op-amp. Due to the feedback capacitor?s small capacitance, 1pF, the input resistor
must have a large value to obtain the desired RC time constant. The main attraction the
ACR has is its high resistance. The integral stage is arranged as shown in Figure 3.14.
The integral stage performs the following mathematical operation.
VI = KI ?
integraldisplay ?
0
Verr ?d? (3.9)
39
Figure 3.14: Integral Stage of Controller
The transfer function for the integrator is given in equation (3.10).
H(s) = ?1sCR (3.10)
An AC simulation was performed on the integrator circuit to determine its performance
and judge whether it is a suitable integrator. The input voltage frequency was swept from
10Hz to 100MHz while the tuning current was stepped from 50nA to 3.2?A, doubling
with each step. From the transfer function, equation (3.10), at very low frequencies the
gain should be nearly infinite, however, as can be seen in Figure 3.15, the output is limited
by the open loop gain of the op-amp. The magnitude plot has a slope of ?20dB per decade.
It can be seen that with each step of the tuning current the gain and frequency response
of the integrator changes. Along with the magnitude plot, the phase plot, Figure 3.16, of
the output voltage starts at 180?, because of the inverting configuration of the integrator,
40
and moves toward 90? at the frequencies that the circuit integrates. The integrator circuit,
with a CMOS input resistor, behaves in much the same way as an integrator circuit with
a passive input resistor. Not only can the ACR provide the high resistance needed, but it
also affords the designer the flexibility of adjusting the integrator to perform the way that
is optimal.
Figure 3.15: Integral Stage Output Magnitude vs Input Voltage Frequency
3.2.3 Differential Stage
The configuration of the differential stage, shown in Figure 3.17, is an inverting op amp
with a input capacitor and a feedback resistor. As with the integrator, the input capacitor
has a very small capacitance. To combat this the feedback resistor must be very large,
which makes the ACR ideal for this application as well. The differential stage performs the
mathematical operation in equation (3.11).
41
Figure 3.16: Integral Stage Output Phase vs Frequency
VD = KD ? dVerrd? (3.11)
The transfer function for the differential stage is give in equation (3.12).
H(s) = ?sCR (3.12)
To maintain stability in the differentiator, the high frequency gain of the circuit must be
limited. To do this, a capacitor with the same value as the input capacitor, is placed in
parallel with the feedback resistor, to provide a high frequency pole. The transfer function
of the new circuit is given in equation (3.13).
42
H(s) = ?sCRsCR +1 (3.13)
The differential stage frequency response plot, Figure 3.18, shows how feedback resistor
tuning current changes affect the response of the circuit. The output voltage magnitude
increases at 20dB per decade until it reaches the pole of the circuit, caused by the parallel
combination of the feedback R and C. As the tuning current of the feedback resistor is
decreased the pole of the differentiator decreases in frequency. The phase plot of the output
voltage, Figure 3.19, shows that in the frequencies of differentiation the phase of the output
is ?90? and drops to ?180? when reaching the pole. Both plots also show how the frequency
response changes with changes to the tuning current of the feedback resistor. The pole of
the RC parallel combination changes as well as the gain of the circuit. The plots show that
the ACR behaves in the same manner as a passive resistor would in the differentiator with
the advantage of high resistance values and tuning capability.
43
Figure 3.17: Derivative Stage of Controller
Figure 3.18: Differential Stage Output Magnitude vs Input Voltage Frequency
44
Figure 3.19: Differential Stage Output Phase vs Input Voltage Frequency
45
Chapter 4
Conclusion
Described in this thesis are the limitations of on-chip passive components in integrated
circuits due to their inherent flaws. Many solutions have been attempted to try and over-
come these limitations with limited success. A linear active CMOS resistor using the AMIS
C5 process has been described that meets the limitations of on-chip capacitors by means of
a very high synthesized resistance. It has been shown through simulation that as long as
the bandwidth and input and output voltage levels are within range the CMOS resistor is
a drop in replacement for a passive resistor in many applications. It performs well in single
pole filters as well as more complex circuits such as a PID controller. Not only does the
circuit provide very high resistance values, but it also yields flexibility through its ability
to be tuned to a wide range of resistance values.
The CMOS resistor runs off of ?2.5V supply voltage rails, to meet the requirements
of the technology. The input voltage swing is ?1.5V and the output voltage swing is ?2V.
The bandwidth is more than 100KHz for the highest resistance value. These are more than
adequate for the given application of a PID controller.
The CMOS resistor can be scaled with technology. It has very low quiescent power,
on the order of microwatts. The signal voltage swing limitations can be addressed with
higher voltage rails. The CMOS resistor introduces more noise into the system than a
passive component of the same value, however, since device size makes passive components
impractical and the difference in noise is not that great, about a factor of 8 difference, the
CMOS resistor still provides an good alternative.
46
Bibliography
[1] J.D. Adam, Analog signal processing with microwave magnetics Proceedings of the
IEEE Volume 76, Issue 2, Feb. 1988 Page(s):159 - 170
[2] MOSIS Integrated Circuit Fabrication Service, www.mosis.com
[3] , R. Brederlow, W. Weber, C. Dahl, D. Schmitt-Landsiedel, and R. Thewes, Low-
Frequency Noise of Integrated Poly-Silicon Resistors, Electron Devices, IEEE Transac-
tions on Volume 48, Issue 6, June 2001 Page(s):1180 - 1187
[4] J.R. Pierce, Physical Sources of Noise, Proceedings of the IRE Volume 44, Issue 5,
May 1956 Page(s):601 - 608
[5] S.H. Voldman, E.G. Gebreselasie, and Z.-X. He, ESD TESTING OF ALUMINUM
AND COPPER VERTICAL PARALLEL PLATE (VPP) CAPACITOR STRUC-
TURES, Physics Symposium, 2007. Proceedings. 45th Annual. IEEE International
15-19 April 2007 Page(s):586 - 587
[6] P. Soussan, L. Goux, M. Dehan, H. Vander Meeren, G. Potoms, D.J. Wouters and E.
Beyne, Low Temperature Technology Option For Integraed High Density Capacitors,
Electronic Components and Technology Conference, 2006. Proceedings. 56th 30 May-2
June 2006 Page(s):515 - 519
[7] D. Kim, J. Kim, J.-O. Plouchart, C. Cho, R. Trzcinski, M. Kumar, and C. Norris,
Symmetric Vertical Parallel Plate Capacitors for On-Chip RF Circuits in 65-nm SOI
Technology, Electron Device Letters, IEEE Volume 28, Issue 7, July 2007 Page(s):616
- 618
[8] A. den Dekker, A. van Geelen, P. van der Wel, R. Koster, and E.C. Rodenburg, Passi4:
The next Technology for Passive Integration on Silicon, Electronic Components and
Technology Conference, 2007. ECTC ?07. Proceedings. 57th May 29 2007-June 1 2007
Page(s):968 - 973
[9] P. Majhi, W.C.M. Peters, L. van Marwijk, and M. Murphy, Integration of High-K
Dielectric Thin Films and Hetero-Structures in MIS Capacitors, Semiconductor Man-
ufacturing, 2003 IEEE International Symposium on 30 Sept.-2 Oct. 2003 Page(s):195
- 198
[10] R. Mukhopadhyay, Y. Park, P. Sen, N. Srirattana, J. Lee, C.-H. Lee, S. Muttinck, A.
Joseph, J.D. Cressler, and J. Laskar, Reconfigurable RFICs in Si-Based Technologies
for a Compact Intelligent RF Front-End, Microwave Theory and Techniques, IEEE
Transactions on Volume 53, Issue 1, Jan. 2005 Page(s):81 - 93
47
[11] S.L. Lung, S.S. Chen, C.W. Tsai, T.T. Sheng, S.C. Lia, T.B. Wu, and R. Liu, Low
Temperature PZT Ferroelectric Capacitor Process For High Density Capacitor-Over-
Interconnect(COI) FeRAM Application, Solid-State and Integrated-Circuit Technol-
ogy, 2001. Proceedings. 6th International Conference on Volume 1, 22-25 Oct. 2001
Page(s):692 - 695 vol.1
[12] E. ?Ozalevli and P. Hasler, Programmable Floating-Gate CMOS Resistors, Pro-
grammable floating-gate CMOS resistors Ozalevli, E.; Hasler, P.; Circuits and Systems,
2005. ISCAS 2005. IEEE International Symposium on 23-26 May 2005 Page(s):2168 -
2171 Vol. 3
[13] C. Popa, A. Manolescu, O. Mitre, and M. Glesner, Low-power CMOS Active Resis-
tor Independent on the Threshold VoltageElectronics, Circuits and Systems, 2002. 9th
International Conference on Volume 1, 15-18 Sept. 2002 Page(s):57 - 60 vol.1
[14] M. Ichiki and R. Maeda, High Dielectric Films Prepared By The Nanotransfer Method
Polymers and Adhesives in Microelectronics and Photonics, 2007. Polytronic 2007. 6th
International Conference on Jan. 16 2007-Yearly 18 2007 Page(s):1 - 2
[15] J.R. Maticich, Design Considerations for an Integrated Low-Noise Preampli-
fier,Proceedings of the IEEE Volume 53, Issue 6, June 1965 Page(s):605 - 614
[16] S. Bibian and H. Jin, Time Delay Compensation of Digital Control for DC Switchmode
Power Supplies Using Pridiction Techniques, Power Electronics, IEEE Transactions on
Volume 15, Issue 5, Sept. 2000 Page(s):835 - 842
[17] H. Zouaoui-Abouda, A. Fabre, New High-Value Floating Controlled Resistor in CMOS
Technology, Instrumentation and Measurement, IEEE Transactions on Volume 55, Is-
sue 3, June 2006 Page(s):1017 - 1020
[18] E.B. Liao, L.H. Guo, R. Kumar, G.Q. Lo, N. Balasubramanian, and D.L. Kwong,
High-Density MIM Capacitors (? 85nF/cm2) on Organic Substrates, Electron Device
Letters, IEEE Volume 26, Issue 12, Dec. 2005 Page(s):885 - 887
[19] , O. Roux dit Buisson and G. Morin, Flicker Noise Characterization of Polysili-
con Resistors in Submicron BICMOS Technologies, Microelectronic Test Structures,
1997. ICMTS 1997. Proceedings. IEEE International Conference on 17-20 March 1997
Page(s):49 - 51
[20] S. B. Chen, C. H. Lai, A. Chin, IEEE, J. C. Hsieh, and J. Liu, High-Density MIM Ca-
pacitors Using Al2O3 and AlTiOx Dielectrics, Electron Device Letters, IEEE Volume
23, Issue 4, April 2002 Page(s):185 - 187
[21] R.C. Jaeger, T.N. Blalock, 2004, MICROELECTRONIC CIRCUIT DESIGN, (2nd ed)
48
Appendices
49
Appendix A
Transistor Models
* DATE: Jun 14/07
* LOT: T74S WAF: 8103
* Temperature_parameters=Default
.MODEL CMOSN NMOS ( LEVEL = 7
+VERSION = 3.1 TNOM = 27 TOX = 1.43E-8
+XJ = 1.5E-7 NCH = 1.7E17 VTH0 = 0.6174975
+K1 = 0.8876598 K2 = -0.0951675 K3 = 20.9151529
+K3B = -9.6382243 W0 = 1.020585E-8 NLX = 1.08112E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.8186693 DVT1 = 0.3372827 DVT2 = -0.4471971
+U0 = 449.7033083 UA = 1E-13 UB = 1.481183E-18
+UC = -4.35408E-13 VSAT = 1.750272E5 A0 = 0.6637676
+AGS = 0.1269501 B0 = 2.281394E-6 B1 = 5E-6
+KETA = -2.932031E-3 A1 = 7.951274E-7 A2 = 0.319673
+RDSW = 1.044541E3 PRWG = 0.1113887 PRWB = 0.0124254
+WR = 1 WINT = 2.035444E-7 LINT = 9.118243E-8
+XL = 1E-7 XW = 0 DWG = -6.76768E-10
+DWB = 2.626198E-8 VOFF = -8.709001E-4 NFACTOR = 0.3274632
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 2.542626E-3 ETAB = -9.003453E-4
50
+DSUB = 0.1345826 PCLM = 2.7474125 PDIBLC1 = 0.673548
+PDIBLC2 = 3.953974E-3 PDIBLCB = 0.0676693 DROUT = 0.8884749
+PSCBE1 = 7.0944E8 PSCBE2 = 5.636482E-4 PVAG = 0
+DELTA = 0.01 RSH = 81.6 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 2.22E-10 CGSO = 2.22E-10 CGBO = 1E-9
+CJ = 4.258295E-4 PB = 0.9372076 MJ = 0.4456534
+CJSW = 3.076063E-10 PBSW = 0.8 MJSW = 0.181535
+CJSWG = 1.64E-10 PBSWG = 0.8 MJSWG = 0.181535
+CF = 0 PVTH0 = 0.0162776 PRDSW = 278.4786758
+PK2 = -0.0814166 WKETA = -7.283165E-3 LKETA = -4.020995E-3)
*
.MODEL CMOSP PMOS ( LEVEL = 7
+VERSION = 3.1 TNOM = 27 TOX = 1.43E-8
+XJ = 1.5E-7 NCH = 1.7E17 VTH0 = -0.9152268
+K1 = 0.553472 K2 = 7.871921E-3 K3 = 53.4949014
+K3B = -3.7856731 W0 = 6.738971E-6 NLX = 2.795695E-7
51
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.3395264 DVT1 = 0.267458 DVT2 = -0.0568881
+U0 = 201.3603195 UA = 2.408572E-9 UB = 1E-21
+UC = -1E-10 VSAT = 1.272242E5 A0 = 0.7748807
+AGS = 0.0598168 B0 = 6.64175E-7 B1 = 5E-6
+KETA = -4.865785E-3 A1 = 1.799339E-4 A2 = 0.4844663
+RDSW = 3E3 PRWG = -0.0304277 PRWB = -0.0443398
+WR = 1 WINT = 2.824041E-7 LINT = 1.186971E-7
+XL = 1E-7 XW = 0 DWG = -1.16725E-9
+DWB = -1.237634E-8 VOFF = -0.0735326 NFACTOR = 0.6345367
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 9.767795E-4 ETAB = -0.2
+DSUB = 1 PCLM = 2.2583753 PDIBLC1 = 0.0394748
+PDIBLC2 = 3.705722E-3 PDIBLCB = -0.0320804 DROUT = 0.212888
+PSCBE1 = 2.49175E10 PSCBE2 = 2.457905E-9 PVAG = 0
+DELTA = 0.01 RSH = 109 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
52
+CGDO = 2.89E-10 CGSO = 2.89E-10 CGBO = 1E-9
+CJ = 7.243769E-4 PB = 0.9580741 MJ = 0.4957715
+CJSW = 2.398685E-10 PBSW = 0.99 MJSW = 0.3331245
+CJSWG = 6.4E-11 PBSWG = 0.99 MJSWG = 0.3331245
+CF = 0 PVTH0 = 5.98016E-3 PRDSW = 14.8598424
+PK2 = 3.73981E-3 WKETA = 6.989253E-3 LKETA = -7.31204E-3)
*
53