FREQUENCY SYNTHESES WITH DELTA-SIGMA MODULATIONS AND THEIR APPLICATIONS FOR MIXED SIGNAL TESTING Except where reference is made to the work of others, the work described in this dissertation is my own or was done in collaboration with my advisory committee. This dissertation does not include proprietary or classified information. Dayu Yang Certificate of Approval: Richard C. Jaeger Fa Foster Dai, Chair Distinguished University Professor Associate Professor Electrical & Computer Engineering Electrical & Computer Engineering Charles E. Stroud Guofu Niu Professor Alumni Professor Electrical & Computer Engineering Electrical & Computer Engineering Stephen L. McFarland Acting Dean Graduate School FREQUENCY SYNTHESES WITH DELTA-SIGMA MODULATIONS AND THEIR APPLICATIONS FOR MIXED SIGNAL TESTING Dayu Yang A Dissertation Submitted to the Graduate Faculty of Auburn University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy Auburn, Alabama December 15, 2006 iii FREQUENCY SYNTHESES WITH DELTA-SIGMA MODULATIONS AND THEIR APPLICATIONS FOR MIXED SIGNAL TESTING Dayu Yang Permission is granted to Auburn University to make copies of this dissertation at its discretion, upon the request of individuals or institutions and at their expense. The author reserves all publication rights. Signature of Author Date of Graduation iv VITA Dayu Yang, son of Shangda Yang and Meilin Yao, was born in April 02, 1977 in Shanghai, P. R. China. He attended Shanghai Jiao Tong University in May 1995 and graduated with a Bachelor of Engineering degree in Communication Engineering in July 1999. He entered the Graduate School, Shanghai Jiao Tong University in September 1999 and received the Master of Science degree in Circuits and Systems in March 2002. Then he worked at Pericom Technology (Shanghai) Co. Ltd. as a mixed signal circuit design engineer. In January 2003, he joined Ph.D. program of the Department of Electrical and Computer Engineering, Auburn University. v DISSERTATION ABSTRACT FREQUENCY SYNTHESES WITH DELTA-SIGMA MODULATIONS AND THEIR APPLICATIONS FOR MIXED SIGNAL TESTING Dayu Yang Doctor of Philosophy, December 15, 2006 (M.S., Shanghai Jiao Tong University, 2002) (B.S., Shanghai Jiao Tong University, 1999) 129 Typed Pages Directed by Fa Foster Dai This dissertation presents design and application of two popular frequency synthesizers, namely, the direct digital frequency synthesis (DDS) and phase lock loop (PLL) synthesis. DDS is a digital technique for frequency synthesis, waveform generation, sensor excitation, and digital modulation/demodulation in modern communication systems. DDS provides many advantages including fine frequency-tuning resolution, continuous-phase switching and accurate matched quadrature signals. DDS can directly generate and modulate signal at microwave frequencies. A high-speed DDS can be significantly simplified the transceiver architecture. Thus the cost of radio and radar systems can be reduced considerably. vi High speed DDS over GHz is demanding for wireless communication systems. This research proposes work on designing a high speed DDS chip with nonlinear DAC in Silicon Germanium (SiGe) process and using DDS as test pattern generator for analog circuitry built-in self test. Nonlinear DAC is needed for high speed DDS for it replaces conventional ROM and linear DAC. The structure and system performance are analyzed with experimental data for a DDS with nonlinear DAC. Tradeoffs should be made to gain the best performance with feasible hardware implementation. Spurious components in the DDS output spectrum introduced by the phase truncation are problems and delta-sigma modulators can be used either in phase or frequency domain to suppress in-band spurs. The formula deductions of delta-sigma modulation in both phase and frequency domain are presented and various delta-sigma modulators such as MASH, feed-forward, feedback and error feedback have been implemented in both phase and frequency in a CMOS DDS chip and their performances are compared. Circuit and layout designs using SiGe technology of DDS building blocks such as current mode logic (CML), 11-bit pipe-lined accumulator, 12-bit carry look-ahead accumulator, 1-1-1 Mash type delta-sigma modulator and a nonlinear DAC are discussed. A DDS-based built-in-self-test (BIST) is presented for analogy circuit test. It uses DDS for test pattern generator (TPG) and a multiplier and accumulator as output response analyzer (ORA) and thus avoids traditional FFT-based spectrum analysis. Detail methods of frequency response and linearity test are introduced and verified by a field programmable gate array (FPGA) experimental results. vii PLL is another important frequency synthesis for its small area and power consumption. Fractional-N type PLL can have a wide loop bandwidth and fast settling time. The fractional spurs are reduced by delta-sigma modulators with new coefficients that have less out-band noise in order to suppress the modulators output bit pattern. A 2.5 GHz fractional-N PLL is designed in silicon on insulator (SOI) technology for its full dielectric device isolation, less junction capacitances, lower average device threshold voltages and less body effect and source follower effect. viii ACKNOWLEDGMENTS I would like to express my appreciation and sincere thanks to my advisor, Dr. Fa Foster Dai, who guided and encouraged me throughout my studies. His advice and research attitude have provided me with a model for my entire future career. I also wish to thank my advisory committee members, Dr. Charles E. Stroud, Dr. Richard C. Jaeger, Dr. Guofu Niu and Dr. Alvin Lim, for their guidance and advices on this work. Appreciation is also expressed to those who have made contributions to my research. I am especially indebted to Shengfang Wei, Shuying Qi, Vasanth Kakani, Xuefeng Yu, Weining Ni, Yuan Yao, Wenting Deng, Xueyang Geng and Yi Liu for their cooperation and continued assistance throughout the course of this research. Finally, I would like to thank, although this is too weak a word, my parents and family members for their continual encouragement and support throughout this work. ix Style manual or journal used: IEEE Journal on Solid State Circuits Computer software used: Microsoft Word 2003 x TABLE OF CONTENTS LIST OF TABLES???????????????????????????.xi LIST OF FIGURES??????????????????????????...xii CHAPTER 1 INTRODUCTION........................................................................................ 1 1.1 RFIC Design .......................................................................................................... 1 1.2 Frequency Syntheses.............................................................................................. 3 1.3 Dissertation Organization ...................................................................................... 5 CHAPTER 2 DIRECT DIGITAL SYNTHESIS ................................................................ 6 2.1 Introduction............................................................................................................ 6 2.2 DDS Fundamentals ................................................................................................ 6 2.2.1 Conventional ROM-based DDS .................................................................. 6 2.2.2 Quadrant Compression of ROM .................................................................. 9 2.3 DDS with Nonlinear DAC................................................................................... 11 2.4 Optimization of DDS Structure Parameters......................................................... 13 2.5 Experimental Structure Design and Results ........................................................ 16 CHAPTER 3 DELTA-SIGMA MODULATION IN DIRECT DIGITAL SYNTHESIS 18 3.1 Introduction.......................................................................................................... 18 3.2 Delta-Sigma Modulation Basics .......................................................................... 18 3.3 Linear Model of Delta-Sigma Modulator ............................................................ 20 3.4 Delta-sigma Modulation in DDS ......................................................................... 25 3.4.1 Introduction................................................................................................ 25 3.4.2 Phase Domain Modulation......................................................................... 26 3.4.3 Frequency Domain Modulation ................................................................. 29 3.4.4 Comparison of Measured NCO Output Spectra for Various Delta-sigma Modulators .......................................................................................................... 32 3.4.5 Implementation of DDS with Various Delta-sigma Modulators in 0.35?m CMOS Technology ............................................................................................. 37 3.4.6 Conclusions................................................................................................ 40 CHAPTER 4 HIGH SPEED DDS DESIGN .................................................................... 43 4.1 Introduction.......................................................................................................... 43 4.2 .SiGe BiCMOS .................................................................................................... 43 4.3 CML Digital Blocks............................................................................................. 44 4.4 Pipeline and Carry Look-Ahead Accumulators................................................... 47 4.4.1 Pipeline Accumulator................................................................................. 48 4.4.2 Carry Look-Ahead Adder .......................................................................... 50 4.5 Nonlinear DAC .................................................................................................... 53 xi 4.6 Ultra High Speed DDS with MASH Delta-sigma Modulation............................ 58 4.7 Conclusions.......................................................................................................... 63 CHAPTER 5 DDS BASED BUILT-IN SELF TEST........................................................ 64 5.1 Introduction.......................................................................................................... 64 5.2 Linearity Test Using DDS ................................................................................... 65 5.3 Implementation and Test Results......................................................................... 71 5.4 Frequency Response Test Using DDS ................................................................. 74 5.5 BIST Measurement of Frequency Response........................................................ 78 5.6 Conclusions.......................................................................................................... 79 CHAPTER 6 PHASE LOCKED LOOP FREQUENCY SYNTHESIZER...................... 80 6.1 Introduction.......................................................................................................... 80 6.2 Charge Pump PLL................................................................................................ 81 6.3 Fractional-N Frequency Synthesizer.................................................................... 84 6.4 Fractional Spurs ................................................................................................... 86 6.5 Delta-sigma Modulation in Fractional-N PLL..................................................... 88 6.5.1 Dynamic Range of Modulator.................................................................... 88 6.5.2 Multibit Quantizer...................................................................................... 89 6.5.3 NTF Optimization...................................................................................... 89 6.6 Digital Modulations in PLL and Band-Widening Techniques ............................ 92 6.7 Circuit Design of a Fractional-N PLL in SOI...................................................... 95 6.7.1 SOI Technology ......................................................................................... 95 6.7.2 SOI Devices ............................................................................................... 96 6.7.3 MOS Current Mode Logic ......................................................................... 98 6.7.4 Phase Frequency Detector.......................................................................... 99 6.7.5 Charge Pump and Loop Filter.................................................................. 101 6.7.6 Multi-Modulus Divider............................................................................ 103 6.7.9 Die Photo ................................................................................................. 106 6.8 Conclusion ......................................................................................................... 107 CHAPTER 7 CONCLUSIONS ...................................................................................... 108 BIBLIOGRAPHY........................................................................................................... 110 xii LIST OF TABLES Table 2-1 Quadrant table of a sine wave in one period .................................................... 10 Table 2-2 Flipping Operations from first quadrant to other quadrants............................. 10 Table 3-1 Performance comparison of delta-sigma modulators in frequency and phase domains of DDS. (In-band SFDR and SINAD are measured from NCO) ....................... 40 Table 4-1 Thermometer-code representation of 2-bit binary values ................................ 55 xiii LIST OF FIGURES Figure 1-1 Frequency synthesizer in a super-heterodyne receiver. .................................... 3 Figure 2-1 Conventional ROM-based DDS........................................................................ 7 Figure 2-2 Spurs and noise in output spectrum caused by phase, amplitude quantization (L=16, W=10, D=12).......................................................................................................... 9 Figure 2-3 Quadrant compression of sine ROM............................................................... 10 Figure 2-4 High-speed DDS with a nonlinear DAC......................................................... 11 Figure 2-5 First quadrant sine wave construction using nonlinear DAC cells. ................ 12 Figure 2-6 Worst case spur versus phase bit W and output bits D of nonlinear DAC. .... 14 Figure 2-7 SINAD with different DAC bits D and phase bits W (BW=0.25?fclk)............. 15 Figure 2-8 Structure design of DDS with nonlinear DAC with L=16, W=12, D=11 ....... 16 Figure 3-1 Linear model of delta-sigma modulator.......................................................... 19 Figure 3-2 MASH delta-sigma modulator with quantization noise e[n] at each stage..... 22 Figure 3-3 Autocorrelation of second order MASH type modulator?s quantization error. ........................................................................................................................................... 24 Figure 3-4 DDS with NCO and DAC............................................................................... 26 Figure 3-5 Phase domain delta-sigma modulation in DDS. ............................................. 27 Figure 3-6 Error feedback modulator in phase domain. ................................................... 28 Figure 3-7 Proposed DDS with frequency domain delta-sigma modulation.................... 30 xiv Figure 3-8 Four types delta-sigma modulators implemented in a DDS and NCO for comparison........................................................................................................................ 33 Figure 3-9 Measured in-band SINAD and SFDR of the NCO output with various delta-sigma modulators in frequency and phase domains. ............................................... 34 Figure 3-10 simulated noise transfer function of MASH and feedforward delta-sigma modulators......................................................................................................................... 35 Figure 3-11 Comparison of measured NCO output spectrum with different noise shaping effects................................................................................................................................ 36 Figure 3-12 Die photo of the CMOS DDS prototype chip with various delta-sigma modulators in frequency and phase domain...................................................................... 38 Figure 3-13 Comparison of the measured output spectra for (a) conventional DDS without delta-sigma modulation and (b) proposed DDS with frequency domain delta-sigma modulation, fo=750KHz, Fclk=30MHz. ......................................................... 39 Figure 3-14 Measured DDS output spectra (FCW=00000000,11111111)....................... 41 Figure 3-15 Measured DDS output spectra with third order MASH type delta-sigma modulation. ....................................................................................................................... 41 Figure 3-16 Measured DDS output spectra with third order feedback type delta-sigma modulation. ....................................................................................................................... 41 Figure 4-1 A four-level AND CML logic......................................................................... 44 Figure 4-2 Output resistance of emitter follower at high bias and high frequency. ......... 46 Figure 4-3 Oscillation caused by emitter followers inductive output............................... 46 Figure 4-4 A generic architecture of an N?M pipelined accumulator.............................. 48 Figure 4-5 1-bit CML full adder. ...................................................................................... 49 xv Figure 4-6 A 12-bit carry look-ahead adder using CML logics........................................ 52 Figure 4-7 Architecture of the nonlinear DAC in DDS.................................................... 54 Figure 4-8 Non-symmetry effect of sine waveform. ........................................................ 55 Figure 4-9 DAC cell matrix structure and its symmetry effect. ....................................... 56 Figure 4-10 DAC current cell circuit................................................................................ 57 Figure 4-11 Simulated DAC output waveform at 10GHz. ............................................... 58 Figure 4-12 Schematic of DDS with delta-sigma modulation.......................................... 58 Figure 4-13 Third order MASH delta-sigma modulator architecture............................... 60 Figure 4-14 Delta-sigma modulated accumulator output running at 7GHz. .................... 61 Figure 4-15 Delta-sigma modulated DDS output waveform and spectrum (Fclk=7GHz). 62 Figure 5-1 Two-tone test using DDS for linearity test. .................................................... 66 Figure 5-2 DUT output spectrum measured by FFT. ....................................................... 66 Figure 5-3 Automatic Linearity (IP3) Test using DDS. ................................................... 68 Figure 5-4 DC from the accumulator at different sampling points................................... 70 Figure 5-5 P? (30dB) measurement.................................................................................. 71 Figure 5-6 Hardware measurements of two-tone test at the DUT output......................... 72 Figure 5-7 Hardware measurements of DC1 and DC2..................................................... 73 Figure 5-8 P? measurement per 100 points and its distribution. .................................... 73 Figure 5-9 Frequency response test using DDS................................................................ 75 Figure 5-10 BIST of frequency response of an analog circuit.......................................... 76 Figure 5-11 BIST measured frequency response of a low pass filter. .............................. 78 Figure 6-1 Typical PLL frequency synthesizer. ............................................................... 80 Figure 6-2 Charge pump PLL........................................................................................... 82 xvi Figure 6-3 Fractional-N PLL frequency synthesizer. ....................................................... 84 Figure 6-4 Block diagrams illustrating the proposed 3rd order feedforward delta-sigma modulators in PLL. ........................................................................................................... 90 Figure 6-5 Simulated noise transfer function of MASH and feedforward delta-sigma modulators (k1 = 2, k2 = 1.75, k3 = 0.5). ............................................................................ 91 Figure 6-6 The PZ map of the new transfer function (Stable).......................................... 91 Figure 6-7 Simulated noise transfer function of MASH and new feedforward delta-sigma modulators (k1 = 1.75, k2 = 1, k3 = 0.25)........................................................................... 92 Figure 6-8 Modulation frequency up-conversion using mixer. ........................................ 92 Figure 6-9 Modulation frequency up-conversion using direct modulation of VCO. ....... 93 Figure 6-10 Modulation frequency up-conversion using indirect modulation of VCO. .. 94 Figure 6-11 Cross-section of SOI NMOS......................................................................... 96 Figure 6-12 MOS Current Mode Logic. ........................................................................... 98 Figure 6-13 PFD and its D flip-flop implementation...................................................... 100 Figure 6-14 PFD simulation results. ............................................................................... 100 Figure 6-15 Charge pump schematic. ............................................................................. 101 Figure 6-16 Charge pump simulation results.................................................................. 102 Figure 6-17 Divider by 2 or 3 cell. ................................................................................. 103 Figure 6-18 Simulation result of Divider by 2 or 3 cell.................................................. 104 Figure 6-19 Multi-modulus divider. ............................................................................... 105 Figure 6-20 MMD simulation result............................................................................... 106 Figure 6-21 Die photo of the PLL in SOI....................................................................... 106 1 CHAPTER 1 INTRODUCTION 1.1 RFIC Design Radio frequency integrated circuit (RFIC) design becomes challenging with the growing demand of wireless and communication market. The competence resides in high performance, high compatibility [1], lower cost and low power dissipation. In addition, high levels of integration, which may include all of the analog and digital functions related to transceiver and built-in self-test (BIST) are the design goals to achieve better performance. The thesis presents research work on one of the building blocks of RFIC-- frequency synthesizer design and its application for analog circuit build-in-self-test (BIST). Device technology plays an important role in RF IC design. Bipolar device takes its advantages in high speed, high trans-conductance (gm), low noise of its npn transistor, but it has a slow pnp transistor and high power consumption [2]. CMOS technology is gaining its popularity in RF circuits [3][4]. It?s preferred for low quiescent power dissipation, complementary transistors, low cost and easy scaling. Its disadvantage is its low speed and large noise, the limited set of available passive devices. The modeling for the CMOS technology is mainly optimized for digital design and it needs accurate model for RF design [5]. Bipolar complementary metal-oxide-semiconductor (BiCMOS) technology can provide high integration capability of both digital and analog circuitry as well as high performance 2 levels. BiCMOS IC technology is viewed as a good candidate for implementing the relatively complex digital functions because the high current-drive capability of the bipolar transistors greatly facilitates driving large capacitive loads. The hetero-junction bipolar transistor uses two different materials such as Si and Ge to form a pn junction inside the transistor to reach higher unity gain-bandwidth product (fT), low noise, good linearity and low power consumption compared to BJT. Mature SiGe technology [6] that has many generations provides a full device suite for RF IC design, including a trench isolated, highly planar SiGe hetero-junction bipolar transistor (HBT), n-MOS and p-MOS devices, poly-silicon and diffused resistors, high-density MOS and high quality-factor metal-insulator-metal (MIM) capacitors, varactor diodes, and spiral inductors. It makes it possible to achieve full mixed-signal design and high levels of integration in RF IC design. Silicon-On-Insulator (SOI) CMOS circuits differentiate from conventional bulk CMOS for its device is built on a thin silicon layer placed upon an insulator. Circuits fabricated in a SOI process can operate with higher speed and lower power consumption than circuits fabricated with bulk CMOS because the reduced parasitic capacitances intrinsic to the device structure is isolated from the substrate. The buried insulator layer allows the use of a high resistance substrate, which significantly reduces the device capacitance and the loss of passive components, such as inductors, that are commonly used in analog and RF circuits. Thus, SOI provides an advantage over bulk MOS to realize complete systems on a chip by integrating high speed digital devices with high performance analog and RF devices. 3 1.2 Frequency Syntheses Figure 1-1 Frequency synthesizer in a super-heterodyne receiver. In a RF transceiver, a frequency synthesizer is needed to generate the local oscillation (LO) frequency to mix with the received RF signal and down-convert it to IF and base band. A typical super-heterodyne receiver is shown in Figure 1-1, two frequency synthesizers are used to provide different local oscillation signals. Quadrant signals from the IF synthesizer are used to get rid of the image signal from the mixers. Ideal frequency synthesizer generates a pure sinusoidal wave form for frequency translation. Its purity is highly demanded such that no image signal caused by synthesizer after mixer. But due to systematic design, repetitive pattern disturbance and noise from circuits, the synthesizer output?s amplitude and phase varies from the desired design values, the output spectrum is never an ideal single tone. It usually contains of unwanted spurious frequency components and phase noise and it could mix with the input signal and produce side bands and noise in the desired channel. This reduces the sensitivity and selectivity of a receiver. So the main frequency synthesizer design goal is to get low spurious tones and low phase noise in the output spectrum with minimum power and area consumption. On other aspects, fine channel spacing in transceivers require high frequency resolution as low as Hz and quick 4 frequency toggling needs fast frequency switching speed as high as GHz. Besides generating pure local oscillation frequency, synthesizers need to combine modulation techniques to realize a modulated transmitter. There are mainly two types of frequency synthesizer, namely, the phase locked loop (PLL) and direct digital synthesizer (DDS). PLL is a conventional way to realize low phase noise and low spurious tone frequency synthesizer. But the need of high-Q passive component and off chip components makes it a hard for a full integration. Besides, narrow bandwidth of the integer-N type PLL makes it relatively low frequency switching speed of the system. Fractional-N type PLL achieves fine step size since the output frequency can vary by a fraction of the input reference frequency. As a result, the fractional-N PLL can have high reference frequency and low division ratio, which leads to lower in-band noise. However, it also generates fractional spurs in the output spectrum due to periodic switching of the divider ratio. DDS can provide fast frequency switching, fine resolution and wide tuning range in frequency-agile communication systems and it is suitable for integration for no need of off-chip components. It can also provide various direct modulations such as chirp, MSK, FSK and GMSK. DDS is also flexible as a test pattern generator in testing area and addresses an application in BIST for RF circuits. Its drawback is that high speed and high resolution is usually achieved at the cost of big area and huge power consumption. These two types of frequency synthesizers both suffer from unwanted spurs in the vicinity of the main output frequency. These spurs are caused by the periodic disturbance due to their own mechanisms. Delta-sigma modulation technique is used to decrease the 5 periodic disturbance without affecting the synthesizer?s function. Various types of delta-sigma modulators in frequency synthesizers can have different effects in spur reduction. 1.3 Dissertation Organization In Chapter 2, the fundamentals of direct digital synthesis including the spurs and quantization noises introduced by phase and amplitude truncation are reviewed. Nonlinear DAC is introduced to DDS to replace the speed bottle neck ROM lookup table and linear DAC. Top level structure and system performance are analyzed and design tradeoffs are evaluated. In Chapter 3, the basics of delta-sigma modulation are introduced and its white noise linear model is examined. The effectiveness of various types of delta-sigma modulators in both frequency domain and phase domain of DDS is verified by math deduction and real implementation in a CMOS chip. Their performances including spur reduction effect, area, speed and stability are compared. In Chapter 4, the RF circuit designs of DDS building blocks such as CML digital circuits, phase accumulators, delta-sigma modulator and nonlinear DAC are discussed In Chapter 5, a DDS-based BIST approach for analog frequency response and linearity test is proposed. In Chapter 6, a fractional-N type wide-band PLL in SOI technology is presented. Chapter 7 concludes the thesis with a summary. 6 CHAPTER 2 DIRECT DIGITAL SYNTHESIS 2.1 Introduction In this chapter, basic ROM-based the direct digital synthesis(DDS) and its mechanism are first reviewed in section 2.2. Phase truncation after the accumulator and DAC?s amplitude quantization can cause unwanted the spurs and noise in the output spectrum. The location and strength of the spurs can be determined by the phase accumulator?s length L and phase word W that addresses the ROM. Increasing the W and DAC bits D can lead to reduction of spur and noise but may cause bigger area and power consumption. Standard Sine ROM compression technique stores only first quadrant amplitude value to reduce 75% the ROM. In section 2.3, a nonlinear DAC replaces the conventional ROM lookup table and linear DAC in DDS to reach high speed. In section 2.4, the structure and system performance such as SNR and SFDR of DDS with a nonlinear DAC are analyzed. An experimental structure design is given in section 2.5. 2.2 DDS Fundamentals 2.2.1 Conventional ROM-based DDS Figure 2-1 shows a conventional ROM-based DDS, The output frequency of the DDS depends on the input L-bit word named frequency control word (FCW). At each positive 7 edge of the reference clock cycle the FCW is added to an accumulator. At any instant, the value in the accumulator represents the phase of the output sinusoid, so it is referred as phase accumulator register. The value in the phase accumulator register is used to address the ROM storing the values of the sinusoid in digital domain. The DAC and filter are used to reconstruct the waveform in analog domain. The frequency resolution is determined by the word length of the phase accumulator which is L. Lclkout FCWff 2?= (2.1) Figure 2-1 Conventional ROM-based DDS. Finite phase word length and amplitude word length will cause quantization errors and thus lead to unwanted spurs and noises in the output wave form. The actual word length of the phase information in the sine ROM will determine the phase quantization error, while the number of the bits in the digital-to-analog converter (DAC) will determine the amplitude quantization error. Therefore, it is desirable to increase the resolution of the ROM and DAC. Unfortunately, larger ROM and DAC resolutions mean larger area, higher power consumption, lower reliability, lower speed, and greatly increased costs. Some 8 memory compression techniques can be used to alleviate the problem and will be introduced later. However, the truncation of the phase accumulator bits dressing the sine ROM is necessary. This ?phase truncation error? corrupts the output sinusoid and it?s periodic and results in spurs in output spectrum of DDS as shown in Figure 2-2(a). The location and magnitude of these spurious spurs have been calculated by Nicholas and Samueli[7]. Knowing that FCW is the input frequency control word, L is the accumulator?s size, W is the number of bits addressing the ROM. B=L-W is the truncated phase word bits. The number of spurs is: )2,( 2 1 L B FCWN ? = (2.2) where (FCW, 2L) represents the greatest common divisor of the FCW and 2L. These spurs are equally spaced between 0 and fclk/2(FCW, 2L) in the spectrum. The magnitude of the largest spur in the spectrum is given by: )2/)2,(sin( 2/)2,(2 BB BB LB worst FCW FCW pi pi? ?= (2.3) There is something important between the magnitude of the largest spur and (FCW, 2B). The magnitude of the worst case spur in the spectrum is a decreasing function of (FCW, 2B) with the maximum value provided by (FCW, 2B) = 2B-1. If (FCW, 2B) =1, the worst case spur would be 3.933dB lower than the spur caused by same B, but unrestricted values of FCW. Nicholas has proposed an architecture to force the (FCW, 2B)=1 to get the half bit improvement in worst case spur [7]. Under this situation, when B is bigger than 4, the magnitude of the worst case spur can be approximately estimated as 2-W. 9 Similarly, the amplitude truncation of ROM to DAC can also introduce quantization to the output. The spurious spurs caused by the quantization effects both in phase and amplitude are shown in Figure 2-2(b), the locations of the spurs are mainly determined by phase truncation. ROM and DAC would affect the magnitudes of the spurs and also increase the noise power density in band by 6dB per bit. The in-band noise plus spurs close to the main signal cannot be filtered by the low pass filter afterward. 10-3 10-2 10-1 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 Normalized Power Spectrum of the DDS Output(No DAC truncation) Digital Frequency (Fout/Fclk) Po we r(d B) (a) Spurs caused by pure phase quantization 10-3 10-2 10-1 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 Normalized Power Spectrum of the DDS Output After DAC Digital Frequency (Fout/Fclk) Po we r ( dB ) (b) Spurs and noise caused by both phase and amplitude quantization Figure 2-2 Spurs and noise in output spectrum caused by phase, amplitude quantization (L=16, W=10, D=12). 2.2.2 Quadrant Compression of ROM The size of the ROM can be reduced by more than 75 percent by taking advantage of the fact that only one quadrant of the sine wave form needs to be stored. As shown in Table 2-1 [8], the second, third and fourth quadrants of a sine waveform can be constructed by using the phase to amplitude information of first quadrant and the two MSBs of the phase information W. 10 Table 2-1 Quadrant table of a sine wave in one period Phase MSB MSB-1 Sine 0>fb ? f: PL(f)= s L f P )(2 ? =2(sin sf fpi )2L? e2 /fs ? 22L+1( sf fpi )2L? e2/fs (3.5) 20 The total quantization noise in the band of interest [0?f b] is: ? L2 = dffPbf L )( 0? = 12 2 +L Lpi ? e2( s b f f2 )2L+1= 12 2 +L Lpi ? e2( R1 )2L+1 (3.6) For an input sine wave form with power? x2=E2/2, the signal to noise ratio (SNR) and dynamic range (DR) of Lth order delta-sigma modulator are: SNRL=? x2/? L2= L n 2 1223 pi ?? (2L+1)R2L+1 (3.7) DRL =E2/? L2= L n 2 223 pi ? (2L+1)R2L+1 (3.8) SNR(dB) =10lg3+10(2n-1)lg2+10lg(2L+1)+10(2L+1)lgR-20Llgpi (3.9) From above deductions, increasing the modulator order L can increase the in-band SNR. When the order L is fixed, doubling the over-sampling ratio R will increase the SNR a value of 3(2L+1). If the quantizer inside the modulator is multi-bit (n>2), the SNR can be improved by 6dB with one more bit increase in quantizer. In practice, the modulator?s order L cannot be increased without limit for it would introduce instability and cause the modulator to oscillate. Usually, L is less than 3 to make sure the stability of the modulator. 3.3 Linear Model of Delta-Sigma Modulator The above deductions are based on the linear model of the delta-sigma modulator. The question remains that under what condition does the linear model of the delta-sigma modulator holds. The function of the quantizer inside a delta-sigma modulator is to 21 truncate its input into quantized signal which represent the input signal. The quantization process is an inherently non-linear operation and introduces errors to the conversion. In order to make the analysis tractable, the quantizer is often linearized by using an input-independent additive white noise model. In this white noise model, a number of assumptions are traditionally made on the error process and its statistics. They follow: 1. The quantization error sequence e[n] is statistically independent of the input sequence. 2. The Probability Density Function (PDF) of e[n] is uniform over the range of half the bin width. 3. The random variables of the error process are uncorrelated. If all the above assumptions hold, the linear model of delta-sigma modulator holds. In order to get the delta-sigma modulator which is capable of complying with the signal-independent white noise assumption, the characteristics of the quantization error e[n] introduced inside the delta-sigma modulator is studied. Most of all, the input to the delta-sigma modulator is preferred to be DC so that math equations of the e[n] and its statistical performance can be derived. On the other hand, MASH type delta-sigma modulator (Figure 3-2 [23]) is a widely used for its easy implementation and stability. A rigorous analysis of MASH delta-sigma modulators with DC input and initial values of each accumulator have been proposed in [15]. It mainly examines the statistics of the quantizer error sequences. First of all, the quantization error from different stage is derived: 22 ? ? ?? = ? = ? = ? ??? ? ??? ? ??? ? ??? ? ++???++?= 1 0 1 0 1 0 0,10,10, 3 2 2 2222 1][ n Kl K K K Kl ll l b V b V b Vne ? (3.10) In (3.10), l represents MASH type modulator?s order. b? is the output levels of the single-bit (or binary) quantizer. )1(0, liVi ???= are the initial values in each stage?s accumulator. ? is the normalized the DC input to the delta-sigma modulator. Figure 3-2 MASH delta-sigma modulator with quantization noise e[n] at each stage. Assume ][nel is a stationary ergodic random process, its sample mean, average power and auto-correlation are evaluated below. Sample mean: ][1lim 1 0 nxNxM N nN ?? = ? ?? ? =?????? (3.11) Average power: ][1lim 1 0 22 nx NxM N nN ?? = ? ?? ? =?? ? ? ??? ? (3.12) Auto-correlation: ][][1lim)( 1 0 rnxnxNrr N nNx += ? ? = ?? ??? (3.13) Let the 0,1V be an irrational number, the following results are important. [15] 23 (1) For modulator?s order l > 2, the sample mean and average power of the binary quantizer error from the last stage are : ( ) 0=lM ? (3.14) 121)( 2 =lM ? (3.15) The autocorrelation is different from second order MASH with higher order MASH type modulators. For second order MASH type, the autocorrelation of the binary quantizer error from the second stage is found: ( )?? ? ??? ? ?? ? ?? ? ? ?? = = 0,121412 1 0,121 )( 22 22 2 r r rr pipi??pi ? (3.16) (2) For third or higher order MASH type, the autocorrelation of the binary quantizer error from the last stage is found: ?? ??? ? == 0,0 0,121)( r rrr l? (3.17) From all the math equations, a conclusion is drawn that an irrational initial condition imposed in the 1st accumulator guarantees a linear white noise model for a third or higher order MASH delta-sigma modulator. The real implementation for the irrational number is based on the fact that a rational number, which is represented by a ratio of two relatively prime integer numbers, will tend to an irrational number when the number in the denominator is made very large. Usually, it is desirable to utilize the minimum odd number ?1? in the first accumulator as the initial seed. This is accomplished by setting ?1? LSB in the first accumulator each time the circuit is reset [15]. 24 (3) For second order MASH type delta-sigma modulator, the autocorrelation is not zero and the linear model does not hold. However, dithering can be added to the LSB of the first accumulator to dither the autocorrelation effect in (3.16) and thus to make its linear model hold. We used a second order MASH type delta-sigma modulator to test initial seed and dithering effect. We set L=30, Fr=3. First initial values of all accumulators in the modulator are set to be zero and the autocorrelation of the second MASH type modulator?s quantization error is shown in Figure 3-3. 0 20 40 60 80 100 120-0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 Autocorrelation of 2nd Quantization Error r re( r) (a) Normal autocorrelation of quantization error 0 20 40 60 80 100 120-0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 Autocorrelation of 2nd Quantization Error r re( r) (b) With initial seed ?1? added to the 1st accumulator 0 20 40 60 80 100 120-0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 Autocorrelation of 2nd Quantization Error r re( r) (c) With dithering added to the LSB of 1st accumulator Figure 3-3 Autocorrelation of second order MASH type modulator?s quantization error. First initial values of all accumulators in the modulator are set to be zero and the autocorrelation of the second order MASH type modulator?s quantization error is shown in Figure 3-3 (a). Next an initial seed ?1? is added to the first accumulator in the modulator and the result is shown in Figure 3-3 (b). There?re some improvements in the quantization error autocorrelation in (b) but it?s still not a white noise. So a 16-bit pseudo random series is added to dither the LSB of the 1st accumulator and the result is shown in (c).This is almost a white noise and the linear model of delta-sigma modulator holds. For higher order delta-sigma modulator, the results are even better. 25 In this section, a MASH type delta-sigma modulator with DC input is studied and the quantization errors for its quantizers are examined using the math autocorrelation to verify the effectiveness of linear model of delta-sigma modulator. Modulator with order higher than 3 satisfies the linear white noise model. Lower order modulator needs dithering to approach the linear model. The linear model of delta-sigma modulator is the basis of its use in DDS in next section. 3.4 Delta-sigma Modulation in DDS 3.4.1 Introduction As illustrated in Figure 3-4, a conventional direct digital synthesizer (DDS) consists of a numerically controlled oscillator (NCO) and a digital-to-analog converter (DAC). The NCO further includes a phase accumulator and a lookup table that transforms digital phase information to digital amplitude information. The DDS output spectrum contains spurious components mainly due to phase word truncation before the ROM lookup table. The periodic truncated phase error sequence causes spurs in its output spectrum. Delta-sigma modulators have been implemented in both frequency [16] and phase [17] domains in DDS to reduce the spurs, their noise shaping effects and design tradeoffs have been compared [18]. In this section, we go details of comparison and implementation of eight different delta-sigma modulators including MASH, feed-forward, feedback and error feedback in both frequency and phase domains in a CMOS DDS chip. The noise shaping effects, in-band SFDR, SINAD, operation speeds, area and stability are compared according to measured results. 26 Figure 3-4 DDS with NCO and DAC. 3.4.2 Phase Domain Modulation In an ideal DDS without phase truncation (L = W) and with infinite amplitude precision, the output sequence of the NCO is given by ??????= nFrnS L22sin)( pi (3.18) where Fr is the input frequency control word with L bits and W is the length of phase word to address the accumulator. In order to reduce the ROM size, one can either truncate the phase accumulator output from L bits to W bits. With a phase word truncation, we define B to be the number of bits truncated such that L-W=B. The output of the DDS becomes ??? ? ??? ? ?? ? ?? ?= nFrnS BL B t 22 22sin)( pi (3.19) where the operator [] represents truncation to integer values. Equation (3.19) can alternatively be expressed as [ ]? ? ?? ? ? ??= )( 2 2sin)( nnFrnS pLt ? pi (3.20) 27 where ?p(n) represents the phase error sequence. Applying trigonometric identities, Equation (3.20) can be rewritten as ??? ? ??? ?? ? ?? ? ? ?? ??? ? ??? ?? ? ?? ? ? ?= L p LL p Lt nnFrnnFrnS 2 )(2sin 22cos2 )(2cos 22sin)( ?pipi?pipi (3.21) Assuming ?p(n)<< 2L, we get ?????? ????????? ?= LLpLt nFrnnFrnS 22cos2 )(222sin)( pi?pipi (3.22) Therefore, the output spectrum of the DDS is composed of a sine wave at the desired output frequency corrupted by the cosine modulated harmonics of the phase error?p(n). The periodic sequence ?p(n) can be expressed as Fourier series. Thus, the conventional DDS with phase truncation ends up with spurs at different places in its output spectrum. + Z-1 L L L Phase truncationFrequencyw ord Fr sin/cos w ord length D Look up table D sin w ord DAC ~~~ D eglitch LPF sin output D -bits D AC clkf W nF r ? ?? M odulator B )(np? nF r ? )(np?? W + )(nEp Figure 3-5 Phase domain delta-sigma modulation in DDS. In order to reduce spurs due to phase truncation, we apply delta-sigma modulation in phase domain. There are two ways of adding delta-sigma modulator in phase domain. One is shown in Figure 3-5. The phase word Fr?n after the accumulator is truncated into Fr?n -?p(n)(W bits) and ?p(n) (B bits). The phase error ?p(n) is fed into a delta-sigma modulator. The modulator?s output Ep(n) is expressed as a single-bit or multi-bit word and added back to the truncated phase. Using a linear model for delta-sigma modulators, we get )()()1)(()()( 1 zNoisezzzQzzE pkpp +=?+= ? ?? (3.23) 28 where Q(z) is the quantization noise from the quantizer inside the modulator and k is the order of the modulator. We can rewrite (3.23) as )()()( nNoisennE pp += ? (3.24) where the modulated quantization noise, Noise(n), is the inverse Z-transform of Q(z)(1-z-1)k. The DDS output is thus given by [ ] ( )? ? ?? ? ? +?= ?????? +??= )(22sin )()(22sin)( nNoisenFr nEpnnFrnS L pLt pi ?pi (3.25) Assuming LnNoise 2)( << , we obtain ?????? ????????? ?= LLLt nFrnNoisenFrnS 22cos2 )(222sin)( pipipi (3.26) The second type of delta-sigma modulation in phase domain is phase error feedback as shown in Figure 3-6: g41g85 g43g11g61g12 g36g70g70g88g80g88g79g68g87g82g85 g47 g47 g73g70g79g78 + + g47 + g16 g58 g52g88g68g81g87g76g93g72g85 g40g11g61g12g16 g51g11g61g12 g60g11g61g12 sin/cos w ord length D Look up table D sin w ord D AC ~~~ D eglitch LPF sin output D -bits D AC Figure 3-6 Error feedback modulator in phase domain. From the linear model of error feedback delta-sigma modulator shown in Figure3-6, we can write the modulator?s transfer function: )())(1()()( zEzHzPzY ?+= (3.27) 29 Error feedback delta-sigma modulator actually has a single bit quantizer and the output )(zY represents the input )(zP added with the modulated quantization noise )())(1( zEzH? . The order of the modulator can be changed with different transfer function )(zH . In DDS application, the input L-bit phase is truncated to W-bit. It is a single bit quantization except that the remaining is W-bit in word length. Shown in Figure 3-6, the error feedback modulator?s input is the phase information nFr ? but not the phase error )(np? as the case in the type phase domain modulation shown in figure3-5. The modulator?s output is )(nNoisenFr +? .where Noise(n) is the modulated quantization noise which has high frequency shaping effect. In this way we can get DDS?s output St(n) that is same as (3.25) and (3.26). )))((22sin()( nNoisenFrnS Lt +?= pi ? ? ?? ? ? ???? ? ?? ? ? ?= LLL nFrnNoisenFr 22cos2 )(2 22sin pipipi (3.28) In equation (3.28), the modulated quantization Noise(n) takes place of the original phase error ?p(n). Thus, spurs introduced by the phase truncation are reduced, and modulated quantization noise with high frequency shaping shows up in the spectrum. Delta-sigma modulators with different noise transfer functions thus lead to different DDS output spectra. 3.4.3 Frequency Domain Modulation Delta-sigma modulation can also be implemented in the frequency domain of a DDS. For frequency word truncation, the frequency word Fr is truncated from L bits to W bits 30 before the phase accumulator. The discarded frequency bits B=L-W, and the output sequence of the DDS ROM become ( ) ??? ? ??? ? ? ? ?? ? ? ?+ ?? ? ?? ?= ??? ? ??? ? ??? ? ??? ? ?? ? ?? ? ? ? ?? ? ?? ??+? ?? ? ?? ?= ??? ? ??? ? ?=? ? ?? ? ?= ? W B BB BB W W B L npenFr nFrFrnFr nFrnFrnS 222sin 22222sin 2 )2/(2sin 22sin)( 1 pi pi pipi (3.29) where the operator [] represents truncation to an integer and the frequency error due to frequency word truncation is peFrFr BBB =?? ? ? ??? ? ? ? ?? ? ? ? ?? ? ?? ?? 22 2 (3.30) As shown in (3.29), the phase accumulator size can be reduced to W bits if the input frequency word Fr is truncated to [Fr/2B]. The frequency word truncation will also cause a phase error (pe?n) which is periodic in nature and thus leads to spurs at the DDS output. If the input word Fr? 2B, then [Fr/2B] =0, there will be no DDS output due to frequency word truncation. However, to avoid losing frequency information, the constant frequency error pe needs to be modulated and added back to the accumulator. [ ] sin/cos word length D Look up table D sin word DAC ~~~ Deglitch LPF sin output D-bits DAC pe W Modulator B PE B Fr 2 + Z-1 W W W Frequency word truncationFrequencyword Fr L + ?? Figure 3-7 Proposed DDS with frequency domain delta-sigma modulation. 31 As shown in Figure 3-7, the modulated frequency error pe is added back to the truncated Fr that is represented by [Fr/2B]. Note that in Figure 3-7, the delta-sigma modulator?s input pe is constant, which benefits the modulator design with improved stability, input range and speed. The noise shaped frequency error is thus a series of numbers and is given by )()()1)(()()( 3 zNoisezpezzQzpezPE +=?+= ? (3.31) where Q(z) is the quantization noise introduced by the delta-sigma modulator. With the frequency domain delta-sigma modulation, the DDS output is given by ?????? ???????? ???????? ?? ? ? ?? ? ? ?+?+ ?? ? ?? ?= ? ? ?? ? ? ?+ ?? ? ?? ?= WLL W B W Bt nnNoisenFrnFr nnNoisenpenFr nnPEnFrnS 2 )(2 22cos22sin 2)(22sin 2)(22sin)( pipipi pi pi (3.32) Thus, the DDS output spectrum is composed of a sine wave at the desired output frequency and a cosine wave that is modulated by the quantization noise shaped by the delta-sigma modulator. Based on the linear model of a delta-sigma modulator, the periodic phase error due to frequency word truncation is reduced. Instead, the modulated quantization noise from the modulator occurs at the DDS output. 32 3.4.4 Comparison of Measured NCO Output Spectra for Various Delta-sigma Modulators Although various delta-sigma modulators in both the phase domain and frequency domain can move the spurs and quantization noise to a high frequency band, their performances on noise shaping are different. To compare various delta-sigma modulator performances, we consider factors such as the modulator topology, the order of the modulator, the modulator input, the in-band spurious tones, the number of quantizer bits, the modulator speed and area, etc. We first implemented an NCO with several types of delta-sigma modulators in both frequency and phase domain in FPGA as shown in Figure 3-8. The NCO output is captured into a PC for analysis. First we analyze the output characteristics such as the spurious-free-dynamic-range (SFDR), defined as the ratio between the fundamental signal and the highest spurs and the signal-to-noise-and-distortion ratio (SINAD) shown in (3.33). ( )??? ? ??? ? +?= HarmonicsNoiseSUM SignalSINAD log20 (3.33) The oversampling ratio (OSR) of the delta-sigma modulator is chosen as 64 and the band of interest is from zero to 1/64 of the clock frequency. The measured in-band SINAD and SFDR of the NCO output with various delta-sigma modulators are given in Figure 3-9. The measurements show that without delta-sigma modulation, direct phase truncation has a low SFDR and SINAD. With delta-sigma modulation, in-band SFDR and SINAD increase. In phase domain modulation, the phase error pe (L-W bits LSBs) has different repeating periods with respect to different Fr, which leads to a varying the input to the modulator. In contrast, frequency domain modulators have constant dc input. 33 11 1 ?? z 11 1 ?? z 1 1 1 ? ? ? z z 1 1 1 ? ? ? z z 1 1 1 ? ? ? z z 1 1 1 ? ? ? z z Figure 3-8 Four types delta-sigma modulators implemented in a DDS and NCO for comparison. As a result, the frequency domain delta-sigma modulation has higher SFDR and SINAD than phase domain. Although using a high-order delta-sigma modulator results in sharper noise shaping effect, it suffers from degraded SFDR and SINAD. 34 (a) SINAD of NCO with different modulators (b) SFDR of NCO with different modulators Figure 3-9 Measured in-band SINAD and SFDR of the NCO output with various delta-sigma modulators in frequency and phase domains. Since the modulated quantization noise dominates the DDS output spectrum, its noise transfer function He(Z) can greatly affect the DDS output. We implemented four types of delta-sigma modulators, i.e., MASH, feedforward, feedback and error feedback as shown 35 in Figure 3-8. MASH, feedback and error feedback type delta-sigma modulators have the same noise transfer function of He(Z)=(1-Z-1)k, where k is the order of the modulator. MASH-111 has three 1-bit quantizers, while the feedback type modulator has a multi-bit quantizer and the error feedback delta-sigma modulator has one single-bit quantizer. A feedforward type delta-sigma modulator is first presented in the frequency domain in [16]. It?s a second order feedforward type with a multi-bit quantizer. The modulator?s order can be increased by adding more accumulators in cascade and different noise transfer functions can be obtained by varying the feedforward coefficients k1, k2, k3. We propose a feedforward2 delta-sigma modulator with coefficients of k1 = 2.5, k2 = 2.5, k3 = 1. Figure 3-10 compares the noise transfer function of MASH, feedforward1 [19], and the proposed feedforward2 modulator. It?s clear that MASH has much sharper noise shaping effect in-band. But it has high out-of-band noise that requires a high-order LPF for noise rejection. The feedforward2 modulator has lower in-band noise compared with existing feedforward1 modulator and has flat out-of-band noise compared with MASH type. 0 0.1 0.2 0.3 0.4 0.50 1 2 3 4 5 6 7 8 Normalized Frequency, f/fs MASH Feedforwad2 Feedforward1 Figure 3-10 simulated noise transfer function of MASH and feedforward delta-sigma modulators. 36 Figure 3-11 gives the measured NCO output spectrum for two types of delta-sigma modulators. The measured spectra of the two delta-sigma modulators are almost identical with the modulated noise. Multi-bit quantizer inside the modulator can make feedback signal match input signal more accurately and make the quantization noise more random, which better fits the liner model for delta-sigma modulators. Although feedforward modulator can increase in-band SINAD by a few dB, it has drawback of instability. In contrast, a MASH type modulator is good for its high speed, sharp slope and full input dynamic range, and it is always stable. The drawback of a MASH modulator lies on its fixed number of output bits. The error feedback has the same noise transfer function as that of MASH except for its lower speed. However, error feedback modulator can flexibly choose the number of output bits. Feedback modulator also has the same noise transfer function as MASH and it also has an advantage of a multi-bit quantizer, but it has stability problem. 10-5 10-4 10-3 10-2 10-1 100 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 Normalized Power Spectrum of the DDS Output Digital Frequency (Fout/Fclk) Po we r(d B) (a) NCO output spectrum with 3rd order MASH type delta-sigma modulation in frequency domain(1-bit quantizer) 10-5 10-4 10-3 10-2 10-1 100 -140 -120 -100 -80 -60 -40 -20 0 Normalized Power Spectrum of the DDS Output Digital Frequency (Fout/Fclk) Po we r(d B) (b) NCO output spectrum with frequency domain 3rd order feedforward2 delta-sigma modulation (multi-bit quantizer) Figure 3-11 Comparison of measured NCO output spectrum with different noise shaping effects. 37 The proposed feedforward2 delta-sigma modulator is good in both in-band and out-of-band performances, but its implementation requires more hardware and its speed is lower. 3.4.5 Implementation of DDS with Various Delta-sigma Modulators in 0.35?m CMOS Technology To compare the DDS performance with various delta-sigma modulations, we designed delta-sigma modulators including MASH1-1-1, 3rd order feedforward, feedback and error feedback delta-sigma modulators and error feedback delta-sigma modulator as shown in Figure 3-8 in both frequency and phase domains. Different delta-sigma modulators can be selected individually while other delta-sigma modulators are turned off. The proposed DDS with frequency domain and phase domain delta-sigma modulator was implemented in 0.35?m CMOS technology with two poly and four metal layers. A 16-bit accumulator is designed, and 8 phase bits are used for addressing the look-up ROM. The 12-bit current steering DAC is integrated to convert the ROM output to an analog signal. For 12-bit amplitude resolution in a conventional DDS without a delta-sigma modulator, at least 12 phase bits should be used, which requires a look-up ROM with 212x12 bits. The use of a delta-sigma noise shaper effectively reduces the required number of phase bits. Thus, we use only 8 phase bits to address the ROM, which reduces the ROM size by a factor of 24 or 16 times compared to that of a conventional DDS without a delta-sigma modulator. 38 Figure 3-12 Die photo of the CMOS DDS prototype chip with various delta-sigma modulators in frequency and phase domain. The die photo of the fabricated CMOS delta-sigma DDS prototype chip is shown in Figure 3-12. The total die area is 2x2.5mm2, in which the DDS active core area is 1.7 x 2.1mm2 including the DAC, and the rest of the die area is used for pads and ESD diodes. The 16-bit phase accumulator and ten delta-sigma modulators occupy 0.7x2.1mm2 die area. The 28x12-bit ROM occupies only 0.1x0.8mm2, which would be 16 times larger without the delta-sigma noise shaper. In a conventional DDS, the ROM normally takes the majority of the die area, whereas the ROM takes only a small portion of the total area in this DDS implementation, which clearly demonstrates the advantage of using delta-sigma noise shaping in DDS designs. The measured DDS output spectra with and without delta-sigma modulators are shown in Figure 3-13(a). It?s clear that the in-band spurs shown in figure3-13(a) are reduced in Figure 3-13(b). 3rd order error_feedback g1627g1627 3rd order MASH 1-1-1 g1627g1627 3rd order feedforward g1627g1627 3rd order feedback g1627g1627 4th order error_feedback g1627g1627 DAC RO M 3rd order error_feedback g1627g1627 3rd order MASH 1-1-1 g1627g1627 3rd order feedforward g1627g1627 4th order error_feedback g1627g1627 3rd order feedback g1627g1627 Ph as e D om ain g1627g1627 Fr eq ue nc y D om ain g1627g1627 39 (a) without delta-sigma modulator (b) with frequency domain 3rd order MASH delta-sigma modulator Figure 3-13 Comparison of the measured output spectra for (a) conventional DDS without delta-sigma modulation and (b) proposed DDS with frequency domain delta-sigma modulation, fo=750KHz, Fclk=30MHz. We have implemented various delta-sigma modulators in both frequency and phase domains in a CMOS DDS chip. The measured data demonstrates that frequency domain modulations have better SFDR and SINAD than their phase domain counterparts. Measurements results of output spectrum with different delta-sigma modulators either in frequency domain and phase domain are shown in Figure 3-14 ~Figure 3-18. For clear comparison , they all have a same frequency control word FCW=00000000,11111111. We have also compare factors such as input range, quantizer bits, speed and stability for different type of delta-sigma modulators (Table 3-1). 40 Table 3-1 Performance comparison of delta-sigma modulators in frequency and phase domains of DDS. (In-band SFDR and SINAD are measured from NCO) Frequency domain High freq noise No. of output bits In-band SFDR (dBc) In-band SINAD (dB) Stability Area (mm2) Speed (MHz) 3rd order MASH 111 poor 3 99.5 87.23 ABSOLUTELY STABLE 0.112 180 3rd order Feedback fair 3? 99.4 86.11 FAIR 0.126 140 3rd order Feedforward good 3? 103 89.03 POOR 0.161 150 3rd order EF poor 3? 99.5 87.23 GOOD 0.147 140 4th order EF poor 4? 85.4 75.15 GOOD 0.148 160 Phase domain 3rd order MASH 111 poor 3 85.4 75.15 ABSOLUTELY STABLE 0.112 180 3rd order Feedback fair 3? 84 74.57 FAIR 0.126 140 3rd order Feedforward good 3? 87 78.59 POOR 0.161 150 3rd order EF fair 3? 85.4 75.15 GOOD 0.147 140 4th order EF poor 4? 73 64.10 GOOD 0.148 160 3.4.6 Conclusions Mash 1-1-1 delta-sigma modulator in frequency domain provides a good noise shaping means for DDS application with optimal speed, stability and input dynamic range. Feed-forward delta-sigma modulator can provide both good in-band noise shaping and flat high frequency performance. Error-feedback takes advantage in its flexible output bit numbers. 41 (a) Without modulation (b) Third order feedforward type delta-sigma modulation in phase domain Figure 3-14 Measured DDS output spectra (FCW=00000000,11111111). (a) Phase domain (b) Frequency domain Figure 3-15 Measured DDS output spectra with third order MASH type delta-sigma modulation. (a) Phase domain (b) Frequency domain Figure 3-16 Measured DDS output spectra with third order feedback type delta-sigma modulation. 42 (a) Phase domain (b) Frequency domain Figure 3-17 Measured DDS output spectra with third order error feedback type delta-sigma modulation. (a) Phase domain (b) Frequency domain Figure 3-18 Measured DDS output spectra with fourth order error feedback type delta-sigma modulation. 43 CHAPTER 4 HIGH SPEED DDS DESIGN 4.1 Introduction This chapter discusses the RF circuit design of high speed DDS basic building blocks such as current mode logics, pipelined and carry look-ahead phase accumulators, delta-sigma modulator and a nonlinear DAC that have been discussed in previous chapters. SiGe BiCMOS technology is adopted for its high speed and low noise performance. 4.2.SiGe BiCMOS In contrast to conventional Si bipolar transistors, SiGe bipolar transistor [20] is formed by adding some germanium to its base. The SiGe compound in base has a narrower band-gap compared to the pure silicon one. The relatively large band gap in the emitter can be used to increase the potential barrier to holes that can be injected from the base back to the emitter. Therefore, the emitter doping is can be decreased which leads to the increase of the base-emitter width and hence to reduce the Cje. Meantime, the base doping can be increased which lead to reduction of base width and base-collector depletion region. All these changes bring to higher operating frequency fT, higher gain, increased early voltage VA and lower base resistance rb which are needed for RF circuit design. 44 4.3 CML Digital Blocks Current mode logic (CML) has been employed in the high-speed digital systems for it very fast switching property. The circuit topology is composed of several single current switch pairs which are tied together either in series or parallel with a common current source at the bottom. A current switch pair consists of two bipolar transistors with common emitter connected together. The digital signal in CML circuits is differential and switches on and off each current switch pair at one time. The current is flowing through only one branch from power (VDD) to ground. Figure 4-1 shows a four level 3-input ?AND? circuit. One of the two resistors pulls down the output voltage from VDD to VDD-IBiasRL when bias current flowing through it. The output differential swing is thus 2IBiasRL which many range from 100mv~400mv [21]. So the resistance of RL mainly depends on the swing requirement when the bias current is determined. RL RL VDD A Sum B C Sum C CBASum ??= B A Level1 VDD VDD IBias IBias Level2 Level3 Level1 Level2 Level3 Level shifter Figure 4-1 A four-level AND CML logic. The four-level CML logic (with one current source level) has up to 3 different inputs levels and 3~4 current branches to realize complex combinational logic with less hardware 45 and power compared to ECL logics. The input level voltage of A, B, C under a 3.3V supply is 1.3V, 2.2V and 3.1V so as to make sure the transistors not work in saturation mode. Additional transistors are connected as diode to let each current branch have same voltage drop at each input level. It is necessary for high speed SiGe bipolar transistor has a relatively low BVCEO. A level shifter made of emitter follower buffer to shift down the output voltage level 1 to level2 or level3 to the next stage CML logics. CML circuit?s speed is mainly determined by its propagation delay which is contributed by the base-emitter capacitance, the Miller effect on the intrinsic base-collector capacitance, the inner collector node parasitic such as the collector-substrate capacitance Cs and parasitic resistance rc and of course the load capacitance CL and resistance RL at the output node. SiGe technology has taken its advantages in reducing the parasitics such as rb , Cje and so to Cpi and high current gain. Transistor?s unity current gain-bandwidth product fT is the frequency at which the short-circuit current gain ? is equal to 1. )(2 u m T cc gf += pipi (4.1) In order to achieve maximum speed, it?s a good decision to make the bias current as large as possible by setting it to peak fT. Next, simulations are made to get tradeoff between power consumption and the minimum propagation delay of the CML circuits. For each 3-input AND circuit with minimum transistor size in 0.18um and 0.12um, the bias current is biased at near 70% to its peak fT. With the same AND circuit as load, the propagation delays is 10ps and 5ps. When the emitter follower stage inside the level shifter is running at very high speed, 46 its output impedance would increase with increasing frequency and appear to be inductive [22]. Figure 4-2 Output resistance of emitter follower at high bias and high frequency. For the quite large DC biasing condition: bs rRgm +<1 The output impedance can be approximated by the equivalent circuit of Figure 4-2, where: 0 1 1 ? brRs gmR ++= (4.2) bs rRR +=2 (4.3) )(1 bs T rRL += ? (4.4) Because there are inductive components in the output resistance, when the level shifter is to drive the next stage with quite large capacitive load, it may cause peaking or instability in the overall circuit response as shown in Figure 4-3. Figure 4-3 Oscillation caused by emitter followers inductive output. 47 The edge of the clock signal starts to oscillate when the reset is turn off and circuit begins to work. That?s one reason normally the transistor with minimum size used. Meantime, we need to shrink the load capacitance as small as possible and thus try not let level shifter drive too much loads. 4.4 Pipeline and Carry Look-Ahead Accumulators Accumulator is a major block in the DDS. Phase accumulator in DDS adds up a frequency control word FCW at each clock cycle and generates a phase word of a sine wave at the output. Therefore, accumulator output 0 refers phase 0 and output 2L-1 refers 2pi. The accumulator?s size L determines the final output frequency resolution. The output frequency resolution doubles with one bit increase in accumulator?s length. As discussed in Chapter 2, the phase bits L is truncated to W bits before it goes to ROM or nonlinear DAC and this combined with FCW also determines the spurious spurs. With DAC output bits D, the truncated phase bits W which is connected to ROM determined the quantization noise floor. As a rule of thumb in practical applications, the number bits at the ROM input W should be bigger than or equal to D+2. In high speed DDS design, the accumulator?s speed, area and power consumption would influence the whole DDS performance. The speed is mainly limited by the critical path between the flip-flop registers. 48 4.4.1 Pipeline Accumulator A pipeline accumulator is known for its highest speed. The delay is its critical path is dominated only by a full adder delay. M -1 F lip -flo p s A B S U M Co u tN N -b it A d d e r N N N NN -b it F F N -b it F F 1 -b it F F Cin M -2 F lip -flo p s A B S U M Co u tN N -b it A d d e r N N N N N -b it F F N -b it F F N -b it F F N -b it F F 1 -b it F F Cin N -b it F F A B S U M Co u tN N -b it A d d e r N N N NN -b it F F CinM F lip -flo p s N -b it F F N -b it F F F C W [N :2 N -1 ] M Pi pe lin ed Ro ws F C W [0 :N -1 ] F C W [(M -1 )xN :M X N -1 ] P h a s e [N :2 N -1 ] P h a s e [0 :N -1 ] N -b it F F N -b it F F P h a s e [(M -1 )xN :M x N -1 ] Figure 4-4 A generic architecture of an N?M pipelined accumulator. If the accumulator input is time invariant, each bit of the input word and the adder output bits can be delayed properly such that an N-bit accumulator can operate at the speed of a 1-bit full adder. This type of accumulator, called a pipelined accumulator, uses the most hardware, but achieves the highest speed. Figure 4-4 [23] illustrates a generic architecture of an N?M pipelined accumulator with an N-bit input FCW and a total of M pipelined rows [23]. In the figure, Verilog notation is used to represent the location of the bits. For instance, FCW[N:2N ? 1] denotes bits of FCW from the Nth bit to the (2N ? 1)th bit. Each row has a total of M delay stages placed at the input and output of an N-bit adder. 49 Obviously, an N?M pipelined accumulator has a latency period equal to the propagation delay of M ? 1 clock cycles. Note that an accumulator needs at least one delay stage even without any pipelined stages. The illustrated pipelining accumulator allows the N?M bit accumulator to operate at the speed of an N-bit accumulator, a speed-up of M times. When the number of adder bits is set to one (N = 1), the 1?M bit accumulator can operate at the same speed as a 1-bit adder. To realize an 11-bit accumulator, we can set N = 1 and M = 11. Thereby, an 11-bit accumulator runs at the speed of a 1-bit accumulator consisting of a full-adder and a flip-flop. The sum and carry-out of a full adder can be expressed as: ?? ? ?+?+?= ??= ACCBBAC CBA out Sum (4.5) where A and B are the input bits and C is the carry-in of the adder. Figure 4-5 1-bit CML full adder. The CML circuit for a 1-bit adder is illustrated in Figure 4-5 with four-level transistors. The sum circuit reduces the number of transistors by two and the capacitance load on the 50 output as well, compared to the conventional 3-level logic topology. The simulation results confirmed that the speed of the full adder increases 20% using the four-level logic and the propagation delay is 10ps in SiGe 200GHz technology. For 3.3V supply voltage, four levels of bipolar transistors cannot be vertically stacked without saturating the top level transistors. It is rather critical for high-speed circuit to keep all the transistors from saturation. Therefore the current source for the CML circuit is replaced by an NMOS transistor which can attain low overdrive voltage with large W/L ratio. The clock tree design is very critical for the equal driving capability of the clock signal at each DFF?s input. Clock tree layout is important to make equal phase delay form the original input to each end clock. Due to the fact that the load capacitance is proportional to the bias current, we designed a clock tree with present current to total next stages? current to 1:4. In order to make the clocks have equal delay, the N?M accumulator is split in half and the whole clock tree is inserted inside to make the equal clock path to each DFF. A 20GGz 11-bit pipeline accumulator in 200GHz SiGe technology has been implemented in a DDS tape-out. 4.4.2 Carry Look-Ahead Adder When modulation is implemented using DDS, the pipeline accumulator is no longer suitable for its input is a constant. The intuitive way to construct a N-bit adder with variable input is to place N 1-bit adders in a chain starting with a 1-bit half adder followed by N?1 1-bit full adders with the carry-in of the full adder connected to the carry-out of the 51 previous bit. The most significant bit of the sum must wait for the sequential evaluation of all N-1 1-bit adders. It?s very low for high-speed circuits. The delay of an N-bit ripple adder is hence simply Delay=(N-1)Tcarry+Tsum, where Tcarry is the time for carry generation and Tsum is the time for sum generation in a 1-bit adder. Carry look-ahead adders use methods to reduce the carry propagation delay by adding additional logic. It divides the full adders into subgroups and employs the carry look-ahead logic to speed up the carry propagation process. For the most 3 input levels for our CML logic, we use a 3-bit adder as a single building block to form a 12-bit adder. For a full adder with inputs Ai and Bi and a carry-in Ci-1 from previous adder, the carry out ci ci=ai?bi+(ai+bi)?ci-1 Let the generate gi= ai?bi and propagate pi=(ai+bi), we can calculate all the gi and pi by using the existing ai and bi. and the ci+1 can be get by initial cin and combination of pi and gi at each stages. For a 3-bit adder, the carry out of each stage can be calculated as: ?? ? ??+?+= ?+= in in cppgpgc cpgc 010112 001 (4.6) After getting each carry-in, we can use 3 half-adders to calculate the 2 output sum bits. This single block can be used to construct 3~12bit carry look ahead adder by using 2nd and 3rd level of abstraction logic to calculate the carry-ins between the basic 3-bit adder blocks . 52 Figure 4-6 A 12-bit carry look-ahead adder using CML logics. The level II and III CLA logic is same as level I CLA logic and only one CLA is need to be built. ?? ??? ??+?+= ??+?+= ?+= 1121223 010112 001 CPPGPGC CPPGPGC CPGC in in (4.7) The combinational logic of level II and III carry generate Gi and propagate Pi are also same and reusable. ?? ? ? ? ?? ? ? ? ? ??= ??= ??= ??+?+= ??+?+= ??+?+= 6782 3451 0120 6787882 3454551 0121220 pppP pppP pppP gppgpgG gppgpgG gppgpgG (4.8) The schematic of the 12-bit CLA adder is shown in Figure 4-16. The longest critical path in this carry look-ahead adder is a path that starts from inputs ai bi ->G0-> C1-> C3 ->c10. This path uses 8 AND(OR) gates and assuming each AND(OR) has 10ps propagation delay with same load. The 12-bit CLA adder can run at over 10GHz speed in 200GHz SiGe. 53 4.5 Nonlinear DAC Nonlinear digital-to-analog converter converts the digital phase from accumulator directly into its analog form. It?s most important and hard to realize very high speed DDS. A SiGe cosine-weighted nonlinear DAC [24] with 10GHz sampling rate is presented in this section. It takes the advantage of high switching speed of SiGe current switches and uses the current mode logic (CML) circuits to realize the digital control logics. The DAC is designed using a 47GHz SiGe technology and achieves a maximum 5GHz output frequency with 10GHz clock. The DAC only consumes about 1W power, which is much smaller than that of a prior art cosine-weighted DAC implemented in InP [25]. The total output current doubles when DAC bit increases by one bit and the number of DAC cells also doubles when phase bit W increases by one bit. Thus, the DAC bit and the phase bit W should be chosen as small as possible to minimize the area and power consumption. Moreover, the DAC output using an open collector resistor may encounter headroom problem if the total output current is too large. For low power application, we first choose a reasonable number of DAC output bits based on the required SFDR. Then, we choose the number of phase bits slightly larger than that of the DAC output bits such that the overall quantization noise is dominated by the number of DAC bits. For example, if the SNFR is required to be below -45dB, then according to Figure 2-6, the DAC bit is at least 8. This result is obtained under the assumption that that the phase bit W is equal or greater than the DAC bit. Having known the output DAC bit, the value of phase bit W can be obtained by the SINAD requirement in the band. By adding a delta-sigma modulator in DDS, the quantization noise can be pushed away from the Nyquist band and thus increase 54 the in-band SINAD. So the phase bit W can be reduced using sigma-delta modulation, which further reduces the decoder size and thus increases the circuit speed. The architecture of the nonlinear DAC in DDS is shown in Figure 4-7. The phase bit W from the phase accumulator is fed into a 1?s complementor. The complementor output bits (W-2 in length) are separated into MSBs (a bits in length) and LSBs (b bits in length) and passed to the row and column control blocks using thermometer-decoding scheme. Figure 4-7 Architecture of the nonlinear DAC in DDS. These blocks translate the binary input into thermometer code and pass the values to the control logic in each DAC cells for the selection of the current?cell matrix. The sine wave output is obtained by summing the output currents from all the selected current cells. The thermometer decoding reduces dynamic errors by ensuring that the minimum number of cells switches simultaneously. The number of current sources that are turned on should be equal to the value of the thermometer input code. Let the W=6 and a=b=2, the thermometer decoder logic function is shown in table 4-1. 55 Table 4-1 Thermometer-code representation of 2-bit binary values Phase step(k) Binary (a or b) a1(b1) a2(b2) Thermometer decoder output R1(C1) R2(C2) R3(C3) 0 0 0 0 0 0 1 0 1 1 0 0 2 1 0 1 1 0 3 1 1 1 1 1 Note that a value of 0.5 introduces a 1/2 LSB amplitude offset in equation (2.4) such that XOR gates can be used as 1?s complementor. During the negative region that is from pi to pi2 , the sine wave amplitude is generated by the complementation of the amplitude values in positive region (0 topi ). If there is no 1/2 LSB offset, the amplitude in the last phase step of positive region and the amplitude in the first phase step of negative region would be both zero. This would destroy the symmetry of the output sine wave form. As shown in Figure 4-8: Figure 4-8 Non-symmetry effect of sine waveform. Therefore, the 1/2 LSB is introduced to offset the sine output from value 0 when K equals 0. Yet, this offset conflicts with thermometer decoding. Thus, in this design the first DAC cell 0 is placed out of the thermometer decoder cell matrix and is separately controlled by the MSB. When MSB is low (positive region of sine wave), it turns on and vise versa. The proposed DAC architecture can reduce the glitches in thermometer decoder 56 and meanwhile keep the amplitude symmetry of the output sinusoidal wave. The rest DAC cells from 1 to 2a+b-1 are placed in the DAC cells matrix as shown in Figure 4-9 (a). For the nonlinear DAC with W=6 and a=b=2, the output currents of DAC cells from 0 to 15 are given as follows: Ok= 6 13 13 13 12 12 10 10 9 8 7 5 4 3 1 0 The first DAC cell O0=6 is moved out of the cell matrix and is separately controlled by MSB. Because the last DAC cell O15 =0, this DAC cell is neglected in the DAC cell matrix. The structure leads to the symmetry effect as shown in Figure 4-9 (b). (a) DAC cell matrix with W=6(a=b=2) (b)Symmetry effect of sine waveform Figure 4-9 DAC cell matrix structure and its symmetry effect. The DAC cell with different current source Ok is shown in Figure 4-10, where n represents the number of duplicated minimum current tails that form the desired current value Ok. The CML circuits are used to implement the current switches and the differential transistors both operate in the forward-active region with 400uA bias current. Although higher bias current can speed up the circuit slightly, it?s not preferable because the total 57 power consumption increases and the output pull-up resistor value decreases in order to keep the same full-scale output voltage. A differential input voltage of 400mV is used to switch the current cells. Figure 4-10 DAC current cell circuit. Moreover, during a sampling period, the current is held constant. The two pairs of current switches A and B are used for producing the positive and negative regions of the sine wave outputs, respectively. For the positive region, the signal MSB is low, and the current switch pair A in all the DAC cells are turned on. The thermometer-code decoders will turn on the pair B according to cell control logic. For the negative region, the signal MSB is high and all the current switch pair B are turned off. The thermometer code decoder will turn on each cell?s switch pair A according to the logic control circuit shown in Figure 4-10. We have designed the proposed nonlinear DAC in a 47GHz SiGe technology. Simulations were run with 6-bit phase input W (a=b=2) and 8-bit DAC output under fclk=10GHz. There are total 2(a+b)=16 phase steps in one quadrant and the output frequency is set as 10GHz/(16*4)=125.25MHz. The 125.25MHz output waveform is shown in Figure 4-11 (a). Figure 4-11(b) gives the simulated DAC output waveform with the maximum 58 output frequency of 5GHz with clock frequency of 10GHz. Using the minimum size transistor with 1um emitter length, the total nonlinear DAC power consumption is 0.57 W, including the DAC cells and decoders. (a) Output at 125.25MHz (b) Output at frequency 5GHz Figure 4-11 Simulated DAC output waveform at 10GHz. 4.6 Ultra High Speed DDS with MASH Delta-sigma Modulation A 16b direct digital frequency synthesizer in 120G HBT technology is presented in this section. Its top level schematic is shown in Figure 4-12. Figure 4-12 Schematic of DDS with delta-sigma modulation. It consists of a 7GHz 3rd order MASH delta-sigma modulator in frequency domain, a 8-bit carry look ahead accumulator and a 10 GHz nonlinear current-steering DAC. 59 Differential CML is used in circuit implementation to reach high speed and low power consumption. The prototype IC die area is 3mm?3mm and it consumes 4W with 3.3V supply. It?s better to truncate less phase bits and make the left phase bit W big to keep more phase information. But if the phase input bit W is increased more by 1 bit, the decoder size of the nonlinear DAC would double and would cause more unwanted switch glitches. On the other hand, the total current output of the DAC is proportional to 2D (D is the DAC resolution bits) which is proportional to the DAC power consumption. Considering these tradeoffs, the phase is truncated to W=8 bits before it goes to the nonlinear DAC and the DAC output bits R is chosen to be 8. With DAC input and output both be 8 bits, the spurs generated by the phase truncation become dominant. In this case, the worst case spur in DDS output spectrum is -48dBc. A delta-sigma modulator is used to modulate the truncated B bits (B=L-W) and add them back to the frequency word before it goes to the accumulator as shown in Figure 3-7. With this effort, the worst case spur can be furthermore decreased. It also shows that frequency domain modulation has its advantages due to modulator?s constant input and shrinkage of phase accumulator?s size. The phase accumulator?s size is also decreased from 16 bits to 8 bits. There?re several delta-sigma modulator types that can be implemented and different modulator type would lead to different DDS output spectrum. A 3rd order MASH Delta-Sigma is chosen for its high speed, stability and easy implementation. The accumulator size is fixed to 8bit and no multiplier is needed. 4-level CML is used to realize basic logic gates such as a 1-bit full adder shown in Figure 4-5. Bias 60 current of current switch pair is 400uA. To speed up the circuit, Carry Look-ahead adders are used. Adjacent 3 bits of each input are grouped into a 3-bit CLA cell to match the 3 input levels of basic logic cells. DFFs are inserted into data flow to buffer each adder?s outputs. Two?s complemented format is used to realize the constant minus one. Because each digital bit is realized by differential pair, the opposite value of one bit is simply the reverse of the differential pair. Figure 4-13 Third order MASH delta-sigma modulator architecture. Figure 4-13 shows the whole architecture of the 3rd order MASH delta-sigma modulator. It is composed of 3-bit CLA adders and DFFs. Its inputs are the truncated 8-bit frequency word B from FCW and its output 8 bits are added back to the frequency word W and go to phase accumulator. g36 g37 g36 g37 g36 g37 g38 g53g72g74 g36 g37 g38g76g81 g36 g37g38g76g81 g36 g37g38g76g81 g16g20 g36 g37 g54g76g74g81 g40g91g87g54g76g74g81g40g91g87 g54g76g74g81 g40g91g87 g50g88g87g83g88g87 g62g26g29g19g64 g41g38g58g62g26g29g19g64 g82g89g72g85g73g79g82g90 g53g72g74 g53g72g74 g53g72g74 g53g72g74 g53g72g74 g53g72g74 g53g72g74 g53g72g74 g36 g14 g37 g36g14 g37 g36g14 g37 g53g72g74 g53g72g74 g53g72g74 g53g72g74 g53g72g74 g53g72g74 g53g72g74 g53g72g74 g38g47g36 g38g47g36 g38g47g46 g16g20 g82g89g72g85g73g79g82g90 g82g89g72g85g73g79g82g90 g38g47g46g16g20 g16g20 g16g20 g38g47g46 g38g47g46 g38g47g46 g38g47g46 g38g47g46 g38g47g46 g38g47g36 g38g47g36 g38g47g46 g38g47g46 g38g47g46 g38g47g46 g38g47g46 g38g47g46 g38g47g46g38g47g46 g38g47g46 g27 g27 g27 g36 g37 g38g76g81 g38g47g36 g25 g25 g22g54g76g74g81g40g91g87 g54g76g74g81 g40g91g87 g254g20g20g20g255g254g20g20g20g255g254g20g20g20g255 g22 g27 61 Figure 4-14 shows the simulation result of the third order MASH type delta-sigma modulated accumulator?s output running at 7GHz. Its functionality is verified using Matlab test pattern. The output of delta-sigma modulated accumulator goes to a 10GHz current-steering 8-bit nonlinear DAC and this forms the whole DDS. The DDS current outputs are converted to differential voltages by a pair of off-chip 15? pull-up resistors. Figure 4-14 Delta-sigma modulated accumulator output running at 7GHz. Figure 4-15 shows the whole DDS simulation output at a clock frequency fclk =7GHz. The input frequency control word is set as 00000000,10101111(175d). The generated output frequency is thus (175/65536)*7=18.69(MHz). The output spectrum is shown in figure 4-15(b). The upper picture shows the output spectra of DDS with direct phase truncation from 16bits to 8 bits. The frequency range is from 0 to 0.5*fclk. The lower picture is the output spectra of DDS with delta-sigma modulation. The worst case spur has been reduced from ?48dB to ?64dB by employing the third order MASH type delta-sigma modulation in the frequency domain of the DDS. 62 (a)Sine output at 7GHz clock (b) Worst case improvement in spectrum Figure 4-15 Delta-sigma modulated DDS output waveform and spectrum (Fclk=7GHz). The DDS die diagram is 3?3 mm2 die size. It includes a third order MASH type delta-sigma modulator, 8bit phase accumulator, 8bit nonlinear DAC and VCO. The VCO is used to drive the chip with its output so the whole chip does not need the outside driving 63 clock. The power consumption of the pure DDS with delta-sigma modulation is 2.5W under 3.3V supply. 4.7 Conclusions This chapter introduces the RF circuit design of high speed DDS building blocks such as CML running over 20GHz, pipelined phase accumulators running at 20GHz, Carry look-ahead accumulator running at 10GHz, MASH 1-1-1 delta-sigma modulator running at 7GHz and a nonlinear DAC running at 10GHz. 64 CHAPTER 5 DDS BASED BUILT-IN SELF TEST 5.1 Introduction As discussed in previous chapters, direct digital frequency synthesizer (DDS) can switch its output frequency instantly by changing its frequency control word. It is also capable of generating various waveforms with changeable output amplitude. Moreover, the hardware area and power consumption of DDS can be minimized by adding delta-sigma modulation either in frequency or phase domain [27]. All these characteristics benefit DDS a good test signal source for on-chip analog circuit test. In this chapter, a built-in self-test (BIST) approach based on DDS for analog circuitry test in mixed-signal systems is presented. The BIST can do on chip analog circuitry functional measurement of linearity and frequency response including both phase and gain. The approach has been implemented in Verilog and synthesized into a field programmable gate array (FPGA) where it was used for testing of an actual device under test (DUT) and the measurement is compared to theoretical simulation results and real outside spectrum analyzer measurement. In section 5.2, the theory and application of the proposed BIST approach to linearity test are introduced. In section 5.3, a method for analog frequency response and linearity tests will be presented. Finally, conclusions will be given in section 5.4. 65 5.2 Linearity Test Using DDS Linearity is a critical performance of analog amplifiers and mixers. Third-order intercept point (IP3) is a figure-of-merit for linearity for the fact that the third-order inter-modulation (IM3) distortion products are close in frequency to the fundamental signal in the output spectrum and they cannot be removed easily by filtering. The third-order inter-modulation products can be measured by of mixing two-tone input signals to the DUT. By sweeping the amplitude of the two-tone input signal, we can reach a point that the IM3 product equals the ideal linear amplified fundamental signal. At this point, the input signal level is named as input referred IP3 (IIP3) for the amplifier. Higher IIP3 means better linearity and less distortion. The two-tone test signal contains frequencies ?1 and ?2 for IIP3 test can be generated by DDS embedded on chip. DDS as a test pattern generator can also sweep its test tone amplitude by changing the effective bits that fed into the DAC. With the two-tone inputs, the device under test (DUT) generates the output that contains fundamental signals ?1, ?2, two IM3 tones, 2?2-?1, 2?1-?2 and other inter modulation frequencies. Usually, the IM3 are measured by outside equipment such as frequency analyzer to analyze its spectrum directly. For on chip measurement, traditional way is to convert the DUT output to digital sampling points by an ADC and use FFT to analyze its power spectrum. As shown in the Figure 5-1, the input two tones are added after look up tables in sampled domain and fed into the DAC. The analog output from the DAC is the combination of the two-tone test input. Moreover, by gradually addressing the least significant input bits to most significant bits of the DAC, the test tone amplitude can be swept from small to big. The combination 66 of two-tone test signal is filtered by a LPF on the DAC board and then fed into the DUT (analog amp or filter). Accum 1 + Accum 2 LUP1 LUP2 FFT DAC ADC Mix Board DUT g39g39g54g3g87g90g82g16g87g82g81g72g3g87g72g86g87 g86g76g74g81g68g79g3g74g72g81g72g85g87g68g87g82g85 Spectrum Analyzer AMP g73g85g72g84g88g72g81g70g92g20 g73g85g72g84g88g72g81g70g92g21 g41g85g20 g41g85g21 Figure 5-1 Two-tone test using DDS for linearity test. DUT output spectrum Frequency (Mhz) Figure 5-2 DUT output spectrum measured by FFT. 67 On chip spectrum analysis using FFT requires a big amount of hardware implementation. Its accuracy depends on the frequency sampling points calculated by FFT. For the 1024*64 points FFT of the DUT output spectrum analysis is shown in Figure5-2, the frequency resolution is still not good enough to get the accurate values of two IM3. The two IM3 values are not equal and ?2 is missed for it is between two consecutive frequency sampling points. Increasing the sampling points of FFT would cause more complexity of implementation. The proposed method uses a BIST-based measurement to get the IIP3 of a DUT automatically and accurately with much less hardware compared with usual FFT approach. In this method, an on-chip digital multiplier is used as a down converter that can selectively capture the frequency components ?2 and 2?2??1 in DUT output. It down-converts them into two DC signals. The DC values can be further compacted for evaluation of IIP3 by using an accumulator. 5.2 BIST-based measurement of linearity The DDS based BIST for automatic linearity test is shown in Figure 5-3. Total three lookup tables are used to generate test signals with two fundamental frequency1(?1) and frequency2(?2) and one third order frequency3(2?2??1). The two-tone input test signal is formed by adding the DDS output signals ?1 and ?2. The basic signal ?2(or ?1) and third order test tone 2?2??1 are accurately generated by setting the frequency control word Fr1(=Fr2) and 2Fr2-Fr1 from DDS. They are also used for capturing the correspond components in the DUT output spectrum. This is done by the two simple additional digital 68 multipliers and accumulators that form the output response analyzer to generate tow DC signatures DC1 and DC2 whose values are proportional to the power level of fundamental component and IM3 component in the output spectrum. In this way, the power different of first order component and IM3 in output can be easily got from equation below: Delta_P=20log (DC1)-20log (DC2) (5-1) Accum 1 + Accum 2 LUP1 LUP2 DAC ADC Mix Board DUT g39g39g54g3g69g68g86g72g71g3g87g72g86g87 g86g76g74g81g68g79g3g74g72g81g72g85g87g68g87g82g85 AMP g73g85g72g84g88g72g81g70g92g20 g73g85g72g84g88g72g81g70g92g21 g41g85g20 g41g85g21 Accum 3 LUP3 g21g41g85g21g16g41g85g20 X X g73g85g72g84g88g72g81g70g92g22 g47g72g89g72g79 g86g75g76g73g87g72g85 g47g72g89g72g79 g86g75g76g73g87g72g85 ACCUM1 ACCUM2 g39g38g20 g39g38g21 g21g19g79g82g74g11g39g38g20g12 g16 g21g19g79g82g74g11g39g38g21g12 g32g39g72g79g87g68 g51g82g90g72g85 g55g90g82g16 g87g82g81g72 Figure 5-3 Automatic Linearity (IP3) Test using DDS. Delta_P ( P? ) represents the power difference of the IM3 component between the fundamental signal in output spectrum at a certain input level. The good linearity performance can be proved by measurement of P? . As discussed below, under some circumstance, the IIP3 can be directly measured by P? and input signal power lever. First of all, the DUT is represented by a nonlinear function f(u) for analysis. For more intuitive understanding and a preparation for matlab simulation, let?s look at the nonlinear function f(u) of the model of a BJT: 69 )exp()exp( T be T BE V v V VIsic = = ?? ? ?? ? ++++ ...)( 6 1)( 2 1)(1 32 T be T be T be V v V v V vIc = )3211( 32 bebebe vavavaIc ?+?+?+ (5-2) where a1=1/0.026; a2=1/(2*0.026*0.026); a3=1/(6*0.026*0.026*0.026). The input two tones are from DDS and have same amplitudes A. After normalization, we can get a1=1, a2=20, a3=246, the a2 and a3 are set according to the same proportion to the BJT. In order to comply with the DDS output, the sine waves from ?1 and ?2 both have DC bias A. For small input amplitude A and satisfies the equation below [29][30] : )(3)4/9(1 3AaAa ??>>? (5-3) The input referred IP3 (IIP3) can be calculated by: ][2 ][][3 dBmPdBPdBmIIP in+?= (5-4) where P? is the difference between fundamental and IM3 components in DUT output spectrum and Pin is the signal power at the input. For the input test signal power level is already known, the problem is focused on how to measure the P? more accurately and directly in output spectrum between frequency components ?2 and 2?2-?1. Shown in Figure 5-3, a third DDS in introduced to produce the test waveform with frequency3 (2?2-?1). Frequency3 and original basic signal frequency2 (?2) are level shifted downwards in level A to make the waveform symmetrical with the X-axis. This is in order to use accumulator to get rid of other frequency components the DUT output other than these two. Digital multipliers are used to down convert the two frequencies components ?2 and 2?2-?1 in DUT output to DC values. The output DC series are accumulated to get DC1 and DC2. 70 The DC1 and DC2 from the accumulator in a matlab simulation with BJT nonlinear model are shown in Figure 5-4 and Figure 5-5. (a) DC1 (b) DC2 Figure 5-4 DC from the accumulator at different sampling points. We can see from the accumulator output in Figure 5-4(a) that value of output frequency component ?2 can be picked up by the multiplier. But there are some sine-wave-form disturbs along the DC1. In Figure 5-4(b), these disturbs are more obvious because the IM3 component (2?2??1) is far less than the main output frequency component (?2). These disturbs are further amplified by the dc components in the output of the DUP. So it?s very necessary to deal with sample data that ends at the biggest period of all the disturbances and this will not need very long sampling data. For both DC1 and DC2, the common period is given by 12 2 ?? pi ? . 71 (a) P? (30dB) with different sample points (b) P? (30dB) measurement with spectrum analysis Figure 5-5 P? (30dB) measurement. From Figure 5-5(a), we can see the change of P? with different sample points in BIST. It?s clear that we need to sample at a period that is the integer times of 12 2 ?? pi ? in order to get the correct P? which is 30dB that matches well with the result got from spectrum analysis in Figure 5-5(b). The dc component in the output of DUP is enlarged and it would cause the increase of the disturbance amplitude in DC signatures. On the other hand, when we take longer time to reach a relatively stable P? and use mean value of the P? in this period, we can also get a pretty accurate value of P? . In practical implantation, we need to choose long accumulation time (such as 2^16 accumulation steps). 5.3 Implementation and Test Results We use FPGA, a DAC&ADC board to test the nonlinearity of the DUT generated by a field programmable analog array (FPAA). The nonlinearity of the DUT is tuned by 72 lowering FPAA?s power supply from 5v to 3v. We first measured the P? between the fundamental signal and IM3 by a spectrum analyzer. Then we used the BIST method to calculate the P? on chip automatically. The experiment results are shown below. (a) Input two-tone signal the DUT output with nonlinearity (b) Measured DUT output spectrum Figure 5-6 Hardware measurements of two-tone test at the DUT output. Next, we use the BIST method to measure the DUT?s linearity performance. The period of ?2??1 in our experiment T=1024*Tclk. We use a common period Tc= 1024*110*Tclk which is the integer times of T to get the P? without disturbances. The measured two DC signatures DC1 and DC2 are shown in figure 5-7 and they match well with the theoretical matlab simulations in figure 5-4. 73 g36g38g56g48g20g11g39g38g20g12 g19 g21g19g19g19g19g19g19 g23g19g19g19g19g19g19 g25g19g19g19g19g19g19 g27g19g19g19g19g19g19 g20g19g19g19g19g19g19g19 g20g21g19g19g19g19g19g19 g20g23g19g19g19g19g19g19 g20g25g19g19g19g19g19g19 g20g27g19g19g19g19g19g19 g20 g20g21g25 g21g24g20 g22g26g25 g24g19g20 g25g21g25 g26g24g20 g27g26g25 g20g19g19g20 g20g20g21g25 g20g21g24g20 g20g22g26g25 g20g24g19g20 g20g25g21g25 g20g26g24g20 g20g27g26g25 g21g19g19g20 g21g20g21g25 g21g21g24g20 g21g22g26g25 g21g24g19g20 g38g79g82g70g78g3g54g68g80g83g79g72g86 g39g38 g20 g36g38g56g48g20 (a)DC1 output with different sampling points g36g38g56g48g21g11g39g38g21g12 g16g24g19g19g19g19g19 g19 g24g19g19g19g19g19 g20g19g19g19g19g19g19 g20g24g19g19g19g19g19 g21g19g19g19g19g19g19 g21g24g19g19g19g19g19 g22g19g19g19g19g19g19 g22g24g19g19g19g19g19 g23g19g19g19g19g19g19 g20 g20g21g24 g21g23g28 g22g26g22 g23g28g26 g25g21g20 g26g23g24 g27g25g28 g28g28g22 g20g20g20g26 g20g21g23g20 g20g22g25g24 g20g23g27g28 g20g25g20g22 g20g26g22g26 g20g27g25g20 g20g28g27g24 g21g20g19g28 g21g21g22g22 g21g22g24g26 g21g23g27g20 g21g25g19g24 g38g79g82g70g78g3g54g68g80g83g79g72g86 g39g38 g21 g36g38g56g48g21 (b)DC2 output with different sampling points Figure 5-7 Hardware measurements of DC1 and DC2. We run the experiment for 1000 times and each time the stop time is T and get the BIST result and result?s distribution of a 14dB P? measurement. g39g72g79g87g68g66g51g3g32g3g20g23g3g71g37 g19 g24 g20g19 g20g24 g21g19 g21g24 g22g19 g22g24 g23g19 g23g24 g20 g27g20 g20g25 g20 g21g23 g20 g22g21 g20 g23g19 g20 g23g27 g20 g24g25 g20 g25g23 g20 g26g21 g20 g27g19 g20 g27g27 g20 g28g25 g20 g20g19 g23g20 g20g20 g21g20 g20g21 g19g20 g20g21 g27g20 g38g79g82g70g78g3g54g68g80g83g79g72g86 g39g72 g79g87 g68g66 g51g11 g71g37 g12 (a) BIST measurement of 14dB P? g39g72g79g87g68g66g51g3g71g76g86g87g85g76g69g88g87g76g82g81g11g20g23g71g37g12 g19g17g19g19 g21g17g19g19 g23g17g19g19 g25g17g19g19 g27g17g19g19 g20g19g17g19g19 g20g21g17g19g19 g20g23g17g19g19 g20g25g17g19g19 g20g27g17g19g19 g21g19g17g19g19 g20g22 g17g25 g27g3 g20g22 g17g26 g20g3 g20g22 g17g26 g24g3 g20g22 g17g26 g27g3 g20g22 g17g27 g20g3 g20g22 g17g27 g23g3 g20g22 g17g27 g27g3 g20g22 g17g28 g20g3 g20g22 g17g28 g23g3 g20g22 g17g28 g26g3 g20g23 g17g19 g20g3 g20g23 g17g19 g23g3 g20g23 g17g19 g26g3 g20g23 g17g20 g19g3 g20g23 g17g20 g22g3 g20g23 g17g20 g26g3 g20g23 g17g21 g19g3 g20g23 g17g21 g22g3 g20g23 g17g21 g25g3 g48g72g68g86g88g85g72g71g3g39g72g79g87g68g66g51 g41g85 g72g84 g88g72 g81g70 g92g3 g11g91 g19g17 g19g19 g20g12 (b) P? distribution in BIST test(1000times) Figure 5-8 P? measurement per 100 points and its distribution. DDS based BIST P? measurement matches well with the result obtained using a spectrum analyzer as shown in figure 5-8(a). The measured P? distribution in figure 74 5-8(b) shows deviation 0f 0.0055 and variance of 0.0003 for the value 14dB P? measurement in 1000 BIST runs. But this method also has dynamic range limitations mainly due to the ADC/DAC on the mixed signal board. For this hardware test, the ADC and DAC are both 8 bits and it limits the P? measurement range to within 30dB. 5.4 Frequency Response Test Using DDS Frequency response including amplitude and phase response [28][31] is also critical for analog integrated filters and amplifiers. The commonly interested cut-off frequency of the filters and amplifiers can be found by measuring the pass-band and stop-band amplitude response, while the group delay can be determined from the phase response. To test the analog filter and amplifiers, the DDS generates frequency tones with fine resolution. A DDS-based test pattern generator and output response analyzer can scan the pass and stop bands of the device with fine step size and can thus measure the frequency and amplitude responses of the device, as shown in Figure 5-9(a). Amplifier Transfer Function Test tones generated using DDS Frequency Ma gn itu de (a) Frequency scan through passband and stopband 75 (b) Input and output signal of a DUT at frequency 12.22KHz and a phase delay=46? Figure 5-9 Frequency response test using DDS. In Figure 5-9 (b), when an input test tone is at 12.22KHz, the amplitude of the DUT output is degraded and there is a phase delay of 46? between the input test tone and the output. This is normally a phase difference between the external path through the DUT (amplifier) and the internal path from the test generator to the test analyzer. Phase correction needs to be done prior to the frequency magnitude measurement. The BIST based on DDS approach to measure the phase difference between the input and output of DUT is shown in Figure 5-10. Note that in Figure 5-10 that DDS1 generates a fine-toned sine wave T1 with a DC bias k1. After the test signal T1 passes through the analog device, both its amplitude and phase will change. The signal output of the DUT is given by D=A2cos(?1t+?)+k2. A second DDS (DDS2) is used to generate test signal T2 that has the same frequency and amplitude as T1. A level shifter is used to shift the T2 signal such that it symmetrical to X-axis (from ?A1/2 to A1/2). During the frequency sweep, if all the test 76 signals T2 start from phase 0, namely T2=A1 cos ?1t, the signal after the multiplier is hence given by: [ ] tkAtAA ktAtAMUL 1211 21 21211 sin)2cos(cos2 ))cos(()cos( ???? ??? +++= ++?= (5.5) 1Z )cos(2 11 tAT 111 cos1 ktAT 1k 212 )cos( ktAD 2k Figure 5-10 BIST of frequency response of an analog circuit. We use an accumulator to obtain the above result and to end the accumulation on a common period of all the test sine multiplication. The period of the different test signal is: clk L clkL p TFCW FFCW T ?= ? = 2 2 1 (5.6) By setting the step of input frequency control word to be a power of 2, we can get a same period for all the test signals. In our case, the biggest period of the test signal is when Fr=2 which is 2L-1 Tclk, so we set the time of calculation to be 2LTclk. The phase step is set to 2 to achieve the finest frequency resolution which is 2/2L. The accumulator translates the output to a constant: 77 LAAORA 2.cos 2 21 ?= (5.7) If there is no phase shift, ?=0, the degradation of A2 compared with A1 will be shown in the ORA. When the ORA value decreases to 0.707 times its initial value, we have reached the 3dB amplitude point of the analog circuit. Unfortunately, analog circuits always have phase shift ?. Therefore, we need to measure ? first and make adjustments to the test signal to achieve the same phase shift. The MSB of the test signal T1 and the MSB of the signal D from the ADC are square waveforms with the same frequency and phase as their sine waveforms. Therefore, we can get the phase difference with a phase detector and record the phase shift ? corresponding to this frequency in a register and output it to the computer. For the next test frequency the register will record another phase shift and after the whole frequency sweep, we will get the frequency response of the analog device. Before the change to next test frequency, the BIST circuitry also performs the amplitude response test. When the amplitude test begins, the DDS2 will be reset and thus delayed for a phase ? that is stored in the phase register. In this way, its output T2 would have the same frequency and amplitude as T1 but has a phase shift ? as D does. That is: )cos(2 11 ?? += tAT (5.8) With this modified T2 to be one input to the multiplier, the ORA1?s output in equation (5.7) will have no effect of phase shift ? and we can get both the correct frequency response and amplitude response of the analog device. This idea in this approach is to measure the frequency delay with an additional phase detector and compensate phase delay in the test 78 pattern generator. 5.5 BIST Measurement of Frequency Response We have used the proposed BIST scheme to measure the frequency response of a low pass filter (LPF). As discussed, the built-in DDS generates the test tones that scan over the frequency from 0 to ? fclk with a frequency step (1/2L-1)fclk. A first order low pass filter was used as a device under test to test our BIST method which automatically applied the test tones at the input of the filter and measured its output magnitude response from ORA2. The cutoff frequency of the amplifier and LPF modules, which is 3dB below the pass-band magnitude, can thus be found at 46 kHz from figure 5-11. Figure 5-11 BIST measured frequency response of a low pass filter. The DDS-based TPG, test controller, and multiplier accumulator-based ORA were modeled in Verilog along with an interface to allow PC control of the BIST circuitry and retrieval of the BIST results. The complete Verilog model is approximately 510 lines of non-commented code. The Verilog code can be parameterized to facilitate easy adaptation of the BIST circuitry for different size DAC and ADC for synthesis into standard cell based 79 ASICs or into FPGAs. In our implementation, we used an 8-bit DAC and ADC and synthesized the BIST circuitry into a Xilinx Spartan XC2S50 FPGA. The synthesized circuit required less than 25% of the total logic resources in the Spartan 2S50 and, as a result could easily fit into the smallest Spartan II FPGA. This means that the BIST-based frequency response measurement circuitry can be efficiently implemented in the digital portion of an ASIC with little area overhead. 5.6 Conclusions In this chapter, a BIST approach using DDS is developed for analog circuit functional testing measurement of analog circuitry?s linearity and frequency response including both phase and gain. The DDS-based test pattern generator is used to generate two frequency tones required in the two-tone linearity test as well as single tones for frequency response measurements. The efficient output response analyzer consisting of a multiplier and accumulator avoid using traditional FFT-based spectrum analysis which consumes much more power and die area. We have implemented the BIST approach in Verilog which was subsequently synthesized into an FPGA and verified on actual hardware with close agree to traditional measurement techniques and simulations. 80 CHAPTER 6 PHASE LOCKED LOOP FREQUENCY SYNTHESIZER 6.1 Introduction Phase-locked loop(PLL) is another frequency synthesis technique that has a long history. Different from DDS that generates the output frequency directly by setting input frequency control word, PLL frequency synthesizer uses an oscillator to generate desired output frequency. The oscillator is constantly adjusted by a feedback control loop in order to match in phase and thus lock on the frequency of an input reference signal. A typical PLL structure is shown in Figure 6-1: Figure 6-1 Typical PLL frequency synthesizer. The oscillator is initially tuned to a frequency close to the desired receiving or transmitting frequency. A circuit called phase detector causes the oscillator to seek and lock onto the desired frequency, based on the output of a crystal-controlled reference oscillator. This works by means of a feedback scheme shown in Figure 6-1. If the oscillator frequency departs from the selected crystal reference frequency, the phase detector 81 produces a control signal to bring the oscillator back to the reference frequency. A loop filter is used to stabilize the loop by introducing zeros and poles into the loop. The loop filter, oscillator, reference oscillator, phase detector and feedback frequency divider together comprise a PLL frequency synthesizer. The accuracy, channel spacing, phase noise, side bands and lock time are main performance parameters of a PLL frequency synthesizer and require careful considerations throughout the system, circuit and layout designs. 6.2 Charge Pump PLL Charge pump PLL frequency synthesizer is widely used for its simple structure and good performance. Compared with conventional multiplier PLL or XOR phase detector PLL, it has three main advantages: (1) The output of voltage controlled oscillator determines the lock range of charge pump PLL and its lock range is wide and no mis-lock phenomenon;(2) If the mismatches and offsets of the two branches currents are neglected, the static phase error is zero when in lock mode; (3) The certain amount of time to lock on the frequency of an incoming signal is short and the synthesizer?s switching speed is fast. Moreover, the open-loop transfer function of it has two poles at the origin and root locus shows that more stability of the PLL is achieved with the increasing loop gain. [32] A charge pump PLL is composed of a phase and frequency detector (PFD), charge pump, loop filer and VCO as shown in figure 6-2. 82 Figure 6-2 Charge pump PLL. The basic work theory of charge pump PLL is that tow current sources controlled by the outputs of PFD charges and discharges the loop filter capacitors to generate the voltage control signal to VCO. The PFD transforms the phase or frequency error signal to two switching signal Pu and Pd with corresponding pulse width. For example, when the VCO frequency is lower than reference signal, Pu is high and the up switch is closed for the current source charges the capacitor and make the voltage control signal go high. In the way, VCO frequency is tuned higher. It works vise versa. The whole loop dynamics can be analyzed by the linear mode of each component inside the PLL. The PFD has a gain of KPFD, the loop filter has a transfer function F(s), and the VCO has a gain of Kvco(Hz/V). For the fact that phase is the integration of frequency, an integrator 1/s is included to the VCO transfer function so that VCO has a gain of Kvco/s. Suppose the loop has a phase error ?ref-?d=?e. The average current charging the capacitor is given by I?e/(2pi). The average change in the control voltage after the loop filter is: pi? 2/)/1()( 1sCRIsV ectrl += (6.1) 83 The output phase from VCO is thus: sKvcosVs ctrlout /)()( =? (6.2) ?out(s) is also the open loop transfer function and it has two poles at the origin. The closed-loop transfer function of the PLL is )2/()2/( )2/()1( )(1 )()( 1 2 11 CKvcoIsRKvcoIs CsRCKvcoI s ssH out out pipi pi ? ? ?+???+ +?= += (6.3) The loop transfer function has a zero at ?z=-1/(RC1). The second order system has two parameters; )2/( 1CKvcoIn ??= pi? (6.4) )2/()2/( 1 pi? KvcoCIR ???= (6.5) Suppose the divider modulus changes form M to M+k and k<>1 and ?<<1, N+?=N, The delta-sigma fractional-N PLL loop dynamics and stability issues are identical in delta-sigma fractional-N PLL and integer-N PLL. This is because that each phase noise transfer function in an integer-N PLL is same as the corresponding phase noise transfer function in a delta-sigma fractional-N PLL. In phase-locked loop, the divider output positive edge is separated from the VCO edge by a phase offset (propagation delay). Ideally, this propagation delay is constant if it is independent of the corresponding divider modulus and it does not contribute to the phase noise. Delta-sigma fractional-N PLL has a multi-modulus divider. The modulus dependent divider delays and the nonlinearity introduced by multi-level delta-sigma modulator's output would increase the PLL?s phase noise. One solution is to use a delta-sigma modulator with single-bit quantization. But as discussed before, this would cause decreased nose shaping effect of the modulator. Higher order modulator works but still needs to meet required dynamic range. One solution is to resynchronize the divider output to the nearest VCO edge or at least a higher-frequency edge obtained from within the divider circuitry [35][36].This can get rid 86 of the modulus dependent delays but it takes more power consumption. 6.4 Fractional Spurs The alternation modulus of the divider cause the output frequency to vary between N?fref and (N+l)?fref and during each reference period the difference between the actual divider modulus and the average represents error that gets injected into the PLL and results in increased phase noise. The error is periodical and can generate spurious tones at the fractional offset frequency. If the fractional frequency is low and falls inside the loop bandwidth, large spurious tones appear. One way to suppress these tones is have a very small PLL bandwidth, which negates the potential benefit of the fractional-N technique. There are several methods to suppress these spurs and one is known as the ?fractional compensation?. If the divider's alternating modulus is deterministic, the current generated by the charge pump can be compensated by another current pulses that with the same alternating process but an opposite sign. [37] This technique depends on highly accuracy of the compensation currents. The other way to eliminate fractional spurs is to randomize the sequence of the modulus so as to break up their periodicity. With the randomness of the modulus, the average division modulus can still be achieved and the fractional spurs are converted into white noise. The white noise inside the PLL?s bandwidth is integrated by the PLL transfer function and introduces phase noise contribution no mater what PLL bandwidth is. Delta-sigma fractional-N PLL can solve this problem by shaping the noise spectrum to higher frequency offsets. It generates the sequence of modulus such that the quantization 87 noise has most of its power in a frequency band well above the desired bandwidth of PLL. Chapter3 has discussed the details of the work mechanism of delta-sigma modulator. With a linear model of delta-sigma modulator, the input sequence of delta-sigma modulator x[n] is coarsely quantized into integer-valued y[n] that has the form: y[n]=x[n]+eq[n] (6.10) where eq[n] is the quantization noise introduced inside the modulator and has most of its power at high frequency offset. In order to make white noise of quantization noise model hold, a pseudo-random sequence is usually added to the modulator as described in chapter 3. Its amplitude should be small so it does not appreciably increase the phase noise of the PLL. Suppose x[n] represents an average modulus N+?, y[n] thus represents the N+?+eq. Writing them in continuous time domain, therefore: ))(/()()( teqNtftf outd ++= ? (6.11) The noise in fd is thus: )))(/()(())/()(( ))(/()/()()( teqNteqNtf teqNfNtftn out outoutf ++?+= ++?+= ?? ?? (6.12) By making use of the approximation, eq(t)<