FREQUENCY SYNTHESIZER DESIGNS AND THEIR APPLICATIONS
Except where reference is made to the work of others, the work described in this thesis is
my own or was done in collaboration with my advisory committee. This thesis does not
include proprietary or classified information.
Wenting Deng
Certificate of Approval:
Richard C. Jaeger Fa Foster Dai, Chair
Distinguished University Professor Associate Professor
Electrical & Computer Engineering Electrical & Computer Engineering
Guofu Niu George T. Flowers
Professor Interim Dean
Electrical & Computer Engineering Graduate School
FREQUENCY SYNTHESIZER DESIGNS AND THEIR APPLICATIONS
Wenting Deng
A Thesis
Submitted to
the Graduate Faculty of
Auburn University
in Partial Fulfillment of the
Requirements for the
Degree of
Master of Science
Auburn, Alabama
August 4, 2007
iii
FREQUENCY SYNTHESIZER DESIGNS AND THEIR APPLICATIONS
Wenting Deng
Permission is granted to Auburn University to make copies of this thesis at its discretion,
upon the request of individuals or institutions and at their expense. The author reserves
all publication rights.
Signature of Author
Date of Graduation
iv
VITA
Wenting Deng was born in Nov 6th, 1981 in Chongqing, P. R. China. She attended
Sichuan University in Sep 1999 and graduated with a Bachelor of Science degree in
Microelectronics in July 2003. Then she joined China Electronics Technology Group
Corporation, as a mixed signal circuit design engineer. In August 2005, she entered
graduate program of the Electrical and Computer Engineering Department, Auburn
University.
v
THESIS ABSTRACT
FREQUENCY SYNTHESIZER DESIGNS AND THEIR APPLICATIONS
Wenting Deng
M.S., Auburn University, August 4, 2007
(B.S., Sichuan University, 2003)
87 Typed Pages
Directed by Fa Foster Dai
This thesis discusses design and applications of two main frequency synthesizers:
direct digital frequency synthesis (DDS) and phase lock loop (PLL) synthesis.
DDS is a quickly developed digital technique for frequency synthesis and waveform
generation in modern communication systems. It provides many advantages including
flexible phase and frequency adjustment, highly-stable and fast frequency conversion. A
basic DDS system consists of three main building blocks: accumulator, sine look up table
and a digital to analog converter (DAC). Actually the ROM for sine look-up table
occupies the majority of the DDS area and limits its maximum operation frequency due
to the delay through the multi-layer decoders. To reduce the power dissipation, a
nonlinear DAC has been introduced to replace the ROM-look-up table and the linear
DAC.
vi
In most modern wireless communication systems, digital modulations become more
and more popular since it increases channel capacity, the ability to transmit and receives
information with higher accuracy than an analog communication system in the presence
of noise and distortion. One of the most important applications of DDS is used in the
digital modulations. It is very easy and flexible to implement phase modulations and
frequency modulations by changing the accumulator?s output or frequency control words
respectively.
PLL also has been played an important role in communication systems. Compare to
DDS with the same operation speed, PLL consumes smaller area and less power but has a
relatively narrow tuning range due to voltage control oscillator?s (VCO) ?free running?
[1]. And among kinds of PLLs, fractional-N PLL stands out clearly from others. It can
have a wide loop bandwidth, fast settling time and small channel space. However the
fractional spur is the drawback, it is even worse than in other PLL. In order to reduce the
spurs, delta-sigma modulators was used to decrease the periodic disturbance without
affecting the synthesizer?s function. It moves noise from in-band to out-band, which can
be removed by following low-pass filter.
A 5 GHz differential integer-N PLL is designed and fabricated in 0.5um Silicon
Germanium technology. Circuit designs of main building blocks are discussed in details,
such as phase detector, charge pump, 8 bit multi-modular divider with extension and
programmable divider. And all digital blocks are used current-mode-logic (CML) for its
high speed and relatively low power consumption.
vii
ACKNOWLEDGMENTS
It has been a great privilege to be a graduate student in the Electrical and Computer
Engineering department at Auburn University and work closely with my advisor Dr. Fa
Foster Dai. He guided and encouraged me throughout my studies. And his keen insight
into integrated circuit design is the key factor in the success of this research.
I would also like to thank my advisory committee members, Dr. Richard C. Jaeger
and Dr. Guofu Niu for their guidance and advices on this work.
I greatly appreciate the help from my colleagues in Dr Dai?s group who have made
contributions to my research. I am especially indebted to Dayu Yang, Vasanth Kakani,
Xuefeng Yu, Yuan Yao, Xueyang Geng, Desheng Ma, Yuehai Jin and Zhenqi Chen for
their support and friendship throughout the course of this research.
Last but not the least, I am deeply grateful to my parents Yucheng Deng and
Lizhong Yang for their love and support in my whole life. Their confidence in me and
their high expectation of me are the motive force for me to go forward.
viii
Style manual or journal used: IEEE Journal on Solid State Circuits
Computer software used: Microsoft Word 2003
ix
TABLE OF CONTENTS
LIST OF TABLES???????????????????????????.xi
LIST OF FIGURES????????????????????????....?...xii
CHAPTER 1 INTRODUCTION ........................................................................................ 1
1.1 Background Statement........................................................................................... 1
1.2 Technology Used for Frequency Synthesizer ........................................................ 2
1.3 Thesis Organization ............................................................................................... 3
CHAPTER 2 DIRECT DIGITAL SYTHESIS OPERATION THERORY ....................... 5
2.1 Basic Concepts....................................................................................................... 5
2.2 Phase Accumulator ................................................................................................ 7
2.3 Look Up Table and Sine Rom Compression ....................................................... 10
2.3.1 Look Up Table ROM ................................................................................. 10
2.3.2 Quadrant Compression of ROM ................................................................ 11
2.4 Digital to Analog Converter................................................................................. 13
CHAPTER 3 DIGITAL MODULATIONS IMPLEMENTED IN DDS.......................... 15
3.1 Background .......................................................................................................... 15
3.2 DDS Structure Used For Digital Modulations..................................................... 15
3.3 Phase Modulation in DDS ................................................................................... 16
3.3.1 BPSK & DBPSK........................................................................................ 17
3.3.2 QPSK (Quadrature Phase shift keying) ..................................................... 18
3.3.3 OQPSK ...................................................................................................... 20
3.4 Frequency Modulation in DDS............................................................................ 21
3.4.1 MSK (Minimum shift Keying) .................................................................. 22
3.4.2 GMSK (Gaussian MSK) ............................................................................ 23
3.5 Test Results.......................................................................................................... 27
3.5.1 BPSK.......................................................................................................... 27
3.5.2 QPSK ......................................................................................................... 27
3.5.3 OQPSK ...................................................................................................... 28
3.5.4 MSK........................................................................................................... 29
3.6 Conclusion ........................................................................................................... 29
CHAPTER 4 PHASE-LOCKED LOOP OPERATION THERORY ............................... 30
4.1 Introduction.......................................................................................................... 30
4.2 Integer-N PLL Synthesizer .................................................................................. 31
4.3 Charge Pump PLL................................................................................................ 31
4.4 Fractional-N Frequency Synthesizer.................................................................... 34
4.5 Fractional Spurs ................................................................................................... 36
x
CHAPTER 5 RFIC DESIGNS FOR AN INTEGRATED PLL IN 0.5 UM SIGE
TECHNOLOGY ...................................................................................... 38
5.1 Introduction.......................................................................................................... 38
5.2 Current Mode Logic............................................................................................. 39
5.3 Multi-Modular Divider with Extension ............................................................... 41
5.3.1 Architecture................................................................................................ 41
5.3.2 Dual-Modular Divider ............................................................................... 43
5.3.3 Circuit Implementation of The 2/3 Divider Cell........................................ 44
5.3.4 Power Dissipation Optimization................................................................ 44
5.4 Programmable Divider (divide ratio 1~8)............................................................ 46
5.4.1 Divider?s Architecture ............................................................................... 46
5.4.2 Logic Implementation of Digital Blocks ................................................... 48
5.4.3 Programmable Division Ratio.................................................................... 51
5.4.4 Simulation Result....................................................................................... 51
5.5 Phase Frequency Detector.................................................................................... 52
5.6 Charge Pump & Programmable Bias Current Setting ......................................... 54
5.6.1 Charge Pump.............................................................................................. 54
5.6.2 Programmable Bias Current Setting .......................................................... 55
5.7 Loop Filter ........................................................................................................... 55
CHAPTER 6 MEASUREMENTS AND CONCLUSIONS FOR 5 GHZ PLL IN
0.5 UM SIGE TECHNOLOGY ............................................................... 58
6.1 Background .......................................................................................................... 58
6.2 Design Specifications........................................................................................... 58
6.2.1 Frequency Plan........................................................................................... 58
6.2.2 Loop Parameter Design.............................................................................. 60
6.3 Layout photo and Simulation results ................................................................... 61
6.4 Measurements ...................................................................................................... 63
6.4.1 Die Photos.................................................................................................. 63
6.4.2 Printed Circuit Board Design..................................................................... 64
6.4.3 Results........................................................................................................ 65
CHAPTER 7 CONCLUSION........................................................................................... 69
BIBLIOGRAPHY............................................................................................................. 71
xi
LIST OF TABLES
Table 2-1 Quadrant table of a sine wave in one period .................................................... 12
xii
LIST OF FIGURES
Figure 2-1 Conventional ROM-based DDS........................................................................ 5
Figure 2-2 Carry-look-ahead accumulator structure......................................................... 10
Figure 2-3 Quadrant compression of sine ROM............................................................... 12
Figure 2-4 ROM-less DDS using nonlinear DAC ............................................................ 13
Figure 3-1 Direct modulation through a direct digital synthesizer ................................... 16
Figure 3-2 BPSK in time domain...................................................................................... 17
Figure 3-3 Data de-multiplexer for QPSK........................................................................ 19
Figure 3-4 QPSK in time domain ..................................................................................... 20
Figure 3-5 Data de-multiplexer for OQPSK..................................................................... 20
Figure 3-6 OQPSK in time domain .................................................................................. 21
Figure 3-7 MSK in time domain....................................................................................... 23
Figure 3-8 FIR filter structure........................................................................................... 24
Figure 3-9 FIR with different taps .................................................................................... 25
Figure 3-10 Gaussian waveform with 16 taps .................................................................. 26
Figure 3-11 Input data....................................................................................................... 26
Figure 3-12 Gaussian filter?s output ................................................................................. 26
Figure 3-13 BPSK wave ................................................................................................... 27
Figure 3-14 QPSK wave ................................................................................................... 28
Figure 3-15 OQPSK wave ................................................................................................ 28
xiii
Figure 3-16 MSK wave..................................................................................................... 29
Figure 4-1 Typical PLL frequency synthesizer ................................................................ 30
Figure 4-2 Charge pump PLL........................................................................................... 32
Figure 4-3 Fractional-N PLL frequency synthesizer ........................................................ 35
Figure 5-1 Block diagram of a PLL.................................................................................. 39
Figure 5-2 A CML circuit................................................................................................. 40
Figure 5-3 8 bit MMD architecture with extension .......................................................... 42
Figure 5-4 2/3 divider cell................................................................................................. 43
Figure 5-5 CML circuit design ......................................................................................... 44
Figure 5-6 MMD simulation............................................................................................. 45
Figure 5-7 Programmable divider architecture................................................................. 47
Figure 5-8 8:1 MUX composed by 2:1 MUX................................................................... 48
Figure 5-9 8:1 MUX composed with decoder and logic gate........................................... 48
Figure 5-10 3-bit decoder (8 outputs) ............................................................................... 49
Figure 5-11 ?NEW? MUX structure................................................................................. 50
Figure 5-12 Programmable divider simulation................................................................. 52
Figure 5-13 Phase/frequency detector response with WA ). It stores the
corresponding values of the sinusoid wave. This is also the block that limits the operation
speed and large the chip size.
The DAC and filter following the ROM are used to transforms all the digital
information to an analog signal. And the frequency resolution is determined by the bit
number of the phase accumulator.
Nclkout
FCWff
2?= (2-2)
where N is the bit number of phase accumulator
7
2.2 Phase Accumulator
The accumulator is one of the major elements of direct digital synthesizers. It adds
up a frequency control word FCW at each clock cycle and generates a phase word of a
sine wave at the output. Therefore, state 0 means phase 0 and state 12 ?N means 2pi. And
the bit number of accumulator determines the output resolution and frequency.
The accumulator is a digital integrator, performing the arithmetic function
LnPnP +?= )1()( (2-3)
where P(n) is a N bit word, (n) represents the nth clock cycle, and L is the frequency
control. The accumulator is usually constructed by adders and registers. The register is a
storage device which changes its output only when clocked.
The N bit accumulator determines the output resolution frequency, given by
N
ck
out
FF
2= (2-4)
Since all arithmetic operations are done modulo N2 , any input L having a value
120 ??? NL has an equivalent input given by LL N ?= 2* that will yield exactly the
same DDS output frequency. The two control inputs, L and L*, are completely symmetric,
and can be viewed as the same accumulation rate, one being clockwise and the other
counterclockwise.
When it comes to accumulator?s structure, it is usually constructed from similar
blocks. The only connection between blocks is through the carrier bits. For example, a 24
bits accumulator can use six 4-bit similar blocks or twelve 2-bit adders, and other
combinations. There are kinds of ways to implement accumulator. However, in order to
8
implement frequency modulations, the accumulator used in DDS need to use carry
look-ahead structure.
As we know from binary addition, the carry in for bit 2 of the adder is exactly the
carry out of bit 1, so the formula is
)()()( 1111112 bacacbc ?+?+?= (2-5)
Similarly, carry in for bit 1 is defined as
)()()( 0000001 bacacbc ?+?+?= (2-6)
Substituting the definition of c1 for the first equation results in this formula:
)()(
)()()()()(
11001
0010010010010012
bacbb
cabbabcbacaabaac
?+??+
??+??+??+??+??= (2-7)
We can imagine how the equation expands as we get to higher bits in the adder; it
grows exponentially with the number of bits. This complexity is reflected in the cost of
hardware for fast carry, making this simple scheme prohibitively expensive for wide
adders. Fortunately, carry-look-ahead adder limits the complexity of the equations to
simplify the hardware, while still making substantial speed improvements over ripple
carry. It relies on levels of abstraction in its implementation.
If we were to rewrite the equation for 2c using this equation, we would see some
repeated patterns:
))()(()()( 0000011112 cbabababac ?++??++?= (2-8)
Note the repeated appearance of )( ii ba ? and )( ii ba + in the formula above. We let
iii bag ?= (2-9)
iii bap += (2-10)
9
We can get iiii cpgc ?+=+1 , suppose ig is 1, then 1+ic =1. That is, the adder
generates a carry out ( 1+ic ) independent of the value of carry in ( ic ). Now suppose that
ig is 0, and ip is 1, then 1+ic = ic . That is, the adder propagates carry in to a carry out.
)( 0001 cpgc ?+= (2-11)
)()( 0010112 cppgpgc ??+?+= (2-12)
)()()( 00120121223 cpppgppgpgc ???+??+?+= (2-13)
These equations just represent common sense: ci is a 1 if some earlier adder
generates a carry and all intermediary adders propagate a carry. Therefore, the total delay
of an N-bit accumulator is equal to (N-1)tcarry+tsum, where tcarry is the time for carry
generation and tsum is the time for sum generation in last bit adder.
To go faster, we?ll need carry-look-ahead at a higher level. Here, they are for three
4-bit adder blocks:
01230 ppppP ???= (2-14)
45671 ppppP ???= (2-15)
8910112 ppppP ???= (2-16)
That is, ( iP ) is true only if each of the bits in the group will propagate a carry.
)()()( 01231232330 gpppgppgpgG ???+??+?+= (2-17)
)()()( 45675676771 gpppgppgpgG ???+??+?+= (2-18)
)()()( 891011910111011112 gpppgppgpgG ???+??+?+= (2-19)
For generate signal ( iG ), we care only if there is a carry out of the most significant
bit of the 4-bit group. This obviously occurs if generate is true for that most significant
10
bit; it also occurs if an earlier generate is true and all the intermediate propagates,
including that of the most significant bit, are also true.
Figure 2-2 shows the architecture of carry look-ahead accumulator. It offers a faster
path than waiting for the carries to ripple through all 1-bit adders. This faster path is
paved by two signals, generate and propagate. The former creates a carry regardless of
the carry input, and the other passes a carry along [8].
g36g19
g38g68g85g85g92g76g81
g36g20
g38g68g85g85g92g76g81
g36g21 g38g68g85g85g92g76g81
g51g19g42g19g51g20g42g20
g53g72g86
g88g79g87
g19g16g22
g53g72g86
g88g79g87
g23g16g26
g53g72g86
g88g79g87
g27g16g20
g20
g38g20g38g21g38g22
g38g68g85g85g92g3g82g88g87
g69g22 g68g19g69g19g68g20g69g20g68g21g69g21g68g22g69g26 g68g23g69g23g68g24g69g24g68g25g69g25g68g26g69g20g20 g68g27g69g27g68g28g69g28g68g20g19g69g20g19g68g20g20
g51g21g42g21
g47g72g89g72g79g3g44g44g3g47g82g74g76g70
g47g72g89g72g79g3g44
g47g82g74g76g70
g47g72g89g72g79g3g44
g47g82g74g76g70
g47g72g89g72g79g3g44
g47g82g74g76g70
g51g21g42g21 g51g20g42g20 g51g19g42g19
Figure 2-2 Carry-look-ahead accumulator structure
2.3 Look Up Table and Sine Rom Compression
2.3.1 Look Up Table ROM
In a direct digital synthesizer, the Rom is used as a lookup table to convert its phase
input digital data bits to output digital amplitude data bits, to drive the DAC. The output
of the accumulator is used as the address input of the lookup table and represents the
sine-wave phase. This phase information needs to be converted to its amplitude value to
drive the DAC and achieve the required analog output.
11
In typical RF applications, the ROM output must have a resolution in the range of 10
to 12 bits. It was suggested that increasing accumulator length N yields arbitrarily small
steps in the output frequency?an important property of DDS. While the accumulator can
be chosen to be relatively wide, the ROM may become prohibitively large and the power
consumption is huge. For instance, if the widths of the accumulator and the ROM output
words are 12 bits and 10 bits, respectively, then the ROM requires 41012 101.42 ?=? cells.
For this reason, the accumulator can still be designed with a wide output word so as to
provide fine frequency steps, but only the most significant bits of this word are applied as
ROM input.
However, if the ROM phase steps are not as small as those in the accumulator, a
?phase truncation error? [9] [10] corrupts the output sinusoid. This type of error is also
periodic, resulting in spurs. Assume N is the accumulator?s size, W is the number of bits
addressing the ROM. B=N-W is the truncated phase word bits. The number of spurs is:
)2,(
2 1
N
B
FCWM
?
= (2.20)
where (FCW, 2N) represents the greatest common divisor of the FCW and 2N.
2.3.2 Quadrant Compression of ROM
The size of the ROM can be reduced by more than 75 percent by taking advantage
of the fact that only one quadrant of the sine wave need to be stored. For 0???90,
sin(90-?)=sin(90+?), sin(270-?)=sin(270+?), sin(?)= -sin(-?), and sin(?)= -sin(180+?).
Shown in Table 2-1, the second, third and fourth quadrants of a sine waveform can be
constructed by using the phase to amplitude information of first quadrant 0???90. Just
need to change the two MSBs of the output phase information of accumulator.
12
Table 2-1 Quadrant table of a sine wave in one period
Phase MSB MSB-1 Sine
0 fd, the positive
charge accumulates on C1 steadily. Similarly, if the fref< fd, the I2 removes charge from
C1 on every phase comparison. If the output of phase detector is 0, the voltage on
capacitor remains constant.
Compared with conventional PLL, charge pump PLL has three main advantages: (1)
The capture range is only controlled by the VCO output frequency range; (2) If the
mismatches and offsets of the two branches currents are neglected, the static phase error
is zero; and (3) The certain amount of time to lock on the frequency of an incoming
signal is short and the synthesizer?s switching speed is fast. Moreover, the open-loop
transfer function of it has two poles at the origin and root locus shows that more stability
of the PLL is achieved with the increasing loop gain.
33
The whole loop dynamics can be analyzed by the linearized mode of each component
in the PLL. The PFD has a gain of KPFD, the loop filter has a transfer function F(s), and
the VCO has a gain of Kvco/s. Suppose the loop begins a phase error ?ref-?d=?e. The
average current charging the capacitor is given by I?e/(2pi). The average change in the
control voltage after the loop filter is:
)/1(2)( 1sCRIsV ectrl += pi? (4.2)
The output phase from VCO is:
sKvcosVs ctrlout /)()( =? (4.3)
We obtain the following closed-loop transfer function:
)2/()2/(
)2/()1(
)(1
)()(
1
2
11
CKvcoIsRKvcoIs
CsRCKvcoI
s
ssH
out
out
pipi
pi
?
?
?+???+
+?=
+= (4.4)
The loop transfer function has a zero at ?z=-1/(RC1). And the second order system
has two important parameters, n? is proportional to loop bandwidth and independent of
R;
)2/( 1CKvcoIn ??= pi? (4.5)
)2/()2/( 1 pi? KvcoCIR ???= (4.6)
Suppose the divider modulus changes form M to N+k and k<