FREQUENCY SYNTHESIZER DESIGNS AND THEIR APPLICATIONS  
 
 
 
Except where reference is made to the work of others, the work described in this thesis is 
my own or was done in collaboration with my advisory committee. This thesis does not 
include proprietary or classified information. 
 
 
Wenting Deng 
 
 
 
 
Certificate of Approval: 
 
 
 
 
 
Richard C. Jaeger               Fa Foster Dai, Chair 
Distinguished University Professor              Associate Professor 
Electrical & Computer Engineering Electrical & Computer Engineering 
 
 
 
 
 
 
Guofu Niu                 George T. Flowers 
Professor                     Interim Dean 
Electrical & Computer Engineering     Graduate School 
 
FREQUENCY SYNTHESIZER DESIGNS AND THEIR APPLICATIONS 
 
 
Wenting Deng 
 
A Thesis  
Submitted to  
the Graduate Faculty of  
Auburn University  
in Partial Fulfillment of the 
Requirements for the 
Degree of 
Master of Science 
 
 
 
Auburn, Alabama 
August 4, 2007 
 iii 
 
 
 
 
FREQUENCY SYNTHESIZER DESIGNS AND THEIR APPLICATIONS  
 
 
 
Wenting Deng 
 
 
Permission is granted to Auburn University to make copies of this thesis at its discretion, 
upon the request of individuals or institutions and at their expense. The author reserves 
all publication rights. 
 
 
                                                                                     
 
 
 
 
                                          Signature of Author 
 
 
 
 
Date of Graduation 
 
 
 
 
 
 
 
 
 
 
 iv 
VITA 
Wenting Deng was born in Nov 6th, 1981 in Chongqing, P. R. China. She attended 
Sichuan University in Sep 1999 and graduated with a Bachelor of Science degree in 
Microelectronics in July 2003. Then she joined China Electronics Technology Group 
Corporation, as a mixed signal circuit design engineer. In August 2005, she entered 
graduate program of the Electrical and Computer Engineering Department, Auburn 
University. 
 
 
 
 
 
 
 
 
 
 
 
 
 
 v 
THESIS ABSTRACT 
FREQUENCY SYNTHESIZER DESIGNS AND THEIR APPLICATIONS  
 
Wenting Deng 
 
 
M.S., Auburn University, August 4, 2007 
(B.S., Sichuan University, 2003) 
 
 
87 Typed Pages 
 
Directed by Fa Foster Dai 
 
 
This thesis discusses design and applications of two main frequency synthesizers:  
direct digital frequency synthesis (DDS) and phase lock loop (PLL) synthesis. 
DDS is a quickly developed digital technique for frequency synthesis and waveform 
generation in modern communication systems. It provides many advantages including 
flexible phase and frequency adjustment, highly-stable and fast frequency conversion. A 
basic DDS system consists of three main building blocks: accumulator, sine look up table 
and a digital to analog converter (DAC). Actually the ROM for sine look-up table 
occupies the majority of the DDS area and limits its maximum operation frequency due 
to the delay through the multi-layer decoders. To reduce the power dissipation, a 
nonlinear DAC has been introduced to replace the ROM-look-up table and the linear 
DAC. 
 vi 
In most modern wireless communication systems, digital modulations become more 
and more popular since it increases channel capacity, the ability to transmit and receives 
information with higher accuracy than an analog communication system in the presence 
of noise and distortion. One of the most important applications of DDS is used in the 
digital modulations. It is very easy and flexible to implement phase modulations and 
frequency modulations by changing the accumulator?s output or frequency control words 
respectively.  
PLL also has been played an important role in communication systems. Compare to 
DDS with the same operation speed, PLL consumes smaller area and less power but has a 
relatively narrow tuning range due to voltage control oscillator?s (VCO) ?free running? 
[1]. And among kinds of PLLs, fractional-N PLL stands out clearly from others. It can 
have a wide loop bandwidth, fast settling time and small channel space. However the 
fractional spur is the drawback, it is even worse than in other PLL. In order to reduce the 
spurs, delta-sigma modulators was used to decrease the periodic disturbance without 
affecting the synthesizer?s function. It moves noise from in-band to out-band, which can 
be removed by following low-pass filter.  
A 5 GHz differential integer-N PLL is designed and fabricated in 0.5um Silicon 
Germanium technology. Circuit designs of main building blocks are discussed in details, 
such as phase detector, charge pump, 8 bit multi-modular divider with extension and 
programmable divider. And all digital blocks are used current-mode-logic (CML) for its 
high speed and relatively low power consumption. 
 
 
 vii 
 
 
 
 
ACKNOWLEDGMENTS 
It has been a great privilege to be a graduate student in the Electrical and Computer 
Engineering department at Auburn University and work closely with my advisor Dr. Fa 
Foster Dai. He guided and encouraged me throughout my studies. And his keen insight 
into integrated circuit design is the key factor in the success of this research.  
I would also like to thank my advisory committee members, Dr. Richard C. Jaeger 
and Dr. Guofu Niu for their guidance and advices on this work. 
I greatly appreciate the help from my colleagues in Dr Dai?s group who have made 
contributions to my research. I am especially indebted to Dayu Yang, Vasanth Kakani, 
Xuefeng Yu, Yuan Yao, Xueyang Geng, Desheng Ma, Yuehai Jin and Zhenqi Chen for 
their support and friendship throughout the course of this research.  
Last but not the least, I am deeply grateful to my parents Yucheng Deng and 
Lizhong Yang for their love and support in my whole life. Their confidence in me and 
their high expectation of me are the motive force for me to go forward. 
 
 
 
 
 
 
 
 
 
 
 
 viii 
 
 
 
 
Style manual or journal used: IEEE Journal on Solid State Circuits 
 
Computer software used: Microsoft Word 2003 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 ix 
 
 
 
 
TABLE OF CONTENTS 
 
 
 
LIST OF TABLES???????????????????????????.xi 
LIST OF FIGURES????????????????????????....?...xii 
CHAPTER 1 INTRODUCTION ........................................................................................ 1 
1.1 Background Statement........................................................................................... 1 
1.2 Technology Used for Frequency Synthesizer ........................................................ 2 
1.3 Thesis Organization ............................................................................................... 3 
CHAPTER 2 DIRECT DIGITAL SYTHESIS OPERATION THERORY ....................... 5 
2.1 Basic Concepts....................................................................................................... 5 
2.2 Phase Accumulator ................................................................................................ 7 
2.3 Look Up Table and Sine Rom Compression ....................................................... 10 
2.3.1 Look Up Table ROM ................................................................................. 10 
2.3.2 Quadrant Compression of ROM ................................................................ 11 
2.4 Digital to Analog Converter................................................................................. 13 
CHAPTER 3 DIGITAL MODULATIONS IMPLEMENTED IN DDS.......................... 15 
3.1 Background .......................................................................................................... 15 
3.2 DDS Structure Used For Digital Modulations..................................................... 15 
3.3 Phase Modulation in DDS ................................................................................... 16 
3.3.1 BPSK & DBPSK........................................................................................ 17 
3.3.2 QPSK (Quadrature Phase shift keying) ..................................................... 18 
3.3.3 OQPSK ...................................................................................................... 20 
3.4 Frequency Modulation in DDS............................................................................ 21 
3.4.1 MSK (Minimum shift Keying) .................................................................. 22 
3.4.2 GMSK (Gaussian MSK) ............................................................................ 23 
3.5 Test Results.......................................................................................................... 27 
3.5.1 BPSK.......................................................................................................... 27 
3.5.2 QPSK ......................................................................................................... 27 
3.5.3 OQPSK ...................................................................................................... 28 
3.5.4 MSK........................................................................................................... 29 
3.6 Conclusion ........................................................................................................... 29 
CHAPTER 4 PHASE-LOCKED LOOP OPERATION THERORY ............................... 30 
4.1 Introduction.......................................................................................................... 30 
4.2 Integer-N PLL Synthesizer .................................................................................. 31 
4.3 Charge Pump PLL................................................................................................ 31 
4.4 Fractional-N Frequency Synthesizer.................................................................... 34 
4.5 Fractional Spurs ................................................................................................... 36 
 x 
CHAPTER 5 RFIC DESIGNS FOR AN INTEGRATED PLL IN 0.5 UM SIGE 
TECHNOLOGY ...................................................................................... 38 
5.1 Introduction.......................................................................................................... 38 
5.2 Current Mode Logic............................................................................................. 39 
5.3 Multi-Modular Divider with Extension ............................................................... 41 
5.3.1 Architecture................................................................................................ 41 
5.3.2 Dual-Modular Divider ............................................................................... 43 
5.3.3 Circuit Implementation of The 2/3 Divider Cell........................................ 44 
5.3.4 Power Dissipation Optimization................................................................ 44 
5.4 Programmable Divider (divide ratio 1~8)............................................................ 46 
5.4.1 Divider?s Architecture ............................................................................... 46 
5.4.2 Logic Implementation of Digital Blocks ................................................... 48 
5.4.3 Programmable Division Ratio.................................................................... 51 
5.4.4 Simulation Result....................................................................................... 51 
5.5 Phase Frequency Detector.................................................................................... 52 
5.6 Charge Pump & Programmable Bias Current Setting ......................................... 54 
5.6.1 Charge Pump.............................................................................................. 54 
5.6.2 Programmable Bias Current Setting .......................................................... 55 
5.7 Loop Filter ........................................................................................................... 55 
CHAPTER 6 MEASUREMENTS AND CONCLUSIONS FOR 5 GHZ PLL IN                         
0.5 UM SIGE TECHNOLOGY ............................................................... 58 
6.1 Background .......................................................................................................... 58 
6.2 Design Specifications........................................................................................... 58 
6.2.1 Frequency Plan........................................................................................... 58 
6.2.2 Loop Parameter Design.............................................................................. 60 
6.3 Layout photo and Simulation results ................................................................... 61 
6.4 Measurements ...................................................................................................... 63 
6.4.1 Die Photos.................................................................................................. 63 
6.4.2 Printed Circuit Board Design..................................................................... 64 
6.4.3 Results........................................................................................................ 65 
CHAPTER 7 CONCLUSION........................................................................................... 69 
BIBLIOGRAPHY............................................................................................................. 71 
 
 
 
 
 
 
 
 
 
 
 
 
 
 xi 
 
 
 
 
LIST OF TABLES 
 
 
Table 2-1 Quadrant table of a sine wave in one period .................................................... 12 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 xii 
 
 
 
 
LIST OF FIGURES 
 
 
Figure 2-1 Conventional ROM-based DDS........................................................................ 5 
Figure 2-2 Carry-look-ahead accumulator structure......................................................... 10 
Figure 2-3 Quadrant compression of sine ROM............................................................... 12 
Figure 2-4 ROM-less DDS using nonlinear DAC ............................................................ 13 
Figure 3-1 Direct modulation through a direct digital synthesizer ................................... 16 
Figure 3-2 BPSK in time domain...................................................................................... 17 
Figure 3-3 Data de-multiplexer for QPSK........................................................................ 19 
Figure 3-4 QPSK in time domain ..................................................................................... 20 
Figure 3-5 Data de-multiplexer for OQPSK..................................................................... 20 
Figure 3-6 OQPSK in time domain .................................................................................. 21 
Figure 3-7 MSK in time domain....................................................................................... 23 
Figure 3-8 FIR filter structure........................................................................................... 24 
Figure 3-9 FIR with different taps .................................................................................... 25 
Figure 3-10 Gaussian waveform with 16 taps .................................................................. 26 
Figure 3-11 Input data....................................................................................................... 26 
Figure 3-12 Gaussian filter?s output ................................................................................. 26 
Figure 3-13 BPSK wave ................................................................................................... 27 
Figure 3-14 QPSK wave ................................................................................................... 28 
Figure 3-15 OQPSK wave ................................................................................................ 28 
 xiii 
Figure 3-16 MSK wave..................................................................................................... 29 
Figure 4-1 Typical PLL frequency synthesizer ................................................................ 30 
Figure 4-2 Charge pump PLL........................................................................................... 32 
Figure 4-3 Fractional-N PLL frequency synthesizer ........................................................ 35 
Figure 5-1 Block diagram of a PLL.................................................................................. 39 
Figure 5-2 A CML circuit................................................................................................. 40 
Figure 5-3 8 bit MMD architecture with extension .......................................................... 42 
Figure 5-4 2/3 divider cell................................................................................................. 43 
Figure 5-5 CML circuit design ......................................................................................... 44 
Figure 5-6 MMD simulation............................................................................................. 45 
Figure 5-7 Programmable divider architecture................................................................. 47 
Figure 5-8 8:1 MUX composed by 2:1 MUX................................................................... 48 
Figure 5-9 8:1 MUX composed with decoder and logic gate........................................... 48 
Figure 5-10 3-bit decoder (8 outputs) ............................................................................... 49 
Figure 5-11 ?NEW? MUX structure................................................................................. 50 
Figure 5-12 Programmable divider simulation................................................................. 52 
Figure 5-13 Phase/frequency detector response with WA<WB......................................... 52 
Figure 5-14 Implementation of PFD & DFF used in PFD................................................ 53 
Figure 5-15 Phase/frequency detector simulation............................................................. 54 
Figure 5-16 Charge pump with cascade current mirrors .................................................. 54 
Figure 5-17 Programmable current setting ....................................................................... 55 
Figure 5-18 A typical second order loop filter.................................................................. 56 
Figure 5-19 Phase detector, charge pump, loop filter magnitude response ...................... 57 
 xiv 
Figure 5-20 Phase detector, charge pump, loop filter phase response.............................. 57 
Figure 5-21 Charge pump and phase detector simulation ................................................ 57 
Figure 6-1 Die photo of the PLL in 0.5um SiGe technology............................................ 61 
Figure 6-2 PLL open-loop simulation............................................................................... 62 
Figure 6-3 Die photo of PLL ............................................................................................ 63 
Figure 6-4 PLL with package photo ................................................................................. 63 
Figure 6-5 First copper layer on PCB............................................................................... 64 
Figure 6-6 Second copper layer on PCB........................................................................... 65 
Figure 6-7 Spectrum of MMD?s output frequency (division ratio is 256) ....................... 65 
Figure 6-8 Waveform of MMD?s output frequency (division ratio is 256)...................... 66 
Figure 6-9 Spectrum of MMD?s output frequency (division ratio is 360) ....................... 66 
Figure 6-10 Waveform of MMD?s output frequency (division ratio is 360).................... 67 
Figure 6-11 Spectrum of programmable divider?s output (division ratio is 14)............... 67 
Figure 6-12 Waveform of programmable divider?s output (division ratio is 14)............. 68 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
CHAPTER 1 INTRODUCTION 
1.1 Background Statement 
Frequency synthesis is now so natural that every radio design uses only synthesized 
signals. It has entered a new age because of the huge acceleration of cellular telephony 
and the newly emerging markets of wireless and personal communications services. 
Many efforts are underway to increase the integration level of such circuits in low-cost 
technology. As a result the chip expenses have been dropped by technology improvement 
and better circuit design. 
Meanwhile, on the other hand, frequency synthesis is a challenge area in IC design, 
as it includes both analog and digital technologies. To design a synthesizer one has to 
apply a great variety of disciplines such as oscillators, accumulators, digital-to-analog 
converters, amplifiers, filters, phase detectors and etc. A high performance, low-cost, 
low-power, small-area, long-battery-life solution for designs has been the dream for 
decades.  
In fact, there are major advances in two key syntheses. The first one is Phase Locked 
Loop (PLL), which is the most popular and covers more than 95 percent of the frequency 
synthesis. In the past many years, the PLL frequency synthesizer can only generate exact 
multiple times of a reference. As a result, it limits the output accuracy of voltage-control 
oscillator and the reference frequency must be equal to the channel spacing [1]. In recent 
years, fractional-N type PLL has been used to solve the narrow loop bandwidth and low 
 2 
frequency switching speed problems. Its output frequency can vary by a fraction of the 
input reference frequency, thus It allows the reference frequency to be much bigger than 
the channel spacing [2]. However, it also has its weakness -- fractional spurs in the output 
spectrum caused by periodic switching of the divider mode. 
 Although PLL is a conventional way to realize low phase noise, low power 
consumption frequency synthesizer, the need of high-Q [3] passive component and off 
chip components makes it hard for a full integration. Direct digital synthesis (DDS), the 
second main frequency synthesizer has been greatly developed recent years. It generates 
the signal digitally and converts it via a digital-to-analog converter (DAC) to a sine-kind 
wave. This synthesizer can provide fast frequency switching, fine resolution and wide 
tuning range in frequency-agile communication systems and it is suitable for integration 
for no need of off-chip components. Due to its own architecture, DDS can easily make 
various digital modulations such as BPSK, QPSK, MSK, and GMSK, which have wide 
range applications in wireless communications.  
1.2 Technology Used for Frequency Synthesizer  
With the rapid development of microelectronic technology, the transistor size enters 
deep submicron level. It largely increases the chip integration and operation speed of 
system.  
For many years CMOS technology is a typical option for the low-gigahertz 
frequency design [4] [5]. It takes advantages in low power dissipation, low cost and easy 
scaling. However, its low speed, large noise, and the limited set of available passive 
devices really cumber CMOS in RFIC design. Bipolar complementary 
metal-oxide-semiconductor (BiCMOS) technology is then introduced. It can provide high 
 3 
operation speed, high integration capability of both digital and analog circuit, high 
current-drive capability and high performance levels. In BiCMOS technology, the 
hetero-junction bipolar transistor uses two different materials such as Si and Ge to form a 
PN junction inside the transistor. It makes this technology reach higher unity gain 
bandwidth product (fT), low noise, good linearity and low power consumption compared 
to BJT.  
In this research work, we used 0.5 ?m SiGe technology [6] [7] which is a mature 
BiCMOS technology providing a full device suite for RF IC design such as 
hetero-junction bipolar transistor (HBT), n-MOS & p-MOS, diffused and poly-silicon 
resistors, varactor diodes, spiral inductors and etc. 
1.3 Thesis Organization  
In Chapter 2, the concepts and components of direct digital synthesis including 
accumulator, sin-look-up table, and digital-analog converter are reviewed. An 
introduction of nonlinear DAC is also presented which solves the speed bottleneck 
caused by ROM lookup table and linear DAC.  
In Chapter 3, the basics of digital modulations are introduced. And the main 
objective of this chapter is to discuss how to implement various phase and frequency 
modulations in DDS, plus how to filter the signal so as to reduce the transmitted 
bandwidth. Then a comparison and test result among these modulations will be given.   
In Chapter 4, introduce basic concepts of PLL and generally discuss several types of 
PLL (Charge Pump PLL, Integer-N PLL and Fractional-N PLL) with their structures, 
operation theories advantages and shortages. 
 4 
In Chapter 5, the RF circuit designs of PLL building blocks are presented: 
Phase/Frequency detector, Charge pump, programmable current setting, 3 bit 
Programmable divider, Multiple Modular Divider with extension. Furthermore CML 
digital circuits are introduced to replace trail to trail logic circuits in most digital blocks. 
Low power consumption, easy updating, smaller layout area, and higher operation speed 
are also mentioned.  
In Chapter 6, Analysis and measurement results for fabricated PLL chip is presented 
(including PCB board design, test devices use). At last, conclude the thesis with a 
summary. 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 5 
 
 
 
 
CHAPTER 2  DIRECT DIGITAL SYTHESIS OPERATION THERORY 
2.1 Basic Concepts  
In the last few years, direct digital synthesis (DDS) technology has captured the 
attention of synthesizer designers and enjoys an unusual popularity. Due to its notable 
virtues such as highly-stable, flexible phase and frequency adjustment, fast frequency 
conversion and low phase noise, DDS has been broadly used in communication system, 
electronic apparatus and instrument. Various designs and architectures are used to 
implement DDS. In fact, a standard DDS is a digital-and-analog mixed signal device and 
generates a sine wave at its output, not ?all digital.? shown as Figure 2-1 [1]. 
 
Figure 2-1 Conventional ROM-based DDS 
The input to the accumulator, the first DDS element, is called frequency control 
word (FCW) which determines the output frequency of DDS. At each positive edge of 
the reference clock cycle the FCW is added to an accumulator. Since the bits of 
accumulator is constant and the value in the accumulator represents the phase of the  
 6 
output sinusoid, if the FCW is large, the accumulator will be ?filled? faster, then the 
period of sine wave will be shorter. Otherwise, if the FCW is small, the period of sine 
wave will extend. Therefore, FCW can be used for frequency control and modulation.  
The accumulator, which is a discrete digital integrator, is used as the DDS indexer, 
controlled by the input word and the clock, generates a digital ramp. The output of the 
accumulator represents the sine wave?s phase. And the slope of the accumulator output 
can be viewed as the rate of phase change. As the phase increment is given by 
N
FCW
2
2pi? ?=?                                                 ?2-1?
where N is the bit number of accumulator 
Since at its output we have the digital signal that represents phase, it is rather simple 
to add phase control, just by putting an adder (or subtracter) between the accumulator and 
the ROM. Then phase modulation can be easily implemented. 
The sine lookup table ROM converts the phase information to its amplitude 
presentation, performs the transformation in digital domain ( ?? sin=> ). It stores the 
corresponding values of the sinusoid wave. This is also the block that limits the operation 
speed and large the chip size.  
The DAC and filter following the ROM are used to transforms all the digital 
information to an analog signal. And the frequency resolution is determined by the bit 
number of the phase accumulator. 
Nclkout
FCWff
2?=                                                  (2-2) 
where N is the bit number of phase accumulator 
 7 
2.2 Phase Accumulator  
The accumulator is one of the major elements of direct digital synthesizers. It adds 
up a frequency control word FCW at each clock cycle and generates a phase word of a 
sine wave at the output. Therefore, state 0 means phase 0 and state 12 ?N  means 2pi. And 
the bit number of accumulator determines the output resolution and frequency. 
The accumulator is a digital integrator, performing the arithmetic function 
LnPnP +?= )1()(                                                 (2-3) 
where P(n) is a N bit word, (n) represents the nth clock cycle, and L is the frequency 
control. The accumulator is usually constructed by adders and registers. The register is a 
storage device which changes its output only when clocked. 
The N bit accumulator determines the output resolution frequency, given by  
N
ck
out
FF
2=                                                        (2-4) 
Since all arithmetic operations are done modulo N2 , any input L having a value 
120 ??? NL has an equivalent input given by LL N ?= 2*  that will yield exactly the 
same DDS output frequency. The two control inputs, L and L*, are completely symmetric, 
and can be viewed as the same accumulation rate, one being clockwise and the other 
counterclockwise. 
When it comes to accumulator?s structure, it is usually constructed from similar 
blocks. The only connection between blocks is through the carrier bits. For example, a 24 
bits accumulator can use six 4-bit similar blocks or twelve 2-bit adders, and other 
combinations. There are kinds of ways to implement accumulator. However, in order to 
 8 
implement frequency modulations, the accumulator used in DDS need to use carry 
look-ahead structure.  
As we know from binary addition, the carry in for bit 2 of the adder is exactly the 
carry out of bit 1, so the formula is  
)()()( 1111112 bacacbc ?+?+?=                                      (2-5)  
Similarly, carry in for bit 1 is defined as  
)()()( 0000001 bacacbc ?+?+?=                                     (2-6) 
Substituting the definition of c1 for the first equation results in this formula: 
)()(
)()()()()(
11001
0010010010010012
bacbb
cabbabcbacaabaac
?+??+
??+??+??+??+??=     (2-7) 
We can imagine how the equation expands as we get to higher bits in the adder; it 
grows exponentially with the number of bits. This complexity is reflected in the cost of 
hardware for fast carry, making this simple scheme prohibitively expensive for wide 
adders. Fortunately, carry-look-ahead adder limits the complexity of the equations to 
simplify the hardware, while still making substantial speed improvements over ripple 
carry. It relies on levels of abstraction in its implementation. 
If we were to rewrite the equation for 2c using this equation, we would see some 
repeated patterns: 
))()(()()( 0000011112 cbabababac ?++??++?=                        (2-8) 
Note the repeated appearance of )( ii ba ?  and )( ii ba + in the formula above. We let 
iii bag ?=                                                       (2-9) 
iii bap +=                                                      (2-10) 
 9 
We can get iiii cpgc ?+=+1 , suppose ig is 1, then 1+ic =1. That is, the adder 
generates a carry out ( 1+ic ) independent of the value of carry in ( ic ). Now suppose that 
ig is 0, and ip is 1, then 1+ic = ic . That is, the adder propagates carry in to a carry out. 
)( 0001 cpgc ?+=                                                 (2-11) 
)()( 0010112 cppgpgc ??+?+=                                    (2-12) 
)()()( 00120121223 cpppgppgpgc ???+??+?+=                    (2-13) 
These equations just represent common sense: ci is a 1 if some earlier adder 
generates a carry and all intermediary adders propagate a carry. Therefore, the total delay 
of an N-bit accumulator is equal to (N-1)tcarry+tsum, where tcarry is the time for carry 
generation and tsum is the time for sum generation in last bit adder. 
To go faster, we?ll need carry-look-ahead at a higher level. Here, they are for three 
4-bit adder blocks: 
01230 ppppP ???=                                              (2-14) 
45671 ppppP ???=                                              (2-15) 
8910112 ppppP ???=                                             (2-16) 
That is, ( iP ) is true only if each of the bits in the group will propagate a carry. 
)()()( 01231232330 gpppgppgpgG ???+??+?+=                   (2-17) 
)()()( 45675676771 gpppgppgpgG ???+??+?+=                  (2-18) 
)()()( 891011910111011112 gpppgppgpgG ???+??+?+=               (2-19) 
For generate signal ( iG ), we care only if there is a carry out of the most significant 
bit of the 4-bit group. This obviously occurs if generate is true for that most significant 
 10 
bit; it also occurs if an earlier generate is true and all the intermediate propagates, 
including that of the most significant bit, are also true. 
Figure 2-2 shows the architecture of carry look-ahead accumulator. It offers a faster 
path than waiting for the carries to ripple through all 1-bit adders. This faster path is 
paved by two signals, generate and propagate. The former creates a carry regardless of 
the carry input, and the other passes a carry along [8]. 
g36g19
g38g68g85g85g92g76g81
g36g20
g38g68g85g85g92g76g81
g36g21 g38g68g85g85g92g76g81
g51g19g42g19g51g20g42g20
g53g72g86
g88g79g87
g19g16g22
g53g72g86
g88g79g87
g23g16g26
g53g72g86
g88g79g87
g27g16g20
g20
g38g20g38g21g38g22
g38g68g85g85g92g3g82g88g87
g69g22 g68g19g69g19g68g20g69g20g68g21g69g21g68g22g69g26 g68g23g69g23g68g24g69g24g68g25g69g25g68g26g69g20g20 g68g27g69g27g68g28g69g28g68g20g19g69g20g19g68g20g20
g51g21g42g21
g47g72g89g72g79g3g44g44g3g47g82g74g76g70
g47g72g89g72g79g3g44
g47g82g74g76g70
g47g72g89g72g79g3g44
g47g82g74g76g70
g47g72g89g72g79g3g44
g47g82g74g76g70
g51g21g42g21 g51g20g42g20 g51g19g42g19
 
             Figure 2-2 Carry-look-ahead accumulator structure 
2.3 Look Up Table and Sine Rom Compression  
2.3.1 Look Up Table ROM 
In a direct digital synthesizer, the Rom is used as a lookup table to convert its phase 
input digital data bits to output digital amplitude data bits, to drive the DAC. The output 
of the accumulator is used as the address input of the lookup table and represents the 
sine-wave phase. This phase information needs to be converted to its amplitude value to 
drive the DAC and achieve the required analog output. 
 11 
In typical RF applications, the ROM output must have a resolution in the range of 10 
to 12 bits. It was suggested that increasing accumulator length N yields arbitrarily small 
steps in the output frequency?an important property of DDS. While the accumulator can 
be chosen to be relatively wide, the ROM may become prohibitively large and the power 
consumption is huge. For instance, if the widths of the accumulator and the ROM output 
words are 12 bits and 10 bits, respectively, then the ROM requires 41012 101.42 ?=?   cells. 
For this reason, the accumulator can still be designed with a wide output word so as to 
provide fine frequency steps, but only the most significant bits of this word are applied as 
ROM input. 
However, if the ROM phase steps are not as small as those in the accumulator, a 
?phase truncation error? [9] [10] corrupts the output sinusoid. This type of error is also 
periodic, resulting in spurs. Assume N is the accumulator?s size, W is the number of bits 
addressing the ROM. B=N-W is the truncated phase word bits. The number of spurs is:   
)2,(
2 1
N
B
FCWM
?
=                         (2.20) 
where (FCW, 2N) represents the greatest common divisor of the FCW and 2N. 
2.3.2 Quadrant Compression of ROM 
The size of the ROM can be reduced by more than 75 percent by taking advantage 
of the fact that only one quadrant of the sine wave need to be stored. For 0???90, 
sin(90-?)=sin(90+?), sin(270-?)=sin(270+?), sin(?)= -sin(-?), and sin(?)= -sin(180+?). 
Shown in Table 2-1, the second, third and fourth quadrants of a sine waveform can be 
constructed by using the phase to amplitude information of first quadrant 0???90. Just 
need to change the two MSBs of the output phase information of accumulator.  
 
 12 
Table 2-1 Quadrant table of a sine wave in one period 
Phase MSB MSB-1 Sine 
0<A<90 1 0 Sin A 
90<A<180 1 1 Sin(90-A) 
180<A<270 0 0 -Sin A 
270<A<360 0 1 -Sin(90-A) 
Thus, given sin(X) over only the first quadrant, the operations necessary to flip to the 
other quadrants are as follows: 
Quadrant I:    1/2+1/2 Sin X   X is running index from 0 to 2W-2-1 
Quadrant II:   1/2+1/2 Sin X   X complemented (every bit inverted) 
Quadrant III:  1/2-1/2 Sin X   X is running index from 0 to 2W-2-1 
Quadrant IV:  1/2-1/2 Sin X   X complemented 
The MSB determines the sign of the output and indicates whether the phase is in the 
first two quadrants or in the second. The MSB-1 is the quadrant bit and inverts the bits in 
the second and fourth quadrants 
Figure 2-3 shows the implementation of a quadrant compressed sine ROM, The 
reduction of the ROM size is achieved because of the sine quadrant symmetry and 
because the inside ROM now maps W-2 input bits to D-1 output bits only, compared to 
W to D bits originally. The saving of ROM size is therefore 
2W ?2?D? 1?2W D = ?D? 1?4D ? 75 saving
                               (2-21) 
g58 g58g16g21 g58g16g21 g39g39g16g20 g39g16g20
g20g48g54g37g16g20 g48g54g37
g20g86
g70g82g80g83g79g72g80g72g81g87
g20g86
g70g82g80g83g79g72g80g72g81g87
g21g65g11g90g16g21g12g13g11g39g16g20g12
g53g50g48  
Figure 2-3 Quadrant compression of sine ROM 
 13 
2.4 Digital to Analog Converter 
The digital-to-analog converter (DAC) is the link that connects the digital signal 
generated, modulated, and manipulated in the direct digital synthesizer, and converts it 
into its analog form. And it is the parameter that has the greatest effect on DDS 
performance. In conventional ROM-based DDS, it?s not easy to integrate in a small area 
and achieve output frequency bigger than 2GHz. The reason is the time and area 
consumed by ROM look up table. At present, ROM-less DDS becomes popular because 
it uses a nonlinear DAC to replace the ROM lookup table and the linear DAC and thus 
can generate much higher output frequency and occupy less area. [11][12]. 
W
g38g47g46
g41g38g58 g51g75g68g86g72
g36g70g70g88g80g88g79g68g87g82g85
W -2 g38g82g80g83g79g72g80g72g81g87g68g85g92
g21g81g71g3g48g54g37
g48g54g37
W -2 g54g76g81g72
g58g68g89g72
g49g82g81g79g76g81g72g68g85
g39g36g38
 
Figure 2-4 ROM-less DDS using nonlinear DAC 
The function of a nonlinear DAC in DDS is to convert the linear phase information W 
at the output of the accumulator directly into analog sine waveform shown in Figure 2-4. 
Similar as conventional DDS, the truncated phase information W is divided into several 
parts. The first two MSBs are used to select different quadrants of the sine wave. The rest 
bits are segmented into m, n two parts. The first quadrant phase 2/~0 pi is divided into 
)(2 nm+  phase steps equally. With the corresponding conversion, each phase step 
corresponds to a DAC output magnitude.  
 14 
Generally, a switching matrix with row and column thermometer decoders is used to 
switch on and off each DAC cell according to the phase information. The DAC output is 
the sum of all the cells which?s output of thermo-decoder turn on.  
The first the quadrant sine wave form can be reconstructed by switching on and off 
different DAC cells with different values. For other quadrants of sine wave form can be 
built by flipping the phase and output waveforms as shown in Figure 2-3. The MSB 
output of the phase accumulator is used to provide the proper mirroring of the sine 
waveform at the pi phase point. The second MSB is used to invert the remaining bits for 
the second and fourth quadrant of sine wave. 
 
 
 
 
 
 
 
 
 
 
 
 
 
 15 
 
 
 
 
CHAPTER 3 DIGITAL MODULATIONS IMPLEMENTED IN DDS 
3.1 Background 
Nowadays, digital modulation is more popular than analog modulation in most 
modern wireless communication systems [13]. Actually it offers a number of advantages, 
such as increased channel capacity and the ability to transmit; receive information with 
higher accuracy than an analog communication system in the presence of noise and 
distortion. 
On the other hand, the choice of digital modulation scheme will significantly affect 
the characteristics, performance and resulting physical realization of a communication 
system. It becomes a very attractive area. A DDS can implement various types of digital 
modulations since its circuitry can be used to program the frequency, phase and 
amplitude of a waveform. With the availability of single-chip high-speed DDS, such 
modulations can be done with high accuracy and at high speed.  
The objective of this chapter is to discuss how to implement various phase and 
frequency modulations in DDS, plus how to filter the signal so as to reduce the 
transmitted bandwidth. 
3.2 DDS Structure Used For Digital Modulations 
Digital phase modulation generally adds a number of different phase angles to the 
carrier in a data period for different information. The simplest case is binary phase shift 
keying (BPSK). There are only two phase angles (0 deg or 180 deg) can be added to the 
carrier to represent logic zero or logic one respectively. Of course, we can also add 
 16 
different phase angles to represent groups of bits. For example, byadding one of four 
different phase angles to the carrier (i.e., 45deg, 135 deg, 225 deg, and 315 deg) 
represents two-bit data at a time. This is called quadrature phase shift keying (QPSK). 
This idea can be extended further, eight different phase angles to represent three-bit data 
(8-PSK), or sixteen different phase angles to represent four-bit data (16-PSK).  
On the other hand, instead of breaking the phase angle into discrete pieces, 
sometime we need to change the phase angle from one value to another smoothly. And 
this smooth, continuous phase modulation corresponds to frequency modulation. MSK 
and GMSK are the most popular ones.  
Figure 3-1 [2] is the whole structure for digital modulations implemented in DDS. 
Fc is the carrier frequency, while Fd is the data rate. 
g39g39g54g3g38g79g82g70g78
g41g70g14g41g71g18g23
g41g70g16g41g71g18g23
+ g41g85g72g84g88g72g81g70g92g53g72g74g76g86g87g72g85 +
g51g75g68g86g72
g53g72g74g76g86g87g72g85
g11g68g70g70g88g80g88g79g68g87g82g85g12
+
g54g76g81g18g38g82g86
g47g82g82g78g88g83
g55g68g69g79g72
g54g72g85g76g68g79g3g87g82
g51g68g85g68g79g79g72g79g3g20
g54g72g85g76g68g79g3g87g82
g51g68g85g68g79g79g72g79g3g21
g39g36g38
g42g68g88g86g86g76g68g81
g41g76g79g87g72g85
MUX
g39g39g54
g48g82g71g88g79g68g87g82g85
g50g88g87g83g88g87
g50g52g51g54g46
g44g81g83g88g87
g52g51g54g46
g44g81g83g88g87
g37g51g54g46
g44g81g83g88g87
g48g54g37
g20g69g76g87
g48g54g37
g21g69g76g87
g48g54g37
g21g69g76g87
g48g54g46
g44g81g83g88g87
g42g48g54g46
g44g81g83g88g87
 
Figure 3-1 Direct modulation through a direct digital synthesizer 
3.3 Phase Modulation in DDS  
In order to transmit information, more than just a carrier tone is needed. The tone 
has to change in some way over time to indicate what information is being sent. In 
general, a carrier has two properties that can be changed or modulated in order to convey 
information to the receiver: amplitude and phase (frequency). Some modulation schemes 
only change the amplitude of the signal and some only change the phase (or frequency) 
 17 
of the signal, but some more complicated modulation schemes change both. Here we only 
implement and verify these modulations changing one parameter. Let us begin by 
considering modulation that changes only the phase of the carrier. 
3.3.1 BPSK & DBPSK  
The simplest form of digital phase modulation is BPSK. In this case, when data is 0, 
the waveform has no change; when it becomes 1, the phase inverses 180 degree. Then we 
can write the carrier as 
)](cos[)( ttAts ii ?? +?=                                           (3-1) 
where the instantaneous phase angle, ?i(t), is given by 
iti ?= pi? )( ; 1,0=i                                               (3-2) 
A is the amplitude of the carrier. Logic ?1? corresponds to a phase inversion of the 
carrier, while logic 0 corresponds to no phase inversion. BPSK is often referred to as an 
antipodal modulation, where each of the two binary waveforms is the negative of the 
other shown in figure3-2. Each inversion of the carrier causes a sharp transmitted 
spectrum in the time domain response. These transitions produce a very wide transmitted 
spectrum. 
g19
g20
g19 g19
g20
g39g36g55g36
g38g36g53g53g44g40g53
 
Figure 3-2 BPSK in time domain  
 18 
Recall in Chapter 2, accumulator output represents the phase of sine wave and each 
bit has its own phase value. 
)(2
2
2 nN
N
??= pi?                                                 (3-3)               
where N is the accumulator?s bit length and n is the accumulator?s nth bit (the left one is 
the 1st and the right one is nth) 
Thus, adding one to the highest MSB of accumulator equals adding 180 degrees to 
the present phase value; adding one to the second MSB equals adding 90 degrees to the 
phase value; for the third MSB, adding one equals adding 45 degrees to the phase value 
and etc. Generally, adding one to the nth MSB of phase accumulator is equal to adding 
)1(2
180
?n  degrees to the carrier?s present phase value. 
As a result, to implement BPSK in DDS, we just need to add the data value to the 
accumulator?s MSB (Figure 3-1). If the data is 1, the waveform change 180 degree in 
phase, inversely, if data is 0, it causes no phase transition. Consequently, data stream can 
be represented by the variety of waveform phase.  
3.3.2 QPSK (Quadrature Phase shift keying)  
Sometimes, more than one data bit needs to represent a symbol. Notice that, by 
using by using symbols to represent groups of several bits, we can reduce the rate at 
which the symbols are sent. In other words, if our bit rate is 2Mbps, then by using symbol 
to represent groups of 2 bits each, the signal rate is one-half the bit rate, or 1Mbps.  
When we are doing different phase modulation, we might choose different phase 
angles for different data bits. In QPSK, each group of two bits (one symbol) is 
 19 
represented by a different phase angles, 90 degrees apart from each other (0o, 90o, 180o, 
270o). The phase can be changed ?90 deg or 180 deg. We can write the QPSK signal as  
)](cos[)( ttAts ii ?? +?=                                        (3-4) 
where A is the carrier amplitude, i is an integer, and ?i(t) is the changeable phase 
 angle of the modulated signal with respect to the un-modulated waveform. 
iti ?= 2)( pi?  where .3,2,1,0=i                                    
As mentioned earlier, each symbol represents a group of two bits. Therefore, the 
symbol rate of QPSK is half the bit rate of BPSK. This means that the variety of carrier is 
half rate of BPSK in the time domain response. The spectrum is only ? as wide as that of 
BPSK for a given bit rate. 
In order to implement QPSK in DDS, the only thing we need to do is adding proper 
data value to the highest two MSBs. Here we assign 0, 90, and 180, 270 degrees to 
represent 00, 01, 10, and 11 relatively.  
Then another question comes, how to split one serial data stream into two parallel bit 
streams and each at one-half the rate of the original data? (Since two parallel bits convert 
to a phase change). Figure 3-3 shows the block diagram for a digital de-multiplexer that 
does this. The first two D-flip-flops take duty of alternating bits of serial data. The third  
one adds a 1-bit period delay to realign the two bit streams. 
g39g68g87g68
g39g3g3g3g52
g52g16
g39g3g3g3g52
g52g16
g39g3g3g3g52
g52g16
g38g47g46g18g21 g38g47g46
g52
g44g39g68g87g68
g71g72g80g88g79g87g76g83g79g72g91g72g85
 
Figure 3-3 Data de-multiplexer for QPSK 
 20 
Figure 3-4 shows the time domain response for QPSK. The phase of the carrier wave 
can be changed 0 degree, 90 degree, 180 degree and 270 degree. 
g19
g20
g19 g19
g20
g44g16g39g36g55g36
g38g36g53g53g44g40g53
g19 g19 g19
g20 g20
g52g16g39g36g55g36
 
Figure 3-4 QPSK in time domain  
3.3.3 OQPSK 
Large amplitude variation in the QPSK waveform happened whenever the phase 
was changed by 180 deg. Sometimes, we might expect that if we could made the phase 
transition more gradual, then the QPSK waveform might be more tolerant to limiting. 
OQPSK is introduced for this purpose. In one symbol, there is only one bit changing, the 
other one remains. In order to implement this function, a new data de-multiplexer is 
shown in figure 3-5. We simply remove the third D-flip-flop, then there is a 1/2 bit delay 
between I data and Q data. Every time the symbol changes, only one bit changes. 
Consequently, there is no 180 degree phase transition, only ?90 degree change. 
g39g68g87g68
g39g3g3g3g52
g38g79g78
g39g3g3g3g52
g38g79g78
g43g68g79g73g3g39g68g87g72
g53g68g87g72
g52
g44
g68g21g3g3g68g23g3g3g68g25
g68g20g3g3g68g22g3g3g68g24g39g68g87g68g71g72g80g88g79g87g76g83g79g72g91g72g85
g39g72g79g68g92
g82g81g72g3g69g76g87
 
Figure 3-5 Data de-multiplexer for OQPSK 
 21 
Figure 3-6 shows the time domain response for OQPSK. The phase of the carrier 
wave only changes ?90 degree. Here we assign 0, 90, and 180, 270 degrees to represent 
00, 01, 11, and 10 relatively. 
g19
g20
g19 g19
g20
g44g16g39g36g55g36
g38g36g53g53g44g40g53
g19 g19
g20 g20
g52g16g39g36g55g36
g20
 
Figure 3-6 OQPSK in time domain 
3.4 Frequency Modulation in DDS  
Instead of breaking the phase angle into discrete pieces, sometimes we change the 
phase angle from one value to another smoothly (calls Frequency shift keying).  
Recall that frequency is the derivation of phase 
t
tt
?
?= )()( ??                                                   (3-5) 
Smooth, continuous phase modulation corresponds to frequency modulation. An 
FSK signal is given by: 
))cos(()( ??? ++?= tAtS iRFFSK                                  (3-6) 
where A is the amplitude of the carrier signal (a constant), ?RF is the nominal frequency 
of the carrier, ? is an arbitrary phase, and ?i is the change in carrier frequency that 
determines what bits have been transmitted. 
 22 
3.4.1 MSK (Minimum shift Keying) 
In the MSK, the carrier gradually changes phase by ?90 deg over a bit period. Since 
the phase will continue to advance or retard itself over the course of each bit period, the 
frequency is varied. It can be represented by:  
The frequency difference due to the input data value is shown below [14].   
44
1
2
1
22
1
2)(
d
dd
f
TTtf ==?=??
?=?=+?
pi
pi
pi
?
pi
?                           (3-7) 
44
1
2
1
22
1
2)(
d
dd
f
TTtf
?=?=??=?
?
?=?=??
pi
pi
pi
?
pi
?                           (3-8) 
d
d Tf
1= , 
df is the bit rate and Td is the bit period. 
The frequency difference: 
2)()(
dfff =???+?                                                (3-9) 
We can see in MSK the frequency difference that corresponds to a 90-deg phase 
advance or lag over a bit period is equal to one-half the bit rate. Therefore MSK can be 
easily implemented in a DDS -- to use MSK input data to toggle two frequency words 
corresponding to Fc ? Fd/4, where Fc is the carrier frequency and Fd is the input MSK 
symbol data rate (shown in Figure3-1). When MSK data is zero, the DDS Frequency 
Control Word is given by Fc ? Fd/4, which causes a continuous phase retardation of 90? 
within one bit period 1/Fd. When MSK data is 1, the DDS output frequency is given by 
Fc + Fd/4, which causes a continuous phase advance of 90? within one bit period 1/Fd. 
 As a result, the DDS output can be written as: 
( ) ( )tFtFtFtFtFFS CbCbbC ???
?
??
?
? ??????
?
??
?
? ??=
???
?
???
? ?
?
??
?
? ?= pipipipipi 2cos
2sin2sin2cos42sinout
 (3-10) 
 23 
As shown, the DDS output is an MSK signal, which can also be thought of as OQPSK 
with sinusoidal pulse shaping on the base-band signal. When base-band MSK data is 1, the 
DDS FCW is given by Fc + Fb/4, which causes a continuous phase advance of 90? within 
one bit period 1/Fb. 
Figure 3-7 shows the time domain response for MSK. Here we assign fcarrier=fdata. The 
frequency of the carrier toggles between two different frequency 3/4 fcarrier and 5/4 fcarrier, 
according to the data value 0 and 1 respectively.  
g19
g20
g19 g19
g20
g44g16g39g36g55g36
g38g36g53g53g44g40g53
 
Figure 3-7 MSK in time domain 
3.4.2 GMSK (Gaussian MSK) 
On the other hand, the transmitted spectrum of MSK is sometimes too wide for 
many applications. One way to narrow the transmitted spectrum of MSK is by filtering 
the modulation signal before applying it to the DDS. This can be done by passing the 
modulation signal through a low-pass filter. Also, the filter needs to have a well-behaved 
time domain response. Therefore Gaussian filter is used before the modulators. 
In this chapter we use FIR architecture to implement the Gaussian Filter. 
Fundamentally, an FIR is a very simple structure. There is nothing more than a chain of 
delay, multiply, and add stages. Each stage consists of an input & output data path and a 
fixed coefficient (a number which serves as one of the multiplicands in the multiplier 
section). It is told that increasing N will increase the overall delay through the FIR [15]. 
 24 
This can be a problem in systems that are not delay tolerant. However, there is a distinct 
advantage to increasing N; it increases the sharpness of the filter response. 
Examination of the FIR structure in figure 3-8 leads to an equation for the output y(n), 
in terms of the input x(n) for an FIR of arbitrary length N. The result is: 
)1(....)2()1()()( 1210 ??++?+?+= ? Nnxanxanxanxany N        (3-11) 
(ai is the Gaussian coefficient) 
g59
g59
g59
g59
g14
g14
g14
g61g65g11g16g20g12
g61g65g11g16g20g12
g61g65g11g16g20g12
g59g11g81g12
g59g11g81g16g20g12
g59g11g81g16g21g12
g59g11g81g16g49g16g20g12
g68g19
g68g20
g68g21
g68g49g16g20
g60g11g81g12
g68g20g59g11g81g16g20g12
g68g19g59g11g81g12
g68g21g59g11g81g16g21g12
g68g49g16g20g59g11g81g16g49g16g20g12
 
Figure 3-8 FIR filter structure 
We use following equations to determine the Gaussian coefficient  
)exp()( 2
22
?
pi
?
pi tth ?=                                          (3-12) 
B2
2log=?                                                   (3-13) 
Here B is the filter?s 3-dB bandwidth. The BT product parameter is B times the 
input signal?s symbol period. We let it be 0.5 in our design.  
Examination of the above figure leads to an equation for the output, y(n), in terms of 
the input, x(n) for an FIR of arbitrary length, N. The result is: 
 25 
)1(....)2()1()()( 1210 ??++?+?+= ? Nnxanxanxanxany N             (3-14) 
Application of the z-transform leads to the transfer function, H(z), of an N-tap FIR 
filter.  
)1(
1
2
2
1
10 .....)(
??
?
?? ++++= N
N zazazaazH                       (3-15) 
Earlier, it was mentioned that increasing the number of taps in an FIR increases the 
sharpness of the filter response. Here, we give two instances which are plots of a 10-tap 
& a 2-tap FIR. All coefficients are equal to 0.1.  
g43g11g73g12
g3g19
g19g17g24
g20g17g19
g20g17g24
g3g3g3g20g19g19g19 g21g19g19g19 g22g19g19g19 g23g19g19g19 g24g19g19g19
g43g11g73g12
g3g19
g19g17g24
g20g17g19
g20g17g24
g3g3g3g20g19g19g19 g21g19g19g19 g22g19g19g19 g23g19g19g19 g24g19g19g19
g41g85g72g84g3g11g43g93g12
g41g85g72g84g3g11g43g93g12
g21g16g55g68g83g86
g20g19g16g55g68g83g86
 
Figure 3-9 FIR with different taps 
The main null ends at 1kHz for the 10-tap FIR, instead of at 5kHz for the 2-tap FIR. 
Another point should be mentioned, that the response of the FIR is completely 
determined by the coefficient values. By choosing the appropriate coefficients it is 
possible to design filters with just about any response; low-pass, high-pass, band-pass, 
band-reject, all-pass, and more [16].  
Figure 3-10, Figure 3-11, Figure 3-12 shows a design example of a 16 taps Gaussian 
filters. The input data is NRZ with a rate at 3MHz (bit period T= 6103 1? ). And this 
Gaussian filter?s 3-dB bandwidth B=600 KHz; Thus BT=0.2.  
 26 
Figure 3-10 shows the Gaussian function in time and frequency domain; Figure3-11 
shows the input data in time and frequency domain; and Figure3-12 shows the data in 
time and frequency domain, which has went through the Gaussian filter. From these 
figures, we can see that, the Gaussian filter obviously minished the signal?s frequency  
spectrum without bit errors. 
0 1 2 3 4 5 6 7 8
x 10-6
0
2
4
6
second
am
pli
tud
e
-8 -6 -4 -2 0 2 4 6 8
x 106
0
20
40
60
80
frequency
ma
gn
itu
de
 
Figure 3-10 Gaussian waveform with 16 taps 
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 10-5
-0.1
-0.05
0
0.05
0.1
second
am
pli
tud
e
-8 -6 -4 -2 0 2 4 6 8
x 106
0
1
2
3
frequency
ma
gn
itu
de
 
Figure 3-11 Input data  
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 10-5
-0.5
0
0.5
second
am
pli
tud
e
-8 -6 -4 -2 0 2 4 6 8
x 106
0
50
100
150
200
frequency
ma
gn
itu
de
 
Figure 3-12 Gaussian filter?s output 
 27 
3.5 Test Results  
In this digital modulation verification, AD7303 (provided by AD company) is used. 
It is a dual, 8-bit voltage out DAC that operates from a single +2.7 V to +5.5 V supply. 
Its on-chip precision output buffers allow the DAC outputs to swing rail to rail. And all 
the digital functionality was implemented in a filed programmable gate array (FPGA) 
board provided by Digilent Company. 
A design example is given below with these parameters: bit length of phase 
accumulator =10, bit length of sine look-up table =10, bit length of DAC output =8.  
3.5.1 BPSK   
The carrier frequency is 48.8 KHz and the data rate is 32.6 KHz. The Data stream is 
0 1 1 1 1 0 0, so carrier sine wave will add 180 degree at second data period and remove 
180 degree at fifth data period. Each inversion of the carrier causes a sharp transition in 
the time domain response.  
 
Figure 3-13 BPSK wave 
3.5.2 QPSK  
The carrier frequency is 48.8 KHz and the data rate is 65.6 KHz. Data stream is 0 1 1 
0 1 0 1 0 0 0 0 0 0 0 01. After the de-multiplexer, the data split into two stream and each 
two bits represents one phase variation. The symbols 01, 10, 10, 10, 00, 00, 00, 01 
 28 
represent the output phase changes 180 degree, 0 degree, 0 degree, -90 degree, 0 degree, 
0 degree, 90 degree respectively.  
 
Figure 3-14 QPSK wave 
3.5.3 OQPSK 
The carrier frequency is 48.8 KHz and the data rate is 65.6 KHz. Data stream is 0 1 1 
1 1 1 1 1 1 0 1 0 0 0 0 0. After the de-multiplexer, the data split into two stream and each 
two bits represents one phase variation. Since there is a half bit delay of one stream, there 
is only one bit changing each time. The symbols 01, 11, 11, 11, 10, 10, 00, 00 represent 
the output phase changes -90 degree, 0 degree, 0 degree, 90 degree, 0 degree, 90 degree, 
0 degree respectively. We noticed that the largest phase change is 90 degree. 
 
Figure 3-15 OQPSK wave 
 29 
3.5.4 MSK  
The carrier frequency is 44 KHz and the data rate is 48 KHz. Therefore, 
5641 =+ bC FF KHz  and 3241 =? bC FF KHz. Data stream: 0 0 1 0 1 0; the output 
frequency will be 32kHz, 32kHz, 56kHz, 32kHz, 56kHz, 32kHz respectively, during 
each period new data bit transfers.  
 
Figure 3-16 MSK wave  
3.6Conclusion 
Effective architecture used for BPSK, QPSK, OQPSK, MSK and GMSK have been 
proposed. The implementation was simplified by the use of DDS block, due to its own 
characteristics, which own high operation speed and high accuracy. Besides, FIR filter is 
discussed for narrow spectrum in GMSK.  
From the test and simulation results it is clear that the introduced DDS modulation 
structure achieved our design goal. It goes without saying that this structure is good for 
reuse. The future research goal will be in terms of comparing the spectrums, bit errors, 
inter-symbol interference among these modulations, and make them meet the specific 
requirements in applications. 
 30 
CHAPTER 4 PHASE-LOCKED LOOP OPERATION THERORY 
4.1 Introduction 
In semiconductor industry, phase locked-loop has a long history and a wide range of 
applications. PLL-based synthesizers are among the most common ways to implement 
synthesizers, and this filed attracts a great deal of attention and interest. 
Different from DDS that generates the output frequency directly by setting input 
frequency control words, PLL is a feedback system that causes a particular system to 
track with another one. More detailed, we embed oscillators in a synthesizer environment 
so as to synchronize the output signal with a reference or input signal in frequency as 
well as phase. The comparing block in the circuit is commonly called a phase frequency 
detector. Actually, in a locked state, the frequency and phase errors between the 
oscillator?s output signal and the reference signal are zero. The operation mechanism 
working on the PLL will clear up the phase error once it finds there exists one. As a result, 
the output signal is really locked to the reference signal. A typical PLL structure is shown 
in Figure 4-1 [17].  It includes phase/frequency detector, loop filter, oscillator and  
frequency divider. 
g51g75g68g86g72g18g41g85g72g84
g39g72g87g72g70g87g82g85
g47g82g82g83
g41g76g79g87g72g85 g50g86g70g76g79g79g68g87g82g85
g41g85g72g84g88g72g81g70g92
g39g76g89g76g71g72g85
g41g85g72g73 g41g82g88g87
 
Figure 4-1 Typical PLL frequency synthesizer 
 31 
4.2 Integer-N PLL Synthesizer 
Synthesizers often require that the output frequency of a PLL be a multiple of the 
input frequency. As shown in Figure 4-1, to amplify the input, the output signal is divided 
down before it is fed back. Here, the N called the ?modulus? refers to the frequency 
divider?s divide ratio in the feedback circuit. Therefore, at locked state, the output 
frequency, which is a multiple of the feedback signal, is given by  
refout fNf ?=                                                 (4-1) 
As we know, the frequency synthesizer generates an output frequency can be given 
by chout kfff += 0 , where 0f is the lower end of the range, k is an integer varying from 0 to 
the maximum number of channels and the chf is the frequency step. Consider with (4-1), 
the outfN ?  is to be equal to chkff +0 , where N varies in unity step from NL to NH. Then,  
for the first channel (k=0), we have 0ffN refL =? ; for the second channel, 
chrefL fffN +=?+ 0)1( , implying that refch ff = . The important point here is that the 
 input reference frequency must be equal to the channel spacing. As a result, in order to 
get a smaller step size, the reference frequency must be made smaller.  
4.3 Charge Pump PLL 
Charge pump PLL frequency synthesizer is widely used for its simple structure and 
good performance. In the loop filter considered in Figure 4-1, the average value of the 
phase detector output is obtained by depositing charge on to a capacitor during each 
phase comparison and allowing the charge to decay afterwards. On the other hand, if a 
phase detector is connected to a charge pump, there is negligible decay of charge between 
phase comparison instants. A typical charge pump PLL is composed of a phase detector, 
charge pump, loop filer and VCO as shown in figure 4-2. 
 32 
g51g75g68g86g72
g39g72g87g72g70g87g82g85 g57g38g50
g39g76g89g76g71g72g85
g56g83
g47g72g89g72g79
g39g82g90g81
g47g72g89g72g79
g41g85g72g73
g57g39g39
g42g49g39
g38g20
g53
g41g71
 
Figure 4-2 Charge pump PLL 
The charge pump PLL works as follow. The pump itself consists of two switched 
current sources driving a capacitor. The current sources controlled by the outputs of PFD 
charge and discharge the loop filter capacitors to generate the voltage control signal to 
VCO. Phase detector transforms the phase or frequency error signal to two switching 
signal UP and DOWN with corresponding pulse width. If the fref > fd, the positive 
charge accumulates on C1 steadily. Similarly, if the fref< fd, the I2 removes charge from 
C1 on every phase comparison. If the output of phase detector is 0, the voltage on 
capacitor remains constant.  
Compared with conventional PLL, charge pump PLL has three main advantages: (1) 
The capture range is only controlled by the VCO output frequency range; (2) If the 
mismatches and offsets of the two branches currents are neglected, the static phase error 
is zero; and (3) The certain amount of time to lock on the frequency of an incoming 
signal is short and the synthesizer?s switching speed is fast. Moreover, the open-loop 
transfer function of it has two poles at the origin and root locus shows that more stability 
of the PLL is achieved with the increasing loop gain.  
 33 
The whole loop dynamics can be analyzed by the linearized mode of each component 
in the PLL. The PFD has a gain of KPFD, the loop filter has a transfer function F(s), and 
the VCO has a gain of Kvco/s. Suppose the loop begins a phase error ?ref-?d=?e. The 
average current charging the capacitor is given by I?e/(2pi). The average change in the 
control voltage after the loop filter is: 
)/1(2)( 1sCRIsV ectrl += pi?                     (4.2) 
The output phase from VCO is: 
sKvcosVs ctrlout /)()( =?                                           (4.3) 
We obtain the following closed-loop transfer function:  
)2/()2/(
)2/()1(
)(1
)()(
1
2
11
CKvcoIsRKvcoIs
CsRCKvcoI
s
ssH
out
out
pipi
pi
?
?
?+???+
+?=
+=          (4.4) 
The loop transfer function has a zero at ?z=-1/(RC1). And the second order system 
has two important parameters, n?  is proportional to loop bandwidth and independent of 
R; 
)2/( 1CKvcoIn ??= pi?                                          (4.5) 
)2/()2/( 1 pi? KvcoCIR ???=               (4.6) 
Suppose the divider modulus changes form M to N+k and k<<N, the frequency 
settling time inside the loop is: 
)1/(ln()/1( 2???? ??? Nkt ns                  (4.7) 
Note that the decay time constant of the system is equal to (1/???n)=4pi/(R?I?Kvco) 
which is independent of C1.  
 34 
In many cases, how to maximize the loop bandwidth and shorten the settling time is 
highly desired. This can be achieved by increasing the pump current I and VCO?s 
coefficient Kvco as shown in (4-4). However, as the loop bandwidth becomes 
comparable with the input reference frequency, the loop would become unstable. Usually, 
loop bandwidth ?n should meet equation (4.7) for the stability of the loop d1 [18].  
)/( 2122 pipi??? +< refrefn RC            (4.8) 
   In typical design, the loop bandwidth is roughly one-tenth of the input frequency to 
guarantee stability. 
The loop filter in figure 4-2 indicates that the loop is a second order system. In 
practice, another capacitor C2 is added in parallel to the R and C1. C1 produces the first 
pole for the loop filter and C2 is used to smooth the control voltage ripples and to 
generate the second pole. This modification leads the system to a third order system.  
4.4  Fractional-N Frequency Synthesizer 
In the integer-N architecture, the loop bandwidth is limited and the input reference 
must be equal to the channel spacing. This is often undesirable, so instead, a fractional-N 
design is often used. Instead of an integer-N divider, we put a fractional frequency 
divider in the feedback of PLL, shown in Figure 4-3. It allows the PLL to operate with 
high reference frequency while achieving a small step size. The fractional divider is 
usually a multi-modulus divider (MMD). A modulus control signal is used to toggle 
different modulus at each reference period. 
 35 
g51g75g68g86g72
g39g72g87g72g70g87g82g85 g57g38g50
g48g48g39
g56g83
g47g72g89g72g79
g39g82g90g81
g47g72g89g72g79
g41g85g72g73
g57g39g39
g42g49g39
g38g20
g53
g41g71
g38g21
g48g82g71g88g79g88g86
g38g82g81g87g85g82g79
 
Figure 4-3 Fractional-N PLL frequency synthesizer 
For a two modulus divider case, the divider can divide the input signal from VCO by 
N or N+1. Assume that the divider divide By N for A reference cycles and N+1 for B 
reference clock cycles. The Navg is defined as the average division ratio: 
)]1/(//[)( +++= NBNABANavg              (4-9) 
This value can vary between N and N+1 in fine steps by proper choice of A and B. 
Thus the frequency step can be a fractional of reference signal and fractional-N 
synthesizer can have a higher reference frequency and higher loop bandwidth without 
stability problem. For example, with the reference frequency in the range of tens of 
megahertz, the loop bandwidth of a fractional-N synthesizer can be as high as a few 
megahertz, yielding a fast settling time of the PLL and suppressing the noise contributed 
by the VCO. Furthermore, the smaller division ratio lower the effect contributed by the 
reference source, the PFD, the charge pump noise [19] [20]. 
 Replacing the dual-modulus divider with a MMD in PLL can be modified to a more 
generic form. It is possible to have a much smaller frequency step with the same 
 36 
reference frequency comparing to the traditional PLL synthesizer. The synthesizer output 
frequency is given by [2]. 
 ?????? += FKIRff ro                                                 (4-10) 
where I is the integer portion of the frequency divider and, depending on the 
complexity of the design, I could have many possible integer values. For example, if loop 
division ratio 200.75 is needed, we can program I=200, K=3 and F=4. The MMD 
division ratio is toggled between 200 and 201. 
A popular MMD topology used cascaded 2/3 cells. With an n-bit (P1~Pn) modulus 
control signal, the MMD division ratio is shown as: 
n
n
n
n
n PPPPN 222...2 1
1
2
2
1
1 ++++=
?
?
?                             (4-11) 
4.5 Fractional Spurs 
The alternation modulus of the divider cause the output frequency can vary among 
different division ratios. However, it suffers from a common side effect of generating 
spurious components. As we know, any repeated pattern in the time domain causes 
spurious tones in the frequency domain. The fractional accumulator periodically 
generates the carry-out that toggles the loop division ratio. And if this frequency falls 
inside the loop bandwidth, large spurious tones are expected. One way to suppress these 
tones is have a very small PLL bandwidth, which negates the potential benefit of the 
fractional-N technique. 
Since the phase difference between the feedback and reference signals grows to 
significant values, the amplitude of loop filter output waveform is quite large, yielding 
fractional spurs only 20dB below the carrier magnitude [1]. Consequently, several 
 37 
methods introduced to suppress these spurs. One is known as the ?fractional 
compensation?. If the divider's alternating modulus is deterministic, the current generated 
by the charge pump can be compensated by another current pulses that with the same 
alternating process but an opposite sign. This technique depends on highly accuracy of 
the compensation currents [21].  
The other way to eliminate fractional spurs is to randomize the sequence of the 
modulus so as to break up their periodicity. With the randomness of the modulus, the 
average division modulus can still be achieved and the fractional spurs are converted into 
white noise. The white noise inside the PLL?s bandwidth is integrated by the PLL 
transfer function and introduces phase noise contribution no mater what PLL bandwidth 
is. 
Delta-sigma fractional-N PLL can solve this problem by shaping the noise spectrum 
to higher frequency offsets [22] [23]. It generates the sequence of modulus such that the 
quantization noise has most of its power in a frequency band well above the desired 
bandwidth of PLL. 
 38 
CHAPTER 5 RFIC DESIGNS FOR AN INTEGRATED PLL IN 0.5 UM SIGE 
TECHNOLOGY 
5.1 Introduction 
In semiconductor industry, Phase locked-loop has a wide range of applications. Also 
it is another very important frequency synthesizer in RF system.  
In this chapter, we will discuss the RFIC design of each main block in a fractional-N 
PLL: reference buffer, phase frequency detector, charge pump bias current setting, 
programmable charge pump, LC-tuned VCO, programmable divider and multiple 
modular divider (off-chip loop filter is used). Among these blocks, the integrated VCO is 
very important one. Even though the wideband loop can suppress the noise from the 
VCO, the suppression may not be enough because the integrated VCO is noisy, and the 
loop bandwidth cannot go arbitrarily high. A careful designed VCO is crucial in 
achieving a high performance frequency synthesizer. On the other hand, MMD and 
programmable divider consume more than three-quarter of PLL power, need to run at 
very high operation speed and contribute to a significant part to the in-band phase noise, 
thus they should be also key blocks in phase lock loop. Then how to use less current and 
simple structure to achieve the high speed and less noise is our goal. Of course, phase 
frequency detector, charge pump, and loop filter are also important in realizing a high 
performance frequency synthesizer. Fig. 5.1 shows the fractional-N PLL block diagram 
 39 
g53g72g73g72g85g72g81g70g72
g37g88g73g73g72g85
g51g75g68g86g72
g39g72g87g72g70g87g82g85
g38g75g68g85g74g72
g51g88g80g83
g38g88g85g85g72g81g87
g54g72g87g87g76g81g74
g47g51g41
g50g73g73g16g70g75g76g83
g24g42g43g93
g57g38g50
g11g49g72g74g68g87g76g89g72g12
g51g85g82g74g85g68g80g80g68g69g79g72
g39g76g89g76g71g72g85
g53g41g66g50g56g55g51g56g55
g48g3g48g3g39
g38g85g92g86g87g68g79
g50g86g70g76g79g79g68g87g82g85
g56g83
g47g72g89g72g79
g39g82g90g81
g47g72g89g72g79
 
Figure 5-1 Block diagram of a PLL 
5.2 Current Mode Logic  
When we design low frequency logic circuits, CMOS rail to rail is the most 
commonly used type, for its DC power consumption is zero [24]. However, the 
integration of digital functions with sensitive RF signal processing blocks is hard to 
achieve when using the standard rail-to-rail logic techniques. The reason is the generation 
of large supply and substrate disturbances during logic transitions. Besides the rail to rail 
logic output changes by a large amount and requires larger charge and discharge time and 
can not achieve high speed operation. Therefore, the current mode logic (CML) has been 
introduced and employed in the high-speed digital systems for it very fast switching 
property.  
The basis of all CML is the differential pair [25][26]. That means the input signal 
should have large enough voltage to switch the differential pair in digital applications. 
For bipolar, when the differential voltage is approximately four times of thermal voltage 
or larger, the input pair can be completely switched.  
Normally, the CML circuit is composed of several differential pairs which are tied 
together either in series or parallel with a constant current source at the bottom. When the 
 40 
circuit works, only one branch of each pair switches on at one time and the current is 
flowing through only one path from power supply to ground. Figure 5-2 shows a four 
level 3-input circuit. It is a three inputs AND gate. Here, one of the two resistors pulls 
down the output voltage from VCC to VCC-IBiasRL when bias current flowing through it. 
Then the output differential swing is thus 2IBiasRL. If we want to keep the output swing, 
when the bias current is increase, the resistance of RL should decrease to keep the 
product.  
RL R L
V D D
A
Sum
B
C
Sum
C
B
A
V D D
IB ias
Level1
Level2
Level3
 
Figure 5-2 A CML circuit 
In this research work, with a 3.3 V supply, CML makes it possible to have three level 
inputs which are bias at 3.2V, 2.3V and 1.4V so as to make sure the transistors not work 
in saturation mode. And these inputs share one constant current source, which would 
greatly save the power consumption. (Since more logic gates mean more current streams, 
when we use the CML structure to combine two logic functions together, the power 
consumption would be greatly saved.)  
 41 
Generally speaking, with CML circuits, more current results faster operation. In order 
to achieve maximum speed, it?s a good decision to make the bias current as large as 
possible by setting it to peak fT. However, more current means more power consumption, 
and latter is also a very important specification in RF IC design [27][28]. Thus, we need 
to make a good choice to balance these two.  
5.3 Multi-Modular Divider with Extension  
Synthesizers often require that the output frequency of a phase locked loop be a 
multiple of the input frequency. A PLL can ?amplify? a frequency such as a feedback 
circuit amplifies a voltage. Since the output of a PLL is the frequency, a frequency 
divider must be inserted in the feedback loop, dividing the oscillator output down to the 
reference frequency. As PLL definition says when the loop is locked, ?ref =?div, and 
hence ?f =?vco/M.  If there is only one modular, the VCO output changes by only integer 
multiples of input reference frequency, thus the input reference must be equal to the 
channel spacing. Actually, sometimes the output frequency need vary by a fraction of the 
input frequency, which allows the latter to be much greater than the channel spacing. This 
kind of divider is dynamically switched among different divide ratios to generate the 
equivalent of a fractional-divider ratio. 
5.3.1 Architecture 
Actually, the oscillator drives the divider input and, since this is the highest frequency 
in the circuit, speed is a big challenge in divider design. Also in RF design, high speed 
requires big operation current. So power dissipation is a problem too.  Here we discuss a 
multi-modular divider. In this case, at each subsequent stage, the speed is lower, and the 
 42 
power dissipation is reduced. Fig 5-3 [29] shows the programmable MMD architecture 
we used in the design. 
g21g18g22
g39g76g89g76g71g72g85
g21g18g22
g39g76g89g76g71g72g85
g21g18g22
g39g76g89g76g71g72g85
g21g18g22
g39g76g89g76g71g72g85
g21g18g22
g39g76g89g76g71g72g85
g50g53
g49g82g87
g51g19 g51g20 g51g21 g51g25 g51g26 g51g27
g41g76g81 g73g19 g73g20
g73g25 g73g26
g80g82g71
g41g82g88g87
 
Figure 5-3 8 bit MMD architecture with extension 
The modular structure consists of a chain of 2/3 divider cells and the feedback lines 
are only present between adjacent cells. This ?local feedback? enables less operation 
delay and simple optimization of power dissipation. A D-flip-flop clocked by the VCO 
can be placed at the MMD output so that the noise from the divider does not contribute at 
the output of the PLL. The noise from the PFD, charge pump and loop filter is multiplied 
by the MMD?s divide-ratio at the output of the PLL. 
We can briefly describe the MMD operation. Once in a division period, the last cell 
on the chain generates the signal modn-1. This signal combined with the programming 
input P8 then propagates ?up? the chain, being re-clocked by each cell along the way. 
Pay attention here, no matter what value of modn-1, when P8 is 0, the input mod signal of 
(n-1) block is always 1 without any division. 
An active mod signal enables a cell to divide by 3, provided that its programming 
input p is set to 1. Division by 3 is adding one extra period of each cell?s input signal to 
the period of the output signal. Therefore, a chain of 2/3 cells provides an output signal 
with a period of 
 43 
TinppppTinp
pTinpTinpTin
pTinTinppTinpTin
Tout
n
nn
nn
nn
n
n
n
nn
nn
n
n
n
?+?++?++??+=
?+?++?+
?++??+?=
?
??
?
?
?
?
?
??
?
?
)2.......22()22(
2.....2
2222
012
21
1
1
013
3
2
21
1
1
   (5-1) 
In (4-1) Tin is the period of the input signal, and p0~pn-1 are the binary programming 
values of the cells 1 to n respectively. Pn is the binary input control for extension. The 
equation shows that all integer division ratios ranging from (if all p = 0)2n-1 to 2n+1-1 (if 
all p=1) can be realized. In our design, the n=8, so the divide ratio is from 128 to 511.  
5.3.2 Dual-Modular Divider 
g38g47g46 g38g47g46 g38g47g46 g38g47g46
g39 g39 g39 g39
g48g50g39g76g81
g41g76g81
g52 g52 g52
g52g16 g52g16
g51 g48g50g39g82g88g87
g41g82g88g87
 
 
Figure 5-4 2/3 divider cell 
 
A 2/3 divider cell comprises two functional blocks: AND gate and Latch (as depicted 
in Fig. 5-4) [30][31]. This block divides the frequency of the input signal either by 2 or 
by 3 and outputs the divided signal to the next cell in the chain as clock. The division 
ratio of the cell is based on the state of the modin and p signals. If the modin signal is 0, 
the divide ratio is always 2. When the modin signal becomes active once in a division 
cycle, the state of the p input is checked, and if p = 1, the end-of-cycle logic forces the 
pre-scaler to swallow one extra period of the input signal. In other words, the cell divides 
by 3. If p = 0, the cell stays in division by 2 mode. Regardless of the state of the p input, 
the end-of-cycle logic reclocks the modin signal, and outputs it to the preceding cell in the 
chain (modout signal). 
 44 
5.3.3 Circuit Implementation of The 2/3 Divider Cell 
g50g56g55g51g56g55g83
g50g56g55g51g56g55g81g36g49g39g11g22g76g81g83g88g87g86g12
g47g72g89g72g79g3g20
g76g81g83g88g87g86
g57g38g38g32g22g17g22g57
g47g72g89g72g79g3g21
g76g81g83g88g87g86
g47g72g89g72g79g3g22
g76g81g83g88g87g86
g57g85g72g73
 
Figure 5-5 CML circuit design  
In this circuit design, all digital blocks are using current-mode logic. The reason is the 
generation of large supply and substrate disturbances during logic transitions.  However, 
the CML circuits, due to its constant supply current and relatively smaller differential 
voltage switching operation, have better EMC properties. Besides, CML can reach much 
higher operation frequency than rail-to-rail logic. The logic functions of the 2/3 cells are 
implemented with the CML structure presented in Fig 5-5. The logic three combines an 
AND gate with a latch function. Therefore, seven logic functions are achieved by four 
small blocks and at expense of four tail currents only. 
The differential voltage swing is set to 400 mV and the three level inputs should be 
bias at 3.2V, 2.3V and 1.4V. The constant current source is set by current mirror with the 
same transistors and load resistances 
5.3.4 Power Dissipation Optimization 
As showing in Fig 5-3, the modular structure consists of a chain of 2/3 divider cells 
and the feedback lines are only present between adjacent cells. The absence of long delay 
 45 
loops in the architecture enables fast and reliable optimization of power dissipation, since 
simulation runs may be done for clusters of two cells each time [32]. 
When going through the circuit, we can see that there is a maximum delay between 
the mod and the clock signals in a given cell that still allows properly timed division by 3. 
The maximum delay is Tmax=1.5 * Tin where Tin is the period of the cell?s input previous 
one. As a consequence, the maximum allowed delay increases as one moves ?down? the 
chain. As the delay in a cell is inverse proportional to the cell?s current consumption 
(which is a property of current mode logic circuits), the currents in the cells may be 
scaled down as well. For high frequency, we use big current to operate; when it comes to 
lower frequency, we can use less current to drive. On the other hand, the input signal is 
not shared by all cells. It is only used for the last stage. Others use the outputs of anterior 
stages. In this case, there is no need to build a ?clock tree? to drive all blocks.  
When a D-flip-flop clocked by the VCO is added at the output of the MMD, the noise 
generated by the divider itself is bypassed Simulation of extracted MMD shows in Figure 
5-6. Input clock = 150p (6.7GHz), Division ratio 128; Output signal of MMD=19.2n  
(52.1MHz) 
 
Figure 5-6 MMD simulation 
 46 
5.4 Programmable Divider (divide ratio 1~8) 
The wireless communication market has greatly expanded to many aspects. And 
trends are moving towards lighter weight, smaller size, longer lifetime and higher 
operation speed.  On the other hand, due to the presence of a variety of standards 
covering different applications and employing a wide range of frequencies, having one 
portable device working for several standards with low power and low cost is highly 
desirable.  
The easiest way is to add a high speed programmable divider following the VCO. It is 
an area consuming solution for having several synthesizers each one designed for a 
specific standard.  
In ours circuit, we design a programmable divider whose modulus can be varied 
from 1 to 8. Programmability is achieved by sending the output signal back to the first 
D-flip-flop after the signal going through the new ?MUX?. Based on this structure, the 
modulus can be extended or changed depending on how many control bits and 
D-flip-flops to be chosen. 
5.4.1 Divider?s Architecture  
 
Figure 5-7 shows the divider architecture based on a MUX and a chain of DFFs.  
We first consider a simple ?1 status (when control bits ABC=000). The MUX chooses 
the clock signal and feed it back to the first DFF input. After the signal goes though the 
DFF chain, there is no frequency difference between the input and output except time 
delay. When the control bits (ABC) become 001, the input frequency is divided by 2. In 
this case, MUX chooses Q1- to feed back to the first DFF input. Therefore, the last three 
DFFs do nothing with the division ratio but time delay, only the first DFF output (Q1-) 
 47 
contributes to the division ratio [1]. And if the control bits change to 010, MUX chooses 
combination of Q1-Q2-. The divider employs first two DFFs together with an AND gate 
to create three states (Q1-Q2- =01, 10, 11, but no 00) , and the last two DFFs are only for 
time delay. For other division ratios, operational mechanism is very similar.  
g39g20 g39g21 g39g22 g39g23g52g20 g52g21 g52g22 g52g23
g38 g38 g38 g38
g38g47g46
g53 g53 g53 g53
g53g72g86g72g87
g52g20g16 g52g21g16 g52g22g16 g52g23g16
g36 g37 g38
g48g56g59
g27g3g76g81g83g88g87g86g3g16g3g20g3g82g88g87g83g88g87
g38g82g81g87g85g82g79g3g69g76g87
g36g49g39 g36g49g39 g36g49g39
g39g76g89g76g71g72g85
g50g88g87g83g88g87
g48g56g59 g82g88g87g83
g88g87 g39g76g89g76g71g72g71g69g92g20 g21 g22 g23 g24 g25 g26 g27
 
Figure 5-7 Programmable divider architecture  
Meanwhile, we notice that the reason of propagation delay is the feedback circuit 
(MUX) and the DFF chain. Since the DFF chain?s delay cannot make logic errors, MUX 
is the key block that determines the operation speed. 
Traditionally, there are two ways to implement multiplexer: one is composed of 
simple 2-1 MUX, shown in Figure 5-8 [33]. ABC determine which signal (D1~D8) goes 
through these 2-1 MUX circuits. The shortest signal path has three logic gates in series. 
Another structure built by AND, OR gates and decoder is shown in Figure 5-9.  In this 
architecture, input signals do not go through the decoder circuit, so the decoder does not 
contribute to the propagation delay. However, there are still at least three logic gates in 
the shortest signal path. More logic gates in series means more propagation delays. It 
 48 
greatly affects the operation speed. Therefore, how to decrease the number of logic gates 
in signal path is the key point of operation speed. Besides, the more logic gates are used, 
the more chip area and power consumption would take. 
g21g16g20
g48g56g59
g21g16g20
g48g56g59
g21g16g20
g48g56g59
g21g16g20
g48g56g59
g21g16g20
g48g56g59
g21g16g20
g48g56g59
g21g16g20
g48g56g59
g39g20 g39g21g39g22 g39g23g39g24g39g25 g39g26g39g27
g36
g37
g38
 
Figure 5-8 8:1 MUX composed by 2:1 MUX. 
 
g22g16g37g76g87g3g38g82g81g87g85g82g79g3g39g72g70g82g71g72g85
g36g49g39 g36g49g39 g36g49g39 g36g49g39 g36g49g39 g36g49g39 g36g49g39 g36g49g39
g50g53 g50g53 g50g53
g50g53
g36 g37 g38
g39g20 g39g21 g39g22 g39g23 g39g24 g39g25 g39g26 g39g27
 
Figure 5-9 8:1 MUX composed with decoder and logic gate.  
5.4.2 Logic Implementation of Digital Blocks 
1) Logic Implementation of 3 Bit Decoder 
The schematic of this control block is given in figure 5-10. It consists of three-input 
CMOS-CML gates.  Then the three single inputs will change to three differential pairs 
 49 
of inputs. This differential characteristic of CML makes it very easy to achieve additional 
?NOT? logic, just need to exchange positive and negative signals at inputs.  As we 
know only if the all inputs of the AND gate are one then output would be one, otherwise 
it is zero. We use this principle for our decoder design.  For 3-control-bit, we can get 8 
different logic combinations with using AND gates (A-*B-*C-), (A-*B-*C), (A-*B*C-), 
(A-*B*C), (A*B-*C-), (A*B-*C) (A*B*C-), (A*B*C). At each time, only one 
combination will be logic one. 
g38g48g50g54g16g38g48g47 g38g48g50g54g16g38g48g47 g38g48g50g54g16g38g48g47
g36g49g39 g36g49g39 g36g49g39 g36g49g39 g36g49g39 g36g49g39 g36g49g39 g36g49g39
g36 g37 g38
g36 g36 g37 g37 g38 g38
g27 g26 g25 g24 g23 g22 g21 g20  
Figure 5-10 3-bit decoder (8 outputs) 
2) Logic Implementation of Low-Power MUX 
The MUX presented in this paper takes advantage of CML characteristic -- the whole 
circuit shares only one constant current source. Figure 5-11 shows the details.  
MUX?s first and second level inputs connected to the DFF outputs and MUX?s 
outputs connected to the first DFF inputs. In channel 1, 2, 4, 6, 8, only first level has 
input signals, while second level put diodes there just for voltage bias. In channel 3, 5, 7, 
both first and second levels have input signals. And these two levels can be used as AND 
logic to combine the input signals. Here, we can save three AND gates shown in Figure 
5-7. 
 50 
The third level is the control level. We connected the decoder?s outputs to the third 
level inputs. During the operation, decoder has only one output to be logic high, while 
others are logic zero [34]. For instance, when ABC=000, the input 1 is logic high and the 
upper signals can go through the channel as circuit outputs, while other channels are 
closed and there are no signals pass through; when ABC=001, the input 2 is logic high 
and the combination signal Q1-Q2- go through the channel and are selected as outputs, 
while other channels are closed, etc.. In other words, the decoder?s outputs determine 
which channel works and which upper-level signals are chosen as MUX output.  
In this CML circuit, there are eight differential inputs in the first level. That caused 
parasitic capacitance which is somewhat effect the bipolar switching speed. However, 
comparing to the traditional MUXs with at least three level logic gates delay (shown in 
Fig 3), this structure takes advantage in operation speed. Furthermore, the new MUX has 
only one constant current source, while traditional ones have current source for each logic 
gate.  It goes without saying that the power greatly saves.  
Due to the bipolar characteristic, even there is only one transistor works at third level, 
other signal channel also have little current flows. But the leakage current in these 
channels are very small contrast to the working channel current. When the current source  
is 350uA, the working channel occupies 344uA, and others have only 6uA in total. 
g20
g57g38g38g32g22g17g22
g21 g22 g23 g24 g25 g26 g27
g70g79g78g83 g52g20g16 g52g20g16
g52g21g16
g52g21g16 g52g22g16
g52g21g16
g52g22g16 g52g22g16
g52g23g16
g52g23g16
g57g85g72g73
g52g81g3g16g3g39g20g81
g52g83g3g16g3g39g20g83
g38g40g47g47g20 g38g40g47g47g21
g47g40g57g40g47g3g20
g47g40g57g40g47g3g21
g47g40g57g40g47g3g22
g22g16g27g3g39g40g38g50g39g40g53
g36 g37 g38
g20 g21 g22 g23 g24 g25 g26 g27
 
Figure 5-11 ?NEW? MUX structure 
 51 
5.4.3 Programmable Division Ratio 
As we discussed earlier in the paper, the leakage current of un-working channel is 
very small. It could be very easy to expanding the division ratios without function mess. 
First, we add more DFFs to the DFF chain. Each DFF we add will increase two more 
division ratios. Second, expand the MUX circuit. If the division ratio is odd, add CELL1 
(Figure 5-11); if the division ratio is even, add CELL2. Each CELL corresponds to one 
division ratio. The good thing is even adding more cells to the MUX, the total current 
will keep at 350uA. Consequently, the power dissipation would be still the same. At last, 
we need to increase the decoder?s bits. Three-bit decoder can control eight division ratios, 
four-bit can control sixteen division ratios and N-bit can control n2 division ratios. 
The expanding operation based on ?copy & paste? existing blocks. So it will largely 
save design and layout time, be good for update quickly.    
In some cases, we just need some special division ratio. If the desired ratios are not 
big, this kind of programmable divider would be a good choice. For instance, divided by 
/2, /3, /5, /8, are needed, we can use only two control bits to choose these ratios; and only 
two CELL1 and two CELL2 are enough for building the MUX circuit. 
5.4.4 Simulation Result  
Simulation of extracted programmable divider is shown in Figure 5-12. The peak to 
peak sine wave is 200mV, and the input frequency runs at 7.5GHz. When this divider 
applied in a 5GHz PLL, the maximum input frequency of the divider is limited by the 
oscillation frequency of VCO. When it comes to the power consumption, the current 
drawn from the power supply can slightly vary with input frequency and division factor. 
For 7.5 GHz operation, the divider draws a maximum of 20.8 mA with 3.3 V supply.  
 52 
  
Figure 5-12 Programmable divider simulation 
 
5.5 Phase Frequency Detector 
A Phase/ Frequency Detector produced an output signal proportional to the phase/ 
frequency difference of the signals applied to its inputs. It significantly increases the 
acquisition range and lock speed of PLLs. Sequential phase/frequency detectors (PFDs) 
generate two outputs that are not complementary.  Illustrated in Figure 5-13 
g36
g37
g52g68
g52g69
PFD
g36
g37
g52g68
g52g69
 
Figure 5-13 Phase/frequency detector response with WA<WB 
The operation of a typical PFD is as follows. If the frequency of input A is greater 
than that of input B, then the PFD produces positive pulses at QA, while QB remains at 
zero. Conversely, if ?A <?B, then positive pulses appear at QB while QA = 0. If ?A =?B, 
 53 
then the circuit generates pulses at either QA or QB with a width equal to the phase 
difference between the two inputs. Thus, the average value of QA -- QB is an indication of 
the frequency & phase difference between A and B. The outputs QA and QB are usually 
called ?UP? and ?DOWN? signals. 
The most common implementation of the Phase/Frequency Detector is shown in 
Fig5-14 [1] 
g39 g52
g53g72g86g72g87
g39 g52
g53g72g86g72g87
g39g72g79g68g92 g36g49g39
g51g88
g51g71
g50g81g72
g50g81g72
g73g85g72g73
g73g71
g38g46
g38g46
g49g82g85
g49g82g85
g49g82g85
g49g82g85
g38g46
g53g72g86g72g87
g52
g36
g37
 
Figure 5-14 Implementation of PFD & DFF used in PFD 
The circuit consists of two edge-triggered, resettable D-flip-flops with their D inputs 
connected to logical ONE. Also it contains AND gate and buffer delay (on the feedback 
for reducing dead-zone problem) Signals A and B act as clock inputs of DFFA and DFFB, 
respectively. We note that a rising edge of either the reference frequency or the divider 
output frequency immediately causes the corresponding flip-flop?s output to go high. 
Once the other output is also high, the AND gate produces a one, which resets both 
flip-flops to zero states until the next rising edge of either input arrives. We can use NOR 
gate to build D-flip-flop simply (in Fig5-14). 
Simulation of extracted Phase-Detector (Compare 200MHz and 250MHz) is shown in 
Figure 5-15. The output of a PFD can be converted to DC in different manners. One 
approach is to use the outputs drive a charge pump. 
 54 
 
Figure 5-15 Phase/frequency detector simulation 
5.6Charge Pump & Programmable Bias Current Setting 
5.6.1 Charge Pump 
A Charge Pump is responsible for placing charge into or taking charge out of the loop 
filter, and therefore, moving voltage on the VCO up or down.   
As the input of charge pump is the output of phase/frequency detector and the PFD 
use CML, we implement the circuit illustrated in Fig 5-16[2] 
 
Figure 5-16 Charge pump with cascade current mirrors 
With a BiCMOS technology, the input differential pairs are made with bipolar 
transistor for ease of switching. Others are all CMOS. We use cascade structure here  
In this circuit, when both input differential pairs are low, they steer current either to 
line2 and line 5 and there is no current at the output. Mention that, with the Down signal, 
 55 
there is an extra current direction reversal because the current must be pulled downwards. 
When the Up pair is active and the Down pair is zero, the upper CMOS at the output line 
is turning on, and then the charge pump places charge into loop filter. When the Down 
one active, the lower CMOS at the output line is turning on, and then the charge pump 
takes charge from loop filter.  
5.6.2 Programmable Bias Current Setting 
Often there is a need to be able to adjust the current flowing in the charge pump either 
because the designer would like the flexibility of being able to adjust the loop bandwidth 
or because the exact charge pump current for best phase noise performance is not known 
with certainty before fabrication. The charge pump current can easily be made scalable 
with a simple circuit such as that shown below. This circuit takes the reference current 
produced by band-gap and the scale it up. Placing switches in series with the current 
mirrors allows the current to be programmed in binary steps, such that the output current  
I is give by : I =(8p3+4p2+2p1+p0)Iref [2].                
 Figure 5-17 Programmable current setting 
5.7 Loop Filter  
As mentioned in Chapter 4, VCO is normally controlled by voltage not current; we 
need to turn the current produced by charge pump back into a voltage. Furthermore, it is 
 56 
not desirable to feed pulses into the VCO. Therefore, a low pass filter is needed in the 
loop, called loop filter.  
If using a simple capacitor to convert current to voltage, the loop can not be 
stable[35]. Normally a combination of capacitors and resistors is used. The typical second 
order loop filter is shown in Figure 5-18. The frequency response of phase detector, 
charge pump is mainly determined by the loop filter. 
g53g20
g38g20 g38g21
 
Figure 5-18 A typical second order loop filter 
The The transfer function is given by[2]  
)1)(21(
)11()(
ssRCCCs
sRCsF
++
+=  , where
21
21
CC
CCC
s +=                   ( 5-2 ) 
There are one zero 11RC  and two poles 0 and
sRC
1 . Notice that at low frequencies, 
the response is dominated by the zero in transfer function; thus the circuit acts like an 
integrator. Frequency response is given in Figure 5-19 and 5-20 
g20g18g53g38g20 g20g18g53g38g86
g48g68g74g81g76g87g88g71g72
g53g72g86g83g82g81g86g72
g41g85g72g84g88g72g81g70g92
g42g68g76g81
 
 57 
Figure 5-19 Phase detector, charge pump, loop filter magnitude response 
1/RC1 1/RCs
Phase
Response
Frequency
Phase
 
Figure 5-20 Phase detector, charge pump, loop filter phase response 
The whole phase detector, charge pump and loop filter simulation is shown in Figure 
5-20. 
         
 
Figure 5-21 Charge pump and phase detector simulation 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 58 
 
 
 
CHAPTER 6 MEASUREMENTS AND CONCLUSIONS FOR 5 GHZ PLL IN                         
0.5 UM SIGE TECHNOLOGY 
6.1 Background 
The role of a frequency synthesizer is to provide a reference frequency for frequency 
translation in a transceiver. This means that the frequency synthesizer needs to generate a 
set of frequencies at the frequency bands of the standard. On the other hand, due to the 
presence of a variety of standards covering different applications and employing a wide 
range of frequencies, having one portable device working for several standards with low 
power and low cost is highly desirable. In this research work, we designed a synthesizer 
with 600MHz ~ 5.2 GHz output frequency. Except the off chip loop filter, a prototype 
based on the Fractional-N PLL architecture was fabricated in a 0.5?m 1-poly 4-metal 
SiGe process. 
6.2 Design Specifications  
The block diagram of the prototype shown in Figure 5-5: Phase Detector, 
programmable divider and MMD have differential input and differential output. Charge 
pump has differential input and single output while VCO has single input and differential 
output. the low-noise buffer following the MMD is differentially clocked by VCO?s 
output. 
6.2.1 Frequency Plan  
A good frequency plan is crucial to achieving all the specifications of different 
standards, with a minimal amount of hardware and power consumption. The frequency 
 59 
plan determines how the frequency translation of the carrier is performed in both receive 
and transmit paths. Therefore, the frequency plan determines the amount of hardware and 
power it takes to generate the reference frequency with the frequency synthesizer and has 
a significant impact on the overall synthesizer performance, namely, phase noise, 
spurious tones and the required power consumption.  
The first design choice is the reference frequency. It is desirable to develop a 
frequency plan where only one external reference oscillator is used. The phase noise 
performance of the external oscillator also influences the choice of the reference 
frequency. Currently, the available crystal oscillators on the market below 200MHz 
typically have a phase noise level below -145dBc/Hz at 50kHz offset frequency.  
The VCO?s running range is 4.7GHz~ 5.3GHz and the programmable divider?s 
division ratio is 1~8, thus the output frequency can by used in 802.11a, 802.11b, 
ETS1/BRAN HiperLAN/2, BlueTooth, CT2/CT2+ and etc[36]..  
The MMD?s division ratio ranges from 128 to 511. If we use 511 as a division ratio, 
then the phase noise of the crystal oscillator and phase detector and the divider is 
amplified by 511. With a big noise enhancement from the divider it is virtually 
impossible to meet the phase noise requirement for cellular applications using a wideband 
PLL with an integrated VCO. Furthermore, since the VCO?s lowest frequency in this 
design is 4.7GHz, with a 511 division ratio, the reference frequency would be very small. 
It would not good for the bandwidth and settling time. Therefore, the MMD ratio is 
chosen around the 130, and the reference frequency is chosen as 40MHz. The noise 
amplification of the crystal oscillator, phase detector, and dividers are obviously reduced, 
 60 
making it possible to implement a wide band PLL using an external low phase noise 
crystal oscillator. 
6.2.2 Loop Parameter Design  
The loop bandwidth of the PLL needs to be optimized in order to achieve minimum 
overall phase noise at the offset frequency where the performance is most critical. A 
40MHz reference frequency is chosen for the reason mentioned above. The loop 
bandwidth of PLL should be less than 1/10 of the reference frequency for the stability of 
the loop. For this design, the loop bandwidth is chosen to be about 100KHz for maximum 
suppression of the noise from the reference, loop filter and phase detector. 
Fig. 5.18 shows one way to implement the loop filter based on an RC network. 
Knowing the desired loop bandwidth, we can determine the RC parameters of the loop 
filter by leaving enough phase margin for the loop. The value of C2 is usually less than 
1/5 of the C1 for not increasing the loop settling time. For a 100 KHz bandwidth, it is less 
than 1/10 of crystal input reference to guarantee the loop stability. Here, we pick R=10K, 
C1=11nF, C2=1.1nF. 
 
 
 
 
 
 
 
 
 61 
6.3 Layout photo and Simulation results   
The whole chip layout is shown in Figure 6-1. It occupies 3.1?2.56 mm2 area and 
consumes 431.97mw under 3.3 V power supply in simulations.  
 
Figure 6-1 Die photo of the PLL in 0.5um SiGe technology 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 62 
An open-loop simulation results using Cadence are shown in Figure 6-2. The first row 
shows the output of VCO runs at 4.75GHz with a 3.3V voltage control. The second row 
shows the output of MMD with a division ratio 256. The peak to peak amplitude is 
200mV for a single output of a differential pair. The third row shows a 20 MHz square 
wave is applied to the reference frequency. The forth row shows the difference between 
the reference frequency and the MMD outputs at the phase detector outputs. In this case, 
the reference frequency is much faster than the MMD output, and the VCO has negative 
gain. Therefore, the voltage at the filter?s output should drop to make VCO run faster. 
The fifth row shows the output of charge pump and loop filter. And the current 
discharges from the capacitors. 
 
Figure 6-2 PLL open-loop simulation 
 
 
 
 
 63 
6.4Measurements  
6.4.1 Die Photos 
The 5GHz PLL was fabricated in a 0.5mm 1-poly 4-metal BiCMOS process with 
SiGe, shown in Figure 6-3. The Die Size is 3.14?2.62 mm2.  
 
Figure 6-3 Die photo of PLL 
And Figure 6-4 shows the PLL with ceramic package photo. This package is a 52 
leadless chip carrier package with a 0.300" cavity (topside) and is 0.750" square. 
 
Figure 6-4 PLL with package photo 
 64 
6.4.2 Printed Circuit Board Design 
The PCB is designed for 5GHz PLL using FR4 material with two metal layers. It?s 
about 3 ? 3 inches. There are eight power supply pins, seven ground pins and two sub 
pins. We connect all ground and sub pins together on the PCB; while we separate analog 
and digital power supplies on the board in order to test different single blocks (one for 
VCO; one for MMD, one for programmable divider and one for other blocks). For each 
power supply pin, we leave enough room to place dcaps for reducing high frequency 
noise.  
For VCO outputs, MMD outputs, programmable divider outputs, and crystal 
reference input, we plan to use SMA connector. In order to decrease the calculation errors, 
we use 91.5-mil conductor on board to match the 50 Ohm resistance. 
For other inputs, outputs or control bits, since they are all DC value, we only need to 
use metal wire to connect them from board to DC sources. 
 
Figure 6-5 First copper layer on PCB 
 65 
 
Figure 6-6 Second copper layer on PCB 
6.4.3 Results   
The digital and analog power supplies all connected to 3.3V. Ground and subtract are 
tied together. The total current from power supply is 148mA.  
Test results showed the VCO?s output running at 5.12GHz with 0 V voltage control. 
And the MMD?s division ratio is 256, thus the output frequency of MMD is 20MHz. This 
output re-clocked by VCO?s output to remove noise from the MMD, then feed back to 
the Phase detector?s input.  It compared with the reference frequency to determine 
charging or discharging the filter?s capacitor. MMD?s spectrum shows in Figure 6-7 and 
its waveform shows in Figure 6-8. The output signal is about 55dB above the noise floor. 
 
Figure 6-7 Spectrum of MMD?s output frequency (division ratio is 256) 
 66 
 
Figure 6-8 Waveform of MMD?s output frequency (division ratio is 256) 
When the MMD?s division ratio changed to 360, the output frequency of MMD is 
14.25MHz. Spectrum shows in Figure 6-9 and waveform shows in Figure 6-10. The 
output signal is about 54dB above the noise floor. 
 
Figure 6-9 Spectrum of MMD?s output frequency (division ratio is 360) 
 67 
          
Figure 6-10 Waveform of MMD?s output frequency (division ratio is 360) 
In order to get wide range of PLL output, we added a programmable divider and a 
divided by 2 cell following the VCO serially. When the VCO?s output equals 5.12GHz 
and the divider?s division ratio is 7, thus the output frequency of MMD is 
(51200/14)=364.3MHz.. Divider?s spectrum shows in Figure 6-11 and waveform shows 
in Figure 6-12. The output signal is about 60dB above the noise floor. 
         
Figure 6-11 Spectrum of programmable divider?s output (division ratio is 14) 
 68 
 
Figure 6-12 Waveform of programmable divider?s output (division ratio is 14) 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 69 
 
 
 
 
CHAPTER 7 CONCLUSION 
In this thesis, two kinds of frequency synthesizers are discussed. And the focus part in 
this research work is an integer-N PLL based frequency synthesizer. Various circuit 
techniques to minimize the power consumption and maximum the operation speed are 
explored.  
DDS technique is an easy and flexible way to implement variety digital modulations, 
which can transmit and receive information with higher accuracy in the presence of noise 
and distortion. The realization of BPSK, QPSK, OQPSK and MSK are presented. When 
we used a Gaussian filter before the modulation, the frequency spectrum is obviously 
shrunk.   
Several PLL frequency synthesizers are compared. Each of them has its own 
advantages and disadvantages. In the integer-N architecture, the loop bandwidth is 
limited and the input reference must be equal to the channel spacing and the phase noise 
is worse. While fractional-N PLL has a wide bandwidth, quicker settling time, small 
channel spacing with a high reference frequency, it suffers fractional spurs. This is often 
undesirable, so various methods of suppressing the spurs have been devised, such as 
fractional compensation, randomizing the sequence of the modulus, or using Delta-Sigma 
modulators.  
In the end, RF circuit designs of an integer-N phase locked loop frequency 
synthesizer in SiGe technology are presented. The building blocks include phase detector, 
 70 
charge pump, programmable current setting, loop filter, VCO, programmable divider and 
MMD. Because noise from the VCO is suppressed in wideband PLL architectures, other 
noise sources become more important in the synthesizer performance. Noise from the 
crystal oscillator reference and phase detectors become the most important contributors 
within the loop bandwidth and are referred to the output enhanced in effect by the divider 
ratio N.  
In this PLL design, all digital blocks are used CML structure, which can run over 
10GHz. Except the loop filter, the whole loop is integrated in a 0.5um BiCMOS 
technology. With a regular 3.3V power supply, the whole chip consumes 476.3mW. The 
VCO?s operation range is 4.7GHz~5.3GHz; programmable divider?s maximum speed is 
7.5GHz; MMD?s maximum speed is 8.3GHz, and phase detector can reach 500MHz. 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 71 
 
 
 
 
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