ONWAFER SPARAMETER MEASUREMENT USING FOURPORT TECHNIQUE AND
INTERMODULATION LINEARITY OF RF CMOS
Except where reference is made to the work of others, the work described in this
dissertation is my own or was done in collaboration with my advisory committee. This
dissertation does not include proprietary or classified information.
Xiaoyun Wei
Certificated of approval:
Richard C. Jaeger
Distinguished University Professor
Electrical and Computer Engineering
Guofu Niu, Chair
Alumni Professor
Electrical and Computer Engineering
Fa Foster Dai
Professor
Electrical and Computer Engineering
Stuart Wentworth
Associate Professor
Electrical and Computer Engineering
George T. Flowers
Dean
Graduate School
ONWAFER SPARAMETER MEASUREMENT USING FOURPORT TECHNIQUE AND
INTERMODULATION LINEARITY OF RF CMOS
Xiaoyun Wei
A Dissertation
Submitted to
the Graduate Faculty of
Auburn University
in Partial Fulfillment of the
Requirements for the
Degree of
Doctor of Philosophy
Auburn, Alabama
December 19, 2008
iii
ONWAFER SPARAMETER MEASUREMENT USING FOURPORT TECHNIQUE AND
INTERMODULATION LINEARITY OF RF CMOS
Xiaoyun Wei
Permission is granted to Auburn University to make copies of this dissertation at its
discretion, upon request of individuals or institutions and at their expense.
The author reserves all publication rights.
Signature of Author
Date of Graduation
iv
VITA
Xiaoyun Wei, daughter of Xinli Wei and Xinye Wang, spouse of Tong Zhang, was
born on December 15
th
, 1978, in Xinxiang, Henan Province, P.R. China. She received
her BS degree from Huazhong University of Science and Technology in 2000, majoring
in Communication Engineering. She received her MS degree from Huazhong
University of Science and Technology in 2003, majoring in Circuit and Signal. In Fall
2004, She was accepted into the Electrical and Computer Engineering Department of
Auburn University, Auburn, Alabama, where she has pursued her Ph.D. degree.
v
DISSERTATION ABSTRACT
ONWAFER SPARAMETER MEASUREMENT USING FOURPORT TECHNIQUE AND
INTERMODULATION LINEARITY OF RF CMOS
Xiaoyun Wei
Doctor of Philosophy, December 19, 2008
(M.S., Huazhong University of Science and Technology, 2003)
(B.S., Huazhong University of Science and Technology, 2000)
236 Typed Pages
Directed by Guofu Niu
Accurate onwafer characterization of CMOS transistors at extremely high
frequencies, e.g. above 60GHz, becomes critical for RFIC designs and CMOS
technology development for millimeter wave applications. Traditional twostep error
calibration lumps the linear systematic errors as a fourport error adaptor between the
perfect VNA receivers and the probe tips, and the distributive onwafer parasitics as
equivalent circuits with shunt and series elements. However, the distributive nature of
onwafer parasitics becomes significant, and the lumped equivalent circuits fail at
frequencies above 50GHz.
The distributive onwafer parasitics is essentially a fourport network between the
probe tips and the transistor terminals. This dissertation develops two general fourport
techniques that can solve the onwafer parasitics fourport network, and demonstrates
their utility on a 0.13?m RF CMOS technology. One is an analytical solution solving
vi
the Yparameters of the fourport parasitics network. The other one is a numerical
solution solving the Tparameters of the fourport parasitics network. Even though the
two fourport solutions are developed for onwafer parasitics deembedding at the very
beginning, the two solutions do not make any reciprocal and symmetric assumptions of
the solved fourport network, and can be used for singlestep calibration which solves
the fourport network between perfect VNA receivers and transistor terminals. In this
case, both systematic errors and onwafer parasitics are included in one fourport
network, and can be removed in a single step. With switch error removed, singlestep
calibration can provide as accurate results as twostep calibration from 2110GHz.
Another topic that draws the attention of RFIC designers is the linearity
(nonlinearity) of CMOS transistors. Experimental IP3 results on a 90nm RF CMOS
technology are presented at different biasing voltages, different device width, and
different fundamental frequencies. To understand the biasing, device width, and
frequency dependence of IP3, a complete IP3 expression is developed using Volterra
series analysis and nonlinear current source method. The investigation indicates that not
only the 2
nd
and 3
rd
order nonlinear output conductance but also the cross terms are
important for IP3 sweet spot and high V
GS
IP3 modeling. Guidelines to identify the IP3
sweet spot for large devices used in RFIC designs are provided.
vii
ACKNOWLEDGEMENTS
I would like to express my gratitude to me supervisor, Dr. Guofu Niu. Without him,
this dissertation would not have been possible. His patience and encouragement carried
me on through difficult times. I appreciate his vast knowledge and skill in many areas,
and his valuable feedback that greatly contributed to this dissertation. I would like to
thank the other members of my committee, Dr. Foster Dai, Dr. Stuart M. Wentworth,
and Dr. Richard C. Jaeger for the assistance they provided.
Several people deserve special recognition for their contributions to this work. I
would like to thank Qingqing Liang for his help with deembedding techniques. I would
like to thank Ying Li for her help with device measurement. I would like to thank Susan
Sweeney of IBM Microelectronics for her help with 110GHz Sparameter measurement
and noise measurement. I would like to thank Dr. Stewart S. Taylor of Intel Corporation
for discussions on device and circuit characterization.
Finally, I am forever indebted to my parents for the support they provided me
through my entire life. In particular, I must acknowledge my husband and best friend,
Tong Zhang. Without whose love and encouragement, I would not have finished this
dissertation.
In conclusion, I recognize that this research would not have been possible without
the financial assistance of the Intel Corporation and VodafoneUS foundation. I also
would like to thank IBM Microelectronics for fabrication on various technologies.
viii
Style manual or journal used: Transactions of the Institute of Electrical and
Electronics Engineers
Computer software used: The document was prepared using Microsoft Word, The
plots were generated using Microsoft Visio and Matlab. The Bibliography was
generated using EndNote.
ix
TABLE OF CONTENTS
0TABLE OF CONTENTS........................................................................................................ 229H229HIX
1H1HLIST OF FIGURES..............................................................................................................230H230HXII
2H2HLIST OF TABLES ..............................................................................................................231H231HXIX
3H3HCHAPTER 1 INTRODUCTION............................................................................................... 232H232H1
4H4H1.1 Scattering parameter measurement.................................................................. 233H233H3
5H5H1.2 Intermodulation linearity measurement ......................................................... 234H234H10
6H6H1.3 Motivation and objectives.............................................................................. 235H235H14
7H7H1.3.1 Highfrequency RF CMOS characterization ..................................... 236H236H14
8H8H1.3.2 Fourport network for onwafer parasitics......................................... 237H237H15
9H9H1.3.3 General fourport solution.................................................................. 238H238H17
10H10H1.3.4 Singlestep calibration ....................................................................... 239H239H19
11H11H1.3.5 Validity of BSIM4 model for nonlinear RF modeling....................... 240H240H21
12H12H1.3.6 Third order intercept point modeling................................................. 241H241H21
13H13H1.3.7 Third order intermodulation distortion characterization.................... 242H242H22
14H14H1.4 Outline of Contributions ................................................................................ 243H243H23
15H15HCHAPTER 2 ONWAFER TEST STRUCTURE....................................................................... 244H244H25
16H16H2.1 Typical onwafer transistor test structure ...................................................... 245H245H26
17H17H2.2 Probing pad design considerations................................................................. 246H246H28
18H18H2.3 CMOS transistor design considerations......................................................... 247H247H32
19H19H2.3.1 Gate pattern and multiplier factor...................................................... 248H248H35
20H20H2.3.2 Gate finger configuration................................................................... 249H249H39
21H21H2.4 Summary........................................................................................................ 250H250H41
22H22HCHAPTER 3 ERROR MODELS FOR TWOPORT SPARAMETER MEASUREMENT................. 251H251H42
23H23H3.1 Twoport Sparameter measurement.............................................................. 252H252H44
24H24H3.2 Error adaptor concept..................................................................................... 253H253H49
25H25H3.3 The simplest 8term error model.................................................................... 254H254H50
26H26H3.4 The classical 12term error model ................................................................. 255H255H51
27H27H3.4.1 Forward mode .................................................................................... 256H256H52
28H28H3.4.2 Reverse mode..................................................................................... 257H257H53
29H29H3.4.3 12term model.................................................................................... 258H258H55
30H30H3.4.4 SOLT calibration ............................................................................... 259H259H58
31H31H3.5 The most complete 16term error model ....................................................... 260H260H61
32H32H3.6 Error adaptor for singlestep calibration........................................................ 261H261H66
33H33H3.7 Summary........................................................................................................ 262H262H70
x
34H34HCHAPTER 4 GENERIC ANALYTICAL FOURPORT SOLUTION............................................. 263H263H71
35H35H4.1 Fourport network in Yparameters ............................................................... 264H264H73
36H36H4.2 General fourport Solution............................................................................. 265H265H74
37H37H4.2.1 Relationship between openshort and fourport................................. 266H266H74
38H38H4.2.2 Openshort deembedded LEFT, RIGHT, and THRU....................... 267H267H77
39H39H4.2.3 Analytical solution of A and B .......................................................... 268H268H78
40H40H4.2.4 Summary of general fourport deembedding.................................... 269H269H83
41H41H4.2.5 Impact of nonideal load in LEFT and RIGHT ................................. 270H270H84
42H42H4.2.6 Quantifying errors of openshort ....................................................... 271H271H86
43H43H4.2.7 Reciprocity and symmetry of the fourport parasitics ....................... 272H272H87
44H44H4.3 Reciprocal fourport solution and padopenshort......................................... 273H273H88
45H45H4.4 Summary........................................................................................................ 274H274H90
46H46HCHAPTER 5 NUMERICAL FOURPORT SOLUTION............................................................. 275H275H92
47H47H5.1 Fourport parasitic network in Tparameters ................................................. 276H276H93
48H48H5.2 SVD based fourport Solution ....................................................................... 277H277H94
49H49H5.3 Experimental results for onwafer parasitics deembedding ......................... 278H278H97
50H50H5.4 Reduction of Error Terms and Number of Standards .................................. 279H279H100
51H51H5.4.1 Quantify error terms for fourport onwafer parasitics.................... 280H280H100
52H52H5.4.2 8term solution using three onwafer standards............................... 281H281H102
53H53H5.5 Summary...................................................................................................... 282H282H106
54H54HCHAPTER 6 SINGLESTEP CALIBRATION ....................................................................... 283H283H107
55H55H6.1 Analytical fourport singlestep calibration................................................. 284H284H108
56H56H6.2 Numerical fourport singlestep calibration................................................. 285H285H111
57H57H6.3 Impact of switch errors ................................................................................ 286H286H113
58H58H6.3.1 Quantify error terms using Sparameters......................................... 287H287H115
59H59H6.4 Summary...................................................................................................... 288H288H117
60H60HCHAPTER 7 VALIDITY OF BSIM4 MODEL FOR NONLINEAR RF MODELING................... 289H289H118
61H61H7.1 Linearity measurement and simulation........................................................ 290H290H119
62H62H7.2 DC and linear characteristics ....................................................................... 291H291H121
63H63H7.3 Nonlinear characteristics.............................................................................. 292H292H125
64H64H7.4 Summary...................................................................................................... 293H293H131
65H65HCHAPTER 8 MODELING OF INTERMODULATION LINEARITY .......................................... 294H294H132
66H66H8.1 First order IP3 theory................................................................................... 295H295H133
67H67H8.2 Complete IP3 expression ............................................................................. 296H296H135
68H68H8.2.1 Two dimension nonlinear current source......................................... 297H297H136
69H69H8.2.2 Input IP3 expression ........................................................................ 298H298H138
70H70H8.3 Impact of the additional terms ..................................................................... 299H299H140
71H71H8.4 Device width scaling.................................................................................... 300H300H142
72H72H8.5 DIBL effect .................................................................................................. 301H301H144
73H73H8.6 Summary...................................................................................................... 302H302H147
74H74HCHAPTER 9 CHARACTERIZATION OF RF INTERMODULATION LINEARITY...................... 303H303H149
75H75H9.1 Power gain measurement ............................................................................. 304H304H150
xi
76H76H9.2 Linearity Characteristics .............................................................................. 305H305H151
77H77H9.2.1 Drain voltage dependence................................................................ 306H306H151
78H78H9.2.2 Finger number dependence.............................................................. 307H307H153
79H79H9.2.3 Frequency dependence..................................................................... 308H308H154
80H80H9.2.4 Large signal linearity ....................................................................... 309H309H157
81H81H9.3 Summary...................................................................................................... 310H310H158
82H82HBIBLIOGRAPHY .............................................................................................................. 311H311H160
APPENDICES
83H83HAPPENDIX A ABBREVIATIONS AND SYMBOLS............................................................... 312H312H168
84H84HA.1 Abbreviations............................................................................................... 313H313H168
85H85HA.2 Matrix symbols and matrix index ................................................................ 314H314H168
86H86HAPPENDIX B TWO PORT NETWORK REPRESENTATIONS ................................................ 315H315H170
87H87HAPPENDIX C REVIEW OF ONWAFER DEEMBEDDING METHODS .................................. 316H316H172
88H88HC.1 OpenShort deembedding........................................................................... 317H317H172
89H89HC.2 PadopenShort deembedding..................................................................... 318H318H174
90H90HC.3 Threestep deembedding............................................................................. 319H319H176
91H91HC.4 Transmission line deembedding ................................................................. 320H320H178
92H92HAPPENDIX D SWITCH ERROR REMOVAL ....................................................................... 321H321H182
93H93HD.1 Switch error removal equations ................................................................... 322H322H182
94H94HD.2 Stepbystep guide to measure the switch errors ......................................... 323H323H184
95H95HAPPENDIX E CALIBRATION KIT SETUP.......................................................................... 324H324H188
96H96HAPPENDIX F THE RELATIONSHIP BETWEEN OPENSHORT AND FOURPORT .................. 325H325H192
97H97HAPPENDIX G SINGULARITY OF LINEAR EQUATION SET................................................. 326H326H196
98H98HG.1 Typical calibration standards ....................................................................... 327H327H196
99H99HG.2 Singularity of onwafer standards................................................................ 328H328H197
100H100HAPPENDIX H ONEPORT ERROR CORRECTION............................................................... 329H329H201
101H101HH.1 Error adaptor for oneport system................................................................ 330H330H202
102H102HH.2 Relationship between
M
? and
DUT
? ........................................................... 331H331H203
103H103HH.3 A generalized interpretation......................................................................... 332H332H204
104H104HAPPENDIX I DERIVATION OF FIRST ORDER INPUT IP3................................................... 333H333H207
105H105HAPPENDIX J DERIVATION OF INPUT IP3 BASED ON VOLTERRA SERIES ......................... 334H334H210
106H106HJ.1 First order kernels ........................................................................................ 335H335H211
107H107HJ.2 Second order kernels.................................................................................... 336H336H212
108H108HJ.3 Third order kernels....................................................................................... 337H337H214
109H109HJ.4 Input IP3....................................................................................................... 338H338H215
xii
LIST OF FIGURES
110H110HFig. 1.1 The power spectrum at the drain of a single transistor under a twotone
excitation, measured by a 50? spectrum analyzer. ....................................... 339H339H3
111H111HFig. 1.2 A typical twoport system for onwafer Sparameter measurement. ............ 340H340H4
112H112HFig. 1.3 Onwafer parasitics and reference planes for system error calibration
and onwafer parasitics deembedding.......................................................... 341H341H5
113H113HFig. 1.4 The lumped equivalent circuits for (a) openshort, (b) padopenshort,
and (c) threestep deembedding. .................................................................. 342H342H7
114H114HFig. 1.5 The equivalent input resistance and capacitance extracted from open
short, padopenshort, and improved threestep deembedded results. ......... 343H343H9
115H115HFig. 1.6 An onwafer intermodulation linearity measurement system. .................... 344H344H11
116H116HFig. 1.7 The fundamental and IM3 output products versus input power for a
twotone excited system. ............................................................................. 345H345H12
117H117HFig. 1.8 IIP3 versus
GS
V from first order IP3 theory, linearity simulation, and
twotone measurement................................................................................. 346H346H14
118H118HFig. 1.9 (a) The fourport network for systematic errors. (b) The fourport
network for onwafer parasitics................................................................... 347H347H17
119H119HFig. 2.1 The top view of an onwafer test structure for transistors. (a) The whole
test structure including probing pads. (b) The MOS transistor under test
only. The dimension is not to scale. ............................................................ 348H348H27
120H120HFig. 2.2. Chip pictures of the fabricated transistor structures on three RF CMOS
technologies. (b) and (c) are fabricated at different foundries. ................... 349H349H28
121H121HFig. 2.3 Cross section view of an advanced RF CMOS technology. The
dimension is to scale.................................................................................... 350H350H29
122H122HFig. 2.4 The cross section view of GSG pads and MOS transistor along three
cuts............................................................................................................... 351H351H31
123H123HFig. 2.5. Layout for one cell of the desired transistor................................................ 352H352H32
124H124HFig. 2.6. Layout for the desired transistor, NMOS, and the onwafer standards,
OPEN, SHORT, LEFT, RIGHT and THRU. .............................................. 353H353H34
125H125HFig. 2.7. Layout for NMOS transistors with different gate patterns and multiplier
factors. ......................................................................................................... 354H354H36
126H126HFig. 2.8. An example for
T
f extraction..................................................................... 355H355H37
xiii
127H127HFig. 2.9. An example for
max
f extraction................................................................... 356H356H37
128H128HFig. 2.10. Extracted parameters for three NMOS transistors with different gate
patterns and multiplier factors..................................................................... 357H357H39
129H129HFig. 2.11. Layout for three NMOS transistors with same total channel width but
different finger width and finger number. W
total
=40?m.............................. 358H358H40
130H130HFig. 2.12. Extracted parameters for three NMOS transistors with same total
channel width but different finger width and finger number.
W
total
=40?m................................................................................................. 359H359H41
131H131HFig. 3.1 Block diagram for twoport Sparameter measurement using Agilent
8510C system. ............................................................................................. 360H360H45
132H132HFig. 3.2 A twoport VNA system with four receivers. ............................................. 361H361H46
133H133HFig. 3.3 The magnitude of the measured S
11
of an ideal (a) LOAD and (b)
SHORT........................................................................................................ 362H362H49
134H134HFig. 3.4 The fourport system error adaptor for twoport Sparameter
measurement................................................................................................ 363H363H50
135H135HFig. 3.5 Signal flow graph of 8term error model for a twoport system. ................ 364H364H51
136H136HFig. 3.6 The modified 10term error model with two leakage errors added............. 365H365H51
137H137HFig. 3.7 A twoport Sparameter measurement system configured for forward
mode. ........................................................................................................... 366H366H52
138H138HFig. 3.8 Forward mode signal flow graph for twoport system including non
ideal Z
0
termination. .................................................................................... 367H367H53
139H139HFig. 3.9 Simplified forward mode signal flow graph................................................ 368H368H53
140H140HFig. 3.10 A twoport Sparameter measurement system configured for reverse
mode. ........................................................................................................... 369H369H54
141H141HFig. 3.11 Reverse mode signal flow graph for twoport system including non
ideal Z
0
termination. .................................................................................... 370H370H54
142H142HFig. 3.12 Simplified reverse mode signal flow graph for twoport system. ............... 371H371H54
143H143HFig. 3.13 Forward mode signal flow graph for twoport system. ............................... 372H372H56
144H144HFig. 3.14 Normalized 6term error model for forward mode...................................... 373H373H56
145H145HFig. 3.15 Normalized 6term error model for reverse mode....................................... 374H374H57
146H146HFig. 3.16 (a) OPEN, (b) SHORT, (c) LOAD, and (d) THRU standards for SOLT
calibration on Cascade ISS 101190............................................................ 375H375H59
147H147HFig. 3.17 Raw and corrected data for
11
S and
21
S of a 0.13?m NMOS transistor. .... 376H376H61
148H148HFig. 3.18 Signal flow graph of the 16term model for a twoport system. ................. 377H377H62
xiv
149H149HFig. 3.19 The combined fourport network including system errors and onwafer
parasitics...................................................................................................... 378H378H67
150H150HFig. 4.1. Block diagram of the onwafer parasitics fourport network using IV
representation. ............................................................................................. 379H379H73
151H151HFig. 4.2. The equivalent twoport network of the intrinsic NMOS transistor and
the five onwafer standards OPEN, SHORT, LEFT, RIGHT and THRU.
..................................................................................................................... 380H380H75
152H152HFig. 4.3. The real part of fourport deembedded
21
y using different
21 11
/aa
choices. The
21 11
/aa defined from
22 12
/M M is clearly nosier, and
should not be used. ...................................................................................... 381H381H82
153H153HFig. 4.4. The fourport deembedded transistor Yparameters with and without
including parasitic capacitance in
L
Y and
R
Y . For comparison, open
short deembedded results are also plotted. No reciprocal assumptions
are made for fourport parasitics deembedding. ........................................ 382H382H85
154H154HFig. 4.5. Effective gate resistance and capacitance extracted from fourport de
embedded results with and without parasitic capacitance included in
LEFT and RIGHT. Openshort deembedded results are also shown for
comparison. No reciprocal assumptions are made. ..................................... 383H383H86
155H155HFig. 4.6. The elements of A? and B? versus frequency. ........................................ 384H384H87
156H156HFig. 4.7. Reciprocal fourport deembedded transistor Yparameters versus the
results using openshort and padopenshort deembedding....................... 385H385H90
157H157HFig. 5.1 The fourport error adaptor for onwafer parasitics in wave
representation. ............................................................................................. 386H386H93
158H158HFig. 5.2 Comparison of Yparameters between openshort, padopenshort,
SVD based numerical fourport solution, and analytical fourport
solution. ....................................................................................................... 387H387H98
159H159HFig. 5.3 Comparison of effective gate resistance and capacitance between open
short, padopenshort, SVD based fourport solution, and analytical
fourport solution......................................................................................... 388H388H99
160H160HFig. 5.4 The magnitude of the Sparameters for the fourport onwafer parasitics.
................................................................................................................... 389H389H102
161H161HFig. 5.5 Comparison of Yparameters between openshort, SVD based 16term
solution, and SVD based 8term solution.................................................. 390H390H105
162H162HFig. 5.6 Comparison of Yparameters between openshort, SVD based 16term
solution, and SVD based 8term solution.................................................. 391H391H105
163H163HFig. 6.1. Singlestep versus twostep fourport using the analytical fourport
solution with data measured using a HP 8510XF system from 2 GHz to
110 GHz..................................................................................................... 392H392H110
xv
164H164HFig. 6.2. Singlestep versus twostep fourport using the analytical fourport
solution with data measured using a HP 8510C system from 2 GHz to
26.5 GHz.................................................................................................... 393H393H110
165H165HFig. 6.3 Comparison between twostep openshort and fourport onwafer
parasitics deembedding results with ISS calibration and singlestep
fourport calibration results without any ISS calibration. ......................... 394H394H112
166H166HFig. 6.4 Condition numbers of the coefficient matrix in onwafer parasitics de
embedding and singlestep calibration. ..................................................... 395H395H113
167H167HFig. 6.5 Comparison of the singlestep fourport calibrated results with and
without switching error correction. The analytical fourport solution in
Section 421H519H519H536H4.2 is applied................................................................................. 396H396H114
168H168HFig. 6.6 Comparison of the singlestep fourport calibrated results with and
without switching error correction. The SVD based numerical fourport
solution in Section 422H520H520H537H5.2 is applied............................................................... 397H397H115
169H169HFig. 6.7 The magnitude of the solved 16 error terms of the combined fourport
network...................................................................................................... 398H398H116
170H170HFig. 7.1 Block diagram for twotone intermodulation linearity measurement. ...... 399H399H119
171H171HFig. 7.2 Schematic for twotone intermodulation linearity simulation in Cadence.
................................................................................................................... 400H400H120
172H172HFig. 7.3 Measured and simulated
DS
I 
GS
V for
DS
V =0.6, 0.8, and 1.0V. ................ 401H401H122
173H173HFig. 7.4 Measured and simulated
DS
I 
DS
V for
GS
V =0.4V and 0.8V....................... 402H402H122
174H174HFig. 7.5 (a) S
21
in dB versus frequency at
GS
V = 0.4V and
DS
V =1.0V. (b) S
21
in
dB versus
GS
V at 5GHz and
DS
V =1.0V. .................................................... 403H403H123
175H175HFig. 7.6 f
T
extracted from measured and simulated Sparameters.......................... 404H404H123
176H176HFig. 7.7 Yparameters versus frequency at
GS
V = 0.4V and
DS
V =1.0V. ? and ?
stand for real and imaginary parts. ............................................................ 405H405H124
177H177HFig. 7.8 Yparameters at 5GHz versus
GS
V .
DS
V =1.0V. ? and ? stand for real
and imaginary parts. .................................................................................. 406H406H125
178H178HFig. 7.9 The amplitude of the fundamental output signal versus input power
level at
GS
V =0.4V,
DS
V =0.8V. .................................................................. 407H407H126
179H179HFig. 7.10 The amplitude of the fundamental output signal and the third order
intermodulation product versus
DS
J . ........................................................ 408H408H127
180H180HFig. 7.11 Measured and simulated IIP3 versus
GS
V at multiple
DS
V . ....................... 409H409H128
xvi
181H181HFig. 7.12 Measured and simulated IIP3 versus
DS
J for devices with
f
N =10, 20,
and 64. ....................................................................................................... 410H410H129
182H182HFig. 7.13 Measured and simulated IIP3 versus
GS
V at multiple frequencies for
f
N =10 (W=20?m).................................................................................... 411H411H130
183H183HFig. 7.14 Measured and simulated IIP3 versus
GS
V at multiple frequencies for
f
N =64 (W=128?m).................................................................................. 412H412H131
184H184HFig. 8.1 The small signal equivalent circuit used for IP3 analysis. ........................ 413H413H134
185H185HFig. 8.2 First order IP3 with a sweet spot at 3g
m
K =0............................................. 414H414H135
186H186HFig. 8.3 The nonlinear coefficients versus
GS
V ....................................................... 415H415H137
187H187HFig. 8.4 (a) The denominator in 474H554H554H596H416H416H(8.5) versus
GS
V . (b) Each term in the
denominator of 475H555H555H597H417H417H(8.5) versus
GS
V .
DS
V =0.8V............................................. 418H418H141
188H188HFig. 8.5 IIP3 versus
GS
V from simulation, first order IP3 expression in 479H559H559H601H419H419H(8.3), and
complete IP3 expression in 480H560H560H602H420H420H(8.5) with different nonlinearities included.
DS
V =0.8V................................................................................................... 421H421H142
189H189HFig. 8.6 IIP3 calculated using 486H566H566H608H422H422H(8.5) and 487H567H567H609H423H423H(8.3) versus
DS
J for devices with
multiple finger numbers. ........................................................................... 424H424H143
190H190HFig. 8.7 (a)
DS
I , (b) 3g
m
K versus
GS
V at multiple
DS
V for simulation with and
without
th
V shift due to
th
V? (DIBL)......................................................... 425H425H145
191H191HFig. 8.8 IIP3 calculated using 495H575H575H617H426H426H(8.5) versus
GS
V at multiple
DS
V for simulation
with and without
th
V? (DIBL)................................................................... 427H427H145
192H192HFig. 8.9 (a) 3 /g
mm
K g +?
1
+?
2
+?
3
+?
4
, (b) 3 /g
mm
K g , and (c) ?
1
+?
2
versus
GS
V
at multiple
DS
V for Cadence simulation with and without
th
V? (DIBL). .. 428H428H147
193H193HFig. 9.1 Gain from linearity measurement (
,1out st
P 
in
P ) and gainsparameter
measurement (
21
S ) versus
GS
V .................................................................. 429H429H150
194H194HFig. 9.2 Measured and analytical IIP3 versus
GS
V at multiple
DS
V . Analytical
IIP3 is calculated using 514H595H595H634H430H430H(8.5)..................................................................... 431H431H152
195H195HFig. 9.3 3 /g
mm
K g and 3 /g
mm
K g +?
1
+?
2
+?
3
+?
4
versus
GS
V at multiple
DS
V ....... 432H432H153
196H196HFig. 9.4 Measured and analytical IIP3 versus
DS
J for devices with
f
N =10, 20,
and 64. Analytical IIP3 is calculated using 520H601H601H640H433H433H(8.5)....................................... 434H434H154
xvii
197H197HFig. 9.5 Measured IIP3 versus
DS
J at multiple frequencies for
f
N =10 and 64
(W=20?m and 128?m).............................................................................. 435H435H155
198H198HFig. 9.6 Analytical IIP3 (a) without
gd
C and (b) with
gd
C at multiple
frequencies for
f
N =64 (W=128?m). Analytical IIP3 without
gd
C is
calculated using 528H609H609H648H436H436H(8.5)................................................................................. 437H437H156
199H199HFig. 9.7 Analytical IIP3 with and without
gd
C at multiple frequencies for
f
N =10 (W=20?m). Analytical IIP3 without
gd
C is calculated using
529H610H610H649H438H438H(8.5). .......................................................................................................... 439H439H156
200H200HFig. 9.8 The output power amplitude for fundamental and 3
rd
order
intermodulation products versus input power. .......................................... 440H440H157
201H201HFig. 9.9 Contour of 3
rd
order intermodulation output power with sweeping gate
bias and input power.................................................................................. 441H441H158
202H202HFig. C.1 Equivalent circuit of onwafer parasitics for openshort deembedding. .. 442H442H173
203H203HFig. C.2 Equivalent circuits and layouts of (a) OPEN, and (b) SHORT standards.
................................................................................................................... 443H443H173
204H204HFig. C.3 Equivalent circuit for padopenshort deembedding................................ 444H444H175
205H205HFig. C.4 Equivalent circuits and layouts of PAD, OPEN and SHORT standards
for padopenshort. .................................................................................... 445H445H175
206H206HFig. C.5 Equivalent circuit for improved three step deembedding. ....................... 446H446H177
207H207HFig. C.6 Equivalent circuits and layouts of OPEN, SHORT1, SHORT2, and
THRU standards for improved three step.................................................. 447H447H177
208H208HFig. C.7 Equivalent circuit for transmission line deembedding............................. 448H448H180
209H209HFig. C.8 Equivalent circuits and layouts of THRU1 and THRU2 for
transmission line deembedding. The length of transmission line is not
to scale....................................................................................................... 449H449H181
210H210HFig. D.1 A twoport Sparameter measurement system with four receivers. .......... 450H450H182
211H211HFig. F.1. Block diagram of the 4port network for onwafer parasitics using IV
representation. ........................................................................................... 451H451H193
212H212HFig. G.1 Condition number, minimum and maximum singular value for four
standards.................................................................................................... 452H452H198
213H213HFig. G.2 Condition number, minimum and maximum singular value for five
standards.................................................................................................... 453H453H200
214H214HFig. G.3 Condition number for multiple number of standards. ............................... 454H454H200
215H215HFig. H.1 The block diagram for a oneport measurement........................................ 455H455H201
xviii
216H216HFig. H.2 The combined twoport error adaptor for oneport Sparameter
measurement.............................................................................................. 456H456H202
217H217HFig. H.3 Signal flow graph of the twoport error adaptor in oneport
measurement.............................................................................................. 457H457H203
218H218HFig. H.4 The three error terms solved using OPEN, SHORT and LOAD
standards.................................................................................................... 458H458H204
219H219HFig. I.1 The small signal equivalent circuit used for IP3 analysis. ........................ 459H459H208
220H220HFig. J.1 The small signal equivalent circuit used for IP3 analysis. ........................ 460H460H211
221H221HFig. J.2 The linearized equivalent circuit for solving first order kernels. .............. 461H461H212
222H222HFig. J.3 The equivalent circuit for solving the second order kernels...................... 462H462H213
223H223HFig. J.4 The equivalent circuit for solving the third order kernels ......................... 463H463H215
xix
LIST OF TABLES
224H224HTable 8.1 Definition of nonlinearity coefficients of nonlinear drain current. ........... 464H464H136
225H225HTable B.1 Transformation between two port H, Y, Z, and ABCD representations ... 465H465H171
226H226HTable E.1 Calibration Kit Coefficients ...................................................................... 466H466H191
227H227HTable G.1 Nonsingular combinations of five twoport calibration standards for 16
term error model. Assuming one standard is a zero length THRU. .......... 467H467H199
1
Chapter 1
INTRODUCTION
The growth of wireline and wireless communication demands RF integrated
circuits (RFIC) on CMOS technologies because of the low cost and the eligibility for
high volume integration. As well known, the RF section is the biggest challenge in
CMOS transceiver designs due to the lack of accurate RF CMOS models. This demands
reliable RF measurements, which are mainly done onwafer with the advent of coplanar
probes. The measured data must reflect the intrinsic transistor without the effects of the
surrounding environment.
The notable available models for a bulk MOSFET (Metal Oxide Silicon Field
Effect Transistor) are BSIM3V3 [1], BSIM4 [2], MODEL 11 [3], PSP [4]. BSIM3V3,
BSIM4 are chargebased models, while MODEL 11 and PSP are surfacepotential
based models [5] [6]. Usually, a set of DC, CV, and Sparameter measurements are
carefully designed to evaluate the performance of a technology, and extract the
unknown model parameters [7] [8]. For example, from DC measurement, one can have
an idea of the mathematical relationship between the voltages and currents at each
terminal, and the operating limits of the transistor, e.g. threshold voltage, breakdown
voltage. The accuracy of DC measurement is determined by the DC probes and the
equipments. Essential to obtaining a good RF model is the accuracy of onwafer
scattering parameter (Sparameter) measurements. Sparameter measurement gives an
CHAPTER
2
idea of the RF performance of the transistor, e.g. cutoff frequency, power gain. The
accuracy of measured Sparameters directly affects high frequency model parameters,
e.g. gatesource capacitance. The accuracy of the model determines the time to market
of any RFIC designs [1]. The system setup and the techniques to remove errors in S
parameter measurement will be detailed later in Section 317H317H333H468H468H1.1.
However, Sparameter describes the RF performance of transistors in linear mode
only, because VNA is operated in linear mode, and the measured Sparameters only
include smallsignal information of the transistor at the excitation frequency [9]. The
realworld transistor characteristics are nonlinear that the transistor will generate
harmonics and intermodulation products in addition to the stimulus signal [9] [8]. The
higherorder harmonics and intermodulation products become apparent when the input
power is significant. The 1dB compression point and the twotone third order
intermodulation (IM3) distortion are the most widely used figure of merit to evaluate
the linearity of transistors. 318H318H334H
For a nonlinear system, the IM3 products are the remixed products when the input
signal contains two adjacent channels. 469H469HFig. 1.1 illustrates the impact of the IM3 product
on the desired signals. The spacing between the twotone input signals, f
1
and f
2
, is ?f.
The two components at 2f
1
f
2
and 2f
2
f
1
, are the IM3 products induced by the nonlinear
drain current to gate bias function, which are ?f away from the twotone signals. Since
the frequency step for mobile communication channels ranges from 30KHz to 200KHz,
?f=100KHz is chosen for the twotone intermodulation measurement in 319H319H335H470H470HFig. 1.1. If the
transistor is not very linear, the amplitude of the two IM3 products can be comparable
to the amplitude of the desired signals. And thus the information you received can be
3
way off if the filter?s rolloff is not narrow enough. The third order intercept point (IP3)
is usually used to quantify the third order intermodulation distortion [10] [11]. The
details of IM3 measurement and IP3 extraction are presented in Section 320H320H336H471H471H1.2. The 1dB
compression point can be simultaneously extracted while extracting IP3.
2f1f2 f1=5GHz f2=5GHz+100KHz 2f2f1
100
80
60
40
20
0
20
P
out
(dBm)
Third order
intermodulation products
?f=f
2
f
1
?f?f
Fundamental frequency products
P
in
= 17dBm
V
GS
= 0.6V
V
DS
= 1.0V
Fig. 1.1 The power spectrum at the drain of a single transistor under a twotone
excitation, measured by a 50? spectrum analyzer.
1.1 Scattering parameter measurement
321H321H337H472H472HFig. 1.2 illustrates a typical twoport system for onwafer Sparameter
measurement. It includes a twoport vector network analyzer (VNA), several RF cables
and connectors, two RF probes, and a probe station. The Agilent VNA8510C system in
322H322H338H473H473HFig. 1.2 consists of four equipments, and can work up to 50GHz with proper
configuration. The VNA8510C system is mainly used to measure 26.5GHz and 40GHz
Sparameters in this dissertation due to the limitation of RF cables and connectors. The
110GHz data is measured by an Agilent VNA 8510XF system with helps from IBM,
Essex Junction. One of the most accurate coplanar groundsignalground (GSG) probes,
4
the Cascade RF infinity probe is used to contact the onwafer structures. An Alessi
manual probe station with a round 6" chuck is used to provide mechanical support and
motorization controls of the wafer. Two magnetic positioners are stuck to the metal top
plate of the probe station to support the RF probes and provide motorization controls of
the probes.
Power Meter
VNA
Power Supply
Port1
Port2
Probe Station
Probe1
Probe2
Fig. 1.2 A typical twoport system for onwafer Sparameter measurement.
However, the system is not perfect. Random and systematic measurement errors are
involved in the measured Sparameters [12]. The random errors, e.g. thermal drift,
cannot be removed systematically, but the systematic errors can. VNA usually provides
several standard techniques for correcting systematic errors, e.g. shortopenloadthru
(SOLT). These techniques utilize accurate standards on an impedance standard
substrate (ISS) to solve the error terms between the probe tips and the perfect ports
inside VNA, a step called ?system error calibration.? After system error calibration, the
5
test system ends at the probe tips, which is then defined as the reference plane for
systematic error removal. Reference plane is a factitious separation which defines where
the test system ends and the device under test (DUT) begins [13]. 323H323H339H474H474HFig. 1.3 illustrates the
reference planes defined for onwafer Sparameter measurement. The reference plane at
the probe tips is the reference plan defined for system error calibration.
Ground
Signal
Ground
Ground
Signal
Ground
Ground
Port 1 Port 2
Probe Tip
reference plane
Device Terminal
reference plane
Fig. 1.3 Onwafer parasitics and reference planes for system error calibration and on
wafer parasitics deembedding.
Besides the systematic errors, onwafer parasitics including the probing pads and
the interconnections need to be removed secondly, a process called ?onwafer de
embedding.? As shown in 324H324H340H475H475HFig. 1.3, the probing pads and interconnections often have
much larger dimensions when compared with the intrinsic transistor due to the size
limitations of RF probes. Thus, a second reference plane is defined at the very end of
the interconnections from probing pads to device terminals, which is the device terminal
reference plane in 476H476HFig. 1.3. The standards used to solve error terms are fabricated on the
same wafer as the desired device. The same probing pads and interconnections are
6
shared by the desired device and the onwafer standards to keep the reference plane
consistent. Since systematic errors and onwafer parasitics are removed in two steps,
this approach is identified as ?twostep calibration? in the dissertation. Openshort
developed in 1991 lumps onwafer parasitics as three shunt and three series elements,
which is still the industrial standard onwafer deembedding technique until now. 477H477HFig.
1.4 (a) shows the equivalent circuit for openshort. Two onwafer standards, an OPEN
and a SHORT, are necessary to remove the six lumped elements [14].
478H478HFig. 1.4 (b) and (c) give the equivalent circuits for two alternatives to openshort,
threestep and padopenshort, which make different assumptions of onwafer parallel
parasitics. Openshort assumes that the large probing pads are the only source of
parallel parasitics, and thus the three shunt elements are representing the parasitics at
the pads [14]. Threestep also lumps the parallel parasitics as three shunt elements, but
the third one is between the two series elements instead of the two parallel elements [15]
[16]. This assumes that the parasitics between the two pads can be ignored, while the
parasitics between the ends of the two interconnect lines are considerable, because of
the smaller distance between the two ends when compared with the distance between
the two pads. Four onwafer standards, an OPEN, a THRU, a SHORT1 and a SHORT2,
are necessary for threestep deembedding [15] [16]. Padopenshort lumps the parallel
parasitics at the pads and the interconnect lines separately. Three shunt elements are
used to represent the parallel parasitics at the pads, which can be evaluated from a PAD
standard without any interconnect lines. The distributive parallel parasitics along the
interconnect lines is lumped as three series elements and three shunt elements at the end
of interconnect lines. Although, padopenshort lumps onwafer parasitics as nine
7
elements, it only need three standards, a PAD, an OPEN, and a SHORT [17]. Padopen
short was shown to be better than openshort for onwafer inductor structures measured
above 10GHz. However, this improvement, to a large extent, depends on the layout
design [17]. For onwafer transistor structures, the interconnect lines are not as long and
wide as the interconnect lines for the conductor structures in [17], and the parallel
parasitics along the interconnect lines is not comparable to the pad parasitics. In this
case, padopenshort will not show great advantage over openshort.
Y3
Y1 Y2
Z4 Z5
Z6
[YA]
(a) Openshort
Y1 Y2
Z4 Z5
Z6
[YA]
Y3
(b) Threestep
Y3
Y1 Y2
Z4 Z5
Z6
[YA]
Y7 Y8
Y9
(c) Padopenshort
Fig. 1.4 The lumped equivalent circuits for (a) openshort, (b) padopenshort, and (c)
threestep deembedding.
479H479HFig. 1.5 shows the equivalent input resistance and capacitance,
in
R and
in
C ,
extracted from twostep calibration results [18] [19]. The system errors are calibrated
using SOLT, while the onwafer parasitics are removed using three different techniques,
8
openshort, padopenshort, and the improved threestep. The deembedding procedures
are detailed in Appendix C. As compared in 330H330H346H480H480HFig. 1.5, the three methods give
approximately the same
in
R and
in
C for the examined NMOS transistor, and all of them
show an unphysical frequency dependence of
in
C . This indicates that for transistor
measurement, these three deembedding methods all fail at frequencies above 50GHz,
even though they are using different lumped equivalent circuit with different
complexities. A fourport deembedding technique, which describes the onwafer
parasitics as a fourport network, was developed in [20] with applications on SiGe
HBTs. Advantages over openshort at frequencies above 30GHz were illustrated using
simulated results. However the math is complex and no experimental results are
presented. Furthermore, padopenshort was shown to be more accurate than fourport
for onwafer inductor characterization in [17]. These issues need to be examined on
CMOS technologies.
9
0 20 40 60 80 100
100
150
200
250
300
350
frequency (GHz)
C
i
n (f
F)
0
2
4
6
8
10
12
Ri
n (
?
)
openshort
padopenshort
improved threestep
(a)
(b)
Fig. 1.5 The equivalent input resistance and capacitance extracted from openshort,
padopenshort, and improved threestep deembedded results.
Twostep calibration can provide the most accurate system error information as
long as the ISS standards are accurate. The disadvantage is that the system error
calibration step is time consuming and need to be rechecked several times for hourly
measurement. Also, twostep calibration involves a process to switch between the ISS
substrate and the wafer. Another approach, the so called ?singlestep calibration?,
defines only one reference plane, which is the reference plane at the device terminals.
Onwafer standards are used to determining the error terms. The systematic errors and
onwafer parasitics are removed in a single step. The difficulty is that most IC processes
cannot deposit a precision resistive load with good repeatability [21]. Due to the less
accurate onwafer standards, singlestep calibration are expected to provide less
accurate Sparameters when compared with twostep calibration, and thus not widely
10
used for onwafer characterization. However, the same onwafer standards are used for
onwafer deembedding and these standards are assumed to be ideal for simplicity in
twostep calibration. There is no occasion to have a huge difference between twostep
calibration and singlestep calibration using the same nonideal nwafer standards. With
appropriate error calibration techniques, singlestep calibration may be able to provide
reasonably accurate results. This issue should be examined experimentally on advanced
silicon technologies.
1.2 Intermodulation linearity measurement
The third order intercept point (IP3) is defined as the point where the 3
rd
order
intermodulation (IM3) product equals the fundamental frequency product for a twotone
excited system. To extract IP3, the power levels of the fundamental and the IM3
products at the output have to be measured using a spectrum analyzer. 331H331H347H481H481HFig. 1.6 shows a
twotone intermodulation linearity measurement system with two identical Agilent
performance signal generators (PSG) E8247 at the input and an Agilent 8563EC
performance spectrum analyzer (PSA) at the output [22]. The signals generated by the
two PSGs have the same power level, the same phase, but different frequencies. A
power combiner with good isolation is required to combine the two signals. Otherwise,
the power combiner itself may produce extra intermodulation products. The products
will be amplified by the DUT, which leads to a much larger intermodulation product at
the output, and thus introduce undesired errors when extract IP3 of the DUT. Proper
attenuators maybe included before the power combiner to provide low enough input
power level. DC bias circuits at the input and output are necessary for transistor
11
linearity characterization. The power spectrum is measured at the output by a PSA and
output IP3 (OIP3) is calculated by an Agilent 85672A spurious response utility installed
in the PSA. This utility can give not only the amplitude of the fundamental and IM3
products, but also the OIP3 value for the IM3 products.
Bias Tees
Spectrum Analyzer
Signal Generators
Power Combiner
Power Supply
Input
(DC+f1,f2)
Output
(DC+RF)
Fig. 1.6 An onwafer intermodulation linearity measurement system.
332H332H348H482H482HFig. 1.7 shows the fundamental and IM3 output products as a function of input
power level P
in
in dBm for a typical MOS transistor measurement. The solid lines are
the measured power values in dBm for the fundamental output product and the IM3
output product, P
out,1st
and P
out,3rd
. The dash straight lines are linear extrapolations of
P
out,1st
and P
out,3rd
at a very low reference P
in
. The reference P
in
for extrapolation must
be well below the 1dB compression point, which is 25dBm in 333H333H349H483H483HFig. 1.7. The 1 dB
compression point is the input power level where the small signal gain drops by 1 dB,
which sets the upper limit for small signal linearity analysis The intercept point of the
12
two dash straight lines is the third order intercept point (IP3). The input power level at
the IP3 point is IIP3, and the output power level at the IP3 point is OIP3. In 334H334H350H484H484HFig. 1.7, the
1dB compression point is 12dBm, IIP3=1.8dBm, OIP3=18dBm, and power gain=16.2
dB.
30 25 20 15 10 5 0 5
90
60
30
0
30
P
in
(dBm)
P
out
(dBm)
P
out,1st
P
out,3rd
3:1
1:1
OIP3
II
P
3
3rd order Intercept Point
(IP3)
1dB
Fig. 1.7 The fundamental and IM3 output products versus input power for a twotone
excited system.
Before extracting IIP3, OIP3 and power gain, the power loss on the input and the
output route, including RF cables and connectors, must be calibrated using a power
meter. The power loss on the input and the output route must be calibrated using
'
in in in
dBm dBm dB
PPL=? (1.1)
'
out out out
dBm dBm dB
PPL=+ (1.2)
13
'
in
P is the power level generated by the signal generator.
'
out
P is the output power level
monitored at the spectrum analyzer. P
in
is the actual input power level at the gate of the
NMOS transistor. P
out
is the actual output power level at drain terminal of the transistor.
L
in
and L
out
are the power losses on the input and output routes. L
in
and L
out
are
frequency dependent, and need to be determined for each frequency before
measurement. In practice, L
in
is much larger than L
out
, which can lead to a several dB
shift on IIP3 and power gain. Relatively speaking, the value of OIP3 is much less
sensitive to power calibration.
Instead of using twotone measurement, IIP3 can also be determined using
simulated or measured IV data and smallsignal parameters of the transistor, which just
requires DC and Sparameters measurement. For both measurement and simulation, DC
and Sparameters are much easier to obtained and much less time consuming. 335H335H351H485H485HFig. 1.8
compares first order IP3 with measured and simulated IP3. The derivation of first order
IIP3 is detailed in Appendix I. 3g
m
K is calculated using the 3
rd
order derivative of
DS
I
with respect to
GS
V only. The first order IIP3 expression fails in modeling the position
of the IP3 sweet spot and the gate voltage dependence of IIP3 in strong inversion region.
Analytical IIP3 expressions containing more nonlinearities have been published [11]
[22] [23] [24] [25] [26]. However the results are mainly for 0.13?m and older
technologies, and the MOS model focused is BSIM3V3 [10] [22] [27]. Experimental
results on 90nm technology and simulation results using BSIM4 model need to be
examined as they become the main stream for RFIC designs.
14
0.2 0.4 0.6 0.8 1
10
0
10
20
V
GS
(V)
II
P3 (
d
Bm)
First order IP3
Simulation
Measurement
N
f
= 64, W
f
= 2um, L = 90nm, V
DS
= 0.8V, f0 = 5GHz, ?f = 100KHz
K3
gm
= 0
Fig. 1.8 IIP3 versus
GS
V from first order IP3 theory, linearity simulation, and twotone
measurement.
1.3 Motivation and objectives
1.3.1 Highfrequency RF CMOS characterization
Emerging gigabit wireline and wireless communication applications require
integrated circuits operating at frequencies above 60GHz [28] [29] [30] [31]. This
demands accurate characterization and modeling of transistors at even higher
frequencies. Essential to obtaining a good highfrequency model is the accuracy of the
Sparameter measurement. VNA and RF probes capable of 110GHz Sparameter
measurements are commercially available over 10 years [32]. However, very few
results at such high frequencies are published. This is to a large extent due to the
increased difficulty of error calibration for both system errors and onwafer parasitics.
The industry practice is a twostep approach, which first correct the VNA system
errors using well established calibration standards on an impedance standards substrate
15
(ISS), a process known as system error calibration, and then subtract the onwafer pads
and interconnect lines using onwafer standards, a process known as onwafer de
embedding. Shortopenloadthru (SOLT) calibration is one of the system error
calibration methods embedded in all modern VNAs, e.g. VNA8510C, and is used in this
dissertation where twostep calibration is involved. The defacto standard technique of
onwafer deembedding is openshort [14], which however fails for frequencies above
2040 GHz, depending on layout design and process technology. Various alternatives to
open?short have been proposed, including threestep [15], improved threestep [16],
fourstep [33], and padopen?short [17]. These methods use more complicated, but still
lumped equivalent circuits, and hence require more onwafer standards. For instance,
the threestep methods of [15] and [16] require four onwafer standards. However, due
to the lumped nature of the equivalent circuits used, these methods cannot capture the
distributive nature of onwafer parasitics, and fail above 50 GHz as already shown in
336H336H352H486H486HFig. 1.5. For transistor characterization at extremely high frequencies, onwafer de
embedding methods that can accurately describe the distributive nature of onwafer
parasitics are urgently needed.
1.3.2 Fourport network for onwafer parasitics
As discussed in 337H337H353H487H487HChapter 2, the accuracy of error calibration is determined by the
error model, calibration standards, and calibration techniques. A unified 12term model
was developed in 1970s, and became a standard model for twoport VNAs. The SOLT
calibration technique is implemented in all modern VNAs to solve the 12 error terms
[34]. However, the 12term error model was shown to be insufficient for highfrequency
16
measurement, since the leakage errors were modeled using only two error terms in the
12term model [35] [36]. Same problem exists for error calibration techniques using
8(10)term model. The most complete error model for twoport system is a 4x4 matrix,
a 16term error model, which is essentially a fourport error network relating four
known waves and four unknown waves [35] [36]. Several advanced techniques solving
the fourport network have been developed over the years [36] [37] [38] [39]. The 16
term model and the calibration techniques can in general be applied to remove both
systematic errors and onwafer parasitics.
This leads to an idea of describing everything between the probe tips and the device
terminals as a fourport network instead of using lumped equivalent circuits [40] [20],
an idea that is similar to the 16term error adaptor in system error correction [36], at
least mathematically. 338H338H354H488H488HFig. 1.9 (a) illustrates the fourport network for system errors,
with two ports inside VNA and two ports at probe tips, which was described as 16term
or 15term error model frequently [36] [38] [39] [41] [42] [43]. 339H339H355H489H489HFig. 1.9 (b) shows the
fourport network for onwafer parasitics with two ports at probe tips and two ports at
device terminals, e.g. gate and drain for MOS transistors [20]. Note that all of the a
waves are incident waves which entering the fourport network at each port, while all of
the b waves are reflected waves which leaving the fourport network at each port.
Therefore, the Sparameters of the fourport networks in 339H339H356H490H490HFig. 1.9 can be easily defined
using the a and b waves. Analytical solutions of the fourport parasitic network were
developed in [19] [17] [20] and [44], using three, four, and five onwafer standards with
varying degree of assumptions. For example, with reciprocal assumption, the number of
unknowns is reduced to ten and only four onwafer standards are necessary [45]. With
17
reciprocal and symmetric assumptions, the number of unknowns is reduced to six and
only three onwafer standards are necessary [17].
Port 0
(VNA)
Port 3
(VNA)
0
a
0
b
3
a
3
b
Port 1
(Probe)
Port 2
(Probe)
DUT
4port
error
adaptor
1
b
1
a
2
b
2
a
(a)
Port 1
(Probe)
Port 2
(Probe)
1
b
1
a
2
b
2
a
Port 1*
(Gate)
Port 2*
(Drain)
[SA]
4port
onwafer
parasitics
*
1
b
*
1
a
*
2
b
*
2
a
(b)
Fig. 1.9 (a) The fourport network for systematic errors. (b) The fourport network for
onwafer parasitics.
1.3.3 General fourport solution
Even though onwafer parasitics is passive and the associated fourport network
should be reciprocal, there are two practical reasons to seek for a solution for generic
fourport network, which we will refer to as ?general fourport solution.? First, in order
to arrive at an analytical solution, a must for realtime fast measurement, onwafer
OPEN and SHORT standards are assumed to be ideal in all of the deembedding
algorithms, while the fabricated standards always have parasitics. In board
measurements, inaccuracies of standards are known to lead to nonreciprocal S
parameters for physically passive structure [46]. A general fourport solution will allow
us to examine the reciprocity of the fourport parasitics experimentally.
The second reason for seeking a general fourport solution is to directly obtain
transistor Sparameters from the measured raw Sparameters without having to perform
18
system error calibration using ISS. This can result in significant saving in time and
effort as ISS calibration is time consuming and needs to be repeated frequently, even
during a day of measurement. Also, physical change of substrate is involved. Ideally,
the same general fourport solution obtained for onwafer parasitics deembedding can
be applied to raw Sparameters as is, to remove VNA system errors and onwafer
parasitics in a single step. Not all of the general fourport solutions can be used for
singlestep calibration. For instance, the solution of [20] can be used, while the solution
of [19] cannot be used. The fourport deembedding algorithms of [20] and [19] make
no assumption of the nature of onwafer parasitics, while the algorithm of [17] assumes
that the fourport network for onwafer parasitics is reciprocal and symmetric.
In this dissertation, two general fourport solutions that can be applied as single
step calibration are developed, 1) a Yparameter based analytical solution and 2) a
singularvaluedecomposition (SVD) based numerical solution. With five onwafer
standards, both of them solve a generic fourport network and can be applied on the
measured raw Sparameters without ISS calibration. The results were presented in 2007
Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems [19], 2007
IEEE Trans. On Electron Devices [45] and 2007 IEEE/MTTS International Microwave
Symposium [47]. The analytical fourport solution in [45] is much simpler than [20] and
[19], and considers the parasitic capacitance of the nonideal onwafer load resistors. An
added advantage of this solution is its intimate relation with openshort, which is then
used to quantify the errors left after openshort deembedding. However, the Y
parameter analytical solutions in [20], [19] and [45] are all limited by specified on
wafer standards and cannot take advantage of the redundancy available from the
19
measurements of five onwafer standards, e.g. singularities [36]. These issues are
ideally handled with the SVD based numerical solution in [47]. Although the SVD
based fourport solution cannot give insight views of the parasitic network, it is easy to
apply with multiple combinations of onwafer standards and provides an indication of
the validity of the solution. This dissertation presents detailed derivation of the
analytical solution and the numerical solution, and demonstrates their utility on a
0.13?m RF CMOS technology from 2 to 110GHz for both twostep calibration and
singlestep calibration.
1.3.4 Singlestep calibration
With a general fourport solution, it is possible to solve the fourport network
between the two ports inside VNA and the two ports at the device terminals. The known
standards are fabricated on the same wafer as the desired device. This idea of utilizing
onwafer standards to remove systematic errors and onwafer parasitics in a single step
was not new. Actually it was introduced at the very beginning of VNA error correction.
However, it is not widely used for transistor characterization for several reasons. First,
error calibration using ISS standards are repeatable and traceable, which can be verified
using stated references. For example, National Institute of Standards and Technology
(NIST) in USA and the National Physical Laboratory (NPL) in UK provide and
maintain reference standards. By comparing the calibrated VNA results with the
reference Sparameters, the performance of VNAs can be verified. With onwafer
standards, the Sparameters of these standards are determined by the technology, which
can very a lot from process to process. It is hard to provide reference standards and
20
verification kits. Fortunately, the measurement comparison programs (MCP) provide
another way to assure measurement accuracy. MCP compares the results of the same
device that travel between the participating laboratories to avoid serious errors or
provide verification on areas without reference standards. The MCP program illuminate
us that the singlestep calibrated results can be verified using twostep results for
several onwafer reference standards. Although, ISS calibration is still necessary for
verification purpose, it still greatly reduces the measurement time since these reference
results just need to be measured once for one wafer. It does not need to be repeated for
every test structure.
Secondly, it is hard to accurately model the onwafer standards. The standards on
ISS substrate are modeled using nonideal capacitance, inductance, and delay time
based on physical analysis and verified using reference values. The accuracy of the on
wafer standards affects the accuracy of the error corrected Sparameters. The
experimental results in 491H491HChapter 6 indicate that assuming ideal onwafer standards leads
to reasonably accurate results in the advance CMOS technology examined. The open
capacitance, the short inductance, and the through delay are negligible because of the
small dimension of the transistors. The nonideality of onwafer load resistor can be
modeled using a parasitic capacitor in parallel with a perfect resistor. The experimental
results in 492H492HChapter 6 indicate that singlestep fourport calibrated results are practically
identical to the twostep fourport calibrated results after switch error removal.
21
1.3.5 Validity of BSIM4 model for nonlinear RF modeling
The model parameters extracted from DC, CV, and Sparameters are based on a
smallsignal schematic, and accurate for smallsignal modeling of transistors. For
transistor modeling at signals higher than certain value, they do not represent the real
transistor performance. In general, the linear model need to be verified using nonlinear
simulation [8]. The intermodulation linearity simulation accuracy of the BSIM4 model,
a widely used model for RF design, is examined against measurement, particularly in
the moderate inversion region, where a linearity sweet spot exists and can be utilized for
high linearity RF circuit design [48] [49]. In BSIM4, the moderate inversion region is
modeled by mathematical smoothing functions interpolating between physics based
approximations in the weak and strong inversion regions, instead of physics based
surface potential approximation that can cover all levels of inversion. Its accuracy in
linearity simulation, particularly in moderate inversion, therefore needs to be
experimentally evaluated, as linearity simulation requires not only accurate modeling of
the first order IV relations, but also higher order derivatives. Note that we do not
address simulation of harmonic or intermodulation distortion at
DS
V =0V, a known
problem for BSIM4 [50].
1.3.6 Third order intercept point modeling
The nonlinear performance of transistors is typically measured by the 1dB
compression point and the third order intercept point (IP3). Using either measured or
simulated IV data, IP3 sweet spot biasing current can be determined from zero 3g
m
K
point based on first order IP3 theory [11] [51]. Circuits have been published to utilize
22
this zero 3g
m
K point for high linearity LNA designs [48] [52]. However, experimental
IP3 results indicate that the actual IP3 sweet spot
GS
V is lower than the zero 3g
m
K
GS
V
by a noticeable amount as already shown in 340H340H357H493H493HFig. 1.8 [53]. More accurate analytical IP3
expressions for CMOS devices involving more nonlinearities have been developed
recently [22] [25] [26]. The complete IP3 expression developed in this dissertation
considers not only transconductance nonlinearities, but also output conductance
nonlinearities and cross terms. This expression is used to quantify the impact of these
nonlinearities and explain the biasing, device size, and frequency dependence of IP3.
Furthermore, guidelines for optimal biasing and sizing for high linearity are developed.
1.3.7 Third order intermodulation distortion characterization
Experimental IP3 results of CMOS devices have been examined using twotone IP3
measurement [22]. However the results were primarily for 0.13?m and older
technologies, and the model examined is BSIM3V3 [10] [22] [27]. This dissertation
presents experimental characterization of IP3 in a 90nm RF CMOS process, as well as
comparing measured IP3 with simulated IP3 using a BSIM4 model. For practical
linearity characterization as well as optimal transistor sizing and biasing in circuit
design, the linearity is examined as a function of biasing voltages and device sizes. An
array of devices with different finger numbers are designed, fabricated and
characterized as a function of V
GS
and V
DS
, at multiple frequencies. 2GHz, 5GHz, and
10GHz are selected because most current RFIC applications fall in this range. In
particular, the sweet spot biasing current for practical large device sizes of interest to
RFIC is investigated. The results were presented in 2008 IEEE Radio Frequency
23
Integrated Circuits Symposium [53] and the extended paper was accepted by 2008 IEEE
Trans. Microwave and Techniques [54].
1.4 Outline of Contributions
341H341H358H494H494HChapter 1 gives an overview of topics related to onwafer transistor
characterization including linear and nonlinear performance, and gives the motivation
of this research. 342H342H359H495H495HChapter 2 presents layout details of onwafer transistors and standards.
Carefully designed GSG probing pads, metal ground plane, and shielding structures can
help onwafer parasitics deembedding and transistor characteristics. Transistors with
different gate connection topologies are compared.
The accuracy of Sparameters is determined by error models and correction
techniques. 343H343H360H496H496HChapter 3 presents the fourport error adaptor concept, the classical 12term
model, and the most complete 16term model for a twoport system. As a widely used
system error calibration method, shortopenloadthru (SOLT) calibration is
demonstrated in details. And, the idea of performing singlestep calibration is
introduced.
Starting from 344H344H361H497H497HChapter 4, the concept of fourport error adapter is extended to on
wafer parasitics deembedding from systematic error calibration. A generic analytical
fourport solution for onwafer parasitics using Yparameters is developed in 344H344H361H498H498HChapter 4.
Five specified onwafer standards, OPEN, SHORT, LEFT, RIGHT, and THRU, are
necessary for solving the fourport network. A numerical way to evaluate the errors
remaining after openshort deembedding, and to examine the reciprocity and symmetry
of onwafer parasitics is given using experimental results. 345H345H362H499H499HChapter 5 presents a
24
numerical fourport solution for onwafer parasitics using singularvaluedecomposition
(SVD). Although it does not give insight views of onwafer parasitics, the SVD based
solution is easy to apply and gives the most accurate deembedded results. Although the
set of standards can be any nonsingular combination of five standards, the same OPEN,
SHORT, LEFT, RIGHT, and THRU standards as used in analytical solution is used for
comparison. 346H346H363H500H500HChapter 6 demonstrates the application of the two fourport solutions in
347H347H364H501H501HChapter 4 and 348H348H365H502H502HChapter 5 on singlestep calibration.
Another topic that draws the attention of circuit designers is the linearity
(nonlinearity) of the transistors, which determines upper limit of the spurious dynamic
range of transistors or circuits. 503H503HChapter 7 evaluates the BSIM4 model for a 90nm RF
CMOS technology, which is later used to generate the IV and smallsignal parameters
needed to calculate IP3 analytically. 349H349H366H504H504HChapter 8 develops a valuable analytical IP3
expression for MOS transistor nonlinearity modeling. The expression is developed
based on Volterra series theory using simulated IV and Sparameters. Biasing, channel
width, and frequency dependence of IP3 are well understood using this analytical
expression. 350H350H367H505H505HChapter 9 compares the calculated IP3 with experimental IP3 for the 90nm
RF CMOS technology. Guidelines for optimizing highlinearity applications are given
based on experimental results and calculated IP3.
25
Chapter 2
ONWAFER TEST STRUCTURE
Since a pair of Cascade infinity probes are used to contact the onwafer test
structure, there are several layout rules regarding probe pad placement and sizing that
must be followed [55]. Typical contact size of Cascade infinity probes is 12?m?12?m.
To achieve reliable contact, it is recommended to further bring the probe down by 50
75?m after the probe tip has made initial contact with the wafer surface, which leads to
a 2540?m lateral skating. Thus, the minimum probing area recommended for general
use is 50?m?50?m [55]. And, the minimum centertocenter space between pads is
100?m. The sizing and spacing requirements for onwafer probing make it impossible
to place the probes directly on the terminals of a modern MOS transistor since the
dimension of a typical MOS transistor is only several microns big. Probing pads and
interconnect lines leading to the terminals of the transistor are necessary for onwafer
transistor characterization. The GSG probing pads designed for onwafer
characterization are illustrated in Section 351H351H368H506H506H2.2.
Ground shield was proved to be able to improve noise performance and onwafer
deembedding [56] [57] [58]. The first metal layer is used to build the ground shield
metal plane as detailed in Section 352H352H369H507H507H2.2. It was shown that different gate geometry can
affect the DC and RF performance [56] [59] [60] [61]. An array of CMOS transistors
with different gate pattern are carefully designed and fabricated. Several parameters that
CHAPTER
26
are critical to RF and noise performance of CMOS transistors are extracted and
compared for different gate pattern in Section 353H353H370H508H508H2.3.
2.1 Typical onwafer transistor test structure
354H354H371H509H509HFig. 2.1 (a) is the top view of an onwafer test structure for a MOS transistor with
probing pads and interconnections. GSG probing pads are designed for the GSG
Cascade infinity probes, which can shield the signal path between two balanced ground
paths and provide tight control on the fields around the signal probe. The dimension of
the probing pads and interconnections are much larger than the transistor. 355H355H372H510H510HFig. 2.1 (b)
gives a closer view of the MOS transistor under test. The four terminal MOS transistor
is connected as a twoport system with source and substrate tied together to ground. The
MOS transistor in general has multiple gate fingers to reduce gate resistance and a
substrate ring around the whole active area to provide better shielding from adjacent
structures. The channel width of MOS transistors can be modified by either changing
the width of each finger or changing the number of fingers.
27
PORT2
PORT1
Gate Fingers
Drai
n
Gat
e
GND
GND
Substrate Ring
(a) MOS+PAD (b) MOS only
So
ur
c
e
GND GND
GND GND
150?m
10
0/
15
0
?m
20?m
Fig. 2.1 The top view of an onwafer test structure for transistors. (a) The whole test
structure including probing pads. (b) The MOS transistor under test only. The
dimension is not to scale.
356H356H373H511H511HFig. 2.2 shows the pictures of the chips taken under the microscope. 357H357H374H512H512HFig. 2.2 (a)
shows the chip fabricated on a 0.13?m RF CMOS technology for developing fourport
calibration techniques. Each column contains five onwafer standards and a 0.13?m
NMOS transistor. An array of 90nm NMOS test structures with different gate
connections and different layouts is fabricated on the 90nm chip in 358H358H375H513H513HFig. 2.2 (b). The
measured Sparameters are used for characterizing the effects of different gate patterns
on smallsignal parameter extraction. The chip in 359H359H376H514H514HFig. 2.2 (c) contains an array of
devices for intermodulation linearity characterization on 90nm CMOS technology. The
necessary deembedding standards are also included in 360H360H377H515H515HFig. 2.2 (b) and (c), which are
laid close to the transistor structures to avoid space variation [62]. The smallsignal
parameters for the equivalent circuit used to calculate IP3 can be extracted from the
measured Sparameters.
28
(a) 0.13?m
CMOS
(b) 90nm CMOS (c) 90nm CMOS
Fig. 2.2. Chip pictures of the fabricated transistor structures on three RF CMOS
technologies. (b) and (c) are fabricated at different foundries.
2.2 Probing pad design considerations
361H361H378H516H516HFig. 2.3 illustrates the cross section of a modern RF CMOS technology. It starts
with a silicon substrate, which is normally lightly ptype doped. Active devices,
including diodes, bipolar transistors, and CMOS transistors, and some of the passive
devices, like poly resistors, are built on the very surface of the silicon substrate using
doped materials. 14 thin metal layers (about 30nm thick) either aluminum or copper
will be used for connections close to device terminals. These connections are thin and
narrow, which can only handle low current, and has a higher resistance. Besides, the
first metal layer is usually used as a metal ground plane under the probing pads and the
interconnections to prevent the signal paths from coupling to the substrate [58] [63]. 24
thick metal layers (about 50nm thick) with low sheet resistance will be used for long
29
and high current connection. The RF layer, normally composing two thick aluminum
metal layers (several micron thick), is used to build the probing pads. A passivation
layer is used to protect the whole structure, and opening must be made on top of the
probing pads.
SD
G
PORT1
PAD
PORT2
PAD
GND
PAD
Substrate Ring
Si subst
r
ate
Thi
n
Metal
Th
i
c
k M
e
ta
l
RF
Metal
Me
t
a
l G
r
ou
nd
P
l
an
e
Passivation layer
Pad opening
Ptype substrate
Oxide
Vias
Fig. 2.3 Cross section view of an advanced RF CMOS technology. The dimension is
to scale.
362H362H379H517H517HFig. 2.4 shows the cross section view of three cuts along the test structure in 363H363H380H518H518HFig.
2.1 (a). The maximum pad height variation in a row of pads contacted by one GSG
probe is 0.5?m. To avoid pad height variation, the top metal layer for all ground pads
and signal pads are the same. To support the overtravel of probe tips while probing, the
pads are built using multiple metal layers, since even the thickest metal layer is less than
30
10?m thick. 364H364H381H519H519HFig. 2.4 (a) is just a copy of 520H520HFig. 2.1 (a) with three cut lines for the cross
sections in 521H521HFig. 2.4 (b)(d). The cross section of the GSG pads is shown in 364H364H381H522H522HFig. 2.4 (b).
The ground pad is built using all metal layers, and the signal pad is built using the top
two thick metal layers. The number of metal layers used for signal pads depends on the
number of layers available and the metal layer thickness. The ground pads are all tied to
the same metal ground plane built using the first metal layer to provide an as ideal as
possible connection between the four ground pads. The metal ground plane exceeds the
dimension of the signal pad by a size comparable to the total thickness of all metal
layers to provide good electromagnetic isolation from the silicon substrate [58] [57]. A
large number of substrate contacts are scattered over the wafer to provide good
substrate connection and meet the requirement of doping and active area density.
365H365H382H523H523HFig. 2.4 (c) shows the cross section of the cut along the middle between Port 1 and
Port 2 pads, which shows that the connections between opposing ground pads (Port 1 to
Port 2 side) are built using all available metal layers. This helps to provide an ideal and
unified ground connection. The source is tied to the substrate ring locally, while the
substrate ring is connected to the metal ground plane using short and wide metal lines.
The grounded substrate ring can isolate the transistor from adjacent structures. 366H366H383H524H524HFig. 2.4
(d) is along a cut across the signal pads at Port 1 and Port 2. Not only the signal pads
but also the interconnect lines to the transistor terminals are built using more than one
metal layer. This will evidently reduce series parasitics of the leads, and increase the
accuracy of the SHORT standard, but introduce coupling to the ground shield, thereby
increase the loss. In general, it is safe to apply at least a few of the metal layers [57].
31
PORT2PORT1
GND GND
GND GND
(a) MOS+PAD
Cut#1 Cut#2
Cut#3
(b) Cut#1
Ptype substrate
Oxide
GGS
(c) Cut#2
(d) Cut#3
PORT1
Substrate Ring
Source & Substrate Ring tied
to metal ground plane
SD
Metal on
drain finger
Gate finger
PORT2
Substrate Ring
Metal on
drain finger
Metal ground planeMetal ground plane
Gate finger
Ground shield
extension
Fig. 2.4 The cross section view of GSG pads and MOS transistor along three cuts.
32
2.3 CMOS transistor design considerations
367H367H384H525H525HFig. 2.5 gives the layout of a MOS transistor with 10 gate fingers. Each finger has a
channel length of 0.13?m, and a channel width of 5?m with doublesided gate contact.
This leads to a ?Clook? gate metal connection to Port 1. Port 2 is connected to the drain
terminal of the transistor. The source terminal is tied to the substrate terminal and
grounded. Multiple thick metal layers are used to connect the source and substrate to the
ground pads to reduce substrate effect and nonidealities of onwafer standards.
Gate Fingers
with Doublesided
Gate Contact
(Nf=10)
Dra
i
n (Met
al
2)
G
a
te
(Met
al 1
)
Clook
Gro
und (Th
i
ck Metal
)
Substrate Ring
Source (Metal 2)
(Tied to Substrate Ring)
Gro
und (Th
i
ck Metal
)
Contacts to Ground
Fig. 2.5. Layout for one cell of the desired transistor.
33
369H369H386H526H526HFig. 2.6 gives the layout of the desired NMOS transistor and the five onwafer
standards used to solve fourport error adaptors, OPEN, SHORT, LEFT, RIGHT, and
THRU. 370H370H387H527H527HFig. 2.6 (a) is the desired NMOS transistor without pads and most of the
interconnect lines. The total channel width of the transistor is 150?m, and the channel
length is 0.13?m. The transistor contains three identical cells, i.e. multiplier factor=3.
Each cell has the same layout as shown in 371H371H388H528H528HFig. 2.5. Without specification, the S, Y,
and Z parameters used to perform error correction from 372H372H389H529H529HChapter 4 to 373H373H390H530H530HChapter 6 are
measured on this set of test structures fabricated on the 0.13?m chip in 531H531HFig. 2.2 (a).The
reference plane is selected to be as close as possible to the gate and drain terminals of
the transistor, which is marked out on the OPEN structure in 374H374H391H532H532HFig. 2.6 (b).
34
(a) NMOS (b) OPEN (c) SHORT
(d) LEFT
(e) RIGHT (f) THRU
Port 1
reference
Port 2
reference
Fig. 2.6. Layout for the desired transistor, NMOS, and the onwafer standards, OPEN,
SHORT, LEFT, RIGHT and THRU.
The OPEN structure in 375H375H392H533H533HFig. 2.6 (b) just takes the transistor out together with the
substrate ring and the necessary lowest layer metal connections. The SHORT structure
in 376H376H393H534H534HFig. 2.6 (c) shorts the metal at the Port 1 and Port 2 reference plane to ground using
short and wide metal lines. Multiple metal layers can be used if necessary. LEFT
structure in 377H377H394H535H535HFig. 2.6 (d) has two 100? metal resistors connected to Port 1 in parallel to
provide balanced signal flow at the GSG probe. In like manner, RIGHT structure in 378H378H395H536H536HFig.
2.6 (e) has the same two 100? resistors connected to Port 2 in parallel. One end of the
35
resistors is connected to the reference metal as close as possible to Port 1 or Port 2. The
other end is terminates to ground. However, it is hard to connect this end to the same
ground plane as the SHORT structure because of the size limitation of this backendof
line (BEOL) resistor. So, there is a reference plane variation between OPEN, SHORT
and LEFT, RIGHT. Assuming the ground plane is very well connected throughout the
whole structure, this variation is negligible. The THRU structure in 379H379H396H537H537HFig. 2.6 (f) simply
shorts Port 1 reference to Port 2 reference in the shorted way. Since the metal line used
to short Port 1 and Port 2 are wide and very short, comparable to the pattern of gate
fingers, THRU standard can be considered as ideal THRU without delay and loss.
2.3.1 Gate pattern and multiplier factor
380H380H397H538H538HFig. 2.7 shows the layout for three NMOS transistors with the same gate length and
total gate width, but different gate patterns and multiplier factors (M). The three
transistors have (a) doublesided gate contact with M=1, (b) singlesided gate contact
with M=1, and (c) doublesided gate contact with M=4. Note that the ?Clook? gate
metal connection is used for doublesided gate contact to balance the current flow at the
twoends. The transistor with singlesided gate contact is directly connected to Port 1
using wide metal lines. This set of layout is used to investigate the impact of the ?C
look? gate metal and the multiplier factor on the RF and noise performance.
36
(a)
(b)
(c)
Doublesided
Gate Contact
C
l
ook
Gat
e
Me
tal
Port1
Substrate
Ring
Drain Metal
Port1
Dr
ai
n M
e
tal
Port1
Dr
ai
n
Me
t
al
Port2
C
l
ook
Gat
e
Me
tal
Doublesided
Gate Contact
Singlesided
Gate Contact
M=4
#1 #2
#3 #4
Substrate Ring
(tied with
source)
M=1
M=1
Fig. 2.7. Layout for NMOS transistors with different gate patterns and multiplier
factors.
The gate resistance
g
R , linear transconductance
m
g , cutoff frequency
T
f , and
maximum oscillation frequency
max
f are the critical parameters for evaluating the RF
and noise performances of a MOS transistor [56]. SOLT calibration is used for system
error calibration. Since the parameters examined here are extracted at frequencies below
10GHz, openshort is valid in this frequency range [14] [45].
T
f is extracted using the 
20dB/dec extrapolation method from the
21
H versus frequency curve at each bias point.
max
f is extracted using the 20dB/dec extrapolation method from the Mason?s unilateral
37
gain (MUG) versus frequency curve at each bias point [64]. An example of
T
f and
max
f extraction is shown in 382H382H399H539H539HFig. 2.8 and 540H540HFig. 2.9. Maximum available gain (MAG) and
maximum stable gain (MSG) do not follow the 20dB/dec slope, and thus are not used
for
max
f extraction.
g
R and
m
g are extracted using [65]
()
()
21
2
11
g
low frequency
Y
R
Y
?
=
?
and
( )
21
m
lowest frequency
gY=? (2.1)
10
8
10
9
10
10
10
11
0
20
40
60
frequency (Hz)
H2
1 (
d
B
)
20dB/dec
f
T
Fig. 2.8. An example for
T
f extraction.
10
8
10
9
10
10
10
11
0
20
40
60
frequency (Hz)
MUG (dB) 0
20
40
MAG & MSG
(dB)
20dB/dec f
max
MSG
MAG MUG
Fig. 2.9. An example for
max
f extraction.
38
541H541HFig. 2.10 compares
g
R ,
m
g ,
T
f and
max
f extracted for the three NMOS transistors.
383H383H400H542H542HFig. 2.10 (a) and (c) show that the transconductance and the cutoff frequency for the
three transistors are approximately the same. 384H384H401H543H543HFig. 2.10 (b) shows that the transistor with
doublesided gate contact and M=4 has the smallest gate resistance, and thus the best
noise performance theoretically. Noise parameters are not measured due to lack of
equipments. The transistor with singlesided contact and M=1 does not have the largest
g
R as expected. Instead, the transistor with doublesided contact and M=1 gives the
largest
g
R . The reason may lies on the narrow metal connection from the reference
plane to the doublesided gate contact, while a much wider metal connection is used in
singlesided gate contact transistor in 544H544HFig. 2.7 (b). However, it is not possible to move
the reference plane to the end of the narrow gate metal inside the substrate ring, as it is
impossible to layout deembedding standards in such small area. Fortunately, this
problem can be solved by using different metal connections to the gate. For example,
the transistor layout with M=4 greatly reduces the resistance on the narrow metal lines
because it has four similar parallel connections. 385H385H402H545H545HFig. 2.10 (d) shows that
max
f is quite
different for the three transistors. The device with singlesided gate contact and M=1
and the transistor with doublesided contact and M=4 gives the highest
max
f . This
agrees with the lowest
g
R of these two transistors.
39
0 0.5 1
0
50
100
150
g
m
(mS)
0 0.5 1
4
6
8
10
12
R
g
(
?
)
0 0.5 1
0
60
120
180
f
T
(GHz)
V
GS
(V)
0 0.5 1
0
60
120
180
f
max
(GHz)
V
GS
(V)
double gate, M=1
single gate, M=1
double gate, M=4
(a)
(b)
(c)
(d)
Fig. 2.10. Extracted parameters for three NMOS transistors with different gate patterns
and multiplier factors.
2.3.2 Gate finger configuration
386H386H403H546H546HFig. 2.11 shows the layout for three NMOS transistors with the same gate length
and total gate width, but different number of fingers (N
f
) and finger width (W
f
). The
number of fingers and the finger width of the three transistors are (a) N
f
=20, W
f
=2?m.
(b) N
f
=10, W
f
=4?m. (c) N
f
=5, W
f
=8?m. All of the transistors are laid out using double
sided gate contact and ?Clook? gate metal connection. 387H387H404H547H547HFig. 2.12 (a)(d) compare
g
R ,
m
g ,
T
f , and
max
f extracted from openshort deembedded Yparameters. Again, SOLT
calibration and openshort are used for system error calibration and onwafer parasitics
deembedding. The first two transistors with N
f
=20, W
f
=2?m and N
f
=10, W
f
=4?m are
40
practically the same for the four parameters extracted. The transistor with the longest
W
f
(W
f
=8?m) has the largest
g
R and thus the lowest
max
f as expected. However, the
g
R value difference does not follow ideal scaling rules of CMOS transistors. The
reason may also lies on the narrow metal connection to the doublesided gate contact.
The
g
R value extracted is dominated by the resistance on the metal lines instead of the
gate fingers.
(a)
(b) (c)
Nf=20
Wf=2?m
Nf=10
Wf=4?m
Nf=5
Wf=8?m
Fig. 2.11. Layout for three NMOS transistors with same total channel width but
different finger width and finger number. W
total
=40?m.
41
0 0.5 1
0
10
20
30
40
g
m
(mS
)
0 0.5 1
0
10
20
30
40
R
g
(
?
)
0 0.5 1
0
50
100
150
200
f
T
(G
H
z
)
V
GS
(V)
0 0.5 1
0
50
100
150
200
f
max
(GHz)
V
GS
(V)
N
f
=20, W
f
=2?m
N
f
=10, W
f
=4?m
N
f
=5, W
f
=8?m
(a)
(b)
(d)
(c)
Fig. 2.12. Extracted parameters for three NMOS transistors with same total channel
width but different finger width and finger number. W
total
=40?m.
2.4 Summary
The layout rules concerning reliable onwafer probing are detailed. It is
recommended to use all metal layers for ground pad, and more than one top layer for
signal pads. Ground shield need to be carefully designed. The transistor characteristic
fluctuation caused by layout variation is examined. Doublesided gate contact does not
necessarily provide lower gate resistance. The gate pattern needs to be optimized.
Otherwise, the metal lines connecting out can have considerable impact on gate
resistance. On the other hand, the selection of reference plane is of great important for
transistor characterization.
42
Chapter 3
ERROR MODELS FOR TWOPORT SPARAMETER MEASUREMENT
Of paramount importance in onwafer transistor characterization at RF frequencies
is to properly correct the errors introduced by the VNA system and onwafer parasitics
[66] [13] [21] [12]. The demand for increased measurement accuracy in onwafer S
parameter measurement can be achieved by improving the hardware, the models used
for characterizing measurement errors, the calibration methods used for calculating
these errors, and the definitions of calibration standards [34]. The type of the error
model depends on the hardware topology of the VNA. There are threereceiver VNA
and fourreceiver VNA for twoport measurement. The threereceiver VNA has one
reference receiver for detecting the incident signal, and two measurement receivers, one
at each port. The corresponding error model is a 12term error model, 6 for forward
direction, 6 for reverse direction [67] [68]. For doublereflectometer VNA with four
receivers, a 8term error model was introduced and solved in Sparameters and T
parameters [69] [70] [71]. The leakage terms can be added to the to the 8term error
model, one for each measurement direction, increasing the number of error coefficients
to 10 [72] . Both the 8(10)term model and the 12term models are used for four
receiver VNA, which even have their calibration procedures embedded in modern
VNAs. The error models and their corresponding calibration techniques are compared
in [73] [74] [68] [75]. If required, several techniques with different conversion
CHAPTER
43
equations can be used to convert the 12term model into a 8(10)term model [75] [76].
These equations are slightly different but are based on the same physical principle. One
may also apply the 8(10)term model for the threereceiver VNA, with an assumption
that the source match equals the load match of the test set, which holds only in the case
of an ideal switch. For a real system, this may lead to intolerable measurement
inaccuracy. Only the 12term model guarantees the entire description of threereceiver
VNA [34]. The reasons will be detailed in Section 388H388H405H548H548H3.4.
However, both the 8(10)term model and the 12term model make an arbitrary
assumption that the leakage terms bypassing the unknown twoport are negligible.
Further measurement experiments and practical experiences reveal that the leakage
terms can have a very complicated nature. A much more general concept of error model
was introduced by Speciale and Franzen in 1977 [37] [35]. The systematic errors of a n
port VNA are represented by a 2nport virtual error adapter, with its nport connected to
the nport unknown network, and its other nport connected to the ideal, errorfree VNA.
The error adapter consists of 2n?2n coefficients and describes all possible paths
between the 2n receivers. For twoport measurement, the error adapter is a fourport
network, which involves 4?4 error coefficients, i.e. a 16term model. The 16term
model is only solvable for fourreceiver (2nreceiver) VNA. However, it is also possible
to define a full error model for threereceiver (n+1 receiver) VNA. This includes
significantly more error coefficients, for example, the 22term model for a three
receiver twoport VNA, compared with the 16term model for fourreceiver twoport
VNA [42]. The fourport error adapter can not only be applied on systematic error
removal, but also be used to remove onwafer parasitics as it does not make any
44
assumptions of the error network. The fourport error network is described in Section
389H389H406H549H549H3.5. There are also techniques published to solve the 16term model in S or T
parameters using five standards [35] [37] [36] [41] [43] [39]. Two general approaches
to solve the fourport error network using five standards are developed in this
dissertation, an analytical solution based on Yparameters in 390H390H407H550H550HChapter 4, and a numerical
solution using SVD and Tparameters in 391H391H408H551H551HChapter 5.
3.1 Twoport Sparameter measurement
552H552HFig. 3.1 is the block diagram for the twoport Sparameter measurement system in
553H553HFig. 1.2, which includes VNA8510C system, DC power supply, and a control computer.
The measurement is controlled by a MATLAB program on the computer through a
USB to GPIB controller. For each measurement, the program first biases the DUT by
sending GPIB commands to the DC power supply, then starts one single frequency
sweep by sending GPIB commands to the VNA?s processor. The DC voltage is added
to the DUT through two bias tees inside the VNA test set. Two DC cables connect the
outputs of the DC power supply to the test set from the backside of the two equipments,
which are illustrated using dash lines in 554H554HFig. 3.1.
45
Test Set
Synthesized
Sweeper
Display &
Processor
IF/Detector
(Receiver)
Agilent 8510C system
GPIB
Cable
SYSTEM BU
S
Computer
DUT
GPIB
Controller
Vport1 Vport2
DC power supply
Fig. 3.1 Block diagram for twoport Sparameter measurement using Agilent 8510C
system.
555H555HFig. 3.2 shows the simplified block diagram of a twoport system involving a four
receiver VNA and an unknown twoport. The two bias tees are assumed to be ideal for
AC signals and thus not included. In Section 556H556H3.2, it will be shown that the errors
introduced by the bias tees are actually included in the fourport error adapter. A dual
reflectometer is attached to the input of the unknown twoport DUT, and another one is
attached to the output. Thus, the VNA has four receivers, two at each port, to capture
the incident and reflected waves at each port. A switch changes the direction of the
incident power to the unknown DUT for forward and reverse measurements, and
terminates the unknown DUT at an impedance
0
Z . The four Sparameters exported by
46
the VNA are actually the ratios of the incident and reflected waves monitored by the
two dualreflectometer.
11 0 0
/Sba= and
21 3 0
/Sba= are calculated when the switch is
at forward position as
0
a is the incident signal and
0
b and
3
b are the reflected waves.
12 0 3
/Sba= and
22 3 3
/Sba= are calculated when the switch is at reverse position as
3
a
is now the incident signal.
DUT
0
Z
RF
Source
Dual
Reflectometer
1
b
1
a
2
b
2
a
Forward
Reverse
Port 1
Port 2
3
b
3
a
0
b
0
a
Switch
Fig. 3.2 A twoport VNA system with four receivers.
If
0
Z is a perfect matched load and the switch is ideal, the waves and the S
parameters can be related through
0110123
321023
bSaSa
bSaSa
=+
=+
. (3.1)
Under forward mode,
3
0a = , the equation reduces to
0110
bSa= and
3210
bSa= . Under
reverse mode,
0
0a = , 393H393H410H557H557H(3.1) becomes
0123
bSa= and
3223
bSa= . Therefore, the
measured Sparameters,
M
S , are the wave ratios calculated,
47
11 12 11 12
21 22 21 22
MM
M
MM
SS SS
S
SS SS
? ?? ?
==
? ?? ?
? ?? ?
. (3.2)
If
0
Z is not a perfect matched load or the switch is nonideal, i.e.
3
0a ? in forward
mode, and
0
0a ? in reverse mode. The waves measured under forward mode and
reverse mode can be combined as
''
00 1 111 12
33 3321 22
MM
MM
bb aaSS
bb aaSS
? ?????
=
? ?????
??? ???
. (3.3)
The superscript ?'? differs the waves measured in reverse mode from the waves
measured in forward mode.
M
S can be calculated from the wave ratios as [39]
11 12 21 1 12 11 12 2
21 22 21 1 22 21 12 2
M
SSS SSS
DD
S
SSS SSS
DD
???? ??
??
=
?? ??
??
,
3
1
3
forward
a
b
?= ,
'
0
2
'
0
reverse
a
b
?= . (3.4)
21 12 1 2
1DSS=? ??.
1
? and
2
? are the two additional wave ratios measured under
forward and reverse mode while probing a THRU standard, which can only be
measured by fourreceiver VNAs. The process to remove the switch errors caused by
the nonideal switch and imperfect
0
Z load is called ?switch error removal?, which can
only be performed on fourreceiver VNAs. Fortunately, most of the modern VNAs are
fourreceiver VNA. The derivation of the equations and a stepbystep guide to measure
1
? and
2
? are detailed in Appendix D.
Denote
DUT
S as the Sparameters of the unknown twoport. The directions of the
waves in 558H558HFig. 3.2 are defined in a manner that simplifies the error adapter description in
Section 394H394H411H559H559H3.2. Thus, the directions of
1
a ,
1
b ,
2
a , and
2
b give
48
11
22
DUT
ab
S
? ???
=
? ???
? ???
. (3.5)
Since the real world measurement system is not perfect, there are random errors
and systematic errors contributing to the measurement of the unknown twoport
DUT
S ,
i.e.
M DUT
SS? . For example, 338H395H395H412H560H560HFig. 3.3 (a) shows the magnitude of the measured
,
11
M load
S
of an ideal resistive termination with
,
11
0
DUT load
S = .
,
11
M load
S has 0.01 peaktopeak
variations with respect to frequency. 339H396H396H413H561H561HFig. 3.3 (b) shows the measured
,
11
M short
S for an
ideal short with
,
11
1
DUT short
S =? .
,
11
M short
S has an obvious frequency dependence, and the
values are far away from one. These ideal devices are fabricated on Alumina substrate,
modeled based on physical parameters, and verified by National Institute of Standards
and Technology (NIST) [77] [78] [12]. So, the variations are not in the ideal load or
short. Instead, these errors are introduced by the measurement system. The random
errors, e.g. thermal drift, can only be described statistically, which cannot be
systematically corrected. The systematic errors are reproducible and can be corrected
using computational techniques. However full correction is impossible, due to
superimposed random fluctuations in the measured results [12]. The linear systematic
errors introduced by the imperfect reflectometer can be modeled by a fictitious twoport
error adapter between the reflectometer and the unknown oneport. This results in a
perfect reflectometer with no loss, no mismatch, and no frequency response errors.
49
0 5 10 15 20 25
0
0.05
0.1
0.15
0.2
frequency (GHz)
S
11M,
s
h
o
r
t

0 5 10 15 20 25
0
0.005
0.01
0.015
S
11M,
l
o
a
d

(a)
(b)
Fig. 3.3 The magnitude of the measured S
11
of an ideal (a) LOAD and (b) SHORT.
3.2 Error adaptor concept
In general, all of the linear errors of the imperfect reflectometers, including
directivity errors, frequency response errors, and port match errors, can be lumped into
an error adaptor. This fictitious error adaptor is a fourport network, containing 16 error
terms since fourport network is presented as a 4?4 matrix mathematically. 397H397H414H562H562HFig. 3.4
shows the twoport system with a fourport error adaptor inserted between the perfect
reflectometer and the unknown DUT. Port 0 and Port 3 are the two perfect measurement
ports inside the VNA, while Port 1 and Port 2 are the two terminals of the unknown
twoport.
k
a is the incident wave to the fourport error adaptor, while
k
b is the reflected
wave to the error adaptor. Without specification, the directions of the waves in error
models and calibration techniques are all defined in the same manner. The subscript is
50
the port number where the wave is monitored. k=0,1,2,3. Note that the two bias tees are
threeport components. The return losses and insertion losses of the bias tee are
included in the fourport error adapter, but the leakage errors to the DC power supply
are not. However, the leakages to the DC power supply do not affect the main signal
path, and it is safe to ignore these leakages without any loss in accuracy [68] [79].
Port 0 Port 1
Port 3 Port 2
3
b
3
a
0
a
0
b
DUT
0
Z
4port
Error
Adaptor
Perfect
Reflectometer
0
b
0
a
3
b
3
a
1
b
1
a
2
b
2
a
Forward
Reverse
Perfect
switch
Fig. 3.4 The fourport system error adaptor for twoport Sparameter measurement.
3.3 The simplest 8term error model
The 8term model simply doubles the 4term model for a oneport system at the
two ports [70] [80]. The signal flow graph for the whole error adapter and the DUT is
illustrated in 398H398H415H563H563HFig. 3.5. The two error adapters at the two ports are named as Xadapter
and Yadapter. The error terms are represented using Sparameters. Two additional
leakage terms are added to the 8trem model which turn it to a 10term model as shown
in 399H399H416H564H564HFig. 3.6 [67]. The first explicit solution for 8term model was introduced in 1971 by
Kruppa and Sodomsky. Three reflection standards, open, short, matched load, and one
through standard with the two ports connected together are used to calculate the error
terms in Sparameters [70]. The error terms can be either solved using Sparameters or
Tparameters, and modified approaches for different test structures are developed in [67]
51
[68] [69] [71] [72] [79] [81] [82]. The solution is not shown here as it is not used during
transistor characterization in this dissertation.
0
b
1
b
DUT
00
e
11
e
01
e
0
a
1
a
2
b
2
a
10
e
11
S
21
S
22
S
12
S
3
b
3
a
33
e
22
e
32
e
23
e
Port 0 Port 1
Port 3 Port 2
XAdaptor
YAdaptor
Fig. 3.5 Signal flow graph of 8term error model for a twoport system.
0
b
1
b
DUT
00
e
11
e
01
e
0
a
1
a
2
b
2
a
10
e
11
S
21
S
22
S
12
S
3
b
3
a
33
e
22
e
32
e
23
e
Port 0 Port 1 Port 2 Port 3
03
e
30
e
Fig. 3.6 The modified 10term error model with two leakage errors added.
3.4 The classical 12term error model
The classical 12term model handles the switch error problem by using two
separate error models for forward and reverse mode. This error model can be applied
for both fourreceiver VNA, and threereceiver VNA. The switch errors no longer need
52
to be removed using 565H565H(3.4). This error model is still widely used in error correction
techniques, e.g. shortopenloadthru (SOLT) calibration.
3.4.1 Forward mode
Under forward mode, the incident wave
0
a , the reflected wave
0
b , and the
transmitted wave
3
b can be measured by both threereceiver VNA and fourreceiver
VNA. 400H400H417H566H566HFig. 3.7 shows the block diagram of a twoport VNA configured for forward
measurement. 401H401H418H567H567HFig. 3.8 illustrates the possible signal paths using a signal flow graph for
forward mode operation, based on 8(10)term model.
30
e represents the leakage path
between the incident signal receiver,
0
a , and the transmission receiver,
3
b .
3
? lumps
the impact of nonideal switch or nonideal
0
Z termination. Using signal flow graph
analysis, the
3
a node can be removed, and the signal flow graph in 402H402H419H568H568HFig. 3.9 is
equivalent to the signal flow graph in 403H403H420H569H569HFig. 3.8, with
* 32 23 3
22 22
33 3
()
1
ee
ee
e
?
=+
? ?
,
* 32
32
33 3
()
1
e
e
e
=
? ?
,
3
3
3
a
b
?= . (3.6)
DUT
0
Z
RF
Source
Directional
Couplers
1
b
1
a
2
b
2
a
Forward
Port 1
Port 2
3
b
0
b
0
a
Fig. 3.7 A twoport Sparameter measurement system configured for forward mode.
53
0
b
1
b
DUT
00
e
11
e
01
e
0
a
1
a
2
b
2
a
10
e
30
e
22
e
11
S
21
S
22
S
12
S
3
b
32
e
33
e
23
e
3
a
3
?
Fig. 3.8 Forward mode signal flow graph for twoport system including nonideal Z
0
termination.
0
b
1
b
DUT
00
e
11
e
01
e
0
a
1
a
2
b
2
a
10
e
30
e
*
22
()e
11
S
21
S
22
S
12
S
3
b
*
32
()e
Fig. 3.9 Simplified forward mode signal flow graph.
3.4.2 Reverse mode
404H404H421H570H570HFig. 3.10 shows the block diagram for reverse configuration. Under reverse mode,
the incident wave
3
a , the reflected wave
3
b , and the transmitted wave
0
b are measured
by a threereceiver VNA or a fourreceiver VNA. 405H405H422H571H571HFig. 3.11 illustrates the signal flow
graph for reverse mode operation using Sparameters.
03
e represents the leakage path
between the incident signal receiver,
3
a , and the transmission receiver,
0
b .
0
? lumps
the impact of nonideal switch or nonideal
0
Z termination. Similarly, the
0
a node can
be removed using signal flow graph analysis, and the signal flow graph in 406H406H423H572H572HFig. 3.12 is
equivalent to the signal flow graph in 407H407H424H573H573HFig. 3.11, with
54
* 10 01 0
11 11
00 0
()
1
ee
ee
e
?
=+
? ?
,
* 01
01
00 0
()
1
e
e
e
=
? ?
,
0
0
0
a
b
?= (3.7)
DUT
0
Z
RF
Source
Directional
Couplers
1
b
1
a
2
b
2
a
Reverse
Port 1
Port 2
3
b
0
b
3
a
Fig. 3.10 A twoport Sparameter measurement system configured for reverse mode.
DUT
11
e
01
e
03
e
22
e
11
S
21
S
22
S
12
S
3
b
32
e
3
a0
b
1
b
1
a
2
b
2
a
33
e
23
e
0
a
0
?
00
e
10
e
Fig. 3.11 Reverse mode signal flow graph for twoport system including nonideal Z
0
termination.
DUT
*
11
()e
*
01
()e
03
e
22
e
11
S
21
S
22
S
12
S
3
b
32
e
3
a
0
b
1
b
1
a
2
b
2
a
33
e
23
e
Fig. 3.12 Simplified reverse mode signal flow graph for twoport system.
55
3.4.3 12term model
409H409H426H574H574HFig. 3.13 redraws the signal flow graph for forward mode in 408H408H425H575H575HFig. 3.9. Note that
32
e
and
22
e in 410H410H427H576H576HFig. 3.13 are not the same
32
e and
22
e that defined in 8term model, instead
they are the
*
32
()e and
*
22
()e calculated in 411H411H428H577H577H(3.6), which involve the impact of switch
errors since separate error adaptors are used for forward and reverse mode. This does
not affect the error calibration procedures at all. Based on signal flow graph analysis,
the measured wave ratios
11
S and
21
S are functions of the unknown
DUT
S as [80]
( )
( )10 01 11 22
11 00
11 11 22 22 11 22
1
DUT
DUT
DUT
S
DUT DUT
S
ee S e
Se
eS eS ee
??
=+
??+?
. (3.8)
( )( )
10 32 21
21 30
11 11 22 22 11 22
1
DUT
DUT
DUT DUT
S
ee S
Se
eS eS ee
=+
??+?
. (3.9)
where
11 22 21 12
DUT
DUT DUT DUT DUT
S
SS SS?= ? . The 6 (5 after normalization) error terms for
forward mode are directivity error
00
e , port match error
11
e and
22
e , frequency response
error
10 01
ee and
10 32
ee . The leakage errors
10
e ,
01
e , and
32
e cannot be completely
determined because they can only be measured as products as shown in 412H412H429H578H578H(3.8) and 413H413H430H579H579H(3.9).
Thus, only
10 01
ee and
10 32
ee can be solved, which is sufficient for calibration. This is
equivalent to normalizing the error terms by
10
e , as illustrated in 414H414H431H580H580HFig. 3.14 with the
normalized values on the branches. The 6 error terms for reverse mode are directivity
error
'
33
e , port match error
'
11
e and
'
22
e , frequency response error
''
23 01
ee and
''
23 32
ee .
56
0
b
1
b
DUT
00
e
11
e
01
e
0
a
1
a
2
b
2
a
10
e
30
e
22
e
11
S
21
S
22
S
12
S
3
b
32
e
Fig. 3.13 Forward mode signal flow graph for twoport system.
0
b
1
b
DUT
00
e
11
e
10 01
ee
0
a
1
a
2
b
2
a
1
30
e
22
e
11
S
21
S
22
S
12
S
3
b
10 32
ee
Fig. 3.14 Normalized 6term error model for forward mode.
Since the 6term model in 415H415H432H581H581HFig. 3.14 involves lumped error terms, these error terms
no longer represent signal paths, instead they are just mathematical coefficients. To
separate the error terms in forward mode and reverse mode, a superscript ?'? is used to
identify the waves and error terms in reverse mode. The normalized 6term model for
reverse mode is illustrated using the signal flow graph in 416H416H433H582H582HFig. 3.15. The measured wave
rations
22
S and
12
S are related to
DUT
S as [80]
( )
( )
'' '
23 32 22 11
'
22 33
'' '
11 11 22 22 11 22
1
DUT
DUT
DUT
S
DUT DUT
S
ee S e
Se
eS eS ee
??
=+
??+?
. (3.10)
( )( )
''
23 01 12
'
12 03
'' '
11 11 22 22 11 22
1
DUT
DUT
DUT DUT
S
ee S
Se
eS eS ee
=+
??+?
. (3.11)
57
DUT
'
11
e
''
23 01
ee
'
03
e
'
22
e
11
S
21
S
22
S
12
S
'
3
b
''
23 32
ee
'
3
a
'
0
b
'
1
b
'
1
a
'
2
b
'
2
a
'
33
e
1
Fig. 3.15 Normalized 6term error model for reverse mode.
417H417H434H583H583HFig. 3.14 and 418H418H435H584H584HFig. 3.15 give the complete 12term model. With 12 forward and
reverse measurements, 419H419H436H585H585H(3.8)420H420H437H586H586H(3.11) give 12 equations. The 12 unknowns can be
determined by solving the 12 equations simultaneously. Once the 12 error terms are
determined, the Sparameters of the unknown twoport can be calculated as [80] [83]
''
'
11 00 22 33 21 30 12 03
22 22'' ''
10 01 23 32 10 32 23 01
11
1
DUT
Se Se Se Se
ee
ee ee ee ee
S
D
??? ??????? ??
+?
??? ?????
??? ?????
= , (3.12)
()
'
'
21 30 22 33
22 22''
10 32 23 32
21
1
DUT
Se Se
ee
ee ee
S
D
??????
??
+?
??????
????
??
= , (3.13)
()
'
'
12 03 11 00
11 11''
23 01 10 01
12
1
DUT
Se Se
ee
ee ee
S
D
??????
??
+?
??????
????
??
= , (3.14)
'
22 33 11 00 21 30 12 03
11 11'' ''
23 32 10 01 10 32 23 01
22
1
DUT
Se Se Se Se
ee
ee ee ee ee
S
D
??? ??????? ??
+?
??? ?????
??? ?????
= , (3.15)
''
11 00 22 33 21 30 12 03
11 22 22 11'' ''
10 01 23 32 10 32 23 01
Se Se Se Se
De e
ee ee ee ee
????????????
=+ + ?
????????
????????
. (3.16)
58
Note that all four measured Sparameters are used to calculate any one Sparameter in
DUT
S , and each of the equations in 421H421H438H587H587H(3.12)422H422H439H588H588H(3.15) contains error terms calculated under
forward and reverse mode. Thus, both the forward 6term and the reverse 6term affect
the results of
DUT
S , since essentially the forward error terms and the reverse error terms
describe the same VNA system.
3.4.4 SOLT calibration
The classical 12term model has been widely used for over 10 years. One of its
wellestablished technique is the so called shortopenloadthrough (SOLT) calibration,
or thruopenshortmatch (TOSM) calibration, which is implemented on all modern
VNAs [34]. During SOLT calibration, 12 measurements on four standards are done to
solve the 12 error terms, 6 from forward mode, and 6 from reverse mode. The 6 forward
measurements are three forward reflection measurements on OPEN, SHORT, and
LOAD standards (
11
S ), one forward isolation measurement on twoport LOAD (
21
S ),
one forward match and one forward transmission measurements on twoport THRU
(
11
S and
21
S ). Similarly, the 6 reverse measurements are
22
S on OPEN, SHORT, and
LOAD,
12
S on twoport LOAD,
22
S and
12
S on twoport THRU. The accuracy of
SOLT calibration depends critically on the fabrication and modeling tolerance of the
standards. Additional procedures, such as improving the calibration standard models, or
the use of standards initially characterized with respect to the reference calibration, can
enhance the accuracy of the SOLT calibration [84] [85]. 423H423H440H589H589HFig. 3.16 shows the SHORT,
LOAD, THRU standards on a Cascade impedance standard substrate (ISS) 101190.
59
OPEN is defined as an open in air with a minimum distance of 250?m above the chuck
surface. LOAD is built using two thinfilm 100 ? resistors in parallel [86] [13] [78].
The four standards are characterized using physical measurements and verified by
National Institute of Standards and Technology (NIST) LRM/LRRM calibration [77]
[78] [12].
(a) OPEN
(probes in air)
(b) SHORT (c) LOAD (d) THRU
G
S
G
G
S
G
G
S
G
G
S
G
G
S
G
G
S
G
G
S
G
G
S
G
Fig. 3.16 (a) OPEN, (b) SHORT, (c) LOAD, and (d) THRU standards for SOLT
calibration on Cascade ISS 101190.
A significant assumption of SOLT calibration is that the calibration standards must
be well known. In practice, the internal routine of VNAs uses simple models defined by
several coefficients for each standard [83]. The coefficients of the four standards and
the RF probes must be well defined in the VNA calibration kit for SOLT calibration.
The accuracy of calibration significantly depends on the accuracy of these coefficients.
Appendix E provides a table of the calibration coefficients for Cascade RF infinity
probe with 100?m pitch size and Cascade ISS 101190 with 1 picosecond delay.
VNA8510C can store two CalKits in the system. The Calibration coefficients can be
loaded into VNA system from a floppy disk that came with calibration standards, or
manually entered into VNA following the steps in Appendix E. The 12 error terms
60
determined from SOLT calibration can be saved as a CalSet. Below are the headlines of
a CalSet file,
CITIFILE A.01.01
#NA VERSION HP8510C.07.16
NAME CAL_SET
#NA REGISTER 5
VAR FREQ MAG 93
DATA E[1] RI
DATA E[2] RI
DATA E[3] RI
DATA E[4] RI
DATA E[5] RI
DATA E[6] RI
DATA E[7] RI
DATA E[8] RI
DATA E[9] RI
DATA E[10] RI
DATA E[11] RI
DATA E[12] RI
#NA SWEEP_TIME 1.839999E1
#NA POWER1 2.5E1
#NA POWER2 2.5E1
#NA PARAMS 30
#NA CAL_TYPE 5
#NA DOMAIN_TYPE 0
#NA POWER_SLOPE 0.0E0
#NA POWER_SLOPE2 0.0E0
? ? ? ? ? ?
424H424H441H590H590HFig. 3.17 show
11
S and
21
S of a 0.13?m NMOS transistor for 2110 GHz. Raw data
is the measured Sparameters without any error calibration. Corrected data is the data
with system error calibrated using SOLT calibration. For parameter extraction and
device modeling, both real part and imaginary part of the Sparameters are important.
Error correction is necessary at all frequencies.
61
2
0
2
?
S
11
10
5
0
5
?
S
21
1
0
1
?
S
11
10
5
0
5
?
S
21
0 50 100
0
0.5
1
1.5
frequency (GHz)
S
11

0 50 100
0
5
10
frequency (GHz)
S
21

Raw Data
Corrected Data
N
f
= 30, W
f
= 5?m, L = 130nm, V
GS
= 0.6V, V
DS
= 1.5V
Fig. 3.17 Raw and corrected data for
11
S and
21
S of a 0.13?m NMOS transistor.
3.5 The most complete 16term error model
The most complete mathematic model for a fourport network is 16term model,
since fourport network is essentially a 4?4 matrix. 425H425H442H591H591HFig. 3.18 shows the signal flow
graph of the fourport error adaptor, containing 16 error terms. The reflection at each
port contributes four error terms including two directivity errors (
00
e and
33
e ) and two
port match errors (
11
e and
22
e ). The transmission from measurement ports to DUT
terminals introduces four frequency response error terms;
10
e ,
01
e ,
32
e and
23
e . The
coupling between the four ports adds eight leakage error terms marked with dash lines
in 426H426H443H592H592HFig. 3.18. When the couplings are negligible, it will be reduced to the 8term model
in Section 427H427H444H593H593H3.3.
62
0
b
1
b
DUT
00
e
11
e
01
e
0
a
1
a
2
b
2
a
10
e
11
S
21
S
22
S
12
S
3
b
3
a
33
e
22
e
32
e
23
e
20
e
13
e
31
e
02
e
30
e
12
e
03
e
21
e
Port 0 Port 1
Port 3 Port 2
Fig. 3.18 Signal flow graph of the 16term model for a twoport system.
The 16 error terms are actually the Sparameters of the fourport network, which
can be defined using the incident and reflected waves at each port as
00 03 01 02
30 33 31 3233
1110 13 11 12
2220 23 21 22
ee eeba
ee ee
ee ee
baee ee
???? ??
???? ??
?? ??
=
?? ??
???? ??
?? ??
?? ????
, (3.17)
For simplicity, the above expression is rewritten using 2?2 matrices as
13
24
MM
DUT DUT
bEEa
bEEa
? ?? ?? ?
=
? ?? ?? ?
? ?? ?? ?
. (3.18)
1
E ,
2
E ,
3
E , and
4
E are 2?2 matrices defined as
00 03
1
30 33
ee
E
ee
??
=
??
??
,
10 13
2
20 23
ee
E
ee
? ?
=
? ?
? ?
,
01 02
3
31 32
ee
E
ee
? ?
=
? ?
? ?
,
11 12
4
21 22
ee
E
ee
??
=
??
??
. (3.19)
The vectors
M
b ,
M
a ,
DUT
b and
DUT
a are 2?1 wave vectors defined at the perfect VNA
side (Port 0 and Port 3) and the DUT side (Port 1 and Port 2).
63
0
3
M
b
b
b
??
=
??
??
,
1
2
DUT
b
b
b
? ?
=
? ?
? ?
,
0
3
M
a
a
a
? ?
=
? ?
? ?
,
1
2
DUT
a
a
a
? ?
=
? ?
? ?
. (3.20)
Based on the directions of the waves in 428H428H445H594H594HFig. 3.18, the Sparameters measured by the
VNA,
M
S , and the Sparameters of the unknown DUT,
DUT
S , are defined as
00
33
M
ba
S
ba
?? ??
=
?? ??
?? ??
,
11
22
DUT
ab
S
? ???
=
? ???
? ???
, (3.21)
i.e.
M MM
bSa= and
DUT DUT DUT
aSb= . Thus,
M
S and
DUT
S can be related through a
nonlinear equation in terms of E as
()
1
1
13 4 2
M DUT
SEES EE
?
?
??
=+ ?
??
??
, (3.22)
or
()
1
1
2134
DUT M
SESEEE
?
?
? ?
=?+
? ?
? ?
. (3.23)
It can also be written as
()( ) [ ]
1111
3 124 24 12 2
22
0
DUT M DUT M
E EEE S S EE S EE SE
????
?
?+ +=. (3.24)
It is difficult to solve E from the nonlinear relationship in 595H595H(3.22) and 344H429H429H446H596H596H(3.23).
However, using transmission parameters (Tparameters),
M
S and
DUT
S can be related
through a linear relation in terms of error matrix [35]. In that case, error terms can be
solved using linear algebra algorithms [36]. 345H430H430H447H597H597H(3.18) can be rewritten using Tparameters
as
13
24
M DUT
M DUT
bTTa
aTTb
? ?? ?? ?
=
? ?? ?? ?
? ?? ?? ?
. (3.25)
where
64
15
1
26
tt
T
tt
??
=
??
??
,
37
2
48
tt
T
tt
? ?
=
? ?
? ?
,
913
3
10 14
tt
T
tt
? ?
=
? ?
? ?
,
11 15
4
12 16
tt
T
tt
? ?
=
? ?
? ?
. (3.26)
Recall that
M MM
bSa= and
DUT DUT DUT
aSb= , 346H431H431H448H598H598H(3.25) can be rewritten as [36]
[ ]
1234
22
0
DUT M DUT M
TS STS T ST
?
?+?=. (3.27)
This is equivalent to [35]
( )( )
1
1324
M DUT DUT
STS TTS T
?
=+ +, (3.28)
or
( ) ( )
1
12 43
DUT M M
S T ST ST T
?
=? ?. (3.29)
Comparing 432H432H449H599H599H(3.27) and 433H433H450H600H600H(3.24), the elements in E and T can be related through
1
13124
1
224
1
312
1
42
TEEEE
TEE
TEE
TE
?
?
?
?
=?
=?
=
=
and
1
134
1
24
1
31 342
1
442
ETT
ET
ETTTT
ETT
?
?
?
?
=
=
=?
=?
. (3.30)
Since the matrices in 347H434H434H451H601H601H(3.27) are 2?2 matrices, each twoport measurement will give
four linear equations in terms of T . Four calibration standard measurements seem to
give enough linear equations to solve the 16 elements in T , but in fact this is not true.
Only 14 parameters can be solved by making four measurements for two reasons [41].
First of all, the set of equations is homogeneous, and the maximum number of nonzero
unknowns can be solved is 15, because the only possible solution will be an all zero
solution if the coefficient matrix is full rank. Therefore, 15 error terms can be solved as
a function of the 16
th
no matter how many standards are measured. Secondly, because of
the singularity conditions, besides the freely chosen 16
th
parameter, one error term
65
remains unknown, and it can be solved using the fifth measurement. Numerical
examples in Appendix G show that the set of equations is illconditioned for any four
passive standards.
The previous 8term model and 12term model can also be represented using the
fourport network as they are actually describing the same set of systematic errors. The
8term model is just a special case of 16term model with negligible leakage terms.
Only directivity, port match, and frequency response terms are considered in 8term
model. The leakage terms
30
e and
03
e in 435H435H452H602H602HFig. 3.13 and 436H436H453H603H603HFig. 3.15, can be added to the
signal flow graph, which increases the number of error terms to 10, and can be
determined individually using LOAD standard. Thus the 4?4 error matrix for 8(10)
term model in defined as
00 01
33 3233
1110 11
03
2223 22
30
()
(
00
00
00
)
eeeba
e ee
ee
baee
???? ??
???? ??
?? ??
=
?? ??
?? ??
?? ??
?? ??
. (3.31)
The 12term error model in Section 437H437H454H604H604H3.4 is equivalent to two error matrices, one for
forward mode, one for reverse mode [87]. For forward mode,
3
a is not available, so the
matrix becomes
00 01 020 0
30 31 323
11 10 11 12
22 20 21 22
eeeb a
eeeb
ab eee
ab eee
???? ? ?
???? ? ?
?? ? ?
=
?? ? ?
???? ? ?
?? ? ?
? ?????
. (3.32)
For reverse mode, it is
66
''''
03 01 020
'''''
333 31 323
'' ' ''
11 13 11 12
'' ' ''
22 23 21 22
eeeb
aeeeb
ab eee
ab eee
????
? ?
????
? ?
?? ? ?
=
?? ? ?
????
? ?
?? ? ?
? ???
??
. (3.33)
There are 12 error terms in forward mode, and 12 error terms in reverse mode if all
leakages are considered. It is published in 1997 as a 22term model, because only 11 of
the 12 error terms can be solved for either forward or reverse mode [42]. Six standards
will be wanted to solve this 22term model [42]. As long as two separate error matrices
are used for forward and reverse mode, switch error is naturally removed as discussed
in Section 438H438H455H605H605H3.4.
3.6 Error adaptor for singlestep calibration
Not only systematic errors, but also onwafer parasitics can be described as a four
port network. Onwafer parasitics are the probing pads, and interconnect lines leading to
the device terminals, which actually connects the two ports at the two signal pads, Port
1 and Port 2, to the two ports at the gate and drain of the desired CMOS transistor. That
essentially defines a fourport network between the two probes and the two transistor
terminals. 439H439H456H606H606HFig. 1.9 (a) and (b) show the two fourport networks for systematic errors and
onwafer parasitics. The fourport relations derived in Section 440H440H457H607H607H3.5 do not make any
assumption about the properties of the fourport network. So, the same equations can be
applied on system error fourport or onwafer parasitics fourport. Since the two ports at
the probe tips are shared by the two fourport networks, it is possible to combine the
two fourport networks into one. 441H441H458H608H608HFig. 3.19 shows the combined fourport network. The
technique that solves the combined fourport network between the perfect VNA and the
67
transistor terminals using onwafer standards is called ?singlestep calibration?. The
error models and calibration techniques discussed above can be applied without
modification. However, singlestep calibration is not widely used in the past because of
traceability issue and less accurate onwafer standards compared with ISS standards [34]
[86].
Port 0
(VNA)
Port 1
(Probe)
Port 3
(VNA)
Port 2
(Probe)
4port
Error
Adaptor
0
b
0
a
3
b
3
a
1
b
1
a
2
b
2
a
Port 1*
(Gate)
Port 2*
(Drain)
[SA]
4port
onwafer
parasitics
*
1
b
*
1
a
*
2
b
*
2
a
Combined 4port for
system error & onwafer parasitics
M
S
DUT
S
A
S
Fig. 3.19 The combined fourport network including system errors and onwafer
parasitics.
For transistor characterization purpose, Sparameters are usually measured on a
large number of transistors, which may take hours or days. For twostep calibration, the
accuracy of ISS calibration need to be rechecked frequently as systematic errors may
drift during hourly measurements, e.g. temperature changes. This is time consuming
and requires a manual switch of the test wafer and the ISS substrate. This problem is
naturally solved with singlestep calibration. However, as mentioned in Section 609H609H1.3.4,
68
there are two problems need to be solved. The first is how to verify the accuracy of the
results. The second is how to model the nonideal parasitics of onwafer standards.
This dissertation uses twostep calibration results as a reference to evaluate the
accuracy of singlestep calibration. Since the verification only need to be done for
several reference test structures before large amount of measurements, it can still reduce
the time for measurement and help automation of large volume measurements. The non
ideal parasitics of onwafer standards is also examined in this dissertation. First of all,
OPEN, SHORT standards can be assumed to be ideal from the experimental results in
Section 610H610H4.2. The same assumption is applied in onwafer deembedding step for two
step calibration. Secondly, the length of onwafer THRU is much shorter than the
THRU on ISS substrate, because the dimension of the transistor is usually much less
than the distance between the two signal pads. Thirdly, onwafer resistor standard can
be modeled using a similar mathematical model as ISS calibration does. The parasitics
of onwafer resistor can be lumped as a parallel capacitance whose value is determined
from low frequency measurement. Since the parasitic capacitance will not drift a lot for
a fixed process, the value just need to be checked once for one process.
442H442H459H611H611HFig. 3.19 shows the two fourport error adapters for systematic errors, onwafer
parasitics, and the fourport network combining systematic errors and onwafer
parasitics. Note that the direction of the a and b waves at the probes are defined
differently for the fourport error adapter and the fourport onwafer parasitics, to keep
the rules that all a waves are incident waves entering the fourport, and all of the b
waves are the reflected waves leaving the fourport. For simplicity, the following S
parameters are defined.
69
1.
M
S is the measured Sparameter of the unknown twoport without
switch error.
2.
DUT
S is the measured Sparameter of the unknown twoport after ISS
calibration. The onwafer parasitics, probing pads and interconnects is
still involved in
DUT
S .
3.
A
S is the actual Sparameter of the unknown twoport without system
errors and onwafer parasitics, which means the Sparameter after two
step calibration or singlestep calibration.
M
S , and
A
S can be easily defined using waves with directions shown in 443H443H460H612H612HFig. 3.19 as
00
33
M
ba
S
ba
? ???
=
? ???
? ???
,
**
11
**
22
A
ab
S
ab
? ???
=
? ???
? ???
(3.34)
It is a little complicated to defining
DUT
S . When applied for systematic error calibration,
11
22
DUT
ab
S
? ???
=
? ???
? ???
, (3.35)
since
1
b ,
2
b are the incident waves to DUT, and
1
a ,
2
a are the reflected waves to DUT.
When applied for onwafer parasitics deembedding
11
22
DUT
ba
S
? ???
=
? ???
? ???
, (3.36)
because, now,
1
b ,
2
b leave DUT, and
1
a ,
2
a enter DUT. When applied for singlestep
calibration, it does not matter because
DUT
S do not show up in the calibration
procedures.
70
3.7 Summary
Error adaptor concept for twoport Sparameter measurement is introduced. The
error adaptor is a fictitious linear network that is inserted between the measurement
ports and the unknown twoport. For twoport measurement, the error adaptor is a four
port network, which is described using a 4?4 matrix or 16 error terms, since there are
four waves at the two measurements ports and four waves at the DUT terminals. The 16
term error model is the most complete error model for twoport Sparameter
measurement. 8term and 12term error model can be viewed as special cases of 16
term. The advantage of 12term model is that switch error is naturally removed because
the two error adapters for forward and reverse mode are completely separated. Thus,
12term model can be applied on threereceiver VNA and fourreceiver VNA. SOLT
calibration is based on the 12term error model, and implanted in all modern VNAs. For
high frequency applications, especially when the leakage errors are not negligible when
compared with other error terms, 16term error model is needed. The complete 16 error
model can be used to describe both system errors and onwafer parasitics since both of
them are fourport networks. Singlestep calibration combines the two fourport
networks into one, with two ports inside VNA and two ports at the transistor terminals.
When onwafer standards are available, systematic errors and onwafer parasitics can be
removed in a single step.
71
Chapter 4
GENERIC ANALYTICAL FOURPORT SOLUTION
As the operating frequency increases, the distributive nature of onwafer parasitics
becomes significant. The deembedding techniques based on lumped equivalent circuit
for probing pads and interconnections fail, including openshort, padopen?short, and
threestep in Appendix C. The distributive nature of onwafer parasitics is naturally
accounted for by describing the onwafer parasitics as a fourport network, i.e. a 4?4
matrix. The fourport network is located between the two external ports at the two probe
tips and the two internal ports at the twoport device terminals [20]. This fourport
parasitics network was shown to be solvable using five onwafer standards [20] [19].
These solutions, however, are complicated and involve taking square roots, and thus
choice of positive and negative signs. Furthermore, the solution in [20] does not give
insight into the relationship between openshort and fourport solutions, while the
solution in [19] cannot be applied for singlestep calibration. The solution developed
below retains the openshort relation of [17], is much simpler mathematically than both
[20] and [19], does not involve taking square root, and is applicable to both twostep
and singlestep calibration. All of these improvements are achieved without loss of
accuracy.
One of the standards used is an onwafer load resistor, which was assumed to be
ideal in [20] and [19], but always has parasitics in reality. The reciprocal and symmetric
CHAPTER
72
fourport solution in [17] showed that the parasitic capacitance associated with this load
resistor can affect the deembedding results for onwafer inductor measurements. In this
solution, we first determine the parasitic capacitance of the load resistor using low
frequency openshort deembedding, e.g. below 30 GHz, and then include its effect in
fourport deembedding procedures.
The relationship between openshort deembedding and fourport deembedding
derived in [17] is further examined using two matrices of the general fourport solution,
which reduce to identity matrices at low frequencies where openshort is valid. New
criteria for examining reciprocity and symmetry of the solved fourport network are
developed. Using a reciprocal and symmetric solution, fourport deembedding and pad
openshort deembedding were previously shown to be close for inductors, and pad
openshort was concluded to be superior to fourport due to better tolerance to parasitic
capacitance in [17]. We examine this issue for transistor measurements and show that
these conclusions cannot be generalized, at least to this experiment. Instead, padopen
short gives inaccurate results at high frequencies that are close to openshort.
This chapter details the derivation of an analytical fourport solution for onwafer
parasitics using Yparameters. With five onwafer standards, OPEN, SHORT, LEFT,
RIGHT, and THRU, the 16 error terms in Yformat can be determined. Experimental
results are presented and compared with deembedding methods using lumped
equivalent circuits on 0.13?m RF CMOS technology. An indicator to quantify the
validity of openshort deembedding is given.
73
4.1 Fourport network in Yparameters
444H444H461H613H613HFig. 4.1 illustrates the fourport description of onwafer parasitics using port
currents and voltages. Port 1 and port 2 are formed by the two probe tips, i.e. the two
GSG pads of the whole DUT. Port 1
*
and 2
*
are terminated at the two terminals of the
twoport device, e.g. the gate and drain of the examined NMOS transistor. We define
current and voltage vectors,
e
I ,
e
V ,
i
I , and
i
V as follows:
1
2
e
V
V
V
??
=
??
??
,
1
2
e
I
I
I
? ?
=
? ?
? ?
,
*
1
*
2
i
V
V
V
? ?
=
? ?
? ?
,
*
1
*
2
i
I
I
I
? ?
=
? ?
? ?
. (4.1)
Onwafer Parasitics
Onwafer Parasitics
1
V
+
?
1
I
*
1
I
*
2
I
2
V
+
?
2
I
*
1
V
+
?
*
2
V
+
?
[YA]
Fig. 4.1. Block diagram of the onwafer parasitics fourport network using IV
representation.
The subscript e means external, while the subscript i means internal. These voltage and
current vectors can be related through four 2?2 admittance matrices,
ee
Y ,
ei
Y ,
ie
Y , and
ii
Y as:
eeeeie
iieii
I YYV
I YYV
? ?? ???
=
? ?? ???
? ?? ???
. (4.2)
74
Denoting the twoport Yparameters of the whole DUT as
DUT
Y and the actual
twoport Yparameters of the intrinsic transistor as
A
Y , we have
DUT
ee
I YV= and
A
ii
I YV=? .
A
Y can then be related to
DUT
Y as [20]:
( )
1
DUT A
ee ei ii ie
YYYYYY
?
=? + , (4.3)
or
( )
1
A DUT
ii ie ee ei
YYYY YY
?
=? ? ? . (4.4)
The 16 unknowns in
ee
Y ,
ei
Y ,
ie
Y , and
ii
Y can be determined by measuring at least four
onwafer standards with known
A
Y since each measurement gives four equations.
Actually five onwafer standards are necessary when the standards are combinations of
open, short, matched load, in addition to a through line. Once
ee
Y ,
ei
Y ,
ie
Y , and
ii
Y are
known, the actual Yparameters
A
Y of any transistor, can be easily retrieved from the
measured
DUT
Y .
4.2 General fourport Solution
4.2.1 Relationship between openshort and fourport
Substituting the Yparameters of an ideal OPEN and an ideal SHORT into 364H445H445H462H614H614H(4.3), i.e.
[ ]
,
22
0
Aopen
Y
?
= and
()[]
1
,
22
0
A short
Y
?
?
= , the measured Yparameters of OPEN and
SHORT can be obtained as [20]:
( )
1
,DUT open
ee ei ii ie
YYYYY
?
=? , (4.5)
,DUT short
ee
YY= . (4.6)
75
Note that ideal OPEN and SHORT are used in all analytical deembedding methods to
achieve an analytical solution. The equivalent twoport networks of ideal OPEN and
SHORT standards are shown in 446H446H463H615H615HFig. 4.2 (b) and (c). The SHORT measurement directly
yields
ee
Y . However, solving
ei
Y ,
ie
Y and
ii
Y proves difficult, because of the nonlinear
relationship between
DUT
Y and
A
Y due to matrix inversion and multiplication.
(a) NMOS (c) SHORT(b) OPEN
(d) LEFT (f) THRU(e) RIGHT
L
C
L
G
R
G
R
C
T
Y
S
G
D
Fig. 4.2. The equivalent twoport network of the intrinsic NMOS transistor and the
five onwafer standards OPEN, SHORT, LEFT, RIGHT and THRU.
Recall that the openshort deembedded Yparameters
OS
Y is given by [14]:
()( )
1
11
,,,OS DUT DUT open DUT short DUT open
YYY Y Y
?
??
??
=? ? ?
??
??
. (4.7)
Substituting 366H447H447H464H616H616H(4.3), 367H448H448H465H617H617H(4.5) and 368H449H449H466H618H618H(4.6) into 450H450H467H619H619H(4.7) leads to a simple relationship between
OS
Y
and
A
Y [17]:
( ) ( )
11
OS A
ei ii ii ie
Y YYYYY
??
= . (4.8)
76
Derivation details can be find in Appendix F. Denoting
( )
1
ei ii
AYY
?
= and
( )
1
ii ie
B YY
?
= ,
372H451H451H468H620H620H(4.8) can be rewritten as
OS A
YAYB= , (4.9)
or
11AOS
YAYB
? ?
= . (4.10)
A and B are 2?2 matrices, which relate to the Yparameters of the fourport error
adaptor through
()
()
1
11 22 12 21 12 11 11 12
21 22 22 21 22 11 21 12
1
det
ei ii ei ii ei ii ei ii
ei ii
ei ii ei ii ei ii ei ii
ii
yy yy yy yy
AYY
yy yy yy yyY
? ? ???
==
? ?
? ?
, (4.11)
()
()
1
11 22 21 12 12 22 22 12
21 11 11 21 22 11 12 21
1
det
ie ii ie ii ie ii ie ii
ii ie
ie ii ie ii ie ii ie ii
ii
y yyyyyyy
BY Y
y yyy yyyyY
? ? ???
==
? ?
? ?
. (4.12)
ei
mn
y ,
ie
mn
y , and
ii
mn
y are (),mn elements of the 2?2 matrices
ei
Y ,
ie
Y , and
ii
Y , ,1,2mn= .
Expanding the matrices in 373H452H452H469H621H621H(4.9), the elements of openshort deembedded Yparameters
are
11 11 11 12 21 11 11 12 21 12 22 21 11 11 12 12 21 12 11 12 22 12 22 22
21 11 11 22 21 11 21 12 21 22 22 21 21 11 12 22 21 12 21 12 22 22 22 22
AAAA AAA A
OS
AAAAAAA A
aYb aYb aYb aYb aYb aYb aYb aYb
Y
aYb aYb aYb aYb aYb aYb aYb aYb
??+++ +++
=
??
+++ +++
??
. (4.13)
ij
a and
ij
b are ( ),ij elements of A and B, ,1,2ij= .
Instead of directly solving the 16 unknowns in
ee
Y ,
ei
Y ,
ie
Y , and
ii
Y , as was done in
[20], only the 8 elements in A and B need to be solved after performing openshort de
embedding [17]. Strictly speaking, only 15 of the 16 unknowns can be solved, due to
the ratio nature of Sparameter measurements, similar to the situation in 16term error
calibration [41] [80]. For the same reason, only 7 of the 8 unknowns in A and B can be
77
fully solved, which is sufficient for deembedding purpose [19]. Three additional on
wafer standards, LEFT, RIGHT, and THRU, are used in this dissertation to find out the
8 (7 solvable) unknowns left after openshort deembedding.
4.2.2 Openshort deembedded LEFT, RIGHT, and THRU
We now examine the three additional standards, LEFT, RIGHT, and THRU, as
illustrated in 453H453H470H622H622HFig. 4.2 (d)(f). The Yparameters for actual LEFT, RIGHT, and THRU
standards are modeled by:
,
0
00
Aleft L
Y
Y
??
=
??
??
,
,
00
0
Aright
R
Y
Y
? ?
=
? ?
? ?
,
,Athru TT
TT
YY
Y
YY
? ??
=
? ?
?
? ?
. (4.14)
Note that the onwafer load resistor in LEFT and RIGHT, which are assumed to be
purely resistive in [20] and [19], are represented as
L
Y and
R
Y to account for non
idealities of onwafer resistors. The primary nonideality is a parallel capacitance, as
shown by their openshort deembedded Yparameters at relatively low frequencies
where openshort is accurate. Thus
L
Y and
R
Y are modeled as
L LL
YGjC?=+ and
RR R
YGjC?=+ as shown in 454H454H471H623H623HFig. 4.2 (d) and (e). The admittance and parasitic
capacitance,
L
G ,
R
G ,
L
C , and
R
C , are extracted from openshort deembedded LEFT
and RIGHT below 30 GHz. If high precision low parasitics resistors are used, which are
increasingly available in RF SiGe BiCMOS and RF CMOS processes, one may
determine
L
G and
R
G from DC measurements and neglect
L
C and
R
C . The
T
Y in
,Athru
Y becomes infinity for an ideal through line with zero length. A small length
THRU is typically used in transistor measurement to allow signal propagation from
78
input to output. As a result, the s and t terms used to represent the nonideal THRU in
[19] are close, thus only a single
T
Y term is used here, which helps to considerably
simplify the general fourport solution and make the new solution applicable to single
step calibration.
T
Y does not need to be known as it will be cancelled out during de
embedding.
4.2.3 Analytical solution of A and B
The openshort deembedded Yparameters of LEFT and RIGHT,
,OS left
Y and
,OS right
Y , can be related to elements of A and B by substituting
,Aleft
Y and
,A right
Y in 376H455H455H472H624H624H(4.14)
into 377H456H456H473H625H625H(4.9). Both
,Aleft
Y and
,A right
Y have 3 zero elements, thus the final product of
A
AY B
only contains simple product of the elements in A and B. For convenience, we use M
and N defined below instead of
,OS left
Y and
,OS right
Y :
, 11 11 11 12
21 11 21 12
/
OS left
L
ab ab
MY Y
ab ab
? ?
==
? ?
? ?
, (4.15)
, 12 21 12 22
22 21 22 22
/
OS right
R
ab ab
NY Y
ab ab
? ?
==
? ?
? ?
, (4.16)
where
ij
a ,
ij
b ,
ij
M , and
ij
N are the
( ),ij
elements of A, B, M, and N, ,1,2ij= . Note
that M and N are known matrices for the following procedures.
At first glance, one may attempt to solve the 8 elements of A and B from the 8
equations provided by LEFT and RIGHT (4 each in 378H457H457H474H626H626H(4.15) and 379H458H458H475H627H627H(4.16)). This, however,
is not the case, as only three of the 4 equations provided by each measurement are
independent. For example, the ratios of
21 11
/M M and
22 12
/M M both give
21 11
/aa.
79
Thus, only three unknowns can be solved as a function of the fourth unknown for a
LEFT or a RIGHT measurement.
Using the relationship between the elements of M and N and the unknowns in A and
B, some of the unknowns can be solved first. To make the solution easier and clearer, A
and B are normalized to A? and B? using 'A kA= ,
1
'B kB
?
= by a constant k. As we still
have ''
OS A
YAYB= and
() ()
11
''
AOS
YAYB
? ?
= , we can replace A and B by A? and B?
respectively for deembedding purpose.
The normalization factor k is chosen based on multiple considerations. First, it must
not affect the accuracy of the deembedded results. Second, the errors remaining after
openshort can be easily examined from the elements of the normalized matrices. Third,
it will reduce to unity if the fourport network is reciprocal. A choice satisfying these
requirements is
11 11
/kba= :
12
11'
11 11 11 11
21 22
11 11
1
/
a
a
AkA baA ab
aa
aa
? ?
? ?
? ?
== =
? ?
? ?
? ?
and (4.17)
( )
1
'1 11 11 11 12
11 11 11 11
11 21 11 22
/
ab ab
BkB abB ab
ab ab
?
?
? ?
== =
? ?
? ?
. (4.18)
After normalization, there are only 7 elements that need to be solved in
'
A and
'
B .
We first solve as many terms of A? and B? as possible from M and N, using 380H459H459H476H628H628H(4.15) and
381H460H460H477H629H629H(4.16):
11 11 11
ab M= ,
11 12 12
ab M= , and
21 21
11 11
aM
aM
= , (4.19)
80
11
11 21 21
22
a
ab N
a
= ,
11
11 22 22
22
a
ab N
a
= , and
12 12 22
11 22 11
aNa
aNa
= . (4.20)
6 of the 7 elements are now solved as functions of the 7
th
,
22 11
/aa, which we define as
22 11
/aa? .
For a given set of measured data,
21 11
/aa can be calculated in two ways, either as
21 11
/M M or as
22 12
/M M from 382H461H461H478H630H630H(4.15). The analysis below will show that
21 11
/aa
calculated from
21 11
/M M gives better error tolerance. Assuming the actual LEFT is not
ideal, there will be small error term ? added to
,Aleft
Y as
,Aleft L
Y
Y
?
? ?
? ?
=
? ?
? ?
. (4.21)
The M matrix, which involves the measurement errors in the LEFT measurement and
the calculation errors during openshort deembedding, can be written as
, 11 11 11 12
21 11 21 12
/
OS left
L
ab ab
MY Y
ab ab
? ???
? ?
== +
??? ?
? ?
? ???
. (4.22)
? combines the nonideality factor ?, the measurement errors and the calculation errors.
The physical nature of the LEFT and RIGHT standards dictates that
11
M and
22
N are
the largest elements in M and N, and close to one, respectively, as confirmed by
measurements. Hence,
11 11
ab? , and
21 11
/M M can be calculated as
()
21 21 11 21 11 21
11 11 11 11 11 11 11 11
Mab ab a
O
Mab ababa
+? ?
=?+=+?
+?
. (4.23)
As
()O ? is a very small number,
21 11
/M M is relatively accurate even with nonideal
LEFT structure. However,
22 12
/M M is calculated as
81
22 21 12 21
12 11 12 11
M ab a
M ab a
+?
=?
+?
. (4.24)
Since
11 12
ab and
21 12
ab are close to zero from the physics nature of LEFT, and can be
comparable to ?,
22 12
/M M may give inaccurate
21 11
/aa. A similar situation exists for
12 11
/aa. Hence solutions with
11
M and
22
N as denominators should be used to obtain
better error tolerance.
462H462H479H631H631HFig. 4.3 plots the real part of deembedded
21
y as a function of frequency, from
which
m
g is extracted. The
m
g extracted from the results with
21 11 21 11
//aa MM= is
much smoother and more accurate then the one extracted from the results with
21 11 22 12
//aa M M= . The other unknowns are all determined based on the same principle
as shown in 384H463H463H480H632H632H(4.19) and 385H464H464H481H633H633H(4.20). A? and B? can be rewritten using 386H465H465H482H634H634H(4.19), 387H466H466H483H635H635H(4.20), and
22 11
/aa? as:
12
22
11
21
11
1
'
N
N
AM
M
M
?
?
? ?
? ?
? ?
=
? ?
? ?
? ?
,
11 12
21 22
11
1
'
MM
B
NN
M
? ?
? ?
? ?
=
? ?
? ?
? ?
. (4.25)
? is the only unknown left which relates the unknowns solved from the openshort de
embedded LEFT and RIGHT, and can be solved using the THRU standard.
82
0 20 40 60 80 100 120
0.06
0.07
0.08
0.09
0.1
0.11
0.12
frequency (GHz)
?
Y
21
4port deembedded result with
a
21
/a
11
=M
22
/M
12
noisy and less accurate result
4port deembedded result with
a
21
/a
11
=M
21
/M
11
Fig. 4.3. The real part of fourport deembedded
21
y using different
21 11
/aa choices.
The
21 11
/aa defined from
22 12
/M M is clearly nosier, and should not be used.
The openshort deembedded Yparameters of THRU,
,OS thru
Y , can be calculated by
substituting
,Athru
Y in 388H467H467H484H636H636H(4.14) into
,,OS thru A thru
YAYB= as:
( )( ) ( )( )
()()()()
11 12 11 21 11 12 12 22
,
21 22 11 21 21 22 12 22
OS thru
T
aabb aabb
YY
aabb aabb
??
++?++
??
=
?+ + + +
??
(4.26)
By taking ratios of the elements of
,OS thru
Y , the equations including ? can be constructed
as:
,,
21 22 21 22 21 11
,,
11 12 11 12 12 22
/
=
1/
OS thru OS thru
OS thru OS thru
yy aaMM
y ya NN
?
?
?
+ +
==?=?
++
, (4.27)
,,
12 22 12 22 12 22
,,
11 21 11 21 11 21
/
/
OS thru OS thru
OS thru OS thru
yy bbMN
yy bbMN
?
?
?
++
===? =? . (4.28)
83
Therefore we have four options to solve ?,
,,
21 11
/
OS thru OS thru
yy,
,,
22 12
/
OS thru OS thru
yy,
,,
12 11
/
OS thru OS thru
yy, and
,,
22 21
/
OS thru OS thru
yy. The deembedded transistor Yparameters are
practically the same for all four choices in our experiment. Below, ? is obtained from ?
as:
21 11
12 22
/
1/
M M
NN
?
?
?
+
=?
+
,
,
21
,
11
OS thru
OS thru
y
y
? = . (4.29)
This general fourport solution here is much simpler than that of [19].
4.2.4 Summary of general fourport deembedding
To summarize, for twostep fourport parasitics deembedding, the main procedures
are:
1. Perform VNA system error calibration using Impedance Standard Substrate
(ISS).
2. Measure Sparameters of onwafer standards and the desired transistor or any
twoport DUT. The Sparameters are transformed to Y and Zparameters using
equations in Appendix B [88].
3. Perform openshort deembedding on measured LEFT, RIGHT, THRU, and the
DUT to obtain
,OS left
Y ,
,OS right
Y ,
,OS thru
Y , and
,OS dut
Y .
4. Extract
L
G ,
R
G ,
L
C , and
R
C from
,
11
OS left
Y and
,
22
OS right
Y at low frequencies, e.g.
below 30 GHz.
5. Calculate M and N using 389H468H468H485H637H637H(4.15) and 390H469H469H486H638H638H(4.16).
6. Solve ? from openshort deembedded THRU,
,OS thru
Y , using 391H470H470H487H639H639H(4.29).
7. Find out the elements of A? and B? from M, N, and ? using 392H471H471H488H640H640H(4.25).
84
8. Calculate
,A dut
Y for the examined transistor using
( )()
11
,','A dut OS dut
YAYB
??
= .
4.2.5 Impact of nonideal load in LEFT and RIGHT
In [20] and [19], onwafer load resistor was assumed to be purely resistive.
However, openshort deembedded Yparameters of LEFT and RIGHT show that there
is parasitic capacitance in parallel with the resistance. The parasitic capacitance
L
C and
R
C can be extracted from openshort deembedded LEFT and RIGHT,
,
11
OS left
y and
,
22
OS right
y . The impact of these capacitances is examined by setting 0
LR
CC== during
deembedding procedures. 472H472H489H641H641HFig. 4.4 plots the general fourport deembedded Y
parameters with and without including
L
C and
R
C . The transistor Yparameters are
noticeably different, especially for the input admittance
,
11
Adut
y and the effective
transconductance
{ }
,
21
A dut
y? . This difference indicates that the extracted small signal
parameters can be affected, for example, the effective gate resistance extracted using
{ }
,
11
1/
A dut
in
RY=? and the effective gate capacitance extracted using
{ }
,
11
1/ 2 1/
A dut
in
CfY?
??
=? ?
??
[18].
85
0
0.1
0.2
?
(Y
11
)
0
0.1
0.2
?
(Y
11
)
0
0.05
0.1
?
(Y
21
)
0.1
0.05
0
?
(Y
21
)
0.02
0
?
(Y
12
)
0.04
0.02
0
?
(Y
12
)
0 50 100
0
0.05
?
(Y
22
)
frequency (GHz)
0 50 100
0
0.05
0.1
?
(Y
22
)
frequency (GHz)
openshort
4port with C
L
& C
R
4port without C
L
& C
R
Fig. 4.4. The fourport deembedded transistor Yparameters with and without
including parasitic capacitance in
L
Y and
R
Y . For comparison, openshort de
embedded results are also plotted. No reciprocal assumptions are made for
fourport parasitics deembedding.
473H473H490H642H642HFig. 4.5 compares
in
R and
in
C extracted from
11
Y in 474H474H491H643H643HFig. 4.4. The
in
R extracted
without
L
C and
R
C is 2? larger than the
in
R extracted with
L
C and
R
C . The general
fourport
in
R with
L
C and
R
C is close to the openshort
in
R but shows improved
frequency dependence. The closeness is expected as openshort is valid below 30 GHz.
The
in
C extracted from openshort gives a very strong and unphysical frequency
dependence, while the
in
C extracted from general fourport is almost frequency
independent, no matter
L
C and
R
C are included or not. In strong inversion, for an oxide
86
thickness of only a few nanometers, the effective gate capacitance is expected to be
approximately constant even at 100 GHz for a MOSFET of such short channel length.
0 20 40 60 80 100 120
0
2
4
6
8
R
in
(
?
)
0 20 40 60 80 100 120
100
200
300
400
frequency (GHz)
C
in
(f
F
)
C
in, 4port
=210fF
?
max
>200fF
C
in, OS
R
in, 4port with C
L
& C
R
=3?
R
in, OS
=3?
R
in, 4port without C
L
& C
R
=5?
Fig. 4.5. Effective gate resistance and capacitance extracted from fourport de
embedded results with and without parasitic capacitance included in LEFT
and RIGHT. Openshort deembedded results are also shown for comparison.
No reciprocal assumptions are made.
4.2.6 Quantifying errors of openshort
By examining the elements in A? and B?, the errors remaining after openshort can
be quantified, because
''OS A
YAYB= . Clearly, only when A? and B? are both identity
matrices, openshort will be the same as fourport, .i.e.
OS A
YY= . The deviation of A?
and B? from identity matrix is thus an indicator of the (in)validity of openshort. 475H475H492H644H644HFig. 4.6
plots the real and imaginary parts of the 8 elements in A? and B?. At low frequencies,
'
11
a ,
'
11
b ,
'
22
a , and
'
22
b are close to unity with zero imaginary part, and all of the other
87
elements are close to zero in both real and imaginary part. This indicates that A? and B?
are both identity matrices and openshort is valid within this frequency range. As
frequency goes above 50 GHz, the deviation of A? and B? from identity matrix becomes
noticeable and openshort loses its accuracy.
0.3
0.2
0.1
0
0.1
?
A
'
&
?
B
'
0.9
1
1.1
1.2
1.3
1.4
?
A
'
&
?
B
'
0 50 100
0.1
0.05
0
0.05
frequency (GHz)
?
A
'
&
?
B
'
0 50 100
0.04
0
0.04
0.08
frequency (GHz)
?
A
'
&
?
B
'
?(a
'
11
) & ?(b
'
11
)
?(a
'
22
) & ?(b
'
22
)
?(a
'
11
) & ?(b
'
11
)
?(a
'
22
) & ?(b
'
22
)
?(a
'
12
) & ?(b
'
21
)
?(a
'
21
) & ?(b
'
12
)
?(a
'
21
) & ?
'
(b
12
)
?(a
'
12
) & ?(b
'
21
)
Fig. 4.6. The elements of A? and B? versus frequency.
4.2.7 Reciprocity and symmetry of the fourport parasitics
It was observed in board measurement that nonidealities in the OPEN and SHORT
standards can lead to nonreciprocal parameters for passive structures [46]. Ideal OPEN
and SHORT, however, are necessary in all deembedding methods to achieve analytical
solution. It is therefore necessary to check if the solved fourport parasitics is still
reciprocal or not, and significant deviation from reciprocity would indicate significant
88
error in the analytical solution. Here we propose a simple criterion to examine
reciprocity. From 476H476H493H645H645HFig. 4.6, we notice that
''
11 11
ab= ,
''
22 22
ab= ,
''
12 21
ab= and
''
21 12
ab= , i.e.
()
''
T
AB= . Although
''
11 11
ab= is always true as a result of our choice of normalization,
the agreement of the other 3 (6) elements suggests that the solved fourport parasitics is
reciprocal and the onwafer OPEN and SHORT standards may indeed be viewed as
ideal. Accordingly, the deembedded Yparameters using reciprocal assumption are
almost identical to the general fourport results. However, both A? and B? are clearly not
symmetric matrices, which is a direct result of our asymmetric layout design
necessitated by our choice of the desired reference planes.
4.3 Reciprocal fourport solution and padopenshort
Reciprocal fourport network means
T
ee ee
YY= ,
T
ei ie
YY= , and
T
ii ii
YY= [20]. Thus,
we will have
T
AB= and
11 11
/1kba= = from 398H477H477H494H646H646H(4.11) and 399H478H478H495H647H647H(4.12). Therefore, the
number of unknowns can be reduced to 4. All of them can be directly solved from open
short deembedded LEFT and RIGHT as:
12 21
11
22
12 21
22
11
'
NN
M
N
AA
MM
N
M
? ?
? ?
? ?
==
? ?
? ?
? ?
? ?
, '
T
B BA==, (4.30)
because we have
11 11
ab= ,
22 22
ab= ,
12 21
ab= , and
21 12
ab= in 400H479H479H496H648H648H(4.15) and 401H480H480H497H649H649H(4.16) and
11 11
/1kba== in 402H481H481H498H650H650H(4.17) and 403H482H482H499H651H651H(4.18). The deembedded results using general fourport
solution and reciprocal fourport solution for onwafer parasitics are very close and can
89
be viewed as identical. Given that only one THRU structure is saved, we suggest that
the general fourport solution to be used, as consistency between reciprocity and ideal
OPEN and SHORT can be checked, and singlestep calibration can be made.
Note that with reciprocity, there are only 10 independent terms left in the original
4?4 matrix describing the fourport onwafer parasitics. On the other hand, the pad
openshort of [17] uses a 9element equivalent circuit. It was then suggested and
concluded in [17] with inductor data that padopenshort is better than fourport, as it
gives comparable results, but does not require using onwafer load resistors. We
reexamine this issue for active RF CMOS transistors in 483H483H500H652H652HFig. 4.7, where openshort, pad
openshort, and reciprocal fourport results are compared. The Yparameters of PAD is
estimated from layout using extraction tools, as was done in [17]. Above 50 GHz, open
short is much less accurate, as the lumped equivalent circuit with 6 elements fails.
Although padopenshort includes 9 elements in the lumped equivalent circuit, the
improvement over openshort is very limited. The reciprocal fourport with 10 error
terms does a much better job particularly above 50 GHz. The main reason for the
success of the 10 term reciprocal fourport method, we believe, is that it does not rely
on lumped equivalent circuit, and has little to do with the use of one more term than
padopenshort. One may use an equivalent circuit with more than 10 elements and still
obtain less accurate results, as lumped circuits fail at higher frequencies. Our results
strongly suggest that for higher frequency transistor measurements, fourport is
necessary and superior to padopenshort, despite the need for onwafer load resistors.
90
0
0.1
0.2
?
(Y
11
)
0
0.1
0.2
?
(Y
11
)
0
0.05
0.1
?
(Y
21
)
0.1
0.05
0
?
(Y
21
)
0.02
0
?
(Y
12
)
0.04
0.02
0
?
(Y
12
)
0 50 100
0
0.05
?
(Y
22
)
frequency (GHz)
0 50 100
0
0.05
0.1
?
(Y
22
)
frequency (GHz)
OpenShort
PadOpenShort
Reciprocal 4port solution
Fig. 4.7. Reciprocal fourport deembedded transistor Yparameters versus the results
using openshort and padopenshort deembedding.
4.4 Summary
A new general fourport solution for onwafer transistor measurements is
developed and its utility is demonstrated on a 0.13?m RF CMOS process. The impact
of nonideal onwafer load resistor is examined, and can be accounted for by including
the parallel parasitic capacitances. Through proper normalization, easy to use new
criteria are developed for quantifying the difference between openshort and fourport,
as well as for examining reciprocity and symmetry of the fourport parasitics. Despite
the assumption of ideal OPEN and SHORT, as was done in all deembedding methods
for achieving analytical solution, the solved fourport network for onwafer parasitics is
91
shown to be reciprocal. Comparison with padopenshort shows that for transistor
measurements, padopenshort does not provide significant improvement over open
short, and fourport is necessary despite the need to use onwafer load resistors.
92
Chapter 5
NUMERICAL FOURPORT SOLUTION
Onwafer transistor Sparameter measurement is fundamentally important in both
laboratory and production testing. The most complete system error model is the 16term
model [36], which accounts for all of the possible signal paths between the four waves
measured inside the VNA and the four waves at the two terminals of the DUT, as
illustrated in Section 484H484H501H653H653H3.5. The idea of describing everything between the probe tips and
the device terminals as a fourport network [17] [20], is essentially the same as the 16
term error adaptor concept in system error calibration, at least mathematically, as
illustrated in 485H485H502H654H654HFig. 5.1. Analytical equations for determining the 4?4 Yparameters of the
fourport network are developed in 486H486H503H655H655HChapter 4 and [19] [20], using five onwafer
standards. However, these analytical solutions can only be applied if the specified five
standards, OPEN, SHORT, LEFT, RIGHT, and THRU, are available. Once other
standards are used, new equations need to be derived. Also, due to its analytical nature,
the solutions cannot take advantage of the redundancy available from the measurements
of five onwafer standards, and does not provide information on the relevant importance
of the 16 terms of the parasitic fourport. Furthermore, analytical solutions do not
provide information on systematic measurement errors. These issues are ideally handled
with a singular value decomposition (SVD) based solution which solves the 4?4 S and
Tparameters of the parasitics fourport. Experimental results are demonstrated on a
CHAPTER
93
0.13?m RF CMOS process. Note that SVD was first used to solve for the Tparameters
of the 16 term error model in [36].
Onwafer Parasitics
Onwafer Parasitics
1
a
*
1
a
*
2
a
2
a
[SA]
1
b
2
b
*
1
b
*
2
b
Fig. 5.1 The fourport error adaptor for onwafer parasitics in wave representation.
5.1 Fourport parasitic network in Tparameters
487H487H504H656H656HFig. 5.1 illustrates the fourport error adaptor for onwafer parasitics. a and b are
the incident and reflected waves at each port. Port 1 and Port 2 are the two probe tips,
while Port 1
*
and Port 2
*
are the two device terminals. The linear equation relationship
in 488H488H505H657H657H(3.27) can also be applied for onwafer parasitics. Rewrite the equation as below
[ ]
1234
22
0
A DUT A DUT
TS STSTST
?
?+?=. (5.1)
15913
2 6 10 1413
3 7 11 1524
4 8 12 16
tttt
ttt tTT
T
ttt tTT
ttt t
? ?
? ?
??
? ?
==
??
? ?
??
? ?
? ?
? ?
. (5.2)
A
S is the Sparameter of the internal transistor itself, and
DUT
S is the Sparameter of the
transistor plus the probing pads and interconnects as defined in Section 658H658H3.6. Each
94
measurement on a known twoport standard gives a pair of known
A
S and
DUT
S and
four linear equations in terms of T as expanding 425H489H489H506H659H659H(5.1) gives
11 11 11 11 12 21 21 11 21 12 11 12
11 11 21 11 22 21 21 21 21 22 21 22
12 12 11 12 12 22 22 11 22 12
001000
0 0 01 00 0 0
A A DUT A DUT A A DUT A DUT DUT DUT
A A DUT A DUT A A DUT A DUT DUT DUT
A A DUT A DUT A A DUT A D
SSSSS S S SS
S SS SS S SS SS S S
S SS SS S SS SS
?? ?? ??
?? ?? ??
?? ??
1
2
3
4
11 12
13
12 12 21 12 22 22 22 21 22 22 21 22
14
15
16
0
0
000 0 0 10
000 1
UT DUT DUT
A A DUT A DUT A A DUT A DUT DUT DUT
t
t
t
t
SS
t
S SS SS S SS SS S S
t
t
t
??
??
??
??
??? ? ? ?
??? ? ? ?
??? ? ? ?
=
??? ? ? ?
??
??? ? ? ?
?? ?? ??? ?
? ???? ?
??
??
??
??
??
#
. (5.3)
A
mn
S and
DUT
mn
S are the elements of
A
S and
DUT
S , m , n =1,2.
k
t is the elements of T,
k=116. Written in matrix, the above four linear equations are
[ ]
416 161
41
0CT
??
?
= .
416
C
?
is
the coefficient matrix for each twoport measurement. For two twoport standards, 2?4
equations will be obtained, and the coefficient matrix will be
816
C
?
. For n twoport
standards, n?4 equations will be obtained, and the coefficient matrix will be
()416n
C
? ?
. In
principle, four twoport standards are sufficient to solve the 16 unknowns. However, in
practice, five onwafer standards are required, and only 15 unknowns can be fully
determined.
5.2 SVD based fourport Solution
Given the four linear equations in 660H660H(5.3), four onwafer measurements give 16 linear
equations which can be rewritten in matrix as
[ ]
16 16 16 1
16 1
0CT
??
?
= . It seems like that the
16 unknowns can all be fully determined using the 16 equations. However, the only
possible 16term solution is an all zero solution because the set of equations is
homogenous. In linear algebra, the rank of the coefficient matrix determines the number
95
of the unknowns can be solved. If
16 16
C
?
is full rank, the only possible solution is
[ ]
16 1
16 1
0T
?
?
= . Since it is impossible that the error terms are all zero, the rank of the
coefficient matrix is less than 16, that is to say that the maximum number of unknowns
can be determined is 15, no matter how many onwafer standards are measured.
The equations may be solved by normalizing the unknowns to one of the unknown
terms, preferable one whose magnitude is close to unity. In Appendix H, the
4
t term
was used as normalization factor for oneport error correction, essentially because the
frequency response
10 01
ee can only be solved as product. Since
1
42
TE
?
= and T
1
, T
3
, T
4
are functions of
1
2
E
?
in 427H491H491H508H661H661H(3.30), and the diagonal elements of E
2,
10
e and
23
e , are related
to frequency response, the diagonal elements of T
4
,
11
t and
16
t are good choices for
normalization.
16
t is used as the normalization factor in this dissertation. The
normalized T matrix is
''''
15 913
''' '''
' 2 6 10 1413
''' '''
3 7 11 1524
'''
4812
1
tttt
ttt tTT
T
ttt tTT
ttt
? ?
? ?
??
? ?
==
??
? ?
??
? ?
? ?
? ?
. (5.4)
'
16
/
kk
ttt= , k=115. After normalization, 662H662H(5.1) can be rewritten as
[ ]
''''
1234
22
0
A DUT A DUT
TS STSTST
?
?+?=. (5.5)
The four linear equations for each measurement is then rewritten as
96
11 11 11 11 12 21 21 11 21 12 11 12
11 11 21 11 22 21 21 21 21 22 21 22
12 12 11 12 12 22 22 11 22 12
0 0 10 00 0
0001
A A DUT A DUT A A DUT A DUT DUT DUT
A A DUT A DUT A A DUT A DUT DUT DUT
A A DUT A DUT A A DUT A DUT
S SS SS S SS SS S S
S SS SS S SS SS S S
SSSSSS S
?? ?? ??
?? ?? ??
?? ??
'
1
'
2
'
3
'
4
1211
'
13
2212 12 21 12 22 22 22 21 22 22 21
'
14
'
15
0
0
00 0 0 10
DUTDUT
DUTA A DUT A DUT A A DUT A DUT DUT
t
t
t
t
SS
t
SSSS SS SSS SS S
t
t
??
??
??
??
??? ? ??
??? ? ??
??? ? ??
=
??? ? ??
?
??? ? ??
?? ?? ?? ?
????? ?
??
??
??
??
??
#
. (5.6)
Denoting the 15 normalized unknowns as
'
15 1
T
?
,
[ ]
16 16 16 1
16 1
0CT
??
?
= can be rewritten as
'
16 15 15 1 15 1
A TB
?? ?
= , where
16 16 16 15 15 1
CAB
???
? ?=?
? ?
.
As discussed in Section 663H663H3.4, the
10
e and
23
e error terms cannot be measured
independently because of the ratio nature of Sparameters [35] [36] [41] [42]. Since T
parameters represent the same fourport network as the E matrix, the same singularities
exist in T and E matrices, although they are not that obvious in T matrix. By numerical
simulation it was shown in [39] that the equations are singular for any four standards.
The condition numbers of several sets of four standards are shown in Appendix G.
There must be additional assumptions of the fourport network if 15 unknowns are
solved using four standards [39] [41]. Five onwafer standards are strictly needed for a
general fourport solution. One of the standards should be a twoport standard or a
though connection, e.g. THRU in 664H664HFig. 2.6. There is no upper limit for the number of
standards. However, if the five standards chosen are nonsingular, adding more standards
will not greatly improve the deembedded results as shown in Appendix G.
Given pairs of
A
S and
DUT
S of five known standards, the elements of T can be
determined from twenty (5?4) linear equations using 665H665H(5.6). The set of linear equations
can be written as
'
20 15 15 1 20 1
AT B
?? ?
= . The set of equations
'
20 15 15 1 20 1
AT B
?? ?
= is over
97
determined, and can be solved using SVD. The solution is
'
15 1
T
?
=
?
20 15 20 1
AB
??
, where
?
20 15
A
?
is the pseudoinverse of
20 15
A
?
. The 15term solution
'
15 1
T
?
=
?
20 15 20 1
A B
??
is sufficient
for calculating actual
A
S from measured
DUT
S for any unknown DUT using an
alternative expression of 428H492H492H509H666H666H(5.1) as
( ) ( )
1
'' ''
12 43
A DUT DUT
S TST STT
?
=? ?. (5.7)
To make the comparison between analytical fourport solution and numerical four
port solution easier, the same NMOS transistor and OPEN, SHORT, LEFT, RIGHT and
THRU standards used for the analytical fourport solution in Section 490H490H507H667H667H4.2 are used here
as a demonstration. Backendofline resistors are used as onwafer load in LEFT and
RIGHT. Imperfect onwafer load resistors are still modeled as
L LL
YGjC?=+ and
RR R
YGjC?=+ as shown in 454H454H471H668H668HFig. 4.2 (d) and (e). The value of G
L
, C
L
, G
R
, and C
R
are
determined from lowfrequency openshort deembedding. According to analytical
fourport solution, neglecting the capacitance does not introduce significant errors in
most parameters.
The above process can be directly applied to solve for the combined fourport
network including both system errors and onwafer parasitics. The
DUT
S will be
replaced by the measured raw Sparameters, S
M
. The results will be show in Section 493H493H510H669H669H6.2.
5.3 Experimental results for onwafer parasitics deembedding
494H494H511H670H670HFig. 5.2 shows typical deembedding results on a 32 finger Ntype MOS transistor
at one typical bias,
GS
V =1.5V,
DS
V =1.5V. Each finger has a gate width of 5?m and a
length of 0.13?m. Sparameters are measured using a HP 8510XF system, from 2GHz
98
to 110GHz. ISS calibration using SOLT is first performed. The ISS calibrated S
parameters of the five onwafer standards shown in 495H495H512H671H671HFig. 2.6 are then used to determine
the fourport T matrix (15 independent terms). The transistor Sparameters
A
S are
obtained using 432H496H496H513H672H672H(5.7) and converted to Yparameters. The deembedded results using the
popular openshort [14], padopenshort [17], both of which are based on lumped
equivalent circuits, are compared with the analytical fourport solution in Section 497H497H514H673H673H4.2.
0 50 100
0
0.1
0.2
?
(Y
11
)
0 50 100
0
0.1
0.2
?
(Y
11
)
0 50 100
0
0.05
0.1
?
(Y
21
)
0 50 100
0.2
0.1
0
?
(Y
21
)
0 50 100
0.02
0.01
0
?
(Y
12
)
0 50 100
0.05
0.02
0
?
(Y
12
)
0 50 100
0
0.05
0.1
?
(Y
22
)
frequency (GHz)
0 50 100
0
0.05
0.1
?
(Y
22
)
frequency (GHz)
OpenShort
PadOpenShort
4port SVD solution
4port analytical solution
Fig. 5.2 Comparison of Yparameters between openshort, padopenshort, SVD
based numerical fourport solution, and analytical fourport solution.
The SVD results are practically identical to the analytical fourport results in
Section 498H498H515H674H674H4.2, which are carefully chosen among several possible solutions based on
99
singularity considerations. With SVD, singularity is naturally handled [36], and no
special measurements need to be taken. Redundancy is handled by SVD as well [81].
The SVD and analytical fourport results are significantly different from the open
short and padopenshort results. The frequency dependence of
11
Y from fourport
results is more physical. To observe this better, we plot out the effective gate resistance
in
R =
{ }
11
1/Y? and effective gate capacitance
in
C =
{ }
11
1/ 2 1/fY?
? ?
??
? ?
[27] in 499H499H516H675H675HFig. 5.3.
While openshort and padopenshort give the same
in
R as fourport solutions, they
give a very strong and unphysical frequency dependence of the effective gate
capacitance. In strong inversion, for an oxide thickness of only a few nanometers, the
value of the effective gate capacitance is expected to be approximately constant even at
100GHz for a MOSFET of such short channel length.
0 20 40 60 80 100
0
2
4
6
8
R
in
(
?
)
0 20 40 60 80 100
100
200
300
400
frequency (GHz)
C
in
(f
F
)
OpenShort
PadOpenShort
4port SVD solution
4port analytical solution
Fig. 5.3 Comparison of effective gate resistance and capacitance between openshort,
padopenshort, SVD based fourport solution, and analytical fourport
solution.
100
5.4 Reduction of Error Terms and Number of Standards
Using SVD, the relevant importance of different error terms can be examined
efficiently. For both the parasitics fourport and the combined fourport used in single
step calibration, only 12 terms of the full 16 terms are important as shown below. This
reduces the number of standards from 5 to 4. SHORT, LEFT, RIGHT, and THRU are a
good combination needed for the final T solution. One may then omit the OPEN
structure. The saving in chip area is not significant, and it does not allow the use of
openshort deembedding at lower frequencies for extraction of capacitive parasitics of
the left and right loads. Having openshort can be useful as this serves as the reference
from traditional onwafer deembedding and openshort is known to be accurate at
lower frequencies when used with ISS calibration. Comparison with openshort can
prove useful at the algorithm development stage as consistency of fourport with open
short at low frequencies indicates a correct fourport solution.
5.4.1 Quantify error terms for fourport onwafer parasitics
To quantify the impact of the 16 error terms, the SVD solved Tparameters are
transferred to Sparameters since Sparameters give straightforward physical meanings
of the signal paths. Because the solved T terms are normalized, the relationship between
the normalized T terms and the Sparameters of the fourport network need to be
developed first.
Using the relationship between the E and T elements in 676H676H(3.30), the E elements
calculated from the normalized T elements are
101
( )
()
()
()
1
'''
134 1
1
''
24 162
1
'''' '
3134 2 3
16
1
'''
4424
1
ETT E
ET tE
ETTT T E
t
ETTE
?
?
?
?
==
==
=? =
=? =
. (5.8)
'
1
E ,
'
2
E ,
'
3
E ,
'
4
E represent the fourport network after normalization. The Sparameters
of the fourport network without normalization is
00 03 01 02
''
1163
30 33 31 32
''
24
10 13 11 12
16
20 23 21 22
1
ee ee
EtE
ee ee
E
EE
ee ee
t
ee ee
? ?
? ???
? ???
==
? ?
? ???
??
? ?
? ?
. (5.9)
Although,
'
1
E ,
'
2
E ,
'
3
E , and
'
4
E are no longer the original Sparameters of the four
port network, it does not affect the relative importance of the error terms. 677H677HFig. 5.4 shows
the magnitude of the error terms in
'
1
E ,
'
2
E ,
'
3
E , and
'
4
E . The normalization factor,
16
t ,
does not affect the comparison between the diagonal elements and the nondiagonal
elements in each 2?2 matrix. In Section 678H678H3.3, the 8term model assumes that the leakage
terms, (
30
e ,
03
e ), (
31
e ,
02
e ), (
20
e ,
13
e ), and (
21
e ,
12
e ), are negligible. From 679H679HFig. 5.4, it is
clear that this assumption works well for the whole frequency range as the magnitude of
the nondiagonal elements of each 2?2 matrix is at least 20dB lower than the magnitude
of the diagonal elements. Note that although the magnitude of the diagonal elements of
E
2
and E
3
are much larger than the diagonal elements of E
1
and E
4
, it cannot be
concluded that the diagonal elements of E
2
and E
3
are dominant elements, because the
elements in E
2
and E
3
are normalized Sparameters.
102
0 50 100
60
40
20
0
frequency (GHz)
E2 (dB)
e
10
e
23
e
20
e
13
60
40
20
0
E3 (dB)
e
01
e
32
e
31
e
02
0 50 100
60
40
20
0
frequency (GHz)
E4 (dB)
e
11
e
22
e
21
e
12
60
40
20
0
E1 (dB)
e
00
e
33
e
30
e
03
Fig. 5.4 The magnitude of the Sparameters for the fourport onwafer parasitics.
5.4.2 8term solution using three onwafer standards
Since the nondiagonal elements of
'
1
E ,
'
2
E ,
'
3
E , and
'
4
E are much less than the
diagonal elements, it is possible that 8 error terms is sufficient for onwafer de
embedding. Note that here the 8 error terms are
00
e ,
11
e ,
10
e ,
01
e ,
22
e ,
33
e ,
23
e , and
32
e
as shown in Section 680H680H3.3. Because SVD solves the Tparameters of the fourport on
wafer parasitics, the 8term E matrix is transformed to T matrix using
103
()
'1
13124
16
'1
224
16
'1
312
16
'1
42
16
1
1
1
1
TEEE
t
TEE
t
TEE
t
TE
t
?
?
?
?
=?
=?
=
=
. (5.10)
If only 8 error terms, the diagonal elements of
1
E ,
2
E ,
3
E , and
4
E , are involved, the
nondiagonal elements of the corresponding
'
1
T ,
'
2
T ,
'
3
T , and
'
4
T matrices calculated
using 681H681H(5.10) are all zero.
00 01
33 32
10 11
23 22
00
00
00
ee
ee
E
ee
ee
??
??
=
??
??
?
''
19
''
614
'
' '
3 11
'
8
0 0
0 0
0 0
0 01
t t
t t
T
t t
t
? ?
? ?
? ?
=
? ?
? ?
? ?
? ?
(5.11)
The four linear equations for each measurement are
'
1
'
3
'
611 11 11 21 12 11
'
811 21 21 21 22 21
'
112 12 11 22 12
9
'
12 21 22 22 22
11
'
14
001 0
000
0000
1
A A DUT A DUT DUT
A DUT A A DUT DUT
A A DUT A DUT
A DUT A A DUT
t
t
tSSS SS S
tSS S SS S
SSSS SS
t
SS S SS
t
t
??
??
??
??
?????
??
??
??
=
??
??
??
??
??
??
??
??
??
2
22
DUT
DUT
S
??
??
??
??
??
??
. (5.12)
Three standards give 12 equations, which are sufficient to solve the 7 unknown
elements in 682H682H(5.12). However, the set of nonsingular standards need to be carefully
chosen. Some of onwafer standards may lead to unphysical results. For example, with a
104
perfect matched load at Port 1, the second equation in 683H683H(5.12) is
21 11
0
DUT
St= , which is
obviously not true in practice. The singularity of the standards can be verified using
condition number of the coefficient matrix. Considering the 5 available standards
fabricated, there are six possible combinations of three standards if THRU is chosen as
one standard. Among the six combinations, only three of them are nonsingular, i.e. 1)
SHORT, THRU, LEFT, 2) SHORT, THRU, RIGHT, and 3) THRU, LEFT, RIGHT. 684H684HFig.
5.5 shows the condition number of the coefficient matrix built using the six
combinations of three standards. The condition number for 5 standards is also shown as
reference. 685H685HFig. 5.6 compares the deembedded Yparameters using openshort, SVD
based 16term and 8term solution. The 5 standards used to solve the 16term solution
are OPEN, SHORT, THRU, LEFT, and RIGHT. The 3 standards used for 8term
solution are SHORT, THRU, and LEFT. With nonsingular standards, 8term model
can provide reasonably accurate results.
105
0 20 40 60 80 100 120
0
5
10
15
20
frequency (GHz)
Con
d
it
ion
Numbe
r
20
100
200
300
OPEN, SHORT, THRU
OPEN, THRU, LEFT
OPEN, THRU, RIGHT
SHORT, THRU, LEFT
SHORT, THRU, RIGHT
THRU, LEFT, RIGHT
16term,
5 standards
8 term model
with three standards
Fig. 5.5 Comparison of Yparameters between openshort, SVD based 16term
solution, and SVD based 8term solution.
0
0.1
0.2
?
(Y
11
)
0
0.1
0.2
?
(Y
11
)
0
0.05
0.1
?
(Y
21
)
0.2
0.1
0
?
(Y
21
)
0.02
0
0.02
?
(Y
12
)
0.05
0.02
0
?
(Y
12
)
0 50 100
0
0.05
0.1
?
(Y
22
)
frequency (GHz)
0 50 100
0
0.05
0.1
?
(Y
22
)
frequency (GHz)
openshort
16term, 5 stadnards
8term, 3 standards
Fig. 5.6 Comparison of Yparameters between openshort, SVD based 16term
solution, and SVD based 8term solution.
106
5.5 Summary
Onwafer parasitics deembedding using a SVD based numerical fourport solution
is demonstrated on a 0.13?m RF CMOS process. The SVD fourport results are shown
to be close to the analytical fourport results in Section 500H500H517H686H686H4.2. Redundancy and
singularities are naturally handled by SVD. The leakage errors are much smaller than
the directivity errors, frequency response errors, and port match errors. 8term error
model is sufficient for onwafer parasitics deembedding. Three standards are necessary
for solving the 8term error matrix. Nonsingular standards must be carefully designed.
The condition number of the coefficient matrix can be used as an indicator of the
singularity of the sets of standards and thus the validity of the deembedded results.
107
Chapter 6
SINGLESTEP CALIBRATION
As discussed in Section 687H687H3.6, both system errors and onwafer parasitics can be
described as a fourport network. A significant difference between the fourport system
error adaptor and the fourport onwafer parasitics network is that system errors drift
over time, and for this reason, ISS calibration must be performed at least once a day,
and validated often, e.g. before measurement of each wafer lot. This inevitably requires
an operator to load a special ISS holder on the wafer prober, making measurement time
consuming and impossible to automate in production testing. A solution to this problem
is to combine the fourport system error adaptor and the fourport onwafer parasitics
into one fourport network, and directly solve the combined fourport network without
ISS calibration using the same onwafer standards previously used for onwafer four
port parasitics deembedding. In practice, this singlestep approach is rarely used,
particularly for transistor measurements, for various reasons, the most important being
that onwafer standards are less accurately known compared to precision ISS calibration
standards. In this work, we will compare the results from the twostep approach, i.e. ISS
calibration plus fourport onwafer parasitics deembedding, and the results from the
singlestep approach to quantify the errors introduced in the much simpler and easier to
automate singlestep approach on a 0.13?m RF CMOS process. This is facilitated for
two fourport deembedding approaches, the analytical fourport solution in Section 502H502H519H688H688H4.2,
CHAPTER
108
and the numerical fourport solution in Section 503H503H520H689H689H5.2. We will show that the singlestep
approach can give as accurate transistor Yparameters as twostep calibration, from
2GHz to 110GHz. However, switch errors must be removed first, since switch errors are
not involved in the fourport network. Switch errors are introduced by nonideal
0
Z or
nonideal switch. The fourport error adaptor only lumps the linear errors between the
measured fourwaves, the four receivers, and the four desired waves.
6.1 Analytical fourport singlestep calibration
Although the combined fourport network is no longer reciprocal, the intrinsic
device parameters can still be retrieved from measured raw Sparameters using the
general fourport solution in Section 504H504H521H690H690H4.2 as is, without performing ISS calibration. For
best accuracy, the parasitic capacitance of the load resistor in LEFT and RIGHT can be
included in the same way as in the twostep fourport calibration described in Section
505H505H522H691H691H4.2. The parasitic capacitance needs to be determined from ISS calibrated LEFT and
RIGHT measurement. As the onwafer parasitics do not drift a lot as the VNA system
errors do, the capacitance only needs to be determined once. The value can then be used
for all measurements sharing the same load resistor. It does not need to be frequently
verified or recalibrated as VNA system error calibration does, which, in general, will
cost at least 30 minutes for one full twoport calibration. Moreover, poor calibration
associated with less accurate calibration standards can also degrade the overall accuracy
of the measured results. Singlestep calibration results, using the general fourport
solutions, can save a lot of time and effort during RF onwafer measurements.
109
To perform singlestep calibration, the measured raw Sparameters without ISS
calibration are directly used for all of the calculations from step 2) to step 8) in Section
506H506H523H692H692H4.2.4. As the onwafer standards are all assumed to be ideal, e.g. ideal OPEN and
SHORT, relatively ideal onwafer load resistor with a capacitive parasitics, the single
step calibration results are expected to be less accurate than the twostep calibration
results. 507H507H524H693H693HFig. 6.1 compares singlestep and twostep fourport calibration results for the
HP 8510XF system, from 2 GHz to 110 GHz. As expected, the Yparameters from
singlestep calibration are not as well behaved as the Yparameters from twostep
calibration. However, the overall values of Yparameters are still fairly accurate,
particularly for critical parameters like imaginary part of
11
Y , which indicates the gate
capacitance. To further analysis the source of the small ripples, the same measurements
are repeated using another system, a HP 8510C system, from 2 GHz to 26 GHz. The
results are shown in 508H508H525H694H694HFig. 6.2. The 8510C results are much less noisy than the 8510XF
result, even when compared over the same frequency range. Given the measurement
system dependence and the frequency dependence, these ripples in singlestep
calibration are believed to be due to the system errors that are not calibrated out by the
onwafer standards. Since the SVD based numerical fourport solution can give
information of the singularity of the solution, examining the condition number during
singlestep calibration using the SVD based solution in Section 695H695H6.2 may give some
information of the ripples.
110
0
0.02
0.05
?
(Y
11
)
0
0.05
0.1
?
(Y
11
)
0
0.05
0.1
?
(Y
21
)
0.1
0.05
0
?
(Y
21
)
0.02
0
?
(Y
12
)
0.04
0.02
0
?
(Y
12
)
0 50 100
0
0.02
0.05
?
(Y
22
)
frequency (GHz)
0 50 100
0
0.05
0.1
?
(Y
22
)
frequency (GHz)
Twostep 4port with SOLT calibration
Singlestep 4port calibration
(a)
Fig. 6.1. Singlestep versus twostep fourport using the analytical fourport solution
with data measured using a HP 8510XF system from 2 GHz to 110 GHz.
0
0.005
0.01
?
(Y
11
)
0
0.02
0.04
?
(Y
11
)
0
0.05
0.1
?
(Y
21
)
0.04
0.02
0
?
(Y
21
)
0.01
0
?
(Y
12
)
0.01
0.005
0
?
(Y
12
)
0 10 20 30
0
0.02
0.04
?
(Y
22
)
frequency (GHz)
0 10 20 30
0
0.02
0.04
?
(Y
22
)
frequency (GHz)
Twostep 4port with SOLT calibration
Singlestep 4port calibration
(b)
Fig. 6.2. Singlestep versus twostep fourport using the analytical fourport solution
with data measured using a HP 8510C system from 2 GHz to 26.5 GHz.
111
6.2 Numerical fourport singlestep calibration
The same fourport SVD algorithm in Section 509H509H526H696H696H5.2 is applied on the raw S
parameters without ISS calibration to remove the combined fourport network including
both system errors and onwafer parasitics.
DUT
S in 437H510H510H527H697H697H(5.1) and 438H511H511H528H698H698H(5.7) is replaced by
M
S .
Again, the onwafer standards are all assumed to be ideal, e.g. ideal open and short,
relatively ideal resistor loads with a capacitive parasitics.
512H512H529H699H699HFig. 6.3 compares the singlestep SVD fourport results with the twostep SVD
fourport results. Also shown are the openshort results with ISS calibration, the most
popular practice today. The padopenshort results are similar to openshort results, and
thus not repeated here. Similar to the singlestep calibration using analytical fourport
solution, the Yparameters from singlestep SVD fourport are noisier than the Y
parameters from twostep SVD fourport. To summarize, singlestep calibration using
fourport techniques has led to reasonably accurate transistor Yparameters, despite the
less accurate onwafer standards compared to precision ISS standards. The ability to
avoid ISS calibration makes this attractive for production testing, as ISS calibration
needs to be performed and checked often, and involves a separate manual step of
loading ISS holder.
112
0 50 100
0
0.1
0.2
?
(Y
11
)
0 50 100
0
0.1
0.2
?
(Y
11
)
0 50 100
0
0.05
0.1
?
(Y
21
)
0 50 100
0.2
0.1
0
?
(Y
21
)
0 50 100
0.02
0.01
0
?
(Y
12
)
0 50 100
0.05
0.02
0
?
(Y
12
)
0 50 100
0
0.05
0.1
?
(Y
22
)
frequency (GHz)
0 50 100
0
0.05
0.1
?
(Y
22
)
frequency (GHz)
ISS Calibration + OpenShort
ISS Calibration + 4port SVD
Singlestep 4port SVD
Fig. 6.3 Comparison between twostep openshort and fourport onwafer parasitics
deembedding results with ISS calibration and singlestep fourport
calibration results without any ISS calibration.
Another advantage of using singlestep calibration is that the distributive nature of
onwafer parasitics is naturally included, as evidenced by the closeness of the single
step results to the twostep results. Above 50GHz, the openshort results are much less
accurate, simply because the lumped equivalent circuit used for openshort de
embedding fails. Even though system errors are removed more accurately with ISS
standards when compared with singlestep calibration, the failure of openshort on
wafer deembedding makes the final result invalid.
The added advantage of using SVD is that it not only solves the system equations,
but also gives valuable information about the system [36] [89]. The condition number of
113
the coefficient matrix is an indicator of the error sensitivity. For the same inaccurate on
wafer standards, the condition number is noticeably higher for singlestep fourport
calibration, as shown in 513H513H530H700H700HFig. 6.4, indicating less tolerance to measurement errors. This is
another reason for the less accurate singlestep result compared to the twostep result
with ISS calibration.
0 20 40 60 80 100
5
10
15
20
25
30
Frequency (GHz)
C
o
n
d
i
t
i
o
n nu
m
b
e
r
Without ISS calibration
With ISS calibration
Fig. 6.4 Condition numbers of the coefficient matrix in onwafer parasitics de
embedding and singlestep calibration.
6.3 Impact of switch errors
One possible reason for the ripples is the switch errors. To investigate this, the
switch errors are removed using the algorithm in Section 514H514H531H701H701H3.1 [80]. 515H515H532H702H702HFig. 6.5 and 516H516H533H703H703HFig. 6.6
compare the singlestep calibrated results with and without switch error removal for the
two fourport solutions. The twostep fourport calibrated results are also shown for
comparison. 517H517H534H704H704HFig. 6.5 compares results using analytical fourport, while 518H518H535H705H705HFig. 6.6
compares results using SVD based numerical fourport. Both of them indicate that
switch errors are the most important reason for the ripples in singlestep calibration.
114
Switch error terms
1
? and
2
? are determined by the load impedance connected to the
switch inside the VNA system, which does not change a lot even for months. Adding
switch error removal will not cost a lot of labor for large volume measurements.
0
0.02
0.04
?
(Y
11
)
0
0.05
0.1
?
(Y
11
)
0
0.05
0.1
?
(Y
21
)
0.1
0.05
0
?
(Y
21
)
0.02
0.01
0
?
(Y
12
)
0.04
0.02
0
?
(Y
12
)
0 50 100
0
0.02
0.04
?
(Y
22
)
frequency (GHz)
0 50 100
0
0.05
0.1
?
(Y
22
)
frequency (GHz)
ISS Calibration + analytical 4port
Singlestep analytical 4port with switch error
Singlestep analytical 4port without switch error
Fig. 6.5 Comparison of the singlestep fourport calibrated results with and without
switching error correction. The analytical fourport solution in Section 421H519H519H536H706H706H4.2 is
applied.
115
0
0.02
0.04
?
(Y
11
)
0
0.05
0.1
?
(Y
11
)
0
0.05
0.1
?
(Y
21
)
0.1
0.05
0
?
(Y
21
)
0.02
0.01
0
?
(Y
12
)
0.04
0.02
0
?
(Y
12
)
0 50 100
0
0.02
0.04
?
(Y
22
)
frequency (GHz)
0 50 100
0
0.05
0.1
?
(Y
22
)
frequency (GHz)
ISS Calibration + SVD 4port
Singlestep SVD 4port with switch error
Singlestep SVD 4port without switch error
Fig. 6.6 Comparison of the singlestep fourport calibrated results with and without
switching error correction. The SVD based numerical fourport solution in
Section 422H520H520H537H707H707H5.2 is applied.
6.3.1 Quantify error terms using Sparameters
As discussed in Section 708H708H5.4, although,
'
1
E ,
'
2
E ,
'
3
E , and
'
4
E are no longer the
original Sparameters of the fourport network, it does not affect the relative importance
of the error terms. 709H709HFig. 6.7 shows the magnitude of the error terms in
'
1
E ,
'
2
E ,
'
3
E , and
'
4
E . The normalization factor,
16
t , does not affect the comparison between the diagonal
elements and the nondiagonal elements in each 2?2 matrix. From 710H710HFig. 6.7, it is clear
that this assumption limits the application of 8term model on singlestep calibration.
First, (
30
e ,
03
e ) are not that small when compared with (
00
e ,
33
e ) even at low frequencies.
116
Similar situation exist when evaluating the elements in E
4
. Secondly, as frequency
increases, the difference between the diagonal elements and the nondiagonal elements
in E
2
and E
3
reduces, which means the leakage errors become comparable to the
dominant errors. Note that although the magnitude of the diagonal elements of E
2
and
E
3
are 10dB larger than the diagonal elements of E
1
and E
4
, it cannot be concluded that
the diagonal elements of E
2
and E
3
are dominant elements, because the elements in E
2
and E
3
are normalized Sparameters.
0 50 100
60
40
20
0
E2 (dB)
frequency (GHz)
60
40
20
0
E3 (dB)
0 50 100
60
40
20
0
frequency (GHz)
E4 (dB)
60
40
20
0
E1 (dB)
e
10
e
23
e
20
e
13
e
01
e
32
e
31
e
02
e
11
e
22
e
21
e
12
e
00
e
33
e
30
e
03
Fig. 6.7 The magnitude of the solved 16 error terms of the combined fourport
network.
117
6.4 Summary
The accuracy of singlestep calibration using two general fourport solutions is
experimentally investigated on a 0.13?m RF CMOS process. In contrast to popular
belief, singlestep fourport calibration produces reasonably accurate and acceptable
transistor Yparameters from 2GHz to 110GHz, despite the less accurate onwafer
standards compared to precision ISS standards, which facilitates production testing and
process monitoring. The distributive nature of onwafer parasitics is also naturally
included, due to the fourport description of the combined error adaptor. The singlestep
approach to transistor measurements is thus valuable as it does not require ISS
calibration and thus facilitates production testing. The impact of switch errors on single
step measurement is also investigated. After removing switch error, singlestep
calibration provides practically the same results as twostep calibration for both the
analytical fourport solution which was first developed for onwafer parasitics and the
numerical fourport solution based on SVD.
118
Chapter 7
VALIDITY OF BSIM4 MODEL FOR NONLINEAR RF MODELING
Once the model parameters are extracted from a set of DC, CV, and Sparameter
measurements, it is important to verify the developed model by performing model
validation experiments. The idea is to provide an environment as close as possible to the
real measurement, and to verify whether the model can predict the measured results.
Only after the model passes the validation test, the model can be transferred to
designers. Note that the measurements used for model parameter extraction can be quite
different from the measurements used for model validation. For example, distortion
measurement with high input power is not used for parameter extraction, but it is
necessary for verifying the linear model developed as distortion exists in real
applications. In this chapter, the DC, AC, and nonlinear performance of a BSIM4 model
is verified.
BSIM4 model is one of the widely used MOS transistor model for RF designs. In
BSIM4, the moderate inversion region is modeled by mathematical smoothing functions
interpolating between physics based approximations in the weak and strong inversion
regions, instead of physics based surface potential approximation that can cover all
levels of inversion. Its accuracy in linearity simulation, particularly in moderate
inversion region, needs to be experimentally evaluated, since an IP3 sweet spot exists in
this region.
CHAPTER
119
7.1 Linearity measurement and simulation
The twotone onwafer system in 579H579H538H711H711HFig. 1.6 is used to measure the output spectrum at
the drain of the examined NMOS transistor [22]. 712H712HFig. 7.1 shows the simplified block
diagram for this 50? system. The gate and the drain of the NMOS transistor in linearity
simulation are also terminated at 50? ports. 713H713HFig. 7.2 shows the schematic for twotone
intermodulation distortion simulation. A ?psin? component from the ?analoglib? of
Cadence generates the twotone excitation at the gate. Since linearity measurement is
made at the probe tips, and it is impossible to calibrate onwafer parasitics, a passive
RLC network, which models the low frequency onwafer parasitics, is inserted between
bias tees and device terminals to make the environment as close as possible to real
measurement. An array of transistors with number of fingers (
f
N ) ranging from 5 to 64
are measured and simulated with sweeping biasing voltages at different fundamental
frequencies. Although QPSS analysis is selected to speed the linearity simulation, it
may still take days even with a high performance computer.
10
,
in
P ff=
20
,
in
P ff f=+?
Fig. 7.1 Block diagram for twotone intermodulation linearity measurement.
120
Fig. 7.2 Schematic for twotone intermodulation linearity simulation in Cadence.
Each finger of the NMOS transistor is 2?m wide and 90nm long. For
f
N = 64, the
total width is 128?m, which is close to those found in 5GHz low power 90nm CMOS
LNAs [49] . Therefore, the analysis will be focused on this device size. In practice,
because of low gain and low levels of intermodulation products in small width
transistors as well as dynamic range limits of the spectrum analyzer, the minimum gate
width that IP3 can be measured reliably is 10?2?m for this 90nm CMOS technology.
IIP3, OIP3, and power gain are measured at different V
GS
, V
DS
, and fundamental
frequencies to examine the biasing and frequency dependence of IP3 sweet spot. For
each measurement, the power amplitude at the signal generators, P
in
, is swept, and the
121
output power level for the 1
st
order output and the 3
rd
order intermodulation product are
monitored, P
out,1st
and P
out,3rd
. After power calibration, the third order intercept point is
obtained using linear extrapolation illustrated in Section 580H580H539H714H714H1.2. P
in,ref
=25dBm.
7.2 DC and linear characteristics
581H581H540H715H715HFig. 7.3 shows
DS
I 
GS
V curves for
DS
V = 0.6, 0.8 and 1.0V and 582H582H541H716H716HFig. 7.4 shows
DS
I 
DS
V curves for
GS
V =0.4 and 0.8V. 542H717H717HFig. 7.5 (a) shows S
21
versus frequency at one fixed
biasing point,
GS
V = 0.4V and
DS
V =1.0V, while 543H718H718HFig. 7.5 (b) shows S
21
versus gate
biasing voltage at a fixed frequency, 5GHz. 544H719H719HFig. 7.6 compares the cutoff frequency, f
T
,
extracted from Sparameters versus gate voltage. 545H720H720HFig. 7.7 shows all Yparameters versus
frequency at
GS
V =0.4V and
DS
V =1.0V, a representative moderate inversion bias. 584H584H546H721H721HFig.
7.8 shows all Yparameters at 5 GHz versus
GS
V for
DS
V =1.0V. Both simulation and
measurement data are shown in 547H722H722HFig. 7.3548H723H723HFig. 7.8. The Yparameters here include pad
parasitics by design, as IP3 is measured onwafer including probing pads. Overall, the
BSIM4 based subcircuit model does a good job in modeling
DS
I 
GS
V ,
DS
I 
DS
V , S
parameters, f
T
, and both frequency and bias dependence of most Yparameters over the
whole
GS
V region, including the moderate inversion region.
122
0.2 0.4 0.6 0.8 1
0
30
60
90
V
GS
(V)
I
DS
(mA)
10
1
10
0
10
1
10
2
Symbol: Measurement
Line: Simulation
N
f
= 64, W
f
= 2um, L = 90nm
V
DS
increase
V
DS
=0.6, 0.8, 1.0V
log scale
linear scale
Fig. 7.3 Measured and simulated
DS
I 
GS
V for
DS
V =0.6, 0.8, and 1.0V.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
10
20
30
40
50
60
V
DS
(V)
I
DS
(mA)
Symbol: Measurement
Line: Simulation
N
f
= 64, W
f
= 2um, L = 90nm
V
GS
= 0.4V
V
GS
= 0.8V
Fig. 7.4 Measured and simulated
DS
I 
DS
V for
GS
V =0.4V and 0.8V.
123
5 10 15 20 25 30 35 40
0
5
10
15
20
frequency (GHz)
S
21
(dB)
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
5
0
5
10
15
20
V
GS
(V)
S
21
(dB)
measurement
simulation
N
f
= 64, W
f
= 2um, L = 90nm
V
GS
= 0.4V, V
DS
= 1.0V
f0 = 5GHz, V
DS
= 1.0V
(a)
(b)
Fig. 7.5 (a) S
21
in dB versus frequency at
GS
V = 0.4V and
DS
V =1.0V. (b) S
21
in dB
versus
GS
V at 5GHz and
DS
V =1.0V.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
50
100
150
V
GS
(V)
f
T
(GHz)
V
DS
= 0.6V
V
DS
= 0.8V
V
DS
= 1.0V
Line: simulation
Symbol: measurement
N
f
= 64, W
f
= 2um, L = 90nm
Fig. 7.6 f
T
extracted from measured and simulated Sparameters.
124
0.02
0
0.02
?
(Y
11
)
0
0.05
0.1
?
(Y
11
)
0
0.05
0.1
?
(Y
21
)
0.04
0.02
0
?
(Y
21
)
5
0
5
x 10
3
?
(Y
12
)
0.02
0.01
0
?
(Y
12
)
0 10 20 30 40
0
0.01
0.02
?
(Y
22
)
frequency (GHz)
0 10 20 30 40
0
0.05
?
(Y
22
)
frequency (GHz)
Simulation
Measurement
V
GS
= 0.4V, V
DS
= 1.0V
N
f
= 64, W
f
= 2um, L = 90nm
Fig. 7.7 Yparameters versus frequency at
GS
V = 0.4V and
DS
V =1.0V. ? and ? stand
for real and imaginary parts.
125
0
0.5
1
x 10
3
?
(Y
11
)
0
0.005
0.01
?
(Y
11
)
0
0.1
0.2
?
(Y
21
)
0.01
0.005
0
?
(Y
21
)
2
1
0
x 10
5
?
(Y
12
)
2
1
0
x 10
3
?
(Y
12
)
0 0.5 1
0
0.05
?
(Y
22
)
V
GS
(V)
0 0.5 1
0
0.005
0.01
?
(Y
22
)
V
GS
(V)
Simulation
Measurement
f0 = 5GHz, V
DS
= 1.0V
N
f
= 64, W
f
= 2um, L = 90nm
Fig. 7.8 Yparameters at 5GHz versus
GS
V .
DS
V =1.0V. ? and ? stand for real and
imaginary parts.
7.3 Nonlinear characteristics
In real applications, the nonlinearities of the transistors and other components can
introduce undesired harmonic products to the output signal. Since the amplitudes of
harmonics and intermodulation products are higher order functions of the amplitude of
the input signal, and the amplitude of the fundamental signal is a linear function of the
input power level, the amplitudes of the harmonics and intermodulation products
increase in a much faster way than the fundamental signal amplitudes as input power
increases. 549H724H724HFig. 7.9 compares the amplitudes of the measured and simulated output
signals at the fundamental frequency. The transistor is biased in moderate inversion
126
region with
GS
V =0.4V,
DS
V =0.8V. At low input power, the higher order products are
much less than the fundamental signal, so the power gain from measurement and
simulation are both approximately constant. As P
in
increases, power gain starts to drop
because of the amplitude of the harmonics and intermodulation products added to the
desired signal are negative. The gain drop in the simulated result is clearly observed in
550H725H725HFig. 7.9. Because of the limitation of the maximum power level that can be generated
by the signal generators, the P
in
in measurement is not high enough to show this gain
drop obviously. The 1dB compression point, where power gain drops by 1dB, can be
determined as illustrated in 551H726H726HFig. 7.9.
40 35 30 25 20 15 10 5 0
30
25
20
15
10
5
0
5
10
Pin (dBm)
Pout (dBm)
13.211.4
6
4
2
0
2
Line: simulation
Power gain = 14.2dB
1dB compression point = 13.2dBm
Symbol: measurement
Power gain = 12.5dB
Estimated 1dB point = 11.4dBm
ideal 1:1 slope
N
f
= 64, W
f
= 2um, L = 90nm, V
GS
= 0.4V, V
DS
= 0.8V
1dB
Fig. 7.9 The amplitude of the fundamental output signal versus input power level at
GS
V =0.4V,
DS
V =0.8V.
127
552H727H727HFig. 7.10 shows the power level for the fundamental signal and the third order
intermodulation product versus drain current density for multiple drain biasing voltages.
Due to the limitation of the maximum power level can be generated in experiments, the
results are for P
in
=28dBm, which means the transistor is operated in linear mode. Only
when P
in
is larger than 10dBm, the transistor is driven into nonlinear mode. However,
as shown in 553H728H728HFig. 7.9, it is hard to realize in experiments. Therefore, the nonlinear RF
modeling performance is not directly evaluated by comparing the output power level.
Instead, IP3 is extracted from low P
in
measurement and used as an indicator for the
linearity of the transistor.
10
2
10
1
10
0
25
20
15
10
P
out
,1
s
t
(dBm)
10
2
10
1
10
0
90
80
70
60
J
DS
(mA/um)
P
out
,
3
r
d
(dBm)
V
DS
= 0.6V
V
DS
= 0.8V
V
DS
= 1.0V
Line: simulation
Symbol: measurement
Pin = 28dBm
N
f
= 64, W
f
= 2um, L = 90nm, f0 = 5GHz, ?f = 100KHz
Fig. 7.10 The amplitude of the fundamental output signal and the third order
intermodulation product versus
DS
J .
128
590H590H554H729H729HFig. 7.11 shows input IP3, IIP3, from measurement and simulation for multiple
DS
V .
f
N = 64. With
DS
V increasing from 0.6 to 1.0V,
DS
I increases only slightly, but IIP3
increases by a much larger factor, particularly at higher
GS
V when the device is biased
closer to linear operation region. And, the IP3 sweet spot
GS
V decreases as
DS
V
increases. The
DS
V dependence of IP3 sweet spot is determined by the threshold voltage
change due to DIBL, which will be verified using simulation results with and without
DIBL induced
th
V change in Section 593H593H555H730H730H8.5.
0.2 0.4 0.6 0.8 1
10
0
10
V
GS
(V)
IIP3 (dBm)
Symbol: Measurement
Line: Simulation
N
f
= 64, W
f
= 2um, L = 90nm, f0 = 5GHz, ?f = 100KHz
V
DS
increase
V
DS
= 0.6, 0.8, 1.0V
Fig. 7.11 Measured and simulated IIP3 versus
GS
V at multiple
DS
V .
556H731H731HFig. 7.12 shows IIP3 from measurement and simulation versus
DS
J for
f
N =10, 20,
and 64. The peak of measured IIP3 is not perfect because IP3 is not measured in a very
fine biasing step. Linearity simulation can predict IP3 sweet spot accurately for devices
with
f
N =10, 20, and 64. Note that the sweet spot
DS
J decreases from 35?A/?m for
129
f
N =10 to 20?A/?m for
f
N =64. Note that, the zero 3g
m
K point is marked as it is the
IP3 sweet spot estimated using first order IP3 theory. The zero 3g
m
K points for the three
transistors are practically the same since the devices scale well. So, just the zero 3g
m
K
point for
f
N =64 is shown in 557H732H732HFig. 7.12. The deviation between the actual IP3 sweet spot
and the zero 3g
m
K point increases as device size increases.
0 10 20 30 40 50 60 70 80 90 100
10
5
0
5
10
15
20
J
DS
(?A/?m)
IIP3 (d
Bm
)
N
f
=10
N
f
=20
N
f
=64
Symbol: Measurement
Line: Simulation
W
f
= 2um, L = 90nm, V
DS
= 0.8V, f0 = 5GHz, ?f = 100KHz
Number of finger
increase
K3
gm
=0
Fig. 7.12 Measured and simulated IIP3 versus
DS
J for devices with
f
N =10, 20, and 64.
558H733H733HFig. 7.13 and 559H734H734HFig. 7.14 show the measured IIP3 at 2, 5, and 10GHz for devices with
f
N =10 and 64 ( a total width of 20?m and 128?m). For
f
N =10, IIP3 at 2, 5, and
10GHz are practically identical. For
f
N =64, IIP3 increases as frequency increases. This
frequency dependence can be attributed to capacitive components in the transistor as
130
detailed in Section 560H735H735H9.2.3. The frequency dependence of simulated IIP3 in 561H736H736HFig. 7.13 and
562H737H737HFig. 7.14 is similar to the frequency dependence of measured IIP3.
0.2 0.4 0.6 0.8 1
10
5
0
5
10
15
20
V
GS
(V)
II
P3 (
d
Bm
)
f0=2GHz
f0=5GHz
f0=10GHz
Symbol: Measurement
Line: Simulation
N
f
= 10, W
f
= 2um, L = 90nm, ?f = 100KHz
Fig. 7.13 Measured and simulated IIP3 versus
GS
V at multiple frequencies for
f
N =10
(W=20?m).
131
0.2 0.4 0.6 0.8 1
10
5
0
5
10
15
V
GS
(V)
IIP
3 (dB
m)
f0=2GHz
f0=5GHz
f0=10GHz
Symbol: Measurement
Line: Simulation
N
f
= 64, W
f
= 2um, L = 90nm, ?f = 100KHz
frequency increase
Fig. 7.14 Measured and simulated IIP3 versus
GS
V at multiple frequencies for
f
N =64
(W=128?m).
7.4 Summary
This chapter evaluates the BSIM4 model of the NMOS transistor for linear and
nonlinear performance using a set of DC, Sparameter, and power spectrum
measurements, especially in the moderate inversion region. The results demonstrate
good fittings on both DC and AC characteristics. Despite its interpolating nature of
moderate inversion modeling, the BSIM4 model can accurately describe IV, and Y
parameters in moderate inversion region. The subcircuit based BSIM4 model can
predict the distortion behavior of a CMOS transistor correctly, which enables distortion
optimization of RFIC circuits using mathematical models and simulators. The linearity
sweet spot is investigated to be deviated significantly from the widely accepted zero
3g
m
K point for a practically large device size found in LNAs.
132
Chapter 8
MODELING OF INTERMODULATION LINEARITY
An important consideration in RFIC design is linearity, which sets the upper limit
of spurious free dynamic range. Among various linearity measures, the twotone third
order intermodulation distortion (IM3) is the most widely used, and is typically
characterized by the third order intercept point (IP3) [11]. Using either measured or
simulated IV data, IP3 sweet spot biasing current can be determined from zero 3g
m
K
point based on first order IP3 theory [11]. 3g
m
K is defined as the 3
rd
order coefficient of
the nonlinear transconductance . Circuits have been published to utilize this zero 3g
m
K
point for high linearity LNA designs [48] [52].
However, it was shown in [53] that the IP3 sweet spot from measurement and
simulation both shift to a lower
GS
V than the zero 3g
m
K point and the first order IP3
theory cannot correctly model the biasing and device scaling dependence of IIP3. More
accurate analytical IP3 expressions need to be developed. The complete IP3 expression
in this work is developed using the nonlinear current source method based on Volterra
series. The nonlinear drain current source includes nonlinear transconductance, output
conductance and the cross terms. The IP3 expression published in [22] [25] [26] are
just special cases of this complete IP3 expression. It will be shown later that the cross
CHAPTER
133
terms ignored in [22] [25] are important for accurate IP3 modeling and are responsible
for the
DS
V dependence of IP3 sweet spot
GS
V to drain induced barrier lowering (DIBL).
Linearity simulation results using BSIM4 model are compared with calculated
results. For the frequencies examined in this work, 2GHz, 5GHz, and 10GHz, open
short deembedding is valid for the layout design used. Thus, the pads and
interconnections are modeled using openshort equivalent circuit consisting of three
series and three shunt elements in Cadence. However, this added parasitics network
does not affect IIP3 that much.
8.1 First order IP3 theory
521H521H563H738H738HFig. 8.1 shows the small signal equivalent circuit used for analytical IP3 analysis.
()
12
cos cos
SS
vV t t? ?=+ is the two tone input signal.
11
2 f? ?= and
12
2 f? ?= . f
1
and f
2
are the frequencies of the twotone excitation spacing by ?f=100KHz.
S
R is the
source resistance, while
L
R is the load resistance. Here
S
R and
L
R are both 50?.
gs
C
and
d
C are the smallsignal gate to source capacitance and drain to substrate
capacitance with values extracted from Sparameters. First order IP3 theory considers
nonlinear transconductance only. The linear and the second and third order nonlinear
transconductance can be identified with the coefficients of Taylor expansion as
DS
m
GS
I
g
V
?
=
?
,
2
2
2
1
2
DS
g
m
GS
I
K
V
?
=
?
,
3
3
3
1
6
DS
g
m
GS
I
K
V
?
=
?
. (8.1)
The smallsignal nonlinear current source
ds
i can then be approximated by the first three
order nonlinearities as
134
23
23gg
ds m gs m gs m gs
igvKvKv=+ + . (8.2)
The first order input referred IP3 (IIP3) for the smallsignal equivalent circuit in 522H522H564H739H739HFig. 8.1
is then calculated as
( )
2
3
1
1
3
6
gs s
g
s
m
m
CR
IIP
R
K
g
?+
= . (8.3)
The derivation is detailed in Appendix J.
S
R
S
v
+

+

gs
v
gs
C
L
R
ds
i
d
C
+

ds
v
Fig. 8.1 The small signal equivalent circuit used for IP3 analysis.
When 3 0g
m
K = , first order IP3 gives the maximum IIP3, which is the well known
IP3 sweet spot used to improve linearity in circuit designs. 523H523H565H740H740HFig. 8.2 plots
m
g , 3g
m
K , and
the first order IP3 calculated using 444H524H524H566H741H741H(8.3). A sharp IIP3 peak is observed near the
threshold voltage, during the transition from subthreshold to strong inversion when
3g
m
K becomes zero. However, the sweet spot IIP3 is not necessarily the highest. The
calculated IIP3 can be higher in strong inversion since
m
g saturates and 3g
m
K is very
135
small as
GS
V increases. Experimental results also show that IIP3 varies strongly with
DS
V at sweet spot position and high
GS
V as detailed in Section 525H525H567H742H742H9.2.
0.2 0.4 0.6 0.8 1
10
0
10
20
V
GS
(V)
II
P3
(
d
B
m
)
0
V
DS
= 0.8V, f0 = 5GHzN
f
=64, W
f
= 2um, L = 90nm
First order analytical IIP3
K3gm
g
m
K3gm = 0
Fig. 8.2 First order IP3 with a sweet spot at 3g
m
K =0.
8.2 Complete IP3 expression
An IP3 expression including all of the nonlinear coefficients of order 3 and below
is derived using Volterra series. The nonlinear current source method together with the
small signal equivalent circuit in 743H743HFig. 8.1 is used to calculate the Volterra kernels [24]. 526H526H568
Although
gd
C is not included in 528H528H570H744H744HFig. 8.1, Volterra series analysis with
gd
C can also be
done. The expression with
gd
C is too complicated and thus not shown. The IP3
expression without
gd
C is sufficient for understanding the biasing and device size
dependence of IP3. Only when frequency is high and device size is large,
gd
C is needed
as illustrated in Section 529H529H571H745H745H9.2.3.
136
8.2.1 Two dimension nonlinear current source
The nonlinear current source
ds
i in 530H530H572H746H746HFig. 8.1 controlled by gatesource and drain
source voltages is written as [24]
23
23
22
22
23
23
23 3
gg
ds mgs mgs mgs
gg
ods ods ods
gg gg g g
m o gs ds m o gs ds m o gs ds
igvKvKv
gv K v K v
KvvK vvK vv
=+ +
++ +
+
. (8.4)
m
g and
o
g are the linear transconductance and output conductance. 2g
m
K and 3g
m
K are
the 2
nd
and 3
rd
order nonlinear transconductance, while 2g
o
K and 3g
o
K are the 2
nd
and
3
rd
order nonlinear output conductance. 2g g
mo
K , 23 g g
mo
K , and 23g g
mo
K are the 2
nd
, and
3
rd
order cross terms. The nonlinearity coefficients are defined in 531H531H573H747H747HTable 8.1.
Table 8.1 Definition of nonlinearity coefficients of nonlinear drain current.
Transconductance Output Conductance Cross term
DS
m
GS
I
g
V
?
=
?
DS
o
DS
I
g
V
?
=
?
2
2
DS
gg
mo
GS DS
I
K
VV
?
=
??
2
2
2
1
2
DS
g
m
GS
I
K
V
?
=
?
2
2
2
1
2
DS
g
o
DS
I
K
V
?
=
?
3
2
2
3
DS
gg
mo
GS DS
I
K
VV
?
=
??
3
3
3
1
6
DS
g
m
GS
I
K
V
?
=
?
3
3
3
1
6
DS
g
o
DS
I
K
V
?
=
?
3
2
2
3
DS
gg
mo
GS DS
I
K
VV
?
=
??
532H532H574H748H748HFig. 8.3 shows all of the nonlinear coefficients versus
GS
V at
DS
V =0.8V for a large
device width used in practical circuits, W=128?m. The zero 3g
m
K
GS
V is marked
because it is the IP3 sweet spot estimated from first order IP3 theory. All of the
137
derivatives are calculated from simulated IV data. The IV data are simulated using
BSIM4 model in Cadence and exported with 12 digits to ensure accurate numerical
evaluation of 2
nd
and 3
rd
order derivatives. 533H533H575H749H749HFig. 8.3 (a) and (d) show the linear
transconductance and output conductance versus
GS
V . 534H534H576H750H750HFig. 8.3 (b) and (c) show the 2
nd
and 3
rd
order nonlinear transconductance, while 535H535H577H751H751HFig. 8.3 (e) and (f) show the 2
nd
and 3
rd
order nonlinear output conductance. 536H536H578H752H752HFig. 8.3 (g)(i) are the 2
nd
and 3
rd
order cross terms.
Compared with the cross terms, the output conductance nonlinearities are much smaller,
especially at the sweet spot. The impact of cross terms on IIP3 sweet spot location
should be negligible, which is evaluated numerically in Section 537H537H579H753H753H8.3.
0.2 0.3754 0.7
20
10
0
5
K3
gm2
g
o
(mS/V
2
)
V
GS
(V)
0.2 0.3754 0.7
100
0
100
200
K3
2g
mg
o
(mS/V
2
)
V
GS
(V)
0.2 0.3754 0.7
0
25
50
K2
gmgo
(mS/V)
V
GS
(V)
2
0
4
8
K3
go
(mS/V
2
)
8
4
0
2
K2
go
(mS/V)
0
10
20
g
o
(mS)
600
0
800
K3
gm
(mS/V
2
)
0
150
300
K2
gm
(mS/V)
0
60
120
180
g
m
(mS)
K3
gm
=0
(a)
(b)
(c)
(d)
(e)
(f)
(g) (h) (i)
N
f
=64, W
f
=2?m, L=90nm, V
DS
= 0.8V
Fig. 8.3 The nonlinear coefficients versus
GS
V .
138
8.2.2 Input IP3 expression
Using Volterra series analysis, the complete IIP3 expression with
ds
i in 458H538H538H580H754H754H(8.4) is
derived as
2
3
1234
1( )
1
3
6
gs s
g
s
m
m
CR
IIP
R
K
g
?+
=
+?+?+?+?
. (8.5)
The derivation of 459H539H539H581H755H755H(8.5) is detailed in Appendix J. The first term in the denominator,
3 /g
mm
Kg, is due to the 3
rd
order transconductance as found in first order IP3 expression
460H540H540H582H756H756H(8.3). The other terms containing nonlinear output conductance and cross terms are
grouped as ?
1
, ?
2
, ?
3
, and ?
4
.
()
2
2
23
112
33
g
m
gg gg
mo mo
m
K
KZKZ
g
?=? ? , (8.6)
() ()
2
2
22 3 2
23 4 5
21 1
33 3
gg gg gg
mo mom mo
KKZ K gZ K Z?= + + , (8.7)
2
322
36 7
1
3
gggg
om mo om
KgZ K KgZ?=? ? , (8.8)
()
2
2
2
48
2
3
g
om
KgZ?= , (8.9)
where
() ( )
11 12
22
LL
ZZ Z? ??=+?,
1
21 21
() ( ) ()2
LS S
ZZ Y Y???
?
??=?+
??
,
3121 12
2( )() (2)( )
LLLL
ZZ Z Z Z? ?? ? ?=? + ?,
21
41 21
()2( ) ()1
LSS
ZZ Y Y???
?
??=?+
??
,
139
()()( ) ( )
5122 11
22
LLLL
ZZ Z Z Z? ?? ??=??+ ,
2
612
() ( )
LL
ZZ Z? ?=?,
()
2
711 121 1212
() (2)2 () () (2)6 () ()
LL LL L LL L
ZZ Z Z Z Z Z Z Z? ????????=+ + ?,
( )
2
71 1 1 12
( ) (2 ) 2 (2 ) 6
LL L L
ZZ Z Z Z?? ? ????=++?
??
,
() ( )
2
812 1 12
() ( ) 2 2
LL L L
ZZ Z Z Z?? ? ????=? +?
??
,
1
()
1/
L
odL
Z
gjC R
?
?
=
++
,
1
()
Sgs
S
YjC
R
??=+ .
?
1
, ?
2
, ?
3
, and ?
4
are functions of the 2
nd
and 3
rd
order nonlinear output
conductance and cross terms. The values of the cross terms, especially 2g g
mo
K and
23 g g
mo
K in ?
1
, are comparable to
m
g in moderate inversion region as shown in 541H541H583H757H757HFig. 8.3.
In strong inversion region,
m
g saturates, and 3g
m
K reduces to zero. ?
1
. ?
2
, ?
3
, and ?
4
will be comparable to 3 /g
mm
Kg even if they are close to zero as we will show below.
This indicates that ?
1
, ?
2
, ?
3
, and ?
4
are all important for IP3 modeling. Therefore, the
IP3 expressions without cross terms in [22] [25] are not accurate enough. Note that the
complete IP3 expression derived in [26] is a special case of 462H542H542H584H758H758H(8.5) at low frequencies.
Furthermore, the numerical results in [26] were calculated by neglecting various
nonlinear terms and the derivatives in the nonlinear coefficients were calculated from an
approximate drain current function instead of a complete MOSFET model. Here, the
numerical results are all calculated using the complete IIP3 expression in 463H543H543H585H759H759H(8.5), and all
of the derivatives are calculated using simulated IV data from a BSIM4 model.
140
An inspection of 464H544H544H586H760H760H(8.6)465H545H545H587H761H761H(8.9) shows that ?
1
, ?
2
, ?
3
, and ?
4
depend on
L
Z and
S
Y as
well. The load impedance will thus affect IP3 sweet spot when it dominates
L
Z . In this
work, IP3 is only examined for a 50? load due to its practical relevance and
straightforward measurement. When ?
1
=?
2
=?
3
=?
4
=0, the complete IP3 expression of
466H546H546H588H762H762H(8.5) reduces to the first order IP3 of 467H547H547H589H763H763H(8.3).
First order IP3 does not scale as device size scales because the scaling factors of
3g
m
K and
m
g are cancelled and
2
()
gs s
CR? is much smaller than 1 for the devices used.
?
1
, ?
2
, ?
3
, and ?
4
have quite different scaling factors as device size scales as shown in
Section 764H764H8.4.
8.3 Impact of the additional terms
Instead of the zero 3g
m
K point in 468H548H548H590H765H765H(8.3), IIP3 peaks at the point where the
denominator of 469H549H549H591H766H766H(8.5) is zero. 550H550H592H767H767HFig. 8.4 (a) shows the denominator in 471H551H551H593H768H768H(8.5) versus
GS
V ,
which is the sum of 3 /g
mm
Kg, ?
1
, ?
2
, ?
3
, and ?
4
, while 552H552H594H769H769HFig. 8.4 (b) shows 3 /g
mm
Kg,
?
1
, ?
2
, ?
3
, and ?
4
as a function of
GS
V individually.
DS
V =0.8V. The IP3 sweet spot
from 473H553H553H595H770H770H(8.5), 0.327V, is much lower than the zero 3g
m
K point, 0.3754V. ?
1
and ?
2
are the
two largest terms that affect the shift of the IP3 sweet spot. ?
3
and ?
4
have very little
impact on IP3 sweet spot since they are much smaller than ?
1
and ?
2
near the zero
3g
m
K point. Since ?
1
is negative and ?
2
is positive around the zero 3g
m
K
GS
V , the
impact of ?
1
and ?
2
on the shift of IP3 sweet spot are opposite. ?
1
moves IP3 sweet spot
141
to lower
GS
V , and ?
2
moves IP3 sweet spot to higher
GS
V when compared with the zero
3g
m
K
GS
V . The ?
3
and ?
4
terms, however, are important at higher
GS
V .
10
0
10
K3
gm
/g
m
+
?
1+
?
2+
?
3+
?
4
0.2 0.327 0.3754 0.7
20
10
0
10
20
V
GS
(V)
?
1,
?
2,
?
3 and
?
4
K3
gm
/g
m
?1
?2
?3
?4
K3
gm
/g
m
+?1+?2+?3+?4=0
K3
gm
/g
m
=0
N
f
= 64, W
f
= 2?m, L = 90nm, V
DS
= 0.8V
(a)
(b)
Fig. 8.4 (a) The denominator in 474H554H554H596H771H771H(8.5) versus
GS
V . (b) Each term in the denominator of
475H555H555H597H772H772H(8.5) versus
GS
V .
DS
V =0.8V.
556H556H598H773H773HFig. 8.5 shows the impacts of ?
1
, ?
2
, ?
3
, and ?
4
on IIP3. Since ?
1
is much larger
than ?
2
, a
GS
V lower than the zero 3g
m
K
GS
V is observed at IP3 sweet spot. Although
the deviation between IP3 sweet spot
GS
V and zero 3g
m
K
GS
V is dominated by ?
1
,
adding the other three elements can model IP3 sweet spot better. At high
GS
V ,
3 /g
mm
Kg is close to zero, and is comparable with the value of ?
1
, ?
2
, ?
3
, and ?
4
as
shown in 557H557H599H774H774HFig. 8.4 (b). Thus, ?
1
, ?
2
, ?
3
, and ?
4
all affect the value of IP3 at high
GS
V
142
significantly as shown in 558H558H600H775H775HFig. 8.5. Therefore, all of the nonlinear coefficients are
important for IP3 modeling including cross terms.
0.2 0.3754 0.7
10
0
10
20
V
GS
(V)
II
P3 (d
Bm)
First order IP3 (K3
gm
/g
m
)
K3
gm
/g
m
+?1
K3
gm
/g
m
+?1+?2+?3+?4
Simulation
N
f
= 64, W
f
= 2um, L = 90nm, V
DS
= 0.8V, f0 = 5GHz, ?f = 100KHz
K3
gm
= 0
Shift casued by ?1+?2+?3+?4
Shift casued by ?1
Fig. 8.5 IIP3 versus
GS
V from simulation, first order IP3 expression in 479H559H559H601H776H776H(8.3), and
complete IP3 expression in 480H560H560H602H777H777H(8.5) with different nonlinearities included.
DS
V =0.8V.
8.4 Device width scaling
The linear and nonlinear coefficients in 481H561H561H603H778H778H(8.5) all scale by a factor of K as device
size scales by K. The scaling factors of the Z terms are complicated. For very small
devices,
L
Z is approximately
L
R , and
S
Y is approximately 1/
S
R . Therefore, the scaling
factors for ?
1
, ?
2
, ?
3
, and ?
4
are K, K
2
, K
3
, and K
4
respectively. In the extreme case, if
L
Z and
S
Y are dominated by
o
g ,
d
C and
gs
C , ?
1
, ?
2
, ?
3
, and ?
4
do not scale as device
size scales. For the device sizes and frequencies examined in this work, the
d
C and
gs
C
terms are relatively small, and the scaling factors for ?
1
, ?
2
, ?
3
, and ?
4
are close to K,
K
2
, K
3
, and K
4
. This indicates that the impact of ?
1
, ?
2
, ?
3
, and ?
4
on IP3 sweet spot is
143
much stronger for large devices. As
f
N increases, a decrease of IP3 sweet spot
GS
V is
expected.
562H562H604H779H779HFig. 8.6 shows the calculated IIP3 using 483H563H563H605H780H780H(8.5) versus
DS
J for devices with multiple
finger numbers. Drain current density
DS
J is defined as /
DS
I W . First order IIP3 is
shown for comparison. As
DS
J 
GS
V is nearly identical for varying
f
N , the calculated
first order IP3 for varying
f
N are perfectly overlapped. For
f
N = 1, IP3 from 484H564H564H606H781H781H(8.5) is
almost the same as first order IP3, and the sweet spot is at the zero 3g
m
K point. As
device size increases, the deviation between IP3 calculated using 485H565H565H607H782H782H(8.5) and first order
IP3 increases.
DS
J of the IP3 sweet spot is the lowest for the largest
f
N .
0 50 100
10
5
0
5
10
15
20
J
DS
(?A/?m)
IIP3
(dBm)
W
f
= 2um, L = 90nm, V
DS
= 0.8V, f0 = 5GHz, ?f = 100KHz
(b)
Number of finger
increase
K3
gm
=0
N
f
= 1, 5, 10, 20, 64
Line: First order IIP3 (K3
gm
/g
m
)
Symbol:IIP3 calculated using (5)
(K3
gm
/g
m
+?1+?2+?3+?4)
Fig. 8.6 IIP3 calculated using 486H566H566H608H783H783H(8.5) and 487H567H567H609H784H784H(8.3) versus
DS
J for devices with multiple
finger numbers.
144
8.5 DIBL effect
The
DS
V dependence of IP3 sweet spot
GS
V is a direct result of the DIBL introduced
threshold voltage change from previous analysis. The threshold voltage change caused
by DIBL is modeled using
th
V? (DIBL) in BSIM4 model [2]. To further investigate the
impact of DIBL, simulation results with and without
th
V? (DIBL) are compared.
th
V? (DIBL) is turned off by setting corresponding model parameters to zero.
568H568H610H785H785HFig. 8.7 (a) shows
DS
I 
GS
V results from simulation with and without
th
V? (DIBL).
Without
th
V? (DIBL),
DS
I at low
GS
V for different
DS
V are close. The zero 3g
m
K points
are therefore close for different
DS
V as shown in 569H569H611H786H786HFig. 8.7 (b). 570H570H612H787H787HFig. 8.8 shows simulated
IIP3 with and without
th
V? (DIBL) for
f
N =64. Without DIBL, the
DS
V dependence of
IP3 sweet spot
GS
V is dramatically reduced.
145
0.2 0.4 0.6
10
1
10
0
10
1
10
2
I
DS
(mA
)
0.2 0.4 0.6
500
0
500
V
GS
(V)
K3
gm
(m
S/V
2
)
V
DS
=0.6V
V
DS
=0.8V
V
DS
=1.0V
N
f
= 64, W
f
= 2um, L = 90nm
Simulation with ?V
th
(DIBL)
Simulation without ?V
th
(DIBL)
(a)
(b)
K3
gm
=0
Simulation with ?V
th
(DIBL)
Simulation without ?V
th
(DIBL)
K3
gm
=0
Fig. 8.7 (a)
DS
I , (b) 3g
m
K versus
GS
V at multiple
DS
V for simulation with and without
th
V shift due to
th
V? (DIBL).
0.2 0.4 0.6
10
0
10
V
GS
(V)
II
P3
(dB
m
)
V
DS
=0.6V
V
DS
=0.8V
V
DS
=1.0V
N
f
= 64, W
f
= 2um, L = 90nm
Simulation with ?V
th
(DIBL)
Simulation without ?V
th
(DIBL)
Fig. 8.8 IIP3 calculated using 495H575H575H617H788H788H(8.5) versus
GS
V at multiple
DS
V for simulation with
and without
th
V? (DIBL).
146
571H571H613H789H789HFig. 8.9 (a) compares the denominator of 492H572H572H614H790H790H(8.5) for simulations with and without
th
V? (DIBL). 573H573H615H791H791HFig. 8.9 (b) and (c) compare the most important terms in the denominator
of 494H574H574H616H792H792H(8.5), 3 /g
mm
Kg and ?
1
+?
2
individually. ?
3
and ?
4
are not shown here because they
have very little impact on IP3 sweet spot. The variation of ?
1
+?
2
with
DS
V is
approximately the same for simulation with and without
th
V? (DIBL). Thus, the impact
of ?
1
+?
2
on the
DS
V dependence of the deviation of IP3 sweet spot
GS
V from zero 3g
m
K
point is approximately the same for simulation with and without
th
V? (DIBL). The
DS
V
dependence of IP3 sweet spot
GS
V is thus mainly a result of the
DS
V dependence of the
zero 3g
m
K
147
10
5
0
5
10
K3
gm
/g
m
+
?
1+
?
2+
?
3+
?
4
10
5
0
5
10
K3
gm
/g
m
0.2 0.4 0.6
15
10
5
0
5
V
GS
(V)
?
1+
?
2
V
DS
= 0.6V
V
Ds
= 0.8V
V
DS
= 1.0V
N
f
= 64, W
f
= 2?m, L = 90nm
K3
gm
/g
m
=0
K3
gm
/g
m
+?1+?2+?3+?4=0
(a)
(b)
(c)
Simulation with ?V
th
(DIBL)
Simulation without ?V
th
(DIBL)
Fig. 8.9 (a) 3 /g
mm
K g +?
1
+?
2
+?
3
+?
4
, (b) 3 /g
mm
K g , and (c) ?
1
+?
2
versus
GS
V at
multiple
DS
V for Cadence simulation with and without
th
V? (DIBL).
8.6 Summary
This chapter develops a complete analytical IP3 expression which involves not only
nonlinear transconductance but also nonlinear output conductance and cross terms. The
deviation of the sweet spot
GS
V from the widely accepted zero 3g
m
K point for a
practically large device size found in LNAs is attributed to output conductance
nonlinearities and cross terms through this expression. The impacts of these additional
terms added to 3 /g
mm
K g are examined individually to figure out the dominant factor
for IP3 sweet spot shift. The significance of the additional terms scales with device
148
width. Therefore, the deviation of IP3 sweet spot from zero 3g
m
K point is the largest,
and IP3 sweet spot
DS
J is the lowest for the largest device. In the 90nm CMOS
technology used, the sweet spot
DS
J decreases from 40 to 20?A/?m as gate width
increases from 2 to 128 ?m. For large devices of interest to RFIC design, simulation
using a good model and measurement of IP3 must be used to accurately identify the
sweet spot biasing current density. Simulation results without
th
V? (DIBL) indicate that
the
DS
V dependence of IP3 sweet spot
GS
V is dominated by the threshold voltage shift
caused by DIBL effect.
149
Chapter 9
CHARACTERIZATION OF RF INTERMODULATION LINEARITY
After developing the complete IP3 expression in Section 576H576H618H793H793H8.2, IP3 sweet spot of
single transistor and simple circuits can be estimated using measured IV and S
parameters of single transistor, instead of twotone intermodulation measurement.
However, because of the IV data measured using Agilent 4155 only has 5 digits, which
is not sufficient to provide smooth 2
nd
and 3
rd
order nonlinearity coefficients in 577H577H619H794H794HTable
8.1, the calculated IP3 are all from simulated IV and Sparameters using the BSIM4
model examined in 620H795H795HChapter 7. The same set of equations can be applied on measured I
V and Sparameters once the measured data has enough digits.
This chapter compares the measured and calculated IP3 results for a 90nm RF
CMOS technology. The complete IP3 expression developed in Section 578H578H621H796H796H8.2 is used. IV
data and device small signal parameters are extracted from DC and Sparameter
simulations using the BSIM4 model validated in 622H797H797HChapter 7. The IP3 expression can
accurately predict the biasing and device size dependence of IP3 sweet spot. The
frequency dependence of IP3 is determined by the small signal capacitance. Thus, the
frequency dependence is very weak and negligible for small device. For large device,
not only gatesource capacitance and drainbulk capacitance but also gatedrain
capacitance are important. To determine the value of IP3 accurately, more complete
equivalent circuit of MOS transistor must be used in Volterra series analysis.
CHAPTER
150
9.1 Power gain measurement
Of particular interest to linearity measurement is the power gain. Since 50? source
and load are used in IP3 measurement, at low input power, the power gain obtained
from sweeping input power linearity measurement should agree with the small signal
power gain
21
S from Sparameter measurement, which involves much more systematic
error correction. Therefore, the power gain (at low
in
P ) from linearity measurement
using spectrum analyzer with
21
S from Sparameter measurement using VNA, are
compared in 585H585H625H798H798HFig. 9.1, as a means of assuring power calibration accuracy for linearity
measurement. The power gains extracted from intermodulation measurement are close
to
21
S from Sparameter measurement within 0.5dB for most measurements in this
dissertation.
0.2 0.4 0.6 0.8 1
0
10
20
V
GS
(V)
Gain
(dB)
S
21
P
out,1st
P
in
N
f
= 64, W
f
= 2um, L = 90nm, V
DS
=0.8V, f0 = 5GHz
Fig. 9.1 Gain from linearity measurement (
,1out st
P 
in
P ) and gainsparameter
measurement (
21
S ) versus
GS
V .
151
9.2 Linearity Characteristics
From analysis in Section 587H587H626H799H799H8.3, the IP3 sweet spot is not only determined by 3g
m
K ,
but also the 2
nd
and 3
rd
order cross terms through ?
1
and ?
2
in 507H588H588H627H800H800H(8.5). Here, the accuracy
of 508H589H589H628H801H801H(8.5) is examined against measured IP3 for different biasing voltages, different
device sizes, and different fundamental frequencies to further verify the impact of the
additional terms. Overall, the analytical expression is not bad for this 90nm RF CMOS
technology.
9.2.1 Drain voltage dependence
590H590H629H802H802HFig. 9.2 shows IIP3 from measurement and 510H591H591H630H803H803H(8.5) for multiple
DS
V .
f
N = 64. With
DS
V increasing from 0.6 to 1.0V,
DS
I increases only slightly, IIP3 increases by a much
larger factor, particularly at higher
GS
V , and the IP3 sweet spot
GS
V decreases.
To explain the
DS
V dependence of IP3 sweet spot and high
GS
V IP3, 3 /g
mm
K g and
3 /g
mm
K g +?
1
+?
2
+?
3
+?
4
are plotted in 592H592H631H804H804HFig. 9.3. The zero 3g
m
K point shifts to lower
GS
V as
DS
V increases because of the threshold voltage change due to DIBL. The
GS
V
gaps between IP3 sweet spot and zero 3g
m
K point for different
DS
V are approximately
the same. Thus, the
DS
V dependence of IP3 sweet spot is determined by the threshold
voltage change due to DIBL, and the impacts of the ? terms on IP3 sweet spot are
similar for different
DS
V . This was verified using simulation results with and without
DIBL induced
th
V change in Section 593H593H632H805H805H8.5. At high
GS
V , 3 /g
mm
K g are close while
3 /g
mm
K g +?
1
+?
2
+?
3
+?
4
split for different
DS
V . Both 3g
m
K and
m
g do not show great
152
DS
V dependence at high
GS
V because the transistor is biased in saturation region for all
three
DS
V . However, the
DS
V dependence of the 2
nd
and 3
rd
order output conductance
nonlinearities and cross terms is noticeable. This directly leads to highly
DS
V dependent
? terms at high
GS
V . Therefore, the denominator of 513H594H594H633H806H806H(8.5) and thus the calculated IIP3
are
DS
V dependent at high
GS
V .
0.2 0.4 0.6
10
0
10
V
GS
(V)
II
P3
(dBm)
V
DS
=0.6V
V
DS
=0.8V
V
DS
=1.0V
N
f
= 64, W
f
= 2um, L = 90nm, f0 = 5GHz, ?f = 100KHz
Line: Analytical IIP3
Symbol: Measurement
Fig. 9.2 Measured and analytical IIP3 versus
GS
V at multiple
DS
V . Analytical IIP3 is
calculated using 514H595H595H634H807H807H(8.5).
153
0.2 0.327 0.3754 0.7
10
5
0
5
10
V
GS
(V)
N
online
a
r Terms
V
DS
=0.6V
V
DS
=0.8V
V
DS
=1.0V
K3
gm
/g
m
+?1+?2+?3+?4=0
(IP3 sweet spot)
K3
gm
/g
m
=0
N
f
= 64, W
f
= 2um, L = 90nm, f0 = 5GHz, ?f = 100KHz
Fig. 9.3 3 /g
mm
K g and 3 /g
mm
K g +?
1
+?
2
+?
3
+?
4
versus
GS
V at multiple
DS
V .
9.2.2 Finger number dependence
To verify the analysis of device scaling in Section 596H596H635H808H808H8.4, 597H597H636H809H809HFig. 9.4 shows IIP3 from
measurement and 517H598H598H637H810H810H(8.5) versus
DS
J for
f
N =10, 20, and 64. The peak of measured IIP3
is not perfect because IP3 is not measured in a very fine biasing step. 518H599H599H638H811H811H(8.5) can predict
IP3 sweet spot accurately for devices with
f
N =10, 20, and 64. Note that the sweet spot
DS
J decreases from 35?A/?m for
f
N =10 to 20?A/?m for
f
N =64. 3 /g
mm
K g for
f
N =10, 20, and 64 are so close that only the zero 3g
m
K point for
f
N =64 is shown in
600H600H639H812H812HFig. 9.4 for reference.
154
0 20 40 60 80 100
10
5
0
5
10
15
20
J
DS
(?A/?m)
IIP3
(dBm)
N
f
=10
N
f
=20
N
f
=64
Symbol: Measurement
Line: Analytical IIP3
W
f
= 2um, L = 90nm, V
DS
= 0.8V, f0 = 5GHz, ?f = 100KHz
Number of finger
increase
K3
gm
=0
Fig. 9.4 Measured and analytical IIP3 versus
DS
J for devices with
f
N =10, 20, and 64.
Analytical IIP3 is calculated using 520H601H601H640H813H813H(8.5).
9.2.3 Frequency dependence
602H602H641H814H814HFig. 9.5 shows measured IIP3 at 2, 5, and 10GHz for devices with
f
N =10 and 64
( a total width of 20?m and 128?m). For
f
N =10, IIP3 at 2, 5, and 10GHz are
practically identical. For
f
N =64, IIP3 increases as frequency increases. This frequency
dependence can only be attributed to
gs
C and
d
C in 522H603H603H642H815H815H(8.5). However, IIP3 calculated
using 523H604H604H643H816H816H(8.5) does not show a strong frequency dependence for
f
N =64 as shown in 605H605H644H817H817HFig.
9.6 (a). To further explore this,
gd
C is added to the small signal equivalent circuit. 606H606H645H818H818HFig.
9.6 (b) shows IIP3 calculated using Volterra series with
gd
C added at multiple
frequencies. The strong frequency dependence of calculated IIP3 with
gd
C is similar to
the frequency dependence of measured IIP3.
155
For small devices,
gs
C ,
d
C , and
gd
C are small, and thus the terms containing these
capacitances are relatively small. For frequencies below 10GHz, the IIP3 calculated are
practically the same for different frequencies. 607H607H646H819H819HFig. 9.7 shows IIP3 calculated using 527H608H608H647H820H820H(8.5)
and Volterra series with
gd
C for
f
N =10 at 2, 5, and 10GHz. The results are overlapped.
0 200 400 600
0
10
20
J
DS
(?A/?m)
IIP3
(dB
m
)
f0=2GHz
f0=5GHz
f0=10GHz
W
f
= 2um, L = 90nm, ?f = 100KHz
N
f
=64
N
f
=10
Fig. 9.5 Measured IIP3 versus
DS
J at multiple frequencies for
f
N =10 and 64
(W=20?m and 128?m).
156
0 200 400 600
5
0
5
10
J
DS
(?A/?m)
IIP3(dBm)
5
0
5
10
IIP3(dBm)
f0=2GHz
f0=5GHz
f0=10GHz
N
f
=64
N
f
=64
N
f
=64, W
f
=2?m, L=100nm, V
DS
=0.8V, ?f=100KHz
(a)
(b)
Analitical IP3 without C
gd
Analitical IP3 with C
gd
Fig. 9.6 Analytical IIP3 (a) without
gd
C and (b) with
gd
C at multiple frequencies for
f
N =64 (W=128?m). Analytical IIP3 without
gd
C is calculated using 528H609H609H648H821H821H(8.5).
0 200 400 600
0
10
20
J
DS
(?A/?m)
IIP
3(dB
m)
f0=2GHz
f0=5GHz
f0=10GHz
N
f
=10, W
f
=2?m, L=100nm, V
DS
=0.8V, ?f=100KHz
Symbol: Analitical IP3 without C
gd
Line: Analitical IP3 with C
gd
N
f
=10
Fig. 9.7 Analytical IIP3 with and without
gd
C at multiple frequencies for
f
N =10
(W=20?m). Analytical IIP3 without
gd
C is calculated using 529H610H610H649H822H822H(8.5).
157
9.2.4 Large signal linearity
The solid lines in 611H611H650H823H823HFig. 9.8 represents the typical fundamental frequency output
power, P
out,1st
, and the third order intermodulation (IM3) output power, P
out,3rd
, versus
input power, P
in
, curves for a moderate inversion gate bias. By observing the two curves,
an unexpected minimum IM3 output power point at certain input power level is
investigated. A better output signal power to distortion ratio can be achieved by
selecting this P
in
level as the circuits working point [23]. This largesignal IM3 sweet
spot is not defined for smallsignal operation, and cannot be evaluated using the
extrapolated IP3 point. Note that instead of a gain compression at certain input power as
shown in 612H612H651H824H824HFig. 1.7, the output signal first linearly follows the input power, then it
experiences a faster rate of rise before it saturates. This phenomena is named as gain
expansion, and can be observed sometimes [23].
30 20 10 0 5
90
60
30
0
10
Pin (dBm)
Pou
t
(
d
B
m
)
V
GS
= 0.3V, V
DS
= 0.8V
f0 = 5GHz, ?f = 100KHz
ATTN = 0dB
N
f
= 64, W
f
= 2um, L = 100nm
P
out,3rd
P
out,1st
large signal sweet spot
Fig. 9.8 The output power amplitude for fundamental and 3
rd
order intermodulation
products versus input power.
158
613H613H652H825H825HFig. 9.9 shows a contour plot for sweeping gate bias and input power. The deep
valley marked using square symbols are the IM3 sweet spots [90]. Below 10dBm input
power, the sweet spots appear at around gate bias 0.33V, which is the IP3 sweet spot.
As the input power increases, the IM3 sweet spot shifts to lower gate bias voltage
obviously.
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
25
20
15
10
5
0
V
GS
(V)
P
in
(dBm)
0.6 0.8 0.9
6
0
50
40
32
24
20
10
P
out,3rd
N
f
=64, W
f
=2um, L=100nm
V
DS
=0.8V, ATTN=0dB
f0=5GHz, ?f=100KHz
Fig. 9.9 Contour of 3
rd
order intermodulation output power with sweeping gate bias
and input power.
9.3 Summary
In this chapter, the measured IIP3 is compared with calculated IIP3 using IV and
Sparameters from BSIM4 based simulation. The complete IP3 expression can correctly
model the biasing, frequency, and device size dependence of IIP3 even with simulated
IV and Sparameters as long as the model is valid in DC IV and Sparameters. In the
159
90nm CMOS technology used, the sweet spot
DS
J decreases from 40 to 20 ?A/?m as
gate width increases from 2 to 128?m. The
DS
V dependence and its device width
dependence are also investigated using experimental results. These results provide
useful guidelines to linearity characterization, simulation as well as optimal biasing and
sizing for high linearity in RFIC design.
160
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Appendix A
ABBREVIATIONS AND SYMBOLS
A.1 Abbreviations
DUT: device under test. (Everything probed by the probes is a DUT.)
GSG: groundsignalground.
IM3: third order intermodulation.
IP3: third order intercept point. (IIP3: input IP3) and (OIP3: output IP3)
ISS: impedance standard substrate.
PSA: performance spectrum analyzer.
PSG: performance signal generator.
SOLT: shortopenloadthru.
SVD: singularvaluedecomposition.
TRL: thrureflectionline
VNA: vector network analyzer.
A.2 Matrix symbols and matrix index
,OS left
Y : Yparameters of LEFT after openshort deembedding.
,OS right
Y : Yparameters of RIGHT after openshort deembedding.
M
S : Measured Sparameter without switch errors.
APPENDIX
169
DUT
S : Sparameter of the whole onwafer test structure being probed.
A
S : The actual Sparameter of the desired twoport.
Comments:
1) If Q is a twodimension matrix,
mn
Q or
mn
q is the (m,n) element in the matrix.
The subscript is the row and column index of the element.
2) If Q is the name of a test structure or a multiport network, then
Q
S (
Q
E ),
Q
Y ,
Q
Z ,
Q
T , and
Q
A are the S, Y, Z, T, and ABCD parameters of the structure
or the network. The transformation between them is listed in 826H826HAppendix B.
170
Appendix B
TWO PORT NETWORK REPRESENTATIONS
Two port network can be represented using S, H, Y, Z, and ABCDparameters.
The transformation between these representations is important for system error
calibration, onwafer parasitics deembedding and model parameter extraction. 827H827HTable
B.1 gives the transformation between H, Y, Z, and ABCD parameters. The
transformation from S to Y and Z are given as
()()
1
0
YYISIS
?
=?+ ?
( ) ( )
1
00
SYY YY
?
= +?, (B.1)
()()
1
0
Z ZISIS
?
=+? ?
( ) ( )
1
00
SZZ ZZ
?
=+ ?, (B.2)
where
0
Z is system characteristic impedance.
0
Z =50?.
1
00
YZ
?
= . The 2?2 matrices for
the transformation from S to Y and Z are listed below:
11 22 12
00
11 22 11 22
11 12
21 22
11 2221
00
11 22 11 22
1 2
12
11
S
SS
S
SS
SS S
YY
SS SS
YY
YY SS
S
YY
SS SS
? ??+?? ?
? ?
+ ++? +++???
? ?
=
??
? ?
+ ????
??
? ?
+ ++? +++?
? ?
? ?
, (B.3)
11 22 21
00
11 22 11 22
11 12
21 22
11 2212
00
11 22 11 22
1 2
12
S
SS
S
SS
SS S
ZZ
SS SS
ZZ
ZZ SS
S
ZZ
SS SS
? ?+???
? ?
? ?+? ??+???
? ?
=
??
? ?
? +??
??
? ?
? ?+? ??+?
? ?
? ?
, (B.4)
where
11 22 12 21S
SS SS?= ? .
APPENDIX
171
Table B.1 Transformation between two port H, Y, Z, and ABCD representations
H Y Z ABCD
H
11 12
21 22
HH
HH
12
11 11
21
11 11
1
Y
Y
YY
Y
YY
?
?
12
22 22
21
22 22
1
Z
Z
Z Z
Z
Z Z
?
?
1
ABCD
B
DD
C
DD
?
?
Y
12
11 11
21
11 11
1
H
H
HH
H
HH
?
?
11 12
21 22
YY
YY
22 12
21 11
ZZ
ZZ
Z Z
Z Z
?
? ?
?
? ?
1
ABCD
D
BB
A
BB
??
?
Z
12
22 22
21
22 22
1
H
H
H H
H
H H
?
?
22 12
21 11
YY
YY
YY
YY
?
? ?
?
? ?
11 12
21 22
Z Z
Z Z
1
ABCD
A
CC
D
CC
?
ABCD
11
21 21
22
21 21
1
H
H
HH
H
HH
?? ?
? ?
22
21 21
11
21 21
1
Y
Y
YY
Y
YY
? ?
???
11
21 21
22
21 21
1
Z
Z
Z Z
Z
Z Z
?
AB
CD
11 22 12 21H
HH HH?= ? ,
11 22 12 21Y
YY YY?= ? ,
11 22 12 21Z
Z ZZZ?= ? ,
ABCD
AD BC?=?.
172
Appendix C
REVIEW OF ONWAFER DEEMBEDDING METHODS
C.1 OpenShort deembedding
828H828HFig. C.1 shows the equivalent circuit for openshort deembedding. 829H829HFig. C.2 shows
the equivalent circuits and layouts of the OPEN and SHORT standards. Denoting
13 3
323
E
YY Y
Y
YYY
? ?+?
=
? ?
?+
? ?
, (C.1)
and
46 6
656
S
ZZ Z
Z
Z ZZ
? ?+
=
? ?
+
? ?
, (C.2)
the measured Yparameters of OPEN and SHORT are
,M open
E
YY= and
,1Mshort
ES
YYZ
?
=+ . That leads to
( )
1
,,M short M open
S
ZY Y
?
=? .
Using the properties of shunt and series connected twoport networks, the measured
Yparameter of any DUT,
M
Y , in 830H830HFig. C.1 is
{ }
1
1
MA
ES
YYZY
?
?
??=+ +
??
. (C.3)
Thus, the actual Yparameters,
A
Y , can be obtained as
()( )
( )
1
11
,,,A M M open M short M open
YYY Y Y
?
??
=? ? ? . (C.4)
APPENDIX
173
Openshort deembedding is valid as long as the parallel parasitics is mainly located at
the probing pads. It is still an industry standard deembedding method, and can provide
valuable device parameters below 30GHz.
Y3
Y1 Y2
Z4 Z5
Z6
[YA]
Fig. C.1 Equivalent circuit of onwafer parasitics for openshort deembedding.
(a) OPEN (b) SHORT
Y3
Y1 Y2
Y3
Y1 Y2
Z4 Z5
Z6
Fig. C.2 Equivalent circuits and layouts of (a) OPEN, and (b) SHORT standards.
174
C.2 PadopenShort deembedding
831H831HFig. C.3 shows the equivalent circuit for padopenshort deembedding. 832H832HFig. C.4
shows the equivalent circuits and layouts of the PAD, OPEN, and SHORT standards.
Denoting
E
Y as 833H833H(C.1),
S
Z as 834H834H(C.2), and
I
Y as
79 9
989
I
YY Y
Y
YYY
? ?+?
=
? ?
?+
? ?
, (C.5)
Thus,
,M pad
E
YY= ,
,1Mshort
ES
YYZ
?
=+ , and
( )
1
,1M open
ESI
YYZY
?
?
=+ + .
S
Z and
I
Y can
be solved as
( )
1
,,Mshort Mpad
S
ZY Y
?
=? , (C.6)
()()
1
11
,, , , ,,M open M pad M short M pad M open M pad
I
YY Y Y Y Y Y
?
??
??
=??? ??
??
??
. (C.7)
The equivalent circuit that shown in 835H835HFig. C.3 gives
()
1
1
MA
ESI
YYZYY
?
?
? ?
=+ + +
? ?
? ?
, (C.8)
A
Y can then be obtained as
()
( )
1
1
AM
ESI
YYY ZY
?
?
= ???. (C.9)
Padopenshort deembedding lumps the distributive parasitics along the connections at
the pad and the end of connections, which can work up to 50GHz.
175
Y3
Y1 Y2
Z4 Z5
Z6
[YA]
Y7 Y8
Y9
Fig. C.3 Equivalent circuit for padopenshort deembedding.
(a) PAD (b) OPEN (c) SHORT
Y3
Y1 Y2
Y3
Y1 Y2
Z4 Z5
Z6
Y3
Y1 Y2
Z4 Z5
Z6
Y7 Y8
Y9
Fig. C.4 Equivalent circuits and layouts of PAD, OPEN and SHORT standards for
padopenshort.
176
C.3 Threestep deembedding
836H836HFig. C.5 shows the equivalent circuit for threestep deembedding. 837H837HFig. C.6 shows
the equivalent circuits and layouts of the OPEN, SHORT1, SHORT2 and THRU
standards. Denoting
1
2
0
0
E
Y
Y
Y
? ?
=
? ?
? ?
, (C.10)
46 6
656
S
ZZ Z
Z
Z ZZ
? ?+
=
? ?
+
? ?
, (C.11)
33
33
I
YY
Y
YY
? ??
=
? ?
?
? ?
, (C.12)
M
Y and
A
Y can be related through 838H838H(C.8) and 839H839H(C.9). The elements of
E
Y ,
S
Z , and
I
Y
can be solved from onwafer standards since
''
, 33
''
33
M open
E
YY
YY
YY
? ??
=+
? ?
?
? ?
,
( )
1
'1
33 45
YYZZ
?
?
=++ (C.13)
,1 1
1
Mshort
ES
YYZ
?
=+ ,
46 6
1
1
6536
S
ZZ Z
Z
Z ZY Z
?
? ?+
=
? ?
++
? ?
, (C.14)
,2 1
2
M short
ES
YYZ
?
=+ ,
1
43 6 6
2
656
S
ZY Z Z
Z
Z ZZ
?
? ?++
=
? ?
+
? ?
, (C.15)
'' ''
, 13 3
'' ''
323
Mthru
YY Y
Y
YYY
? ?+?
=
? ?
?+
? ?
,
( )
1
''
345
YZZ
?
=+ . (C.16)
The elements of
E
Y ,
S
Z , and
I
Y are
,,
111 12
M open M open
YY Y=+, (C.17)
,,
222 12
M open M open
YY Y=+, (C.18)
177
()()
1
,
41,12,12
1
2
Mthru
SS
ZZZY
?
? ?
=??
? ?
? ?
, (C.19)
()()
1
,
52,21,12
1
2
Mthru
SS
ZZZY
?
? ?
=??
? ?
? ?
, (C.20)
()()
1
,
61,12,12
1
2
Mthru
SS
ZZZY
?
? ?
=++
? ?
? ?
, (C.21)
()()
1
11
,,
312 12
Mopen Mthru
YY Y
?
??
? ?
=? +
? ?
? ?
. (C.22)
Y1 Y2
Z4 Z5
Z6
[YA]
Y3
Fig. C.5 Equivalent circuit for improved three step deembedding.
(a) OPEN (b) SHORT1 (c) SHORT2 (d) THRU
Y1 Y2 Y1 Y2
Z4 Z5'
Z6 Y1 Y2
Z4' Z5
Z6 Y1 Y2
Z4 Z5Y3'
Fig. C.6 Equivalent circuits and layouts of OPEN, SHORT1, SHORT2, and THRU
standards for improved three step.
178
C.4 Transmission line deembedding
The onwafer parasitics and the desired device can be represented as a cascade of
several two port networks as shown in 840H840HFig. C.7. The input and output networks, which
are composed of the probe pads and the interconnections leading to the device, are
represented using ABCD parameters,
IN
A and
OUT
A .
1IN PAD X
AAA= and
2OUT Y PAD
AAA= , where,
1PAD
A and
2PAD
A are the ABCD parameters of the probe pads
at input and output,
X
A and
Y
A are ABCD parameters of input and output
interconnections. 841H841HFig. C.8 shows the equivalent circuits and layouts for the THRU1 and
THRU2 standards. The two transmission line structures have different length
S
A and
L
A .
The measured ABCD parameters of the desired device is
M IN A OUT
AA= . (C.23)
Thus, the measured ABCD parameters of THRU1 and THRU2 are
,,1 ,1 1 2
S
AM thru IN A thru OUT PAD PAD
AA AA==
A
, (C.24)
,,2 ,2 1 2
L
AM thru IN A thru OUT PAD PAD
AA AA==
A
. (C.25)
The ABCD parameters of a transmission line with length
LS
?AA can be calculated as
()
1
,,,
LS SL
AAA
A
?
?
=
AA AA
because the ABCD parameters of a transmission line of length
A are given by
cosh sinh
1
sinh cosh
C
C
Z
AB
CD
Z
? ?
??
? ?
??
? ?
=
??
? ?
??
? ?
? ?
AA
AA
, (C.26)
179
where
C
Z is the characteristic impedance, and ? is the propagation constant.
C
Z and ?
are the same for THRU1 and THRU2. Denoting
()
1
, ,2 ,1
LS
M Athru Athru
AAA
?
?
=
AA
, one will
have
( )
1
,,11
LS LS
MAPAD PAD
AAAA
?
??
=
AA AA
(C.27)
In special case, 2
LS
=AA, the ABCD parameters of symmetric pads can be determined
from THRU1 and THRU2.
() ()
11
1 2 ,1 ,2 ,1PAD PAD M thru M thru M thru
AA A A A
? ?
== . If 2
LS
?AA,
it is hard to solve the ABCD parameters without a PAD standard. However, it is not
necessary to solve PAD parameters for deembedding purpose because the PAD
parameters are cancelled out during deembedding as shown below.
To solve
,
L S
A
A
?AA
without solve
1PAD
A and
2PAD
A ,
,
L S
M
A
?AA
is transformed to
,
L S
M
Y
?AA
using equations in 842H842HAppendix B. From padopenshort deembedding, the Y
parameters of a symmetric PAD standard can be represented as
,
0
0
MPAD P
P
Y
Y
Y
? ?
=
? ?
? ?
(C.28)
Thus, using Yparameter representation, we have
,,
0
0
LS LS
AM P
P
Y
YY
Y
??
? ?
=?
? ?
?
? ?
AA AA
(C.29)
Because transmission line is a symmetric structure, the Yparameters of PAD can be
cancelled out using
( )
,, ,
/2
LS LS LS
AM M
YYswapY
?? ?
? ?
=+
? ?
AA AA AA
.
()
,
LS
M
swap Y
?AA
swaps
the two ports of
,
L S
M
Y
?AA
.
,
L S
A
A
?AA
can then be obtained from
,
L S
A
Y
?AA
.
180
The Yparameters of the left and right half of THRU1 both contains one probing
pad and a transmission line with length / 2
S
A . Denoting the left half as
*IN
Y , and the
right half as
*OUT
Y ,
*IN
Y and
*OUT
Y are calculated as
,1 ,1 ,1
11 12 12
*
,1 ,1
12 12
2
4
22
4
Mthru Mthru MthruS
CIN
Mthru MthruS
C
yy y
Z
Y
yy
Z
?
?
??
??
??
=
?
??
A
A
, (C.30)
**OUT IN
YPYP= ,
01
10
P
? ?
=
? ?
? ?
. (C.31)
C
Z and ? are extracted from
,
L S
A
A
?AA
as
,
12
,
21
L S
L S
A
C
A
A
Z
A
?
?
=
AA
AA
and
,1
11
cosh
L S
A
LS
A
?
??
=
?
AA
AA
. (C.32)
Thus, the ABCD parameters of the input and output networks are then given by
/2*
XS
IN IN
AAA
?
=
AA
and
/2*
YS
OUT OUT
AAA
?
=
AA
. The ABCD parameters of the desired
device is obtained as
( ) ( )
11
AINMOUT
AAAA
? ?
= . (C.33)
[ABCD]
A
[ABCD]
Y
[ABCD]
X
[ABCD]
PAD1
[ABCD]
PAD2
INPUT OUTPUT
Fig. C.7 Equivalent circuit for transmission line deembedding.
181
(a) THRU1 (b) THRU2
S
A
YX
L
A
D1
PAD
1
PAD
2
X Y
S
A
D2
PAD
1
PAD
2
X Y
L
A
Fig. C.8 Equivalent circuits and layouts of THRU1 and THRU2 for transmission line
deembedding. The length of transmission line is not to scale.
182
Appendix D
SWITCH ERROR REMOVAL
D.1 Switch error removal equations
843H843HFig. 3.2 shows a twoport measurement system with four receivers. The
characteristics of the switch can be removed by making no assumption of
0
Z . For each
twoport measurement,
11 0 0
/Sba= and
21 3 0
/Sba= are calculated in forward mode,
while
''
12 0 3
/Sba= and
''
22 3 3
/Sba= are calculated in reverse mode. The subscript is the
port number where the wave is monitored, while the superscript ?'? means reverse
mode.
[SA]
0
Z
Sweep
Oscillator
Dual
Reflectometer
1
b
1
a
2
b
2
a
Forward
Reverse
Port 1
Port 2
3
b
3
a
0
b
0
a
Switch
Fig. D.1 A twoport Sparameter measurement system with four receivers.
APPENDIX
183
Under forward mode, if
3
0a = , matched
0
Z termination, then the calculated
11
S
and
21
S are the measured
11
M
S and
21
M
S of the twoport. If
3
0a ? , not matched
0
Z
termination, the Sparameters of the twoport are defined using
0011 12
3321 22
MM
MM
baSS
SS
? ?????
=
? ?????
??? ???
. (D.1)
Similarly, under reverse mode, if
'
0
0a = , the calculated
12
S and
22
S are the measured
12
M
S and
22
M
S of the twoport. If
'
0
0a ? , the Sparameters of the twoport are defined
using
''
0011 12
3321 22
MM
MM
baSS
SS
? ?????
=
? ?????
??? ???
. (D.2)
Combining the forward and reverse mode configurations,
''
00 0011 12
33 3321 22
MM
MM
bb aaSS
bb aaSS
? ?????
=
? ?????
??? ???
. (D.3)
Therefore, the Sparameter of the twoport,
M
S , is calculated as
1
''
00 0011 12
''
333321 22
MM
MM
bbaaSS
bbaaSS
?
? ?? ???
=
? ?? ???
??? ?? ?
, (D.4)
which can be rewritten as
'' ' '
03 03 00 00
'' ' '
33 33 30 30
M
ba ba ba ba
S
ba ba ba ba
????
??
??
=
??
?? ??
,
''
03 30
aa aa?= ? (D.5)
Substituting
11 0 0
/Sba= ,
21 3 3
/Sba= ,
''
12 3 3
/Sba= and
''
22 0 0
/Sba= into 844H844H(D.5),
M
S with
switch error removed is calculated from the raw Sparameters exported from VNA as
184
11 12 21 1 12 11 12 2
21 22 21 1 22 21 12 2
M
SSS SSS
DD
S
SSS SSS
DD
???? ??
??
=
?? ??
??
,
3
1
3
forward
a
b
?= ,
'
0
2
'
0
reverse
a
b
?= (D.6)
1
? and
2
? are user functions defined above for forward and reverse mode, which can
only be measured using fourreceiver VNA.
21 12 1 2
1DSS= ???.
M
S is the measured S
parameters of the DUT after removing switch errors, while
11
S ,
21
S ,
12
S , and
22
S are
the raw Sparameters directly saved from the VNA without switch error removal.
D.2 Stepbystep guide to measure the switch errors
1. Setup VNA
Define the frequency list, the input power level, and the averaging factor as the
same as the setup used for onwafer standards and transistor measurement.
2. Define user functions in VNA
Press the MENU key in PARAMETER block to bring the user parameter menu
onto the CRT/LCD screen.
Define
133
/ab?= under forward mode first.
3
a and
3
b are the waves monitored
by the receivers at Port 2. Thus, in VNA, they are named as a2 and b2.
? Select USER1.
? Press REDEFINE PARAMETER.
? Press DRIVE, PORT1.
? Press PHASE LOCK, a1.
? Press NUMERATOR, b2.
? Press DENOMINATOR, a2.
185
? Press CONVERSION, 1/S.
? Press PARAMETER LABEL, then enter a2/b2, then press TITLE DOWN,
REDEFINE DONE.
Define
200
/ab?= under reverse mode.
0
a and
0
b are the waves monitored by the
receivers at Port 1. Thus, in VNA, they are named as a1 and b1.
? Select USER2.
? Press REDEFINE PARAMETER.
? Press DRIVE, PORT2.
? Press PHASE LOCK, a2.
? Press NUMERATOR, b1.
? Press DENOMINATOR, a1.
? Press CONVERSION, 1/S.
? Press PARAMETER LABEL, then enter a1/b1, then press TITLE DOWN,
REDEFINE DONE.
3. Measure
1
? and
2
?
Display all of the four Sparameters on the screen first. Press the DISPLAY key in
MENUS block. Select DISPLAY MODE, FOUR PARAM SPLIT. All of the four S
parameters, S11, S21, S12, and S22 are displayed on the screen.
Then, replace two of the Sparameters with the defined user functions, USER1 and
USER2. Press the MENU key in PARAMETER block, select USER1 and USER2. The
four parameters displayed on the screen are now 1/USER1, 1/USER2, S12, and S22.
186
Probe THRU standard on the Cascade ISS 101190 substrate. Press the MENU key
in STIMULUS block to bring the stimulus control menu onto the CRT/LCD screen.
Select the MORE, then SINGLE to make a single measurement. Wait until the
measurement is finished and HOLD is marked with underline.
4. Export data as a CITI file
Insert a floppy disk. Press the DISK key in the AUXILIARY MENUS block. Press
STORE, MORE, DATA, enter the name of the file DD_ERR, and then press STORE
FILE.
5. Example CITI file exported
CITIFILE A.01.01
#NA VERSION HP8510XF.01.02
NAME RAW_DATA
#NA REGISTER 6
VAR FREQ MAG 35
DATA USER[1] RI
DATA USER[2] RI
DATA S[1,2] RI
DATA S[2,2] RI
#NA DUPLICATES 0
#NA ARB_SEG 2000000000 70000000000 35
VAR_LIST_BEGIN
2000000000
4000000000
6000000000
8000000000
10000000000
12000000000
? ? ? ?.
64000000000
66000000000
68000000000
70000000000
VAR_LIST_END
COMMENT YEAR MONTH DAY HOUR MINUTE SECONDS
CONSTANT TIME 2007 08 10 15 00 03.0
BEGIN
2.35986E0,1.20932E1
7.40478E0,3.54687E0
6.18872E0,6.42651E0
6.24414E0,1.01318E1
2.61523E1,9.20996E0
2.70185E1,1.02001E1
187
? ? ? ?.
1.75854E0,5.03784E0
3.19091E0,3.38647E0
6.30932E0,4.04101E0
1.53857E1,3.04736E1
END
BEGIN
3.03686E0,7.43920E0
6.72070E0,3.75439E0
4.42919E0,5.90649E0
8.03173E0,3.51220E0
2.05234E1,0.71484E0
? ? ? ?.
5.20507E0,1.43994E1
2.87963E0,3.32666E0
3.16540E0,2.25952E1
3.81811E0,4.58984E0
END
BEGIN
1.07403E0,6.15478E1
3.27758E1,1.46313E0
1.61621E1,1.29162E0
7.56713E1,1.14001E0
9.71008E1,7.04650E1
4.18945E1,9.37377E1
? ? ? ?.
3.78418E1,3.74939E1
5.19653E1,1.14196E1
0.25878E1,5.13000E1
3.73977E1,2.49313E1
END
BEGIN
1.68396E1,0.82214E1
2.12471E1,0.45509E1
0.3302E1,2.36198E1
2.22015E1,0.30609E1
1.02417E1,1.53465E2
0.18722E1,1.90048E1
? ? ? ?.
1.18751E1,1.54907E1
0.9021E1,1.97334E1
0.75592E1,1.50070E1
0.87142E1,3.28628E1
END
188
Appendix E
CALIBRATION KIT SETUP
This is a stepbystep tutorial for calibration kit setup on Agilent VNA 8510C.
MENUS means the block?s name of a group of the keys which is printed on the front
panel of the equipment. CAL means hardkey which is the button on the front panel
under each block. The number and unit keys on the right side of the screen are not
included. MORE means softkey on the screen which can be selected using the buttons
on the right side of the screen. The following steps are for Cascade RF infinity probe
with pitch size of 100?m, and Cascade ISS 101190 substrate. The values entered are
from the data sheet of the probes and the substrate, which are also listed in 845H845HTable E.1.
1. Modify CalKit
Press hardkey CAL in the MENUS block, then select MORE, MODIFY 1 to
modify the calibration coefficients for CalKit 1. Select MODIFY 2 to modify the
calibration coefficients for CalKit 2.
2. Define calibration standards
Select DEFINE STANDARD.
Press 1, x1. Make sure the OPEN is underlined.
Press OPEN.
Select C0, enter6.5, x1. Enter 0, x1 for C2, C3, and C4.
Select SPECIFY OFFSET, enter 0, x1.
APPENDIX
189
Press STD OFFSET DONE.
Press LABEL STD, enter the name of the standard, e.g. OPEN6.5.
Press TITLE DONE.
Press STD DONE.
3. Repeat Step 2 for SHORT, LOAD, and THRU standards
SHORT: Press DEFINE STANDARD, enter 2, x1, and then select SHORT.
LOAD: Press DEFINE STANDARD, enter 3, x1, and then select LOAD.
THRU: Press DEFINE STANDARD, enter 4, x1, and then DELAY/THRU.
4. Class assignment
Press SPECIFY CLASS
Select S11A, enter 1, x1. OPEN is defined as standard 1 in step 2.
Select S11B, enter 2, x1. SHORT is standard 2 in step 3.
Select S11C, enter 3, x1. LOAD is standard 3 in step 3.
Do the same for S22A, S22B, S22C, FWD TRANS, REV TRANS, FWD
MATCH, REV MATCH, FWD ISOL`N, REV ISOL`N, using the corresponding
class assignment values from 846H846HTable E.1 (c).
Press SPECIFY CLASS DONE.
5. Label classes
Press LABEL CLASS
Select S11A, enter `OPEN6.5`, and then LABEL DONE.
Select S11B, enter `SHORT 3.3`, and then LABEL DONE.
Select S11C, enter `LOAD 50`, and then LABEL DONE.
190
Do the same for S22A, S22B, S22C, FWD TRANS, REV TRANS, FWD
MATCH, REV MATCH, FWD ISOL`N, REV ISOL`N, using the corresponding
standard labels from 847H847HTable E.1 (c).
Press LABEL CLASS DONE.
6. Label the calibration kit
Press LABEL KIT, enter the title of the calibration kit, e.g. `ISS100UM`, and
then TITLE DONE, KIT DONE (MODIFIED).
7. Save calibration kit in VNA and floppy disk
Press SAVE. To save the calibration kit to CALKIT 1 in the VNA memory.
Press DISC, in the AUXILIARY MENUS block, the select STORE, CALKIT1
2, CALKIT 1, enter a filename, e.g. `CK_100`. The calibration kit will be saved
on a floppy disk with name CK_100, which can be loaded into VNA later using
LOAD, CALKIT12, CALKIT 1.
191
Table E.1 Calibration Kit Coefficients
STANDARD
LABEL
OPEN6.5
SHORT 3.3
LOAD 50 THRU 1
P
CO
AX or
WAVEG
UIDE
Coax Coax Coax Coax
MAX 999 999 999 999
FREQUENCY GHz
MIN
0 0 0 0
Z
0
?
50 50
500
50
LO
SS
M
?
/s
0 0 0 0
O
F
FSET
DELAY
psec
0 0
0.0008
1
FIXED or SLIDING
Fixed
C3
10
4
5
F/
Hz
0
C2
10
3
6
F/
Hz
0
C1
10
2
7
F/
Hz
0
C0
10
1
5
F
6.5
3.3
TYPE
OPEN
SHOR
T
LOAD THRU
(a) SOLT calibration standard
definitions for Cascade RF infinity GS
G probe, 100um pitch, and C
a
scade ISS 101190.
STANDARD
NO
1 2 3 4
L Term
0.4pH
3.7pH
L Short
3.3pH 8.2pH
C Open
6.5fF 6.7fF
(b) Constant for Cascade RF infinity GSG probes
Pitch
100um 150um
1)
ISS substrate : Cascade ISS 101190.
2)
Probe : Cascade RF infinity GSG probe.
3)
L Term : Modeled as
a high imp
edance trans
mission line offset with Z
0
=500
?
, delay=L/ Z
0
.
4)
THRU dela
y is pitch size independent, which
depends on the signal to signal pad distance of the test structure onl
y. For transistor test
structures, T
H
RU with
200um length and 1psec
delay is alw
a
ys used.
STANDARD CL
ASS
LABEL
OPEN6.5 SHORT 3.3 LOAD 50 OPEN6.5 SHORT 3.3 LOAD 50 THRU 1
P
THRU 1
P
THRU 1
P
THRU 1
P
LOAD 50 LOAD 50
G
F
E
D
C
B
A 1 2 3 1 2 3 4 4 4 4 3 3
(c) Stand
ard
Class Assig
n
ments
S
11
A
S
11
B
S
11
C
S
22
A
S
22
B
S
22
C
Forwa
r
d T
r
ansmi
ssion
Rever
s
e T
r
ansmission
Forwa
r
d Match
Reverse Match Forwa
r
d Isolation
Reverse Isolation
192
Appendix F
THE RELATIONSHIP BETWEEN OPENSHORT AND FOURPORT
848H848HFig. 4.1 illustrates the fourport network for onwafer parasitics. There are two
external ports, and two internal ports.
m
V ,
m
I ,
*
m
V , and
*
m
I , are the voltages and currents
at each port. The subscript m is the port number, m=1,2. The superscript * means
internal ports. Based on the definition of Yparameters, the voltages and currents can be
related through the Yparameters of the fourport network as
11 12 11 12
21 22 21 2222
**
11 12 11 12
21 22 21 22
ee ee ei ei
ee ee ei ei
ie ie ii ii
ie ie ii ii
yy yyVI
yy yy
yy yy
VIyy yy
???? ??
???? ??
?? ??
=
?? ??
?? ??
???? ??
?? ????
. (F.1)
To make the following derivations easier to read, voltage and current vectors are
defined as
1
2
e
V
V
V
??
=
??
??
,
1
2
e
I
I
I
? ?
=
? ?
? ?
,
*
1
*
2
i
V
V
V
? ?
=
? ?
? ?
,
*
1
*
2
i
I
I
I
? ?
=
? ?
? ?
. (F.2)
The superscript e means external ports, while i means internal ports. The relationship in
849H849H(F.1) can be rewritten as
ee ei
ee
ie ii
ii
I VYY
I VYY
? ?????
=
? ?????
??? ???
, (F.3)
where
APPENDIX
193
11 12
21 22
ee ee
ee
ee ee
y y
Y
y y
??
=
??
??
,
11 12
21 22
ei ei
ei
ei ei
y y
Y
y y
? ?
=
? ?
? ?
,
11 12
21 22
ie ie
ie
ie ie
y y
Y
y y
? ?
=
? ?
? ?
,
11 12
21 22
ii ii
ii
ii ii
y y
Y
y y
??
=
??
??
. (F.4)
The twoport network between the external ports gives
111121
22122
DUT DUT
DUT DUT
VyyI
VyyI
??? ???
=
??? ???
??? ???
,
11 12
21 22
DUT DUT
DUT
DUT DUT
yy
Y
yy
? ?
=
? ?
? ?
. (F.5)
With the direction of currents defined in 850H850HFig. 4.1, the twoport network between the
internal ports gives
**
111121
22122
AA
AA
VyyI
VyyI
??? ?? ??
=
??? ?? ?
?
??? ?? ?
,
11 12
21 22
AA
A
AA
y y
Y
y y
? ?
=
? ?
? ?
. (F.6)
Through the Yparameters of the fourport network,
DUT
Y and
A
Y are related as
( )
1
DUT ee ei A ii ie
YYYYYY
?
=? + , (F.7)
or,
( )
1
AiiieMeei
YYYYYY
?
=? ? ? . (F.8)
Onwafer Parasitics
Onwafer Parasitics
1
V
+
?
1
I
*
1
I
*
2
I
2
V
+
?
2
I
*
1
V
+
?
*
2
V
+
?
[SA]
Fig. F.1. Block diagram of the 4port network for onwafer parasitics using IV
representation.
194
Since the Yparameters of ideal OPEN and SHORT are
[ ]
,
22
0
A open
Y
?
= and
()[]
1
,
22
0
A short
Y
?
?
= , using 851H851H(F.7),
,DUT open
Y and
,DUT short
Y are
( )
1
,DUT open
ee ei ii ie
YYYYY
?
=? , (F.9)
,DUT short
ee
YY= . (F.10)
Recall the openshort deembedded Yparameters of the device,
OS
Y ,
()( )
1
11
,,,OS DUT DUT open DUT short DUT open
YYY Y Y
?
??
??
=? ? ?
??
??
. (F.11)
Substituting 852H852H(F.9) and 853H853H(F.10) into the
OS
Y expression above,
( ) ( )
11
,DUT DUT open ei ii A ii ie
YY YY YYY
??
? ?
?= ?+
? ?
? ?
, (F.12)
( )
1
,,DUT short DUT open ei ii ie
YYYYY
?
?= , (F.13)
and thus
() ( ) ()
( )
1
1 1
11 1
OS ei ii A ii ie ei ii ie
YYYYYY YYY
?
? ?
?? ???
=?+
??
??
. (F.14)
The equation is too complicated to give any clue of the relationship between
OS
Y and
A
Y . It must be simplified. The first thing can be done is taking the
ei
Y and
ie
Y out.
() ( )
1
1
11
OS ei ii A ii ii ie
YY Y YY YY
?
?
??
??
??
=?+
??
??
??
??
. (F.15)
It is difficult to further simplify the equation because of the plusminus operators inside
the brace. To eliminate the plusminus operations, two identity matrices,
()()
1
Aii Ai
YY YY
?
++ and
()( )
1
ii ii
YY
?
are added to 854H854H(F.15),
195
()()() ( )()()
1
1
111
OS ei A ii A ii ii A ii ii ii ii ie
Y Y YY YY Y YY YY Y Y
?
?
???
??
??
=++ ?+
??
??
??
??
. (F.16)
Taking the common elements,
( )
1
Aii
YY
?
+ and
( )
1
ii
Y
?
, out of the square brackets leads
to
() ( )
{ }
1
1
OS ei ii A A ii ii ie
YYYY YYYY
?
?
??=+
??
, (F.17)
which is equivalent to
{ }
1
1
OS ei ii ii A ii ii ie
YYYYYYYY
?
?
??=+ ?
??
. (F.18)
This gives a very simple relationship between
OS
Y and
A
Y ,
( ) ( )
11
OS ei ii A ii ie
YYYYYY
??
= . (F.19)
Although 855H855H(F.19) is derived for onwafer parasitics and starts from openshort de
embedding, the solution is general to singlestep calibration as long as
[ ]
,
22
0
Aopen
Y
?
=
and
()[]
1
,
22
0
A short
Y
?
?
= . The only difference is that, when it is applied on the measured
raw Sparameters without ISS calibration,
,DUT open
Y ,
,DUT short
Y , and
OS
Y do not have
their physical meanings as what they have in twostep calibration.
196
Appendix G
SINGULARITY OF LINEAR EQUATION SET
G.1 Typical calibration standards
The most common calibration standards used for Sparameter measurement are
twoport standards, through (THRU) and delay(DELAY), and oneport standards,
match (M), short (S), and open (O). The oneport standards are used in pairs to build a
twoport standard for twoport system calibration. For example, the LEFT standard used
for fourport calibration can be viewed as a MO standard, which means a matched load
at Port 1, and an open standard at Port 2. A zero length THRU is kept for all of the
combinations examined below for two reasons. First, the set of standards must includes
a twoport standard to measure the transmission errors. That means, a THRU or
DELAY standard must be included. Secondly, the ends of the interconnects of Port 1
and Port 2 are very close for onwafer transistor structures. Thus, a zero length THRU
structure is the one of the simplest structures to be built onwafer. The results shown
below are from Cadence simulation. The parasitic network is built using ideal resistor,
capacitor, and inductors with values close to the values extracted from measurement.
The M standard is an ideal 50? resistor since the VNA system is a 50? system.
APPENDIX
197
G.2 Singularity of onwafer standards
An analytical proof for the singularity of the combinations of standards is
complicated. However, it can be easily examined by numerical simulation examples
using condition number of the coefficient matrix. The condition number is defined as
the ratio of the largest singular value over the smallest singular value of the matrix. For
four standards, there are 16 equations written in matrix as
'
16 15 15 1 16 1
AT B
?? ?
= . If the
coefficient matrix
16 15
A
?
has zero singular values,
16 15
A
?
is not full rank, and the number
of unknowns can be solved equals to the number of nonzero singular values. If
16 15
A
?
is
full rank, but has extremely small singular values, which leads to an extremely large
condition number, the set of equation is illconditioned (singular), and the validity of
the solution is questionable. Assuming THRU is taken as one of the four standards, and
the other three standards are chosen from the pairs consisting O, S or M, i.e. OO, SS,
MM, OS, SO, OM, MO, SM, MS, there are 84 different combinations.
856H856HFig. G.1 compares the condition number, the minimum singular value and the
maximum singular value for four sets of standards. The coefficient matrix
16 15
A
?
are all
singular since the condition numbers are extremely large for all cases. For five
standards, the coefficient matrix is
20 15
A
?
, and there are 126 possible combinations if
THRU is chosen. 46 combinations was shown to be singular in the reference. The
nonsingular combinations are listed in 857H857HTable G.1.
858H858HFig. G.2 compares condition number, minimum and maximum singular values for
five sets of standards. The results indicate that these combinations are nonsingular and
can provide valuable T solutions. Among the five sets of standards, the combination of
198
THRU, OO, SS, SM, MS gives the smallest condition number, and thus the best
tolerance to measurement errors. If the five standards are nonsingular, then adding more
standards will not help to improve the validity of the T solution. 859H859HFig. G.3 compares the
condition number, minimum and maximum singular values for 5, 6, and 7 standards.
Two sets of nonsingular five standards are compared. Both of them show that adding
more standards do not reduce the condition number of the coefficient matrix.
0
2
4
x 10
7
co
nd
itio
n nu
mb
er
0
2
4
6
x 10
7
m
i
nimu
m sing
ular valu
e
0 20 40 60 80 100
2.6
2.8
3
ma
x
i
mum
si
n
g
u
l
ar
va
l
u
e
frequency (GHz)
THRU, MM, OS, SO
THRU, MM, OO, SS
THRU, OM, MO, SS
THRU, SM, MS, OO
Fig. G.1 Condition number, minimum and maximum singular value for four standards.
199
Table G.1 Nonsingular combinations of five twoport calibration standards for 16
term error model. Assuming one standard is a zero length THRU.
THRU AM MA AA BB
THRU AM BA AA BB
THRU AM BM AA BB
THRU AM MA BM AA
THRU AM MB BM AA
THRU AM BA BM AA
THRU AM BA MB AA
THRU AM BA AB BB
THRU AM MA AB BB
THRU AM BM AB BB
THRU AM MB BA BB
THRU AM MB BM BB
THRU AM MA BM BB
THRU AM MA BM AB
THRU AM MA BM BA
THRU AM MB AB BA
THRU AM MB BM AB
THRU AM MB BM BA
THRU AM BM AB BA
THRU MM AA BB AB
THRU MM AA BB AM
THRU MM AA AB BA
THRU MM AA AB MA
THRU MM AA AB MB
THRU MM AA AM MA
THRU MM AA AM MB
THRU MM AA BM MB
THRU MM AB AM BA
THRU MM AB AM MA
THRU MM AB AM MB
THRU MM AB BM MA
A = open, B = short, or A = short, B = open.
Reference: K. J. Silvonen, "Calibration of 16term error model," Electronics Lett., vol.
29, no. 17, pp. 15441545, 1993.
200
0
20
40
cond
it
ion nu
mber
0
0.5
1
min
i
mu
m singu
lar
value
0 20 40 60 80 100
2.8
3.2
3.6
maximum sin
gular valu
e
frequency (GHz)
THRU, OO, SS, OM, MO
THRU, OO, SS, SM, MS
THRU, MM, SS, OM, MO
THRU, MM, OO, OS, SO
THRU, MM, OO, SM, MS
Fig. G.2 Condition number, minimum and maximum singular value for five standards.
0 20 40 60 80 100
0
5
10
15
20
25
condition number
frequency (GHz)
THRU, OO, SS, OM, MO
THRU, OO, SS, SM, MS
Dash Line: 5 standards + MM
Dot Line: 5 standards + MM & L=400?m transmission line
Fig. G.3 Condition number for multiple number of standards.
201
Appendix H
ONEPORT ERROR CORRECTION
860H860HFig. H.1 shows the block diagram for a oneport system. The system consists of a
sweep oscillator, a dualreflectometer consisting of two couplers connected backto
back, and the unknown oneport DUT,
DUT
? . The direction of power flow through the
system is indicated using arrows.
0
a and
0
b are the incident and reflected waves
measured by the VNA. The measured reflection coefficient of the unknown oneport is
defined as
00
/
M
ba?= . The linear errors introduced by the imperfect reflectometer can
be modeled by a fictitious twoport error adapter between the reflectometer and the
unknown oneport. This results in a perfect reflectometer with no loss, no mismatch,
and no frequency response errors.
DUT
Reflectometer
1
b
1
a
0
0
M
b
a
?=
1
1
DUT
a
b
?=
0
b
0
a
Incident Reflected
Fig. H.1 The block diagram for a oneport measurement.
APPENDIX
202
H.1 Error adaptor for oneport system
861H861HFig. H.2 shows the fictitious twoport error adaptor for a oneport system. The error
adapter has four error terms. Defining incident waves to the error adapter as
0
a and
1
a ,
the reflected waves to the error adapter as
0
b and
1
b . a means incident wave, b means
reflected wave. The subscript is the port number. The measured and the actual reflection
coefficients of the unknown oneport are
00
/
M
ba?= and
11
/
DUT
ab?= . Written in
matrix, the Sparameters of the twoport error adapter can be defined using the waves as
00 0100
10 1111
eeba
ee
???? ??
=
???? ??
?? ????
,
00 01
10 11
ee
E
ee
? ?
=
? ?
? ?
(H.1)
The 2?2 matrix E is the Sparameters of the twoport error adapter.
The same relation can be equivalently represented using the signal flow graph in
862H862HFig. H.3. The system directivity
00
e can be best understood when an ideal match load is
under test. Part of the incident
0
a is reflected back to
0
b through the branch labeled
00
e ,
independent of the
DUT
? . Thus, when measuring
M
? , there must be some residual
signals measured.
0
a
0
b
DUT
2port
Error
Adaptor
Sweep
Oscillator
Perfect
Reflectometer
0
b
0
a
1
b
1
a
4 error terms
M
?
DUT
?
Fig. H.2 The combined twoport error adaptor for oneport Sparameter measurement.
203
0
b
1
b
00
e
11
e
01
e
0
a
1
a
10
e
Error Adaptor
M
?
DUT
?
Fig. H.3 Signal flow graph of the twoport error adaptor in oneport measurement.
H.2 Relationship between
M
? and
DUT
?
Denoting
00
/
M
ba?= and
11
/
DUT
ab?= in 863H863H(H.1),
M
? and
DUT
? can be related
through
()
10 01 00 11 11 00
DUT M DUT M
ee ee e e? ?+??+=?. (H.2)
By measuring three standards with known
DUT
? , three equations containing the
unknown error terms are built. Then the error terms
00
e ,
( )
10 01
ee , and
11
e can be solved.
After that,
DUT
? for any measured
M
? can be obtained using
()
00
00 11 10 01
M
DUT
M
e
ee ee
??
?=
?? +
. (H.3)
Note that, only three error terms,
00
e ,
( )
10 01
ee , and
11
e , need to be solved for error
correction purpose. This is because of the ratio nature of Sparameter measurement. The
most widely used standards are OPEN, SHORT, and LOAD. Without specification,
LOAD standard in this work means matched
0
Z load. 864H864HFig. H.4 show the magnitude of
the solved error terms,
00
e ,
10 01
ee , and
11
e .
204
0 5 10 15 20 25
0
0.05
0.1
0.15
0.2
e
00
 & e
11

0 5 10 15 20 25
0
0.05
0.1
0.15
0.2
frequency (GHz)
e
10
e
01

e
00

e
11

(a)
(b)
Fig. H.4 The three error terms solved using OPEN, SHORT and LOAD standards.
The relationship between
M
? and
DUT
? in 865H865H(H.2) is a nonlinear function in terms of
the error terms,
00
e ,
()
10 01
ee , and
11
e . Due to the difficulty in solving nonlinear
equations, a linear equation in terms of the error terms is developed next as a
generalized interpretation which can be easily extended to twoport system.
H.3 A generalized interpretation
The linear equation is derived from the transmission parameters (Tparameters) of
the twoport error adapter. In matrix, the Tparameters of the error adapter is written as
0131
0 24 1
b tta
attb
??? ?? ?
=
??? ?? ?
? ?? ???
. (H.4)
205
Similarly, denoting
00
/
M
ba?= and
11
/
DUT
ab?= ,
M
? and
DUT
? are related through
1234
0
DUT M DUT M
tttt? ?? ? + ?? = . (H.5)
This is a linear equation in terms of the elements in T. Since Tparameters represent the
Sparameters of the same error adapter, 866H866H(H.5) can be rewritten in a similar format as
867H867H(H.2),
312
444
DUT M DUT M
ttt
? ?? ? + =? (H.6)
Comparing 868H868H(H.2) and 869H869H(H.6), the elements in T can be related to the elements in E as
1
10 01 00 11
4
t
ee ee
t
=?,
2
11
4
t
e
t
=? ,
3
00
4
t
e
t
= . (H.7)
Note that all of the unknown terms are normalized to
4
t and the equation is still a linear
equation of the unknown terms. After normalization, only three unknowns need to be
solved. Three standards, e.g. OPEN, SHORT, and LOAD, can be used to solve the three
equations as below
111 1
14
222 2
24
333 3
34
1/
1/
1/
DUT M DUT M
DUT M DUT M
DUT M DUT M
tt
tt
tt
?????????? ?
??????
???? =?
???? ?
??????
. (8.8)
Once the three error terms are solved, the system errors of any measured
M
? can then
be calibrated using an alternative of 870H870H(H.6) as
3
4
12
44
M
DUT
M
t
t
tt
tt
??
?=
??
. (H.9)
206
Considering the linear equation in 871H871H(H.5), at first glance, one may think with four
measurements,
1
t ,
2
t ,
3
t , and
4
t can be completely solved without normalization.
However the resulting linear matrix problem is homogenous. For four measurements,
the four linear equations written in matrix are
111 1
1
222 2
2
333 3
3
444 4
4
01
01
01
01
DUT M DUT M
DUT M DUT M
DUT M DUT M
DUT M DUT M
t
t
t
t
???????? ?? ? ?
????? ?
???? ??
? ?
=
? ?
???? ??
? ?
???? ??
? ???
. (H.10)
If the four unknowns can all be solved, the coefficient matrix must be full rank. This
leads to an all zero solution of T. So the rank of the coefficient matrix must be smaller
than 4, which means in maximum, only three of the unknowns can be solved. This is
theoretically attributed to the ratio nature of Sparameters and the inability to solve
10
e
and
01
e independently. The normalization of T elements will not affect error calibration
at all.
207
Appendix I
DERIVATION OF FIRST ORDER INPUT IP3
872H872HFig. 8.1 shows the small signal equivalent circuit used for analytical IP3 analysis.
()
12
cos cos
SS
vV t t? ?=+ is the two tone input signal.
11
2 f? ?= and
12
2 f? ?= .
S
R
is the source resistance, while
L
R is the load resistance.
gs
C and
d
C are small signal
gate to source capacitance and drain to substrate capacitance. First order IP3 theory
considers the smallsignal nonlinear current source
ds
i as a function of
gs
v only. With
smallsignal input, it can be approximated by the first three order Taylor expansion as
23
23gg
ds m gs m gs m gs
igvKvKv=+ + . (I.1)
m
g , 2g
m
K , and 3g
m
K are the first three order nonlinearity coefficients of
ds
i , which can
be calculated as
DS
m
GS
I
g
V
?
=
?
,
2
2
2
1
2
DS
g
m
GS
I
K
V
?
=
?
,
3
3
3
1
6
DS
g
m
GS
I
K
V
?
=
?
. (I.2)
APPENDIX
208
S
R
S
v
+

+

gs
v
gs
C
L
R
ds
i
d
C
+

ds
v
Fig. I.1 The small signal equivalent circuit used for IP3 analysis.
For a twotone input signal,
( )
12
cos cos
gs
vA t t? ?=+. The amplitudes of
s
v and
gs
v are related by 1
SgsS
VAjCR?=+ . The two frequencies are
1
f and
2
f .
11
2 f? ?= , and
22
2 f? ?= . Therefore, the output drain current in 873H873H(I.1) contains
components at frequencies
12
mn? ?+ , m and n are integers. The magnitude of the
fundamental components at
1
? and
2
? are
3
39/4 g
mm
gA K A+ , and the 3
rd
order
intermodulation components at
12
2? ?? and
21
2? ?? are
3
33/4 g
m
KA. Under small
signal excitation, the magnitude of the fundamental components are approximately
m
gA, since the second term can be ignored when compared with the
m
gA term.
The 3
rd
order intermodulation distortion (IM3) is defined as the ratio of the 3
rd
order intermodulation components and the fundamental components,
3
3
3
3
4
g
m
m
KA
IM
gA
= . (I.3)
The 3
rd
order intercept point is the point where the fundamental and the 3
rd
order
intermodulation components are equal, which is
3
1IM = in 874H874H(I.3). The amplitude of
gs
v
at the 3
rd
order intercept point is calculated as
209
2
3
4
3
m
g
m
g
A
K
= . (I.4)
Therefore,
S
V at the 3
rd
order intercept point is
()
2
2
3
4
1
3
m
SgsS
g
m
g
VCR
K
?
? ?
=+
? ?
? ?
. (I.5)
The corresponding maximum available power at the power source
S
v is defined as input
referred IP3 (IIP3) as
( )
2
2
3
1
1
3
86
gs s
S
g
Ss
m
m
CR
V
IIP
RR K
g
?+
== . (I.6)
210
Appendix J
DERIVATION OF INPUT IP3 BASED ON VOLTERRA SERIES
Volterra Series approximates the output of a nonlinear system in a manner similar
to Taylor series approximation. For sufficiently small inputs, the output of a nonlinear
system can be described as the sum of the transfer functions below order three. The first
order transfer function
()1Hs is essentially the transfer function of the linearized circuit.
The 2
nd
and 3
rd
order transfer functions,
( )
12
2 ,Hss and
( )
123
3 ,,Hsss, can be solved in
increasing order by repeatedly solving the same linear circuit using different order
excitations.
875H875HFig. J.1 shows the small signal equivalent circuit for a MOS transistor excited by a
voltage source with source resistance
S
R and loaded with a resistance
L
R .
gs
C and
d
C
are the gatesource and drainbulk capacitance. The nonlinear current
ds
i is controlled
by gatesource and drainsource voltages, which can be approximately calculated as the
sum of a series containing powers of the control voltages. The
ds
i expression limited to
first, second, and thirdorder nonlinear behavior is
22
33 2 2
22
222
333 3
()
ds m gs o ds
ggg
m gs o ds m o gs ds
gg g g
m gs o ds m o gs ds m o gs ds
i g v g v first order linear
K v K v K v v second order
K v K v K v v K v v third order
=+
+++
+++ +
"""""""""""""""
"""""""
"
. (J.1)
APPENDIX
211
S
R
S
v
+

+

gs
v
gs
C
L
R
ds
i
d
C
+

ds
v
1 2
Fig. J.1 The small signal equivalent circuit used for IP3 analysis.
Applying Kircoff?s current law at node 1 and 2 in 876H876HFig. J.1 yield
1
2
1
0
1
1
0
gs
SS
S
mod
L
sC
VR
V
R
V
ggsC
R
??
+
? ?
??
??
? ?
=
??
? ?
??
++
? ?
? ?
??
(J.2)
The voltages above are Laplace transforms. Denoting ( ) 1/
LodL
Ys g sC R=+ + and
() 1/
SSgs
Ys R sC=+, 877H877H(J.2) can be rewritten as
()
()
1
2
1
0
0
S
S
S
mL
V
Ys V
R
gYsV
? ?
????
? ?
=
????
? ?
????
? ?
? ?
. (J.3)
The 2?2 matrix in the lefthand side is the admittance matrix of the circuit.
1
V ,
2
V and
S
V are Laplace transforms.
J.1 First order kernels
The first order kernels are calculated from the response of the linearized circuit to
external input
S
V . 878H878HFig. J.2 gives the linearized equivalent circuit. The voltage source is
converted to a current source, which is the only excitation of the circuit when
212
calculating the first order kernels.
1
V and
2
V reduce to the first order transfer functions
of the voltages at node 1 and 2 when
S
V is set to one. The transfer functions at node 1
and 2 are denoted as
()
1
1Hs and ( )
2
1Hs. The first subscript indicates the order of the
transfer functions, while the second subscript corresponds to the number of the node.
Hence the transfer functions can be solved from the matrix equation below,
()
()
()
()
1
2
1
1
1
0
0
S
S
mL
Ys H s
R
gYsHs
? ?
????
? ?
=
????
? ?
????
? ?
? ?
(J.4)
Solving 879H879H(J.4) gives the first order transfer functions at node 1 and 2 as
()
()
1
1
11
SS
Hs
YsR
= (J.5)
()
() ()
2
1
1
m
SL S
g
Hs
YsYsR
?
= (J.6)
S
R
+

gs
v
gs
C
L
R
d
C
+

ds
v
1 2
mgs ods
g v g v+
1
S
S
v
R
Fig. J.2 The linearized equivalent circuit for solving first order kernels.
J.2 Second order kernels
The second order kernels are calculated from the response of the linearized circuit
to the second order virtual nonlinear current source, 2NLi as shown in 880H880HFig. J.3. The
213
virtual excitation 2NLi is placed in parallel with the corresponding linearized element,
and is the only excitation applied to the circuit when calculating second order kernels.
The external excitation
S
V is grounded. Denoting the second order kernels at node 1
and 2 as
()
112
2 ,Hss and
( )
212
2 ,Hss, these transfer functions can be solved from the
matrix equation as
()
()
( )
()
12 112
12 212
2
2
2
0,
0
,
S
mL
NL
Ys s H ss
i
gYssHs
????
+
? ?
????
=
? ?
?
+ ? ?
????
. (J.7)
2NLi is determined by the second order coefficients in 881H881H(J.1) and the first order kernels of
their corresponding controlling voltages,
( ) ( )
() ()
() () () ()
11 12
21 22
11 22 21 12
221
21 1
211 1
1
2
g
m
g
o
gg
mo
NLi KHsHs
KHsHs
KHsHsHsHs
=
+
? ?
++
? ?
. (J.8)
Solving 882H882H(J.7) gives the second order kernels at node 1 and 2 as
( )
112
2 ,0Hss= (J.9)
()
()
212
12
2
2 ,
L
NLi
Hss
Ys s
?
=
+
(J.10)
S
R
+

gs
v
gs
C
L
R
d
C
+

ds
v
1 2
mgs ods
gv gv+
2NLi
Fig. J.3 The equivalent circuit for solving the second order kernels.
214
J.3 Third order kernels
Similarly, the third order kernels are calculated using the equivalent circuit shown
in 883H883HFig. J.4. 3NLi is the third order virtual nonlinear current source. Denoting the third
order kernels at node 1 and 2 as
( )
1123
3 ,,Hsss and
( )
2123
3 ,,Hsss, these transfer
functions can be solved from
()
()
( )
()
123 1123
123 2123
3
3
3
0,,
0
,,
S
mL
NL
Ys s s H sss
i
gYsssHss
????
++
??
????
=
??
?
++ ??
????
(J.11)
3NLi is determined by the third order coefficients in 884H884H(J.1) and the first and second
order kernels of their corresponding controlling voltages,
() () ( )
() ( ) () ( ) () ( )
() () ()
() ( ) () ( ) () ( )
() ( ) () ( ) () ( )
11 12 13
11 123 12 113 13 112
21 22 23
21 223 22 213 23 212
11 223 1 2 213 13 212
33111
2121212
3111
2 21 2
12 12 2
2
2
,,,
3
2
,,,
3
1
3
g
m
g
m
g
o
g
o
gg
mo
NLi KHsHsHs
K H sH ss H sH ss H sH ss
KHsHsHs
K H sH ss H sH ss H sH ss
HsH ss HsH ss HsH ss
K
H
=
??
+++
??
+
+++
++
+
+
() ( ) () ( ) () ( )
() () ()
() () ()
() () ()
() () ()
() () ()
() () ()
21 1 23 22 113 23 112
11 12 23
2
11 13 22
12 13 21
11 22 23
2
12 21 23
13 21 22
12 12 12
111
3 111
111
1
3111
111
,,,
1
3
1
3
gg
mo
gg
mo
sH ss H sH ss H sH ss
HsHsHs
K H sH sH s
HsHsHs
HsHsHs
KHsHsHs
HsHsHs
??
??
??
++
+
??
??
??
++
+
??
(J.12)
Solving 885H885H(J.11) gives the thirdorder kernels at node 1 and 2 as
215
( )
112
3 ,0Hss= (J.13)
()
()
2123
123
3
3 ,,
L
NLi
H sss
Ysss
?
=
++
(J.14)
S
R
+

gs
v
gs
C
L
R
d
C
+

ds
v
1 2
mgs ods
gv gv+
3NLi
Fig. J.4 The equivalent circuit for solving the third order kernels
J.4 Input IP3
For a nonlinear system described using Volterra kernels, the amplitude of the
fundamental output product is
( )
21
1VH j? (or
( )
22
1VH j? ), and the amplitude of
the 3
rd
order intermodulation product is
()
3
211 2
3
3
,,
4
VH j j j? ??? (or
()
3
2122
3
3
,,
4
VH j j j? ??? ), where V is the amplitude of the twotone input signal at
S
v . Then, the input IP3 (IIP3) is calculated as
( )
()
21
211 2
1
3
1
3
6 ,,
S
Hj
IIP
R Hjj j
?
? ??
=
?
(J.15)
where
216
()
()()
21
11
1
1
m
SSL
g
Hj
RYj Yj
?
??
?
= (J.16)
()
()
211 2
12
3
3 ,,
2
L
NLi
Hjj j
Yj j
?? ?
? ?
?
?=
?
(J.17)
Substituting 886H886H(J.16) and 887H887H(J.17) into 888H888H(J.15), we have
()
1
3
1/1
3
6
Sm
S S
NL
R g
IIP
RiYj?
= , (J.18)
since
()()
12 1
2
LL
Yj j Yj? ???? for
21 1
? ?? ??= ? .
Denoting
11
sj?= ,
21
sj?= , and
32
sj?=? 3NLi can be solved from 889H889H(J.4)890H890H(J.12).
The complete IIP3 expression for 891H891H(J.18) is
2
3
1234
1( )
1
3
6
gs s
g
s
m
m
CR
IIP
R K
g
?+
=
+?+?+?+?
. (J.19)
where
()
2
2
23
112
33
g
m
gg gg
mo mo
m
K
KZKZ
g
?=? ? ,
() ()
2
2
22 3 2
23 4 5
21 1
33 3
gg gg gg
mo mom mo
KKZ K gZ K Z?= + + ,
2
322
36 7
1
3
gggg
om mo om
KgZ K KgZ?=? ? ,
()
2
2
2
48
2
3
g
om
KgZ?= .
The impedance elements (Zelements) above are calculated as
217
() ( )
11 12
22
LL
ZZ Z? ??=+?,
1
21 21
() ( ) ()2
LS S
ZZ Y Y???
?
??=?+
??
,
3121 12
2( )() (2)( )
LLLL
ZZ Z Z Z? ?? ? ?=? + ?,
21
41 21
()2( ) ()1
LSS
ZZ Y Y???
?
??=?+
??
()()( ) ( )
5122 11
22
LLLL
ZZ Z Z Z? ?? ??=??+ ,
2
612
() ( )
LL
ZZ Z? ?=?
()
2
711 121 1212
() (2)2 () () (2)6 () ()
LL LL L LL L
ZZ Z Z Z Z Z Z Z? ????????=+ + ?,
( )
2
71 1 1 12
( ) (2 ) 2 (2 ) 6
LL L L
ZZ Z Z Z?? ? ????=++?
??
,
() ( )
2
812 1 12
() ( ) 2 2
LL L L
ZZ Z Z Z?? ? ????=? +?
??
,
with ()
1
Lod
L
Yj g jC
R
? ?=++ ,
1
()
()
L
L
Z
Yj
?
?
= , and
1
()
Sgs
S
Yj jC
R
??=+ .