A Low Power, Low Noise Phase Locked Loop MMIC for Ku and X Band
Applications
Except where reference is made to the work of others, the work described in this thesis is
my own or was done in collaboration with my advisory committee. This thesis does not
include proprietary or classi ed information.
Mark E. Ray
Certi cate of Approval:
Stuart Wentworth
Associate Professor
Electrical and Computer Engineering
Fa Dai, Chair
Professor
Electrical and Computer Engineering
Robert Dean
Assistant Professor
Electrical and Computer Engineering
Mark Nelms
Department Head
Electrical and Computer Engineering
George T. Flowers
Dean
Graduate School
A Low Power, Low Noise Phase Locked Loop MMIC for Ku and X Band
Applications
Mark E. Ray
A Thesis
Submitted to
the Graduate Faculty of
Auburn University
in Partial Ful llment of the
Requirements for the
Degree of
Master of Science
Auburn, Alabama
May 9, 2009
A Low Power, Low Noise Phase Locked Loop MMIC for Ku and X Band
Applications
Mark E. Ray
Permission is granted to Auburn University to make copies of this thesis at its
discretion, upon the request of individuals or institutions and at
their expense. The author reserves all publication rights.
Signature of Author
Date of Graduation
iii
Vita
Mark Edward Ray, son of Roger and Lois (Battles) Ray, was born February 12, 1985, in
Birmingham, Alabama. He graduated from Trinity Christian Academy, Oxford, Alabama,
as co-Valedictorian in 2003. During his Junior and Senior years, he attended Gadsden State
Community College in Gadsden, Alabama, becoming the rst dual-enrollment student at
Trinity Christian Academy. He entered Auburn University as a Sophomore in August, 2003,
and he entered the co-operative education program in May, 2004. Mr. Ray worked for the
U.S. Army Space and Missile Defense Command on alternating semesters and graduated
cum laude with a Bachelor of Electrical Engineering in December, 2007. He entered Grad-
uate School, Auburn University, in January, 2008. He is a Research Assistant for Dr. F.
Dai in the eld of Integrated Circuit (IC) design. He is married to Christina (Pizano) Ray
and has a daughter Kaylee and son Andrew.
iv
Thesis Abstract
A Low Power, Low Noise Phase Locked Loop MMIC for Ku and X Band
Applications
Mark E. Ray
Master of Science, May 9, 2009
(B.S., Auburn University, 2007)
94 Typed Pages
Directed by Fa Dai
This paper presents the analysis, design, simulation, and test results for a Fractional N
PLL frequency synthesizer. The synthesizer is designed to cover multiple frequency bands,
require low power, and have low noise. Detailed analysis is presented on loop dynamics,
stability, and noise. All components in the circuit are designed for low noise and low power.
For example, The Multi Modulus Divider (MMD) is implemented such that it has the
minimum number of gates and the lowest power consumption. The division ratios can
be programmed from 128 to 159 and consumes 11mA under a 2.2V power supply, which
corresponds to 59.2% power reduction compared to the prior art.
v
Acknowledgments
The author would like to thank Dr. Dai for his longsu ering attitude and teacher?s
heart during this student?s learning process. In particular, I would like to thank William
Souder for his design of the VCO, Printed Circuit Board, and immense help in all other facets
of the design. The author would like to acknowledge Xueyang Geng, Desheng Ma, Yuan
Yao, Xuefeng Yu, Zhenqi Chen, Jianjun Yu, and Joseph Cali for their help with the design
and testing. I would like to thank Eric Adler, Geo rey Goldman at U.S. Army Research
Laboratory and Pete Kirkland, Rodney Robertson at U.S. Army Space and Missile Defense
Command for funding this project, Nat Albritton, Bill Fieselman at Amtec Corporation for
business management, and Perry Tapp, Ken Gagnon at Kansas City Plant for fabrication
support.
The author would like to thank his wife, Christina, and children for their patience
and sacri ce during this time. The author would like to thank his parents, Roger and
Lois Ray, who encouraged and facilitated this achievement. A special thanks to Floyd and
Kay Battles, Gaines and Barbara Ray, Robbin and Billy Dunn, Randy Barnett, and Keith
Adams for their encouragement and support.
vi
Style manual or journal used Journal of Approximation Theory (together with the style
known as \aums"). Bibliograpy follows van Leunen?s A Handbook for Scholars.
Computer software used The document preparation package TEX (speci cally LATEX)
together with the departmental style- le aums.sty.
vii
Table of Contents
List of Figures xi
List of Tables xiv
1 Introduction 1
1.1 Purpose Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Technology Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2.1 SiGe HBTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2.2 CMOS Logic and Bipolar Current Mode Logic . . . . . . . . . . . . 3
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 PLL System Analysis 5
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Continuous Time Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Discrete Time Analysis for PLL . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Transient Behavior of PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4.1 Linear Transient Behavior . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4.2 Example: Settling Time of Synthesizer . . . . . . . . . . . . . . . . . 11
2.4.3 Example: Design of Integer-N Synthesizer for Speci ed Settling Time 12
2.4.4 Nonlinear Transient Behavior . . . . . . . . . . . . . . . . . . . . . . 13
2.4.5 Example: Estimation of Loop Settling Times . . . . . . . . . . . . . 15
2.5 Stability Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.1 Gain and Phase Margin . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6 Phase Noise in PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6.1 Noise Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6.2 In Band vs. Out of Band Noise . . . . . . . . . . . . . . . . . . . . 19
2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Phase Frequency Detector 22
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Tristate PFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 PFD Dead Zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4 Charge Pump 26
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 Circuit Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2.1 Saturation Voltage of MOS Transistors . . . . . . . . . . . . . . . . . 26
viii
4.2.2 Current Source Matching . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2.3 Reference Feedthrough . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2.4 Current Source Matching . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3 Di erential Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4 Tunable Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5 Loop Filter 31
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 Passive Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3 Dual Path Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4 Simpli cation of Dual Path Loop Filter Structure . . . . . . . . . . . . . . . 35
5.5 Tunable Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6 Voltage Controlled Oscillator 38
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2 Negative Gm Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7 Divider Circuit Design 42
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2 Design Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.3 Divider Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.3.1 Dual Modulus Prescaler with Pulse Swallow Counter . . . . . . . . . 43
7.3.2 Vaucher?s Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.3.3 Designing P/P+1 Cells . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.3.4 Multi Modulus Divider . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.4 Generic MMD Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.4.1 Example: Design MMD for X-band Radar . . . . . . . . . . . . . . . 51
7.4.2 Design Simulation of MMD in Cadence . . . . . . . . . . . . . . . . 52
7.5 Minimizing Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8 Modulation 56
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.2 Sampling and Quantization Noise . . . . . . . . . . . . . . . . . . . . . . . . 56
8.3 Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.4 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.4.1 First Order Modulators . . . . . . . . . . . . . . . . . . . . . . 58
8.4.2 Second Order Modulators . . . . . . . . . . . . . . . . . . . . . 59
8.5 Modulation for Fractional N PLL . . . . . . . . . . . . . . . . . . . . . 59
8.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ix
9 Circuit Designs for Low Voltage Applications 61
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.2 Large Signal Behavior of Bipolar Di erential Pairs . . . . . . . . . . . . . . 61
9.3 CML D Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.4 CML AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.5 Bu er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.6 Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10 Fabricated Design 67
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10.2 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10.3 Multi Modulus Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.4 Voltage Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
11 Conclusions 72
Bibliography 73
Appendices 76
A Matlab M Files 77
A.1 PLL Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
A.2 PLL Step Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
A.3 Root Locus Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
x
List of Figures
2.1 Complete loop in the frequency domain . . . . . . . . . . . . . . . . . . . . 5
2.2 2nd Order PLL frequency response for di erent values of . . . . . . . . . . 7
2.3 Discrete time equivalent of PLL . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 2nd Order PLL step response for di erent values of . . . . . . . . . . . . . 11
2.5 PFD simulation signals from top to bottom are: Reference, Divider, UP,
DOWN, Charge Pump Output . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 Root locus analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7 Root locus analysis (Expanded View) . . . . . . . . . . . . . . . . . . . . . 17
2.8 Gain and Phase Margins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 Tristate PFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Modi ed folded D Latch with Reset . . . . . . . . . . . . . . . . . . . . . . 23
3.3 PFD simulation signals from top to bottom are: Reference, Divider, UP,
DOWN, Charge Pump Output . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 Di erential BiCMOS Charge Pump . . . . . . . . . . . . . . . . . . . . . . . 28
4.2 Tunable current source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1 2nd order loop lter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2 2nd order loop lter transfer function simulated with Matlab . . . . . . . . . 33
5.3 2nd order loop lter transfer function simulated with Cadence . . . . . . . . 33
5.4 Dual path loop lter circuit diagram . . . . . . . . . . . . . . . . . . . . . . 34
5.5 Dual path loop lter compared to traditional 2nd order loop lter . . . . . . 35
5.6 Proposed tunable loop lter . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
xi
5.7 Tunable current source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.8 Proposed tunable loop lter . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1 AC model of negative gm oscillator analysis . . . . . . . . . . . . . . . . . . 39
6.2 Negative gm oscillator with varactor tuning . . . . . . . . . . . . . . . . . . 39
6.3 Simulated KVCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.4 Simulated VCO phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.1 Pulse Swallow Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2 Divider with all Two/Three Cells . . . . . . . . . . . . . . . . . . . . . . . . 45
7.3 Two/Three Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.4 Divide by Two . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.5 Divide by Two/Three with signals from top to bottom: Fin;Fout;Modin;P 47
7.6 Divide by 8/9 Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.7 Cadence Simulation of 8/9 Cell . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.8 Generic Architecture for Multi Modulus Divider . . . . . . . . . . . . . . . 51
7.9 Multi Modulus Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.10 MMD Output for the Divide by 128 Case with fin = 13:84GHz . . . . . . . 53
7.11 MMD Output for the Divide by 159 Case with fin = 13:84GHz . . . . . . . 53
7.12 MMD Modulus Outputs and 50% Duty Cycle Output for the Divide by 159
Case with fin = 13:84GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.13 Multi Modulus Divider Designed for Minimum Current . . . . . . . . . . . 54
8.1 Feedback model of noise shaping system . . . . . . . . . . . . . . . . . . . 57
8.2 1stOrder Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
8.3 2ndOrder Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.1 CML D Latch for Low Voltage Applications . . . . . . . . . . . . . . . . . 63
9.2 CML D Latch with a Single Current Tail . . . . . . . . . . . . . . . . . . . 63
xii
9.3 CML AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.4 CML Bu er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.5 CML Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
10.1 PLL RFIC implemented in 0:13 technology . . . . . . . . . . . . . . . . . 67
10.2 Printed circuit board developed for PLL testing . . . . . . . . . . . . . . . . 68
10.3 Test Setup for PLL Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.4 MMD output of 86MHz with input frequency of 11GHz . . . . . . . . . . . 69
10.5 Simulated KVCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.6 Measured KVCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
xiii
List of Tables
1.1 Technology Comparison[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
7.1 Comparison of Previous MMD Architectures . . . . . . . . . . . . . . . . . 55
10.1 Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
xiv
Chapter 1
Introduction
1.1 Purpose Statement
The purpose of this thesis is to develop a frequency synthesizer that addresses the
need for exibility to be able to operate in multiple frequency bands. This is accomplished
through fractional N synthesizer design with a Multi Modulus Divider. The PLL Fre-
quency synthesizer design can synthesize channels in Ku and X bands. The designer
seeks to minimize noise through methodical analysis of noise sources and careful design of
circuits. For further reduction in noise a modulator can be employed.
The trend for wireless transceivers is to o er the ability to operate in di erent frequency
bands. To be competitive, a frequency synthesizer must exhibit low noise and be able to
synthesize channels in multiple frequency bands. This means that there must be an emphasis
on divider design. Another challenge in frequency synthesizer design is the demand for fast
switching and high operating frequency. These demands push the limits of the current
technology.
This design of a fractional N frequency synthesizer seeks to obtain the capability of
synthesizing channels in multiple frequency bands. For the purpose of a single chip system,
the designer must seek to cut power consumption. All circuits presented here are designed
for low power applications.
1.2 Technology Overview
1.2.1 SiGe HBTs
There are many bene ts to SiGe over Silicon, GaAs and other technologies. Utiliz-
ing a process where Heterojunction Bipolar Transistors (HBT)s and Complimentary MOS
1
Parameter CMOS Si BJT SiGe BJT
fT High High High
fMAX High High High
Linearity Best Good Better
Vbe (or VT)tracking Poor Good Good
1/f noise Poor Good Good
Broadband noise Poor Good Good
Early Voltage Poor OK Good
Transconductance Poor Good Good
Table 1.1: Technology Comparison[1]
Transistors can be combined gives the designer the opportunity to exploit the best of both
worlds. SiGe provides just such an opportunity. Heterojunction bipolar transistors have
lower current consumption and better high frequency performance than traditional homo-
juntion bipolar transistors because they have higher forward gain and lower reverse gain[1].
Table 1.1 shows how the di erent technologies compare.
Frequency synthesizers are a prime example of mixed signal circuits. The charge pump,
VCO, and loop lter are analog circuits, while the divider and phase detector are usually
digital blocks. HBT technology has several features that are good for frequency synthesizer
application, which needs both digital and analog circuits [2]. For digital applications, fT
must be at least twice the highest ip- op toggling rate [3]. fT higher than 210 GHz
has been obtained for HBT technology. The high transconductance of the HBT allows a
digital circuit to respond to small signal swings, and to drive large output capacitances
in short times. For analog circuit applications, high power gain is required in addition
to high fT . An HBT has low base resistance and low extrinsic base-collector capacitance;
fMAX as high as 285 GHz has been observed for HBTs in current technologies. An HBT is a
vertical structure device that has much lower l/f noise than a MESFET. 1/f noise is a heavy
contributor to phase noise. In turn, the phase noise of the VCO is the key characteristic
for frequency synthesizer application.
2
1.2.2 CMOS Logic and Bipolar Current Mode Logic
HBT technology discussed in the previous section lends itself easily to Current Mode
Logic (CML) circuits. CMOS circuits dissipate energy during switching, thus for low fre-
quency operation it is intuitive that CMOS would have lower power consumption. Con-
versely, for high frequency operation such as the frequency of the synthesizer, CMOS has
high power consumption. The advantage of Bipolar CML over CMOS is in high frequency
operation. CML, which has high current consumption at low frequency, has a more shallow
increase in current versus frequency than does CMOS.
Bipolar CML also has better noise performance and power supply rejection than
rail to rail CMOS. CML is inherently di erential allowing for common mode noise to be
rejected. CML has a very small signal swing compared to CMOS which swings rail to rail
introducing power supply noise. Dc current is constant in CML, making switching noise
smaller. With the ability to operate at much higher maximum speed and lower power
dissipation, CML is the clear choice for high speed synthesizer design.
1.3 Thesis Organization
The body of this document is divided into ten chapters. The rst chapter gives a
summary of the current technology. The bene ts of SiGe over Si and GaAs are discussed.
In this chapter the question of why CML is used instead of high speed CMOS logic is
answered.
Next, the PLL system level analysis is performed. Continuous time and discrete time
models are derived and expressions are evaluated for system parameters. The di erent
behaviors of acquisition mode and phase lock mode are analyzed. PLL component values
are determined through speci c example. Other analyses performed include: stability, noise,
step response and frequency response.
The next chapters cover the design of the PFD, charge pump, loop lter, and VCO.
Included in these chapters is an interesting possibility for a future design to make the loop
3
lter programmable. A brief analysis of the gm oscillator is performed and KVCO and
phase noise are simulated.
A more in depth chapter covers the design of the divider. Di erent architectures are
compared and the analysis is performed to minimize the number of cells for a MMD. The
MMD current is reduced further by reducing the current at each stage at the expense of
modularity (but not area). The noise in the loop is further reduced if a modulator is
added to toggle the MMD bits.
Chapter 9 delves into the circuits designed for low voltage applications. Chapter 10
covers the testing and measurement results of the PLL frequency synthesizer.
4
Chapter 2
PLL System Analysis
2.1 Introduction
To understand the performance of the Phase Locked Loop frequency synthesizer it is
necessary to look at the loop from a control system perspective1. In normal operation,
the PLL is a Linear Time Invariant System, but in acquisition it must be treated as a
nonlinear system. In sections 2.2 2.5 in depth analysis is performed to determine the
loop transfer function, frequency and step response, loop lter component values, damping
constant, natural frequency, stability and phase margin. In section 2.6, the noise sources in
individual blocks are modeled.
2.2 Continuous Time Analysis
Figure 2.1: Complete loop in the frequency domain
1PLL system analysis has been outlined in several texts [4], [18]. Except where stated, the author follows
the analysis performed in [4]. Examples make use of the author?s speci c design requirements and gures
are generated by the author with code listed in Appendix A.
5
In general, the PLL is broken down in the s domain in the following way. In the
frequency domain the complete loop is shown in Figure 2.1. The simpli ed loop equation is
o
R =
AoKphaseF(s)
N
Kvco
s
1 + AoKphaseF(s)N Kvcos
= KF (s)s+KF (s) (2.1)
For a second order PLL (1st order loop filter) the transfer function becomes
o
R =
IKvco
2 NC1 (RC1s+ 1)
s2 + IKvco2 N Rs+ IKvco2 NC1 (2.2)
From control theory, the purpose of R can be seen. If R were not included then the
poles of the equation would sit on the j! axis and the loop would become unstable. From
Equation 2.2 several key expressions for loop dynamics can be determined. The natural
frequency is given by
!n =
s
IKvco
2 NC1 (2.3)
The damping constant is
= R2
s
IKvcoC1
2 N (2.4)
Usually, natural frequency and damping constant are chosen for desired loop perfor-
mance. If natural frequency and damping constant are speci ed then the equations can be
rearranged to solve for R and C1.
C1 = IKvco2 N!2
n
(2.5)
R = 2
s
2 N
IKvcoC1 (2.6)
The PLL frequency response for di ering values of is shown in Figure 2.2. We can
see that the 3 dB bandwidth is dependent on and the equation is provided here
!3dB = !n
r
1 + 2 2 +
q
4 4 + 4 2 + 2 (2.7)
6
It will be shown later that we should choose greater than 1.5. Therefore, the band-
width can be approximated as
!3dB 2 !n (2.8)
Figure 2.2: 2nd Order PLL frequency response for di erent values of
For the 3rd order loop that includes a second capacitor (C2) a high frequency pole is
added. The function of this pole is to further reduce high frequency ripple on the control
line. The value of C2 is usually chosen to be 1=10 of C1. For the 3rd order loop the transfer
function becomes
o
R =
KvcoKphase (1 +sC1R)
s2N (C1 +C2) (1 +sCsR) +KvcoKphase (1 +sC1R) (2.9)
7
2.3 Discrete Time Analysis for PLL
Figure 2.3: Discrete time equivalent of PLL
If the loop bandwidth is a signi cant fraction of the reference frequency the previous
approach becomes inaccurate. Therefore we treat it as a discrete time control system. In
this case we treat the PFD as a sampling element. The loop lter performs a hold function.
We now have a sampled system and can convert from the s domain to the z domain. The
discrete time equivalent of the PLL system is shown in Figure 2.3. The factored open loop
transfer function is shown here without derivation.
GOL (z) = k
"
z
(z 1)2
#
(2.10)
where the open-loop zero is dependent on the reference frequency and is given by
= 4 !nT4 +!
nT
(2.11)
and the open loop gain is
K = !
2nT2
2
1 + 4 !
nT
(2.12)
Some important equations for the purpose of root locus analysis will be given here and
the concepts will be illustrated in a speci c example in a later section. The poles of 2.12
8
are given by
Poles = 1 k2 + 12
q
(k 2)2 4 (1 K) (2.13)
The large positive pole will never leave the unit circle, but we need to determine the point
of instability that occurs when
1 K2 12
q
(K 2)2 4 (1 K) = 1 (2.14)
or when
K (1 + ) = 4 (2.15)
This leads to the critical period TUS where the loop goes unstable.
TUS = 1!
n
= 2 !
ref crt
(2.16)
where !ref crt is the reference frequency at which the loop goes unstable. !ref crt can be
determined by rearranging Equation 2.16.
!ref crt = 2 !n (2.17)
Therefore,
!ref
!n 2 (2.18)
So, if we choose = :707 the ratio of reference to natural frequency must be greater
than 4.4. Therefore, for a reference frequency of 40 MHz, if the loop natural frequency is
set any higher than 9.1 MHz, the loop will go unstable. A rule of thumb is to make the
reference frequency to natural frequency ratio about 10:1[6], [26].
9
2.4 Transient Behavior of PLLs
The analyses of the previous two sections do not determine what happens before the
loop starts to track the phase of the input. If the phase error exceeds 2 then the loop will
experience what is known as cycle slipping. In extreme cases if the VCO is forced beyond
its linear range of operation the loop may lose lock inde nitely.
2.4.1 Linear Transient Behavior
For transient analysis, we desire to nd the phase error. The transer function of phase
error for a 3rd order PLL is derived as follows:
e
R =
s2
s2 + 2 !ns+!2n (2.19)
Normally, for transient analysis we desire to apply a frequency step !. To nd phase error
we take the phase equivalent of a frequency step. The phase equivalent of a frequency step
is a phase ramp. So the input signal is described by
R = !s2 (2.20)
This phase ramp multiplied with the transfer function in Equation 2.19 results in
e = !s2 + 2 !
ns+!2n
(2.21)
Taking the inverse Laplace transform yields the following results
e (t) = !!
n
"
sinh!np 2 1tp
1 2
#
; > 1 (2.22)
e (t) = !!
n
!nt e !nt; = 1 (2.23)
e (t) = !!
n
"
sin!np1 2tp
1 2
#
; < 1 (2.24)
10
From Figure 2.4 it is seen that a damping constant of 0.707 to 1 yields the fastest settling
time. Settling time corresponds to how fast the phase error settles to zero. From Figure
2.4 it is seen that the settling is better than 99% complete when !nt = 7 for = 0:707.
Figure 2.4: 2nd Order PLL step response for di erent values of
2.4.2 Example: Settling Time of Synthesizer
The 2nd order PLL synthesizer designed with a charge pump, PFD, and loop lter
as discussed earlier in this chapter is assumed here. It is assumed that the loop lter is
designed to have a damping constant = 0:707 and a bandwidth of 110 kHz. What is the
maximum frequency step that the synthesizer can handle?
11
Solution: First, compute the natural frequency of the loop from 2.7:
!n !3dB
1 + p2
= 2 110kHz2 = 2 55kHz (2.25)
From Figure 2.4, the maximum phase error from a frequency step is about 0.46 for = 0:707.
So, the maximum phase error is
e max = 0:46 !!
n
(2.26)
With the tristate phase detector the maximum phase error that can be handled is 2 . This
means that the largest frequency step that the system can handle is
!max = 4:72Mrad=sec)751:25kHz (2.27)
For a frequency step > !max then cycle slip occurs. Knowing that the step response
settles to within 99% of its value at !nt = 7. So the transient settles in about t = 20:25 s.
2.4.3 Example: Design of Integer-N Synthesizer for Speci ed Settling Time
Design an integer-N synthesizer to operate from 11.5 14.31 GHz (13.84 GHz is the
operating frequency of the PLL frequency synthesizer). The synthesizer must be able to
settle from a frequency step in 200 s. The channel spacing and the the reference frequency
are 40 MHz. Assume that the damping constant = 0:707 and !nt = 7. Therefore, !n =
35krad=s)5:57kHz. The bandwidth is calculated as BW = (1 + p2)!n = 11:139kHz.
To continue this analysis we must nd the loop gain K, and the divider ratio (N). If
the reference frequency is 40MHz, then the divider ratio (N) must be from 256 to 318. The
VCO tuning range is 223.2MHz. To allow for 10% process variation we will extend the
tuning range to 250MHz. Assuming a 2V supply, Kvco becomes 250MHz/V.
Charge pump current I, and loop lter component values C1 and R can now be cal-
culated. The ratio of loop lter capacitance and charge pump current can be calculated
12
rst.
C1
I =
Kvco
2 !2n =
2 250MHz
2 256 352 [krad=s]2 = 4:4 10
3 (2.28)
Choosing C1 = 5nF yields charge pump current I = 11:33 A. The loop lter resistance can
now be calculated.
R = 2
s
2 N
IKvcoC1 = 19k (2.29)
2.4.4 Nonlinear Transient Behavior
As discussed in the previous section, for large frequency step inputs the linear transient
behavior model does not apply. We must use the nonlinear model. We know that any
frequency step will generate some nonzero phase error. If the loop experiences a transient
frequency step, how long does it take the loop to reacquire lock? The output of the PFD
will look like the simulation in gure 2.5 and the charge pump will output current pulses.
These current pulses vary between close to zero and the reference period. Then the average
current produced by the charge pump is I/2. We assume that the current ows onto the
capacitor C1 and the change in voltage across the capacitor as a function of time is
vC
t =
I
2C1 (2.30)
Therefore, the settling time will be
Ts = 2 vCC1I (2.31)
Using the relationship !vco = Kvcovc the settling time as a function of input frequency
change ! is written as
Ts = 2C1 !NIK
vco
= ! !2
n
(2.32)
For 3rd order loop the capacitor C2 can be included. The function of C2 is to further
lter the high frequency ripple caused by the turning on and o of the control current. For
this reason C2 tends to smooth ripple on control voltage.
13
Figure 2.5: PFD simulation signals from top to bottom are: Reference, Divider, UP, DOWN,
Charge Pump Output
14
2.4.5 Example: Estimation of Loop Settling Times
Using the same PLL synthesizer from the previous example, estimate settling time
for output frequency steps of 50MHz and 500MHz. This results in reference frequencies
of 224kHz and 2.24MHz respectively. The loop from the previous example has a loop
bandwidth of 110kHz and a charge pump current of 11.33 A.
We learned previously that the maximum step that the system can handle is 750kHz.
Since the rst frequency step is smaller than this value the frequency step will be a linear
one and easily handled. From !nt = 7 and for a !n = 2 55kHz the loop will settle in
20.25 s.
For the frequency step of 500MHz, we must include cycle slipping. The acquisition
time is estimated using Equation 2.32 to be 3.75 s. Therefore, the complete settling time
for the loop is 3.75 s for frequency acquisition + 20.25 s for phase lock.
In reality the loop should settle somewhat faster than this. The loop starts phase lock
just before frequency acquisition is nished.
2.5 Stability Analysis
A root locus analysis is performed to determine when the system is stable. For a z
domain analysis, the root locus is stable if the poles are inside the unit circle. From the
root locus analysis we can determine at what frequency the loop becomes unstable.
For this analysis we choose = 0:707, and a reference period of 1/40MHz. Using the
open loop transfer function in Equation 2.12 for !n = 55kHz the open loop zero is:
= 4 !nT4 +!
nT
= 0:9939 (2.33)
and the open loop gain is
K = !
2nT2
2
1 + 4 !
nT
= 0:0123 (2.34)
15
Using the code in Appendix A.3 the root locus plot is generated. From Figure 2.6 we
see that the system is stable to 2:51 108rad/s or 15.7GHz.
Figure 2.6: Root locus analysis
In an expanded view in Figure 2.7, the analysis is con rmed. one pole will pair with
the zero and the other will tend to 1 as the frequency is increased.
2.5.1 Gain and Phase Margin
Another measure of stability for a control system are the gain and phase margins. Gain
margin is de ned as the di erence in dB between unity gain and the gain at the point where
the phase is 180 degrees. Phase margin is de ned as the di erence between the phase at
unity gain and 180 degrees. The target phase margin of 60 degrees is usually accepted as
a tradeo between loop stability and settling time[8]. Gain margin is the minimum gain for
16
Figure 2.7: Root locus analysis (Expanded View)
17
the loop to remain stable. Figure 2.8 shows the gain and phase margins for the 2nd order
phase locked loop frequency synthesizer with component values from the previous example.
Figure 2.8: Gain and Phase Margins
2.6 Phase Noise in PLL
A major e ort in synthesizer design is mitigating noise. It has been stated previously
that phase noise of the VCO is the most important speci cation for the PLL. Noise sources
for the loop include thermal noise, transistor noise, timing jitter from the divider and phase
detector and reference feedthrough in the charge pump. The noise is further subdivided
into in band and out of band noise. This section introduces the noise sources, classi es
them as in band or out of band noise, and explains how to minimize their impact.
2.6.1 Noise Sources
The rst noise source to consider is thermal noise or white noise [19]. Thermal noise
is caused by thermal energy causing electron motion in random directions. The noise in a
18
resistor is
v2n = 4kTR (2.35)
where T is temperature in degrees Kelvin, k is Boltzmann?s constant and R is the value
of the resistor.
Shot noise is another white noise source. Shot noise describes the noise of charge
carriers when they pass through a barrier like the pn junction. Shot noise from Equation
2.36 is proportional to the current owing through the junction.
in shot = p2qI (2.36)
Flicker noise or 1/f noise is a noise source that is dominant in band. The power
spectral density of 1/f noise is inversely proportional to frequency[5]. Flicker noise is more
of a factor in MOS transistors than in BJTs. It is seen that 1/f noise for the MOS transistor
is modeled as a noise voltage and is inversely proportional to area.
v2nf = KfWLC
OXf
(2.37)
where is a process constant and ranges from 2 3. For the BJT it is modeled as a noise
current injected at the base.
For a more complete explanation of noise sources see [5]
2.6.2 In Band vs. Out of Band Noise
All of the noise generated by the PFD, charge pump, divider, and loop lter are consid-
ered in band noise sources. These noise sources are referred to the input. When the noise
source frequency is less than the loop bandwidth, the crystal, divider and charge pump
dominate the noise[18]. The charge pump being the main culprit for phase noise.
The total Power Spectral Density (PSD) of the crystal oscillator is found by using Lee-
son?s equation[10]. PSD is in units of [rad2/Hz] or more commonly converted to [dBc/Hz].
19
Since the Q is very high for crystal oscillators, it only a ects the very close in phase noise.
?2XTAL ( !) = 10 16
+ 1
"
1 +
!
0
2 ! QL
2#
1 + !c !
(2.38)
The divider can be considered to be composed of digital switching circuits that are
susceptible to timing jitter. Timing jitter occurs when spurious signals, thermal noise, or
1/f noise distort the rising or falling edges of the clock. The divider phase noise is modeled
by[12]
?2Div Added ( !) = 10
14+ 1 + 10 27+ 1!2do
2 ! + 10
16+ 1 + 10 22
+ 1
!do
2 (2.39)
Phase detectors generate 1/f and thermal noise. The dead zone of the PFD must also
be minimized because it contributes to the close in phase noise. The dead zone is discussed
in Chapter 3.
?2PD ( !) = 2 10
14+ 1
! + 10
16+ 1 (2.40)
Charge pump noise is generated from mismatch in transistors. Careful matching of
the NMOS and PMOS transistors alleviates much of the problem with charge pump noise.
This subject is handled more in depth in Chapter 4.
For the 2nd order passive loop lter, the only noise source is the thermal noise of the
resistor. The noise current in the lter is modeled by the transfer function in Equation 2.41.
From the transfer function we see that the noise current has a high pass characteristic.
in LPF = 1R vnss+ C1+C2
C1C2R
1R vnss+ 1
C2R
(2.41)
All of the noise sources to this point have a ected the in band phase noise. Conversely,
the noise from the VCO is referred to the output. It can be shown that the noise for the
VCO has a high pass characteristic. Therefore, for frequencies outside the loop bandwidth,
the VCO is the dominant factor.
20
VCO phase noise is described by [9] as:
?2VCO ( !) = C !2 +D (2.42)
where ! is the o set frequency from the carrier and C and D are constants of proportion-
ality.
2.7 Conclusion
Analysis has been performed to determine loop characteristics during phase lock and
acquisition mode. Stability analysis shows that for the given loop dynamics the system is
stable to > 15GHz. Phase noise can be mitigated by following good circuit design practices.
21
Chapter 3
Phase Frequency Detector
3.1 Introduction
In general, the Phase Frequency Detector (PFD) is implemented as a digital block. The
simplest implementation of a PFD is the XOR gate. Next in complexity is the tristate PFD.
More complex phase detectors include the ve state PFD and the Hogge phase detector and
variations of these. This chapter will deal exclusively with the tristate phase detector which
is implemented in the fabricated design.
3.2 Tristate PFD
The tristate PFD can be implemented using well known digital blocks. Figure 3.1
shows the tristate PFD implemented with two D Latches and an AND gate. The divider
output and the reference signal are fed into the clock inputs of the two latches respectively.
The D input is tied to to the VDD line in each latch. In the fabricated design the D Latch
has been modi ed to eliminate the need to tie the D input to VDD and is shown in Figure
3.2.
The PFD operation will be explored next. On the rising edge of either latch the output
goes high corresponding to the divider output or the reference signal. When the other latch
output goes high the AND gate produces a pulse that resets the latches. The Cadence
simulation in Figure 3.3 is included to visualize the functionality of the PFD. When the
reference leads the divider it is easily seen that the DOWN pulse (Falling edge triggered) is
set high on the falling edge of the reference and is set low on the falling edge of the divider.
The UP pulse is a very tiny pulse in this case. It is just wide enough to reset the latches.
22
Figure 3.1: Tristate PFD
Figure 3.2: Modi ed folded D Latch with Reset
23
Figure 3.3: PFD simulation signals from top to bottom are: Reference, Divider, UP, DOWN,
Charge Pump Output
24
3.3 PFD Dead Zone
When the phase di erence of the input signals becomes small, the correction pulses to
the charge pump become small. Finite rise and fall times of the circuit cause narrow pulses
that cannot activate the charge pump. If this is the case, the charge pump can no longer
follow the input phase for small phase errors. This region is known as the dead zone. This
dead zone can be mitigated by adding a delay to the reset line to force the pulses to become
wider. The tradeo is that this widened pulse can cause reference spurs if it becomes too
wide.
3.4 Conclusion
A tristate phase frequency detector has been designed with minimum gate count. The
latches have been modi ed to reduce the number of transistors while still functioning in the
same capacity. The circuit delay must be as uniform as possible to reduce the dead zone.
25
Chapter 4
Charge Pump
4.1 Introduction
The charge pump has a very important function in the loop. It takes the digital pulses
from the phase detector and converts them to an analog current to drive the VCO. The
charge pump must be carefully designed to mitigate reference feedthrough and phase noise.
The Charge pump o ers the circuit designer many opportunities to modify or improve
performance. In spite of alterations, most charge pumps consist of two current sources and
two switches. The main focus of this section will be the di erential charge pump because
it integrates nicely with the CML phase detector.
4.2 Circuit Design Considerations
4.2.1 Saturation Voltage of MOS Transistors
To utilize the full range of the VCO, it is important to design the current mirror
transistors with a small saturation voltage (vDSSat = vGS vT). This can be accomplished
by making the W=L ratio large and the drain current small. This allows the VCO to operate
close to the supply rails.
4.2.2 Current Source Matching
Current matching between PMOS and NMOS transistors is a challenge in charge pump
design. To minimize current mismatches, it is desirable to keep output resistance high. Note
that the output resistance for a MOS transistor is given by
rDS = 1 I
DS
/ LI
DS
(4.1)
26
From Equation 4.1 we see that for purposes of current matching it is good to have a
long device. Bipolar transistors have even higher output resistances, but it can be harder
to match npn and pnp transistors.
There are ways to increase output resistance in the MOS current source. Resistive
degeneration can be added or a cascode transistor can be inserted. For low voltage circuits
these techniques must be thought about carefully because they increase headroom. None
of these techniques to increase output resistance have been employed for the charge pump
in this paper because of the lack of headroom.
4.2.3 Reference Feedthrough
Reference feedthrough occurs when the upper and lower current sources are mis-
matched. When the phase di erence of the input signals to the charge pump is zero, both
upper and lower current sources are on for an instant while the Phase-Frequency Detector
(PFD) resets itself. If the current sources are mismatched, then there will be a current
pulse sent to the VCO that will need to be corrected on the next cycle.
4.2.4 Current Source Matching
To mitigate reference feedthrough the current sources should be matches as closely as
possible. This means that the transconductance of the devices should be matched, where
transconductance is de ned by
gm =
s
2 Cox(WL )IDS (4.2)
The mobility of the transistor is 2 3 times larger for the NMOS transistor than for
a PMOS transistor. The W=L ratio of the PMOS must be scaled by the same amount to
match the NMOS transistors. There are several ways to increase W=L.
1. If the W=L ratio is to be adjusted then the L for the NMOS and PMOS transistors
should be the same.
27
2. The number of ngers can be scaled. If this is the case, then the number of ngers
should be odd for matching reasons.
3. It is best to scale the number of transistors and, if possible, use a common centroid
layout.
The speed of the circuit is also important. If the circuit cannot respond fast enough,
then the charge pump will cause a reduction in gain at low phase di erences. This results
in a dead zone even if the PFD is designed to be dead zone free.
4.3 Di erential Charge Pump
The charge pump shown in Figure 4.2 is a di erential charge pump for a BiCMOS
process. The input transistors are Bipolar for ease of switching, while the charge pump
itself is CMOS.
Figure 4.1: Di erential BiCMOS Charge Pump
This charge pump has good current matching because the UP and DOWN input stages
are very symmetric. By virtue of being a di erential charge pump, this circuit has good
common mode rejection.
28
4.4 Tunable Current Source
A tunable current source can be made simply by taking the reference current produced
by the bandgap and then scaling it up. Programming in binary steps is achieved by placing
swiches in series with the current mirrors. The current is programmed in binary steps as
given by
Iref = (8b3 + 4b2 + 2b1 +b0)Ibias (4.3)
The tunable current source can be implemented to adjust the current owing in the
charge pump for one of a couple of reasons. Because of the uncertainty of the fabrication
process it might be desirable to tune the current for optimal noise performance. The
bandwidth of the loop can be changed by the charge pump, so tuning the charge pump
current could be instrumental in setting the loop dynamics.
Figure 4.2: Tunable current source
29
4.5 Conclusion
Proper sizing of the transistors in the charge pump can mitigate reference feedthrough
and close in spurs in the output spectrum of the VCO. Although not implemented in the
author?s fabricated design, the tunable current source is very useful in optimizing noise
performance. The tunable current source can be used for tuning bandwidth and settling
time. This function is covered because it could be useful to implement in a future design.
30
Chapter 5
Loop Filter
5.1 Introduction
Because the VCO is controlled by voltage and the output of the charge pump is a
current, a function of the loop lter is to convert from current to voltage. The loop lter
low pass lters the tune line to the VCO reducing the ripples that would otherwise cause
undesired e ects in the VCO. In addition, the loop lter adds a loop stabilizing zero as can
be seen in the system level analysis.
Active loop lters use transistor ampli ers to implement the low pass lter [30], [31].
This can be done easily, but it is important that the loop lter does not introduce noise to
the tune line. Active loop lters introduce power supply noise, and transistor noise. For
this reason, active loop lters are not desired.
Passive ltering is the most widely used choice for loop lter. If the loop lter could be
integrated on chip, the only noise that would be added to the system is the thermal noise
in the resistor. Because the loop lter capacitances must be large it is not easy to integrate
the loop lter on chip. Parasitic inductances from bonding wires and PCB level coupling
of noise sources make the tune line very susceptible to noise.
A third option is presented in [27]. Although this paper turns out to be falsi ed, the
concept has been veri ed in [28], [29], and others. This method of implementing the loop
lter o ers promising results for integrating the loop lter on chip without increasing noise.
5.2 Passive Loop Filter
The second order loop lter is shown in Figure 5.1. The second order passive loop
lter yields a straight forward analysis. Figure 5.2 shows the transfer function of the second
31
order passive loop lter. The transfer function of the second order loop lter is of the form
F(s) = vcI
cp
= 1 +sC1Rs(C
1 +C2)(1 +sCsR)
(5.1)
where
Cs = C1C2C
1 +C2
(5.2)
It should be noted that the lter transfer function is a transimpedance function.
A magnitude plot of the second order loop lter is shown in Figure 5.2. Component
values for this loop lter are: R = 20k , C1 = 5nF, and C2 = 500pF. This transfer
function is veri ed with a Cadence simulation in Figure 5.3.
Figure 5.1: 2nd order loop lter
From either of these plots it is seen that there is a pole at DC. The slope continues at
20dB=dec until the zero at s = 1RC1 where the slope levels o . The slope is zero until the
high frequency pole is reached and then the curve resumes its 20dB=dec descent.
For higher order loop lter transfer functions the reader is referred to [24].
5.3 Dual Path Loop Filter
The dual path loop lter presented in [27] is a promising prospect in integrating the
loop lter on chip. Simply put, the dual path loop lter uses two charge pumps that are
32
Figure 5.2: 2nd order loop lter transfer function simulated with Matlab
Figure 5.3: 2nd order loop lter transfer function simulated with Cadence
33
equal in phase but di er in magnitude. The charge pumps interact with the loop lter as
shown in Figure 5.4.
Figure 5.4: Dual path loop lter circuit diagram
Neglecting the higher order components RP2 and CP2 we can nd the transimpedance
transfer function of this loop lter. The transimpedance transfer function is de ned as
Zeq = veqI
CPI
(5.3)
where veq is the voltage from CI to ground and is found analytically as
veq = ZCIICPI +RP (ICPI +ICPP) (5.4)
So the transimpedance transfer function is
Zeq = veqI
CPI
= ZCI +RP (1 + ICPPI
CPI
) (5.5)
We see that the resistance is e ectively multiplied by the ratio of the charge pumps.
The bene t of this structure is that the capacitor can now be reduced in size and the same
1=RC time constant can be achieved. Figure 5.5 shows that for a charge pump ratio of 10:1
the zero in the transfer function can be reduced by a frequency decade.
34
Figure 5.5: Dual path loop lter compared to traditional 2nd order loop lter
The e ective multiplication of the resistance is sometimes called "?Noiseless Resistor
Multiplication[27]"? because the extra charge pump is not connected directly to the tune
line and does not directly add any noise to the tune line.
5.4 Simpli cation of Dual Path Loop Filter Structure
The structure put forth by A. Maxim calls for two charge pumps. We propose a sim-
pli cation to Maxim?s structure. Obtaining the ratio of the two charge pumps as described
earlier is as simple as adding a CMOS current mirror as shown in Figure 5.8. For a current
mirror ratio of 10:1 the same loop lter magni cation can be achieved without the need for
two distinct charge pumps.
5.5 Tunable Loop Filter
The ability to electronically shift the poles and zeros of the loop lter is an entertaining
concept. With this ability it might be feasible to design a frequency synthesizer with one
loop lter speci cation for frequency acquisition (wider bandwidth) and one speci cation
for phase lock (Faster settling time).
35
Figure 5.6: Proposed tunable loop lter
One possibility is to use a tunable current source. A binary weighted current source
has been suggested for the purpose of adjusting charge pump current for optimum noise
performance[6]. A four bit programmable current source like the one in Figure 5.7 allows
for current tuning from Ibias 15Ibias. We propose the use of the tunable current source
for an adjustable loop lter. Diagram for the proposed loop lter is shown in Figure 5.8.
Figure 5.7: Tunable current source
36
Figure 5.8: Proposed tunable loop lter
5.6 Conclusion
The simplest and most direct loop lter is the passive loop lter. This lter is the most
commonly used. Indeed, the second order passive loop lter is the one chosen by the author
to implement ltering for the fabricated design.
The dual path loop lter seems promising for future designs. One problem with this
architecture is that it seems to move the zero but not the pole of the loop lter. It is of
most interest to shift the pole of the system, moving the corner lower in frequency.
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Chapter 6
Voltage Controlled Oscillator
6.1 Introduction
This chapter will brie y discuss the voltage controlled oscillator design. The gm cell
has been designed for the fabricated PLL. Please note that a thorough discussion of VCO
design is omitted. The design e ort for the VCO has been a part of the research e ort by
another student. The full analysis will be presented in a thesis by William Souder.
6.2 Negative Gm Oscillator
The negative transconductance oscillator is so called because the e ective resistance
seen at the output is negative. Looking at Figure 6.1 we immediately see that vbe1 = vbe2
and from that vx = vbe2 vbe1. So then vx = vbe2 vbe2 = 2vbe2. The collector current
can be expressed as ic = gm vbe. From here we see that the output resistance is
vx
ic =
2
gm (6.1)
and does in fact appear negative to the output. This negative resistance is important to
grow oscillations.
The full circuit for the gm oscillator is shown in Figure 6.2. Oscillation occurs when
the imaginary impedances cancel and the negative resistance is grown to be larger than the
positive output resistance.
Figure 6.3 shows a Kvco of 1GHz/V. The charge pump of this PLL must be designed
with care to prevent pulses from occuring on the tune line. Tail current for this design is
8mA to provide adequate drive strength for the divider.
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Figure 6.1: AC model of negative gm oscillator analysis
Figure 6.2: Negative gm oscillator with varactor tuning
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Figure 6.4 shows that, in simulation, the VCO has a phase noise of 95dBc/Hz at
a 1MHz o set from the carrier. The phase noise has a 20dB/dec slope to greater than
100MHz o set from the carrier.
Figure 6.3: Simulated KVCO
6.3 Conclusion
The theory of operation of the gm oscillator has been presented in this chapter. The
fabricated VCO has been carefully designed to provide enough drive strength for the divider.
Phase noise has been simulated and the parameter KVCO has been determined graphically.
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Figure 6.4: Simulated VCO phase noise
41
Chapter 7
Divider Circuit Design
7.1 Introduction
The design of the divider in the frequency synthesizer is a matter for careful consider-
ation. The divider contributes to the close in phase noise, controls the channel spacing and
step size, and is a large contributing factor in total loop power consumption.
There are several options for divider design. Pulse swallow counters are one of the
most common divider implementations, but often they cannot program all frequencies in a
required band. The circuit with all two/three cells is a truly modular option, but does not
always present the lowest power consumption. This chapter presents a third alternative,
the Multi Modulus Divider (MMD). The MMD architecture is similar to the architecture
with all two/three cells. It di ers in the fact that the last stage of the MMD is a divide by
P/P+1 stage.
A generic algorithm [22] is presented to determine the minimum number of cells. A
speci c example is included to illustrate the di erences between the architectures.
Lastly, the approach to minimizing the current in each individual cell is presented.
Simulated results of the MMD designed for 13GHz, implemented in 0.13 m SiGe BiCMOS
technology are presented in the nal section.
7.2 Design Challenges
Divider design is one of the most important challenges in designing a frequency syn-
thesizer. The rst stage of the divider must operate at the highest frequency in the loop.
The divider must be carefully designed to have minimum current consumption, but must
still switch fast enough to handle the highest frequencies in the loop.
42
The divider contributes to the close in phase noise of the loop. Therefore, the output
of the divider must be clean to reduce jitter and spurs. Properly sizing the transistors and
bias current help reduce jitter.
7.3 Divider Architectures
7.3.1 Dual Modulus Prescaler with Pulse Swallow Counter
The pulse swallow counter is a commonly used divider architecture. It consists of a dual
modulus prescaler, programmable frequency divider M, and down counter A as shown in
Figure 7.1. The programmable counter is a frequency divider with programmable division
ratio M. The pulse swallow divider operation is described in [6] and is reiterated here.
1. The M divider divides the output frequency of the dual modulus prescaler by M.
2. The A down counter is loaded with an initial value of A at the rising edge of the M
divider output and is clocked by the input signal of the M divider.
3. The A down counter value is reduced by one at every rising edge of its value reaches
zero, it will remain zero unless the next load signal loads a start value to the counter
4. The A down counter output is high when the counter value is nonzero, which toggles
the dual modulus divider to divide by P + 1, and its output is low when the counter
value is zero, which toggles the dual modulus divider to divide by P.
5. The hold input to the down counter can be connected to a fractional accumulator?s
carry out to achieve a fractional division ratio
The average division ratio of the pulse swallow divider is
Div = (P + 1)A+ (M A)P = PM +A (7.1)
Under some conditions it is not possible to synthesize all channels with this counter.
The programmable blocks must be designed carefully to aleviate this problem. For normal
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Figure 7.1: Pulse Swallow Divider
operation M;A = 0 minfP 1;Mg. The condition so that no channels are skipped is
M >P 2. No channels are overlapped when A