IMPACT OF CHARGE COLLECTION MECHANISMS ON SINGLE EVENT EFFECTS IN SIGE HBT CIRCUITS AND HARDENING IMPLICATIONS Except where reference is made to the work of others, the work described in this thesis is my own or was done in collaboration with my advisory committee. This thesis does not include proprietary or classified information. Tong Zhang Certificate of Approval: Fa Foster Dai Professor Electrical and Computer Engineering Guofu Niu, Chair Alumni Professor Electrical and Computer Engineering Vishwani Agrawal James J. Danaher Professor Electrical and Computer Engineering George T. Flowers Graduate School Dean IMPACT OF CHARGE COLLECTION MECHANISMS ON SINGLE EVENT EFFECTS IN SIGE HBT CIRCUITS AND HARDENING IMPLICATIONS Tong Zhang A Thesis Submitted to the Graduate Faculty of Auburn University in Partial Fulfillment of the Requirements for the Degree of Master of Science Auburn, Alabama August 10, 2009 IMPACT OF CHARGE COLLECTION MECHANISMS ON SINGLE EVENT EFFECTS IN SIGE HBT CIRCUITS AND HARDENING IMPLICATIONS Tong Zhang Permission is granted to Auburn University to make copies of this thesis at its discretion, upon the request of individuals or institutions and at their expense. The author reserves all publication rights. Signature of Author Date of Graduation iii VITA Tong Zhang, son of Duanming, Zhang and Fangming Peng, was born in Hubei, China on February, 6th, 1978. He graduated high school from Middle School of Huazhong University of Science and Technology in 1996. He graduated from Huazhong University of Science and Tech- nology, Wuhan, China with a Bachelor of Communication Engineering degree in 2000. He began his graduate studies in Electrical and Computer Engineering at Auburn University in January, 2007. His research interests include device physics and radiation e?ects in electronic devices. iv THESIS ABSTRACT IMPACT OF CHARGE COLLECTION MECHANISMS ON SINGLE EVENT EFFECTS IN SIGE HBT CIRCUITS AND HARDENING IMPLICATIONS Tong Zhang Master of Science, August 10, 2009 (B.S., Huazhong University of Science and Technology, 2000) 94 Typed Pages Directed by Guofu Niu Investigations into single event e?ect (SEE) induced charge collection in Silicon Germanium (SiGe) heterojunction bipolar transistors (HBT) are made through three-dimensional (3-D) device simulation. The transistor is constructed based on actual device. The results indicate that collector- substrate (CS) junction plays an important role due to the reverse biased CS junction. Therefore by adding a dummy collector to the HBTs, a recently published radiation hardening by design (RHBD) technique, the total collector collected charge can be reduced due to reduction of the di?usion charge collection at the intrinsic CS junction. At present, the single event upset (SEU) sensitivity is primarily characterized using the total amount of collector charge collected during an ion strike. This, however, may not be accurate, as the contributions of di?erent charge collection processes are greatly influenced by external loading and the circuit topology. The individual impact of drift and di?usion charge collection at the collector- base (CB) and CS junctions on SiGe HBT current mode logic (CML) circuit SEU is examined. The CS junction di?usion charge collection has negligible impact on circuit SEU, despite its large charge collection magnitude. The CB drift charge collection is as important as the CS drift charge v collection, even though its charge magnitude is much less, because the resulting current excitation appears between collector and base nodes, and hence is amplified. Using selective ion track place- ment in 3-D simulations, we further find that an ion track passing through the physical CS junction is much more e?ective in causing SEU than an ion track not passing through the CS junction. This is attributed to potential funneling and consequent large induced drift current magnitude, which is necessary for SEU of CML circuit. For emitter followers, the conventional hardening approach to minimize SEE is using a higher emitter biasing current as the emitter current determines output. This, however, is shown to not work at all with 3-D mixed mode simulations. Instead, it is the CB junction charge collection that dominates emitter output SEE, because CB junction charge collection determines the base voltage deviation, and the emitter output follows the base deviation. Therefore, the impedance and the elec- tric field across the CB junction are the most important factors a?ecting emitter follower SEE. From the simulation results, the product of SEE induced base current and the base biasing impedance de- termines the amount of base voltage upset or deviation. For base biasing impedance values found in practical circuits, a smaller base biasing impedance should be used to reduce emitter output voltage SEE, as the emitter voltage upset tracks the base voltage upset. vi ACKNOWLEDGMENTS I am deeply indebted to Dr. Guofu Niu for his technical, educational and moral support throughout my Master program. I am deeply influenced by his research and teaching philosophy which made my graduate work an educational and professionally enriching experience. I would also like to thank Dr. Fa Foster Dai and Dr. Vishwani Agrawal for their encouragement and for being my committee. I would like to thank Muthubalan Varadharajaperumal and Lan Luo for their help on the soft- ware. I would like to thank my wife, Xiaoyun Wei for her great support to my research work as well as my life. Also, I would like to thank my family and friends for their encouragement and support all through my research. This work was supported by NASA-GSFC under NASA Electronic Parts, Packaging Program and DTRA under the Radiation Hardened Microelectronics Program, and the NASA ETDP Program under Contract NNL06AA29C. I would like to thank K. A. LaBel, NASA-GSFC, P. W. Marshall, consultant to NASA-GSFC, J. D. Cressler of Georgia Institute of Technology, R. A. Reed of Vand- abilt University, and Alvin Joseph of IBM Microelectronics, for their contributions and support. vii Style manual or journal used Journal of Approximation Theory (together with the style known as ?aums?). Bibliography follows van Leunen?s A Handbook for Scholars. Computer software used The document preparation package T E X (specifically L A T E X) together with the departmental style-file aums.sty. viii TABLE OF CONTENTS LIST OF FIGURES xi 1INTRODUCTION 1 1.1 Motivation ....................................... 1 1.1.1 Single Event Upset in CML Circuit ..................... 1 1.1.2 Single Event Transient in Emitter Followers ................. 2 1.2 Silicon Germanium HBT ............................... 3 1.3 Single Event E?ect and Single Event Transient ................... 5 1.4 3-D Device Simulation ................................ 6 1.5 Circuit Simulation ................................... 7 1.6 Thesis Contributions ................................. 9 2CHARGE COLLECTION 10 2.1 Regular SiGe HBT Device .............................. 11 2.1.1 Basic Device Structure ............................ 11 2.1.2 Device Construction in MESH ........................ 11 2.1.3 Charge Collection Mechanisms ....................... 16 2.1.4 SEE Current Modeling ............................ 18 2.2 Transistor-level Hardening .............................. 20 2.2.1 Hardening Techniques ............................ 20 2.2.2 Dummy Collector Hardening ......................... 21 2.3 Conclusion ...................................... 26 3CIRCUIT SEU SIMULATION APPROACHES 27 3.1 True Mixed Mode Simulation ............................. 28 3.2 Combined Mixed Mode Simulation ......................... 29 3.3 Simulation Results .................................. 31 3.4 Conclusion ...................................... 33 4MECHANISMS OF SINGLE EVENT UPSET IN DFF 34 4.1 Technical Approach .................................. 35 4.2 Drift vs. Di?usion Charge Collection ........................ 38 4.3 CB Drift Charge vs. CS Drift Charge ......................... 41 4.4 Regional Charge Collection Analysis ......................... 42 4.5 Threshold LET and the SOI Limit .......................... 44 4.6 Importance of Junction Passing and Potential Funneling ............... 45 4.7 Error Cross Section .................................. 46 ix 4.8 Outside DT Charge Deposition ............................ 46 4.9 Dummy Collector Hardened SiGe HBT ....................... 47 4.10 Conclusion ...................................... 47 5SINGLE EVENT TRANSIENTS IN EMITTER FOLLOWERS 56 5.1 Simulation Details and Circuit Topology ....................... 57 5.2 SET in Typical Emitter Followers .......................... 57 5.3 Biasing Current and Resistance Dependence ..................... 62 5.4 Emitter Biasing Current Dependence ......................... 62 5.5 Emitter Biasing Resistance Dependence ....................... 64 5.6 Base Biasing Current Dependence .......................... 65 5.7 Base Biasing Resistance Dependence ........................ 66 5.8 CB Voltage Dependence ............................... 68 5.9 Ion Strike Dependence ................................ 69 5.9.1 Position and Depth Dependence ....................... 69 5.9.2 LET Dependence ............................... 71 5.10 Hardening Implications ................................ 72 5.11 Conclusion ...................................... 75 BIBLIOGRAPHY 77 x LIST OF FIGURES 1.1 2-D cross section of a typical SiGe HBT used in simulation. ............ 4 1.2 Illustration of a heavy ion passing through a pn junction. .............. 6 2.1 Top view of a regular bipolar transistor ........................ 12 2.2 2-D cross section of a regular bipolar transistor ................... 13 2.3 A 3-D HBT device constructed using MESH. .................... 14 2.4 2-D Cross section of the meshed HBT device for emitter center ion strike SET simulation. ...................................... 15 2.5 Terminal currents and integrated charges from DESSIS SET simulation. ...... 17 2.6 Terminal Current and charge from DESSIS transient simulation in linear scale. . . 18 2.7 Illustration of ion-induced current sources in a SiGe HBT and a simplified model used for circuit simulations. .............................. 19 2.8 Top view for a dummy collector hardened HBT device ............... 21 2.9 2-D Cross section for a dummy collector hardened HBT device .......... 22 2.10 A HBT hardened device with dummy collector constructed using MESH . ..... 23 2.11 2-D cross section of a HBT hardened device. .................... 24 2.12 The terminal Currents and the integral charges versus time in log scale for regular and dummy collector hardened HBT. ........................ 25 3.1 Example codes in DESSIS for mixed mode simulation. ............... 28 3.2 An example of load SEE current source into circuit. ................. 30 3.3 Schematic of a master-slave DFF. ........................... 31 3.4 Comparison between true mixed mode output and combined mixed mode output for aDFF.......................................... 32 xi 4.1 Schematic of a master-slave DFF. ........................... 35 4.2 The equivalent circuit model used for including the charge collection currents in circuit simulation. ................................... 36 4.3 The SEE induced CB and CS charge collection currents and the integral charges. . 37 4.4 Output waveform from transient simulation result for the DFF. ........... 39 4.5 Comparison of the simulated?M andQ+, with drift and di?usion currents activated individually. ..................................... 40 4.6 Comparison of the simulated ?M and Q+ with drift and di?usion currents activated individually, for a static clock. ............................ 41 4.7 Comparison of the simulated ?M and Q+ with CB and CS drift currents activated individually. ..................................... 42 4.8 Illustration for regional charge collection analysis. ................. 49 4.9 Terminal currents and charge for regional charge collection analysis. ....... 50 4.10 Circuit output comparison for regional charge collection analysis. ......... 51 4.11 The drift charge collected at CB and CS junctions, individually, and the total col- lector drift charge versus LET. ............................ 52 4.12 Sensitive areas for CB and CS junction charge collection in 2-D cross section illus- tration. ......................................... 53 4.13 The SEE induced CB and CS charge collection currents and the integral charges for regular and hardened SiGe HBTs. .......................... 54 4.14 Comparison of the simulated ?M and Q+ with CB and CS currents from regular and hardened SiGe HBTs. .............................. 55 5.1 2-D cross section of an 8HP regular HBT. ...................... 58 5.2 The circuit topology of a typical emitter follower. .................. 59 5.3 SET on three typical emitter followers. (a) V E , (b) I E,SEE , and (c) V CE versus time. 60 5.4 SET on three typical emitter followers. (a) V B , (b) I B,SEE , and (c) Q B,SEE versus time. .......................................... 61 xii 5.5 The schematic of emitter followers used to examine the impact of (a) I EF and R EE , and (b) I BB and R BB , on emitter voltage SET individually. ............. 63 5.6 SET on emitter followers with di?erent emitter biasing current. (a) I B,SEE , (b) Q B,SEE , (c) V B , and (d) V E versus time. ...................... 64 5.7 SET on emitter followers with di?erent emitter biasing resistance. (a) I B,SEE , (b) Q B,SEE , (c) V E , and (d) I E,SEE versus time. .................... 66 5.8 SET on emitter followers with di?erent base biasing current. (a) I B,SEE , (b) Q B,SEE , (c) V B , (d) V E versus time. ......................... 67 5.9 SET on emitter followers with di?erent base biasing resistance. (a) I B,SEE , (b) Q B,SEE , (c) V B , and (d) V E versus time. ...................... 68 5.10 SET on emitter followers with di?erent CB voltage. (a) I B,SEE , (b) Q B,SEE , (c) V B , and (d) V E versus time. ............................. 70 5.11 Illustration of the ion tracks for a center strike and an o? center strike. ....... 72 5.12 SET on emitter followers under ion strikes at di?erent position and with di?erent depth. (a) I E,SEE , (b) V E versus time. ........................ 73 5.13 SET on emitter followers under ion strikes with di?erent LET. (a) I B,SEE , (b) Q B,SEE , (c) V B , and (d) V E versus time. ...................... 74 5.14 SET on emitter followers with di?erent R BB . (a) V E , (b) Q B,SEE versus time. . . 75 5.15 SET duration on emitter followers with di?erent base biasing resistance. (a) SET duration versus R BB , (b) SET duration versus R ?1 BB ................. 76 xiii CHAPTER 1 INTRODUCTION 1.1 Motivation Electronics in spacecrafts and satellites can be degraded significantly by the natural space radiation environment mainly through three manners, total dose ionizing radiation damage, single event related soft and hard errors, and displacement damage [1] [2]. This work will deal with single event e?ect (SEE) in Silicon-Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) electronics that is being actively investigated for space applications. SiGe HBT has generated considerable interest in the space community due to its robustness to total ionizing dose radiation (TID) without any additional hardening [3] [4]. But, recently, high speed SiGe HBT digital logic circuits were found to be vulnerable to single event upset (SEU) [5] [6]. Hence it is important to study the SEE on SiGe HBT circuits. SEE is defined as deleterious e?ects in the devices caused by the deposition of energy within electronic devices by a single energetic particle. The major types of SEE namely are SEU, single event latchup (SEL), single event snapback (SESB), and single event transient (SET), etc [7] [2]. This work focuses on SEU in current mode logic (CML) circuits and SET in emitter followers. 1.1.1 Single Event Upset in CML Circuit It is di?cult to evaluate circuit SEU sensitivity experimentally. A convenient approach is to study the charge collection characteristics of the struck device, and compare the collected charge to some critical charge to upset. Critical charge is primarily characterized using the total amount of collector charge collected during an ion strike [8] [9]. However, the usefulness of this approach 1 is extremely limited, since the critical charge itself may be ill-defined, and dependent on external loading and specific circuit designs [10] [11] [12] [13]. Nevertheless, unloaded device simulation has been useful for studying the basic physical properties of charge collection, and for studying circuits where loading e?ects are not as prevalent and critical charge is well-defined [14]. Drift and di?usion charge collections at di?erent junctions have di?erent impact on circuit SEU. To find out the most dominate factors responsible for CML circuit SEU, di?erent charge collection processes need to be examined individually. By this way, the mechanisms behind dif- ferent phenomena observed in CML circuits SEU can be better understood, and the guidelines for transistor- and circuit- level hardening techniques can be provided. 1.1.2 Single Event Transient in Emitter Followers Investigations into charge collection in SiGe HBTs indicate that collector charge collection, particularly through the reverse biased collector-substrate (CS) junction, is the dominant path for ion-induced charge to be collected. Therefore, the resulting hardening techniques focus on collector charge collection, and apply to circuits in which the collector current determines circuit output, such as emitter coupled logic (ECL) circuits. Such techniques, however, do not apply to circuits where the emitter current determines circuit output. An example is emitter follower, which is widely used as output bu?er, unity voltage gain amplifier, dc power regulator in analog circuits, as well as level shifter in ECL circuits. SET simulations using three-dimensional (3-D) mixed mode simulation in SiGe HBT emitter followers are demanded. To improve SEE immunity in emitter followers, conventional wisdom of designers tends to use a higher biasing emitter current, as the emitter current determines output. However, our simulations show this intuitive approach is completely incorrect, as it does not consider the complex operation 2 of the circuit during SET. Parametric analysis of emitter followers is performed to find out the design parameters that are essential to emitter follower SET. Guidelines on how to improve emitter follower SET can then be provided. 1.2 Silicon Germanium HBT The basic formulation and operational theory of the HBT was in place by Kroemer in as early as 1957 [15] [16]. Research and development activity in SiGe devices, circuits, and technologies in both industry and at universities worldwide has grown rapidly since the first demonstration of a functional SiGe HBT in 1987 [17] [18]. Commercial SiGe HBT technologies now exist in com- panies around the world, including: IBM, Philips, Infineon, IHP, etc. In recent years, a variety of papers demonstrating impressive digital, analog, RF, and microwave circuit results for wireless and wireline communications applications were published. Fig. 1.1 shows the 2-D cross section of a typical SiGe HBT. A small amount of Germanium is introduced into the base of a silicon (Si) bipolar junction transistor (BJT). As a consequence, the Ge-gradient-induced drift field across the neutral base is aligned in a direction from collector to emitter such that it will accelerate the injected minority electrons across the base and thereby reduce the base transit time. Because the base transit time typically limited the frequency response of a Si BJT, the operating speed can be improved by a factor of 2-3 over conventional BJT. In addition, the Ge-induced band o?set at the emitter-base (EB) junction exponentially enhances the collector current density (and thus ?) of a SiGe HBT compared to a comparably constructed Si BJT. Experimental results suggest that SiGe HBTs have much better TID tolerance than conven- tional di?used or even ion-implanted Si BJT technologies (even radiation-hardened ones) [18]. This observed radiation hardness is attributed to the unique and inherent structural features of the SiGe 3 HBT itself through careful comparisons between identically fabricated SiGe HBTs and Si BJTs (same device geometry and wafer lot, but without Ge in the base for the epitaxial-base Si BJT) [18]. Note that these SiGe HBTs compare very favorably in both performance and radiation hardness with (more expensive) GaAs HBT technologies that are often employed in space applications re- quiring both very high speed and an extreme level of radiation immunity [19]. Furthermore, SiGe?s fabrication compatibility with conventional Si CMOS processing ensures that both high-speed SiGe HBTs and aggressively scaled CMOS devices can be co-integrated on the same Si wafer, making it possible to combine analog, RF/microwave, and digital functions on a single chip. Figure 1.1: 2-D cross section of a typical SiGe HBT used in simulation. 4 1.3 Single Event E?ect and Single Event Transient Space is full of highly energetic particles. As they pass through the semiconductor material, the ions strip electrons from atoms, leaving behind a track of unbound electrons and holes. When the track passing through or near a region with an electric field, such as exists in a semiconductor pn junction, the free electrons and holes are separated and collected at electric contacts, giving rise to an electric current at each contact. It is the electric current that causes all SEEs [2]. In a word, the mechanisms contributing to SEE are charge generation, charge collection and circuit response. Fig. 1.2 shows the electron and hole pairs generated along ion strike path in a pn junction [4]. The electrostatic potential is disturbed in the junction and this disturbed field extends deep to the substrate. The disturbed field collects charge deposited deep in the substrate. SEE can be classified into two categories, destructive SEE and non-destructive SEE. SET and SEU in logic or memory circuits are examples of non-destructive SEE. An SET is defined as a momentary voltage excursion (voltage spike) at a node in an integrated circuit [2]. Under certain conditions, the voltage spike can propagate away from where it was generated and eventually appear at the circuit?s output. When an SET is captured, e.g. by a latch, it becomes an SEU. Up to date, the studies of SET in digital logic circuits are relatively less than those of SEU. Significant increase in error rate due to SET is observed in very fast logic circuits [20] [21] [22]. Besides, SET is also observed in analog (linear) circuits and opto-electronic circuits in space [23] [24]. Therefore, SET simulation becomes indispensable in space applications. 5 Figure 1.2: Illustration of a heavy ion passing through a pn junction. 1.4 3-D Device Simulation The inherently 3-D nature of an ion passing through a microelectronic device needs advanced 3-D modeling tools. The most commonly used formalism for device simulation is that of drift?di?u- sion models. There are three equations to be solved, the Poisson equation and the current continuity equations, together with the constitutive relationships for current density (the actual drift?di?usion equations) [25]. These equations are discretized and solved at each mesh point. A typical SEE simu- lation of single device is performed in three steps, which will be detailed in Chapter 2. First, a stand alone device is built using MESH. The boundaries of all the device regions are constructed using layers of cuboidal blocks, which is a simplified strategy compared to using polyhedrons. Second, 6 the device is doped according to the secondary ion mass spectrometry (SIMS) data and meshed. Finally, an SEE transient simulation is executed in 3-D device simulator, e.g. DESSIS. There are mainly two issues central to any device simulation. One is the ion strike track structure, the other is that of gridding, or mesh generation. Experimental results have highlighted the need to include realistic charge generation profiles in SEE simulations [26] [27]. The variation of charge density along the path and around the path of an incident particle both need to be correctly modeled. Gaussian function is available and prevalent in most device simulators. Dense mesh points are necessary at sensitive regions for both correct device electrical characteristics and SEE results, e.g. at pn junctions, along the ion track path. 1.5 Circuit Simulation Unloaded device simulation has been useful for studying the basic physical properties of charge collection and for studying circuits where loading e?ects are not that important. However, the im- pacts of SEE induced charge collection are greatly influenced by external loading and the feedback mechanism in lots of circuits, e.g. D-flip flop (DFF) in Chapter 4 and emitter follower in Chapter 5 [11]. The coupling of device and circuit response to incident ionizing radiation can be predicted through two mixed mode approaches as below. The first approach models the single event induced transient currents as current sources at the struck nodes and calculates the e?ects on circuit outputs with a circuit simulator such as Cadence Spectre [13] [28] [29]. This approach can handle large scale circuits e?ciently. A drawback is the accuracy of the transient currents used as the input stimulus as the transient currents are normally from 3-D device simulation of a struck unloaded device. The circuit result inherits the inaccuracy of the improperly loaded device simulation. Still, this approach has provided considerable insight 7 into circuit SEU and has resulted in improvements to hardening techniques for a variety of circuits [30] [31] [32]. The second approach finds the concurrent solution of device and circuit equations. The struck device is modeled in the "device domain" (e.g. using 3-D device simulation) while the rest of the circuit is represented by SPICE-like compact circuit models [11]. The two domains are tied together by the boundary conditions at contacts, and the solution to both sets of equations is rolled into one matrix solution [33] [34]. This approach reduces simulation times and greatly increases the complexity of the external circuitry that can be modeled since the circuit consists of computationally e?cient SPICE models except only the struck device. This kind of mixed mode simulation has been incorporated into most of the commercially available 3-D device simulators [35] [36] [37]. The drawback of these two mixed mode methods is that coupling e?ects between adjacent transistors cannot be taken into account, which have been shown to exist at the device level using 2-D simulations [38]. To address this di?culty, it is necessary to simulate the entire circuit in the 3-D device domain, namely full-cell device simulation [39] [40]. As inter-device spacing decreases with increasing integration levels, coupling e?ects can be expected to become more important, and simulating the entire circuit in the device domain may become routinely necessary [39]. However, mixed mode simulation is still useful for in-depth studies of SEU in specific circuits for given ion strikes. Both mixed mode approaches will be detailed in Chapter 3, and applied on circuit simulations in Chapter 4 and 5. 8 1.6 Thesis Contributions The 3-D structure of a regular 0.5?m SiGe HBT is detailed and the SET simulation results are shown in Chapter 2. Based on charge collection mechanisms of this single device, a four-current- source model and a simplified two-current-source model are detailed, which provide a practical approach to include SEE in circuit simulators. A hardened HBT with a dummy collector is examined to reduce the CS junction di?usion charge collection e?ectively. However, this technique does not improve certain circuits? SEU immunity as detailed in Chapter 4 and Chapter 5. Advantages and disadvantages of true and combined mixed mode simulations are discussed in Chapter 3. Taking DFF as an example, combined mixed mode provides similar SEU results to true mixed mode, but with high computational e?ciency and large scale circuit capability. Therefore, combined mixed mode is still favorable for circuit SEU simulations where loading e?ects are not that prevalent. Chapter 4 presents combined mixed mode simulation results for a DFF circuit. The impacts of di?erent charge collection mechanisms are examined by manually separating collector charge collection to collector-base (CB) and CS junction drift and di?usion charge collection. The charge collection processes that dominate the storage cell upset in a DFF are investigated. Regional analysis in device domain is performed to further verify the conclusions. The implications on di?erent ion strike location and hardening techniques are discussed. Chapter 5 presents true mixed mode transient simulation results for a typical emitter follower topology. Parametric analysis is performed to figure out the factors that are responsible for emitter voltage upset. Guidelines to reduce emitter voltage upset in real circuit designs are then provided. 9 CHAPTER 2 CHARGE COLLECTION To understand circuit SEE, it is important to first understand the physical mechanisms respon- sible for SEE in a single transistor [41]. At device level, the SEE induced transient currents are obtained using 3-D device simulation. The 3-D transistor is constructed based on the actual device layout and the SIMS data from the IBM SiGe HBT technology. All of the regions of the device must be accounted for, including the deep and shallow trench isolation (DT and STI). A top sub- strate contact and a su?ciently large simulation area are necessary to keep simulation conditions consistent with physical reality. The 3-D device structure and simulation conditions will be detailed in Section 2.1.2 and Section 2.1.3. SEE is caused by the collection of charge deposited along the ion strike path at the sensitive re- gions of a microelectronic device or circuit. Charge generation depends on the incident ion?s mass and energy and on the properties of the material through which it passes. Therefore, the same charge generation mechanism will apply to all devices and circuits manufactured in silicon. A uniform lin- ear energy transfer (LET) function with a Gaussian radius is used to model the heavy ion strike in this work. Charge collection depends on electrical parameters such as biasing voltage and doping levels in the semiconductor. For single device simulation, the emitter, collector, and base terminals are unloaded and grounded. The substrate is biased at a negative potential, which is always the lowest potential in a practical circuit. The reverse biased CS junction collects most of the deposited charge as shown in Section 2.1.3. Based on charge collection analysis, transistor-level hardening techniques have been developed to improve the SEU immunity. A recently published dummy- collector hardening technique can e?ectively reduce CS di?usion charge collection by adding a 10 dummy CS junction outside DT. The technique will be detailed and verified in Section 2.2.2, which is later used as the hardening technique in Chapter 4. 2.1 Regular SiGe HBT Device 2.1.1 Basic Device Structure Fig. 2.1 shows the top view of a regular SiGe HBT. DT is used to isolate the transistor from the other adjacent devices. NS layer is a heavily doped n + buried layer for low resistance collector contact. The length and width of the transistor are noted as W E and L E , which are much smaller than the dimensions of the silicon region inside DT. Fig. 2.2 illustrates the 2-D cross section of the SiGe HBT along the Y-cut in Fig. 2.1. The transistor is built on a lightly doped p-type silicon substrate. SUB is the top substrate contact. The intrinsic transistor contains an n + emitter, a p-type SiGe base, an n-type collector, and an n + buried layer. With Ge in the base, it makes two heterojunctions, EB junction and CB junction. 2.1.2 Device Construction in MESH Fig. 2.3 shows the 3-D structure built using MESH for the HBT device illustrated in Fig. 2.1 and Fig. 2.2. The construction starts with a large piece of silicon substrate of an area of 28 ?m ? 25 ?m and a depth of 25 ?m, as well as a top substrate contact is used to minimize simulation errors associated with charge collection [42]. Doping of the substrate is boron, 10 15 cm ?3 . The whole surface is covered by silicon oxide except the openings for the transistor, and the contacts for collector and substrate. Fig. 2.4 shows the 2-D cross section with gridding of the 3-D structure at y=0. The transistor is only several microns thick on the top of the silicon substrate surface. The vertical structure consists 11 Figure 2.1: Top view of a regular bipolar transistor of an n + polysilicon emitter, a p-type epitaxial base, an n-type collector, an n + buried layer, and a lightly doped p-type substrate [43]. A gradient Ge profile is added to the base. The equations for potential, electric field, electron concentration, and hole concentration are solved at each node of the mesh grid. Fine meshes are used along the path of the ion strike and at the pn junction interfaces as shown in Fig. 2.4. The average number of nodes is approximately 10 4 for each simulation. 12 Figure 2.2: 2-D cross section of a regular bipolar transistor 13 X Y Z DopingConcentration 1.8E+20 6.5E+16 2.4E+13 -2.8E+13 -7.5E+16 -2.0E+20 01: regular/0x5um/msh_msh.grd : msh_msh.dat Figure 2.3: A 3-D HBT device constructed using MESH. 14 X Z 0 2 4 6 -4 -2 0 DopingConcentration 1.8E+20 6.5E+16 2.4E+13 -2.8E+13 -7.5E+16 -2.0E+20 02: Y-Slice 1 : msh_msh.grd : msh_msh.dat Figure 2.4: 2-D Cross section of the meshed HBT device for emitter center ion strike SET simula- tion. 15 2.1.3 Charge Collection Mechanisms Device-level SEE simulation is significantly more complicated than dc or ac simulation, since the n-p-n-p multi-layer structure makes the charge collection more complicated than in a n-p-n bipo- lar structure. The charge track is generated using a Gaussian waveform, with an 1/e characteristic time scale of 2 picosecond and an 1/e characteristic radius of 0.1 ?m. The peak of the Gaussian occurs at 6 picoseconds [18] [3]. For deep ion strike simulation, the depth of the charge track is 25 ?m, with a uniform LET value along the charge track. Unless specified, the charge track is lo- cated at the emitter center, with a uniform LET=0.037 pC/?m (3.6 MeV?cm 2 /mg ). Physical TCAD models including the Philips unified mobility model, the Slotboom bandgap narrowing model, the high field velocity saturation model, and the Shockley-Read-Hall (SRH) and Auger recombination models, are activated for these DESSIS 3-D simulations [43]. The SiGe HBT is unloaded, with zero biasing voltages at collector, emitter, and base. The CS junction is reverse biased at -4 V. Fig. 2.5 and Fig. 2.6 show the transient currents and the integral charge collected at each terminal versus time in log and linear scale. Note that the linear plots are just for the first 5 nanoseconds, which is the time period when drift charge collection dominates as detailed below. The positive direction of currents is defined as entering the terminals. The positive emitter and collector currents indicate that during the SET process the collector and emitter collect electrons, while the negative base and substrate currents indicates that the base and substrate collect holes. The deposited charge is initially collected from the depletion layer mainly through drift over a very short time span (hundreds of picoseconds), causing a pulse like shape for currents at the four terminals, as shown in Fig. 2.5 (a). Therefore, significant drift charge collection occurs in reverse-biased junctions, e.g. CS junction, due to the high electric field [40]. Fig. 2.5 (b) indicates 16 that CS junction collects 0.5 pC drift charge, while the other junctions collect less than 0.1 pC drift charge. Charge deposited deep in the substrate di?uses towards the CS space charge region (SCR). Those that encounter the electric field are collected via drift, and generate currents on the collector and substrate contacts. This di?usion process lasts for several microseconds, with very low charge collection rate. The peak collector drift current is around 1.8 mA, while the collector di?usion current is less than 0.5?A. 10 ?2 10 0 10 2 10 4 ?0.5 0 0.5 Time (ns) Charge collected (pC) ?2 ?1 0 1 2 Terminal Current (mA) Emitter Collector base Substrate LET = 0.037 pC/um Diffusion dominate Drift dominate Q C Q E Q B Q S I C I E I B I S Figure 2.5: Terminal currents and integrated charges from DESSIS SET simulation. 17 0 1 2 3 4 5 ?0.5 0 0.5 Time (ns) Charge collected (pC) ?2 ?1 0 1 2 Terminal Current (mA) Emitter Collector base Substrate LET = 0.037 pc/um Figure 2.6: Terminal Current and charge from DESSIS transient simulation in linear scale. To reduce the SEE introduced charge collection, transistor-level hardening techniques have been developed. These device hardening techniques focus on reducing CS junction charge collec- tion, such as back junction [44], dummy collector [3], silicon-on-insulator (SOI) technology [45]. The actual e?ect of the dummy collector on charge collection will be examined in Section 2.2.2 2.1.4 SEE Current Modeling Under certain conditions, the ion-induced transient currents can propagate away from the struck device and cause SEU at the circuit output. To study the impact of the transient currents 18 in a circuit, these currents are frequently modeled as current sources at the struck transistor [46] [47] [48] [49]. Fig. 2.7 (a) shows the four-current-source model that includes all possible charge collection processes in a SiGe HBT. i eb is the SEE induced EB junction charge collection current. i cb is the SEE induced CB junction charge collection current. Compared with i cb , i eb is small due to the thin EB depletion layer thickness. The base terminal current is mainly i cb . i cs represents the SEE induced CS junction charge collection current. The substrate current is mainly i cs , which is the most significant part among all ion-induced currents based on the reason introduced in Section 2.1.3. i ce comes from ion track shunt e?ect, which will lead to negative emitter current if it dominates. The positive emitter current in Fig. 2.5 suggests that i ce is negligible compared to the other three current sources in this work [47] [50]. The collector current is thus the sum of i cb and i cs , while the emitter current is mainly i eb . Comparison of base and collector collected charge in Fig. 2.5 (b) suggests that much less charge is collected through base than collector. However, this small amount of charge can produce circuit SEU e?ectively, as will be shown in Section 4.3. cb i eb i ce i cs i cb i cs i Figure 2.7: Illustration of ion-induced current sources in a SiGe HBT and a simplified model used for circuit simulations. 19 Fig. 2.7 (b) shows the simplified two-current-source model. i eb and i ce are removed due to their small current level and the small amount of charge collected. The simplified model makes it easier to determine the value of the current sources. From Fig. 2.7 (b), i cb is equal to the simulated base current, and i cs is calculated as the di?erence of simulated collector and base currents. Our simulation results indicate that with only i cb and i cs ,itissu?cient to investigate the influence of ion-induced currents on circuit response. i cb and i cs include both drift and di?usion currents. i cb is primarily drift dominated, while i cs hasadi?usion component for a typical deep strike. 2.2 Transistor-level Hardening 2.2.1 Hardening Techniques There are approaches for mitigating the e?ects of radiation at all levels of hierarchy from the fabrication process and circuit design, to the system configuration and software levels. Var- ious radiation hardening by design (RHBD) techniques have been published recently, including transistor-level hardening [44] [51] [3] [9], and circuit-level hardening [52] [53]. Transistor-level hardening approaches mainly focus on reducing CS junction charge collection through di?erent techniques, such as a back junction, an SOI process or a dummy collector. A back junction approach is realized by adding another n + layer below the p-type substrate, which shares part of CS junction charge collection [44]. SOI technology removes the CS junction by fabricating a buried oxide to insulate n + buried layer and p-type substrate [45]. However, both of the two techniques require process changes, which may lead to extra cost in fabrication. The dummy collector is built by extending the n + buried layer (NS layer) outside the DT. This added pn junction is more reverse biased than the intrinsic CS pn junction, and can e?ectively reduce 20 CS di?usion charge collection without any process modification [3]. Simulation results of dummy collector hardened HBT will be shown in the following section. 2.2.2 Dummy Collector Hardening Fig. 2.8 and Fig. 2.9 show the top view and 2-D cross section view of a dummy collector hardened SiGe HBT. Compared with the regular SiGe HBT in Fig. 2.1 and Fig. 2.2, the dummy collector hardened HBT simply extends the NS layer outside the DT. Fig. 2.10 shows the 3-D structure of the hardened HBT using MESH, while Fig. 2.11 shows the 2-D cross section at y=0. The dummy collector is biased at +3 V unless specified. The area of the added PN junction is much larger than the CS junction, and the junction is more reverse biased than the CS junction. As a consequence, the added pn junction should be able to collect deposited charge easier and faster. Figure 2.8: Top view for a dummy collector hardened HBT device 21 Figure 2.9: 2-D Cross section for a dummy collector hardened HBT device 22 X Y Z DopingConcentration 2.8E+20 9.5E+16 3.2E+13 -2.3E+13 -6.8E+16 -2.0E+20 01: nring/0p5x1um/msh_msh.grd : msh_msh.dat Figure 2.10: A HBT hardened device with dummy collector constructed using MESH . 23 X Z -2 0 2 4 6 8 -6 -4 -2 0 DopingConcentration 2.8E+20 9.5E+16 3.2E+13 -2.3E+13 -6.8E+16 -2.0E+20 02: Y-Slice 1 : msh_msh.grd : msh_msh.dat Figure 2.11: 2-D cross section of a HBT hardened device. 24 Fig. 2.12 shows the terminals currents and the integral charges versus time in log scale. The two devices are constructed with identical geometries and doping profiles, except the area of NS layer, and simulated under the same conditions, including charge track properties, biasing voltages, etc. For emitter center deep strike, the deposited charge is isolated from the added pn junction by DT. Therefore, drift charge collections are approximately the same for regular and hardened HBTs. After drift charge saturates, the charges left in the substrate start to di?use outward towards the added pn junction instead of the intrinsic CS junction, which significantly reduces CS junction di?usion charge collection. 10 ?2 10 0 10 2 10 4 ?1 ?0.5 0 0.5 Time (ns) Charge collected (pC) ?2 ?1 0 1 2 Terminal Current (mA) Regular Hardened LET = 0.037 pC/um Drift dominate Diffusion dominate I B I C I E I S Q C Q S Q E Q B Figure 2.12: The terminal Currents and the integral charges versus time in log scale for regular and dummy collector hardened HBT. 25 Fabrication of dummy collector is done with a few layout changes. Devices are apart by several microns due to design rules, density requirement and other practical reasons. The unused silicon between the neighbouring devices can be utilized to create the dummy collector. Since multiple HBTs in a circuit can share the same dummy collector, the added dummy collector does not really su?er area penalty. Although the dummy collector can e?ectively reduce total collector charge collected, its impact on circuit SEU needs further investigation. Chapter 4 examines the impact of dummy collector hardening on DFF circuit. Note that the results cannot be generalized to all circuits as the tight coupling between device and circuit determines the circuit response to ion strike on a single device. 2.3 Conclusion A regular SiGe HBT is constructed and simulated under an emitter center deep ion strike. The deposited charges are collected through drift and di?usion. Drift charge collection is fast and dominates at the first several nanoseconds, while di?usion charge collection is much slower and lasts for several microseconds. The total amount of di?usion charge is comparable to that of drift charge. The reverse biased CS junction collects most of the charges. Dummy collector hardening technique is shown to be e?ective in reducing total collector charge by reducing di?usion charge collection. 26 CHAPTER 3 CIRCUIT SEU SIMULATION APPROACHES Fabricated SiGe HBTs are inherently robust to various types of ionizing radiation, in terms of both their dc and ac electrical characteristics [18]. However, high-speed SiGe HBT digital logic circuits were found to be vulnerable to SEU at even low LET values recently [5] [54]. In addition, successfully employed III-V HBT circuit-level hardening schemes were found to be ine?ective for these SiGe HBT logic circuits. To help understanding these SEU results, and to aid in the search for e?ective SEU mitigation approaches, mixed mode circuit simulations are required. Two kinds of circuit simulation approaches are normally used. One is done in DESSIS, namely true mixed mode. The other combines device simulation in DESSIS and circuit simulation in Cadence, namely combined mixed mode. Both of the approaches are detailed below, and the simulated results are compared. This chapter compares the results obtained from a combined mixed mode simulation and a true mixed mode simulation for a master-slave DFF. True mixed mode simulations are performed on analog emitter follower circuits, as will be shown in Chapter 5. In the analog emitter follower circuit the collector is at the supply potential while the emitter is at a lower potential. There is a shunt of the collector and the emitter terminal. The collector to emitter shunt current is complex due to the device/circuit interactions. Mixed mode simulations can capture the device/circuit interactions better. The mixed mode simulation neglects charge sharing when multiple devices are present. 27 3.1 True Mixed Mode Simulation DESSIS mixed mode simulation describes the struck transistor using 3-D device model, while the rest of the transistors using SPICE like compact models. The device and circuit equations are solved simultaneously with continuous boundary conditions at the contacts. The code in Fig. 3.1 shows an example circuit system with one 3-D HBT and several elements using compact models. The codes in the brackets after keyword "system" are used to describe the circuit elements and connection. The transistors defined by "BJT51" are described using Gummel- Poon (GP) model. The parameters for the GP model are transformed from the VBIC model in Cadence with corresponding design kit. The transistor defined by "HBT" is the 3-D HBT device constructed using MESH in Section 2.1.2. The numbers that follow the elements are node numbers, which represent the electric connection of the circuit. Figure 3.1: Example codes in DESSIS for mixed mode simulation. 28 Since all of the circuit elements are involved self consistently, the true mixed mode simulation is more accurate than the combined mixed mode. However, it is extremely time consuming. If there are a bunch of such simulations that need to be run, resource availability is a challenge. Fur- thermore, DESSIS supports only netlist description of circuit, making it di?cult to describe large scale circuits. Circuit connection errors, which may lead to unphysical results, are hard to diag- nose. Based on the reasons described above, in many cases, the combined mixed mode simulation is favorable, as described below. 3.2 Combined Mixed Mode Simulation Although the true mixed mode in DESSIS provides accurate SEU prediction, advanced tran- sistor models used by circuit designers are not supported by DESSIS currently, making true mixed mode simulation less attractive in practice. An alternative and popular methodology, namely com- bined mixed mode, is to simulate the SEE induced transient terminal currents using DESSIS, and then use the equivalent circuit in Section 2.1.4 in a conventional circuit simulator with advanced transistor model capability, e.g. Cadence Spectre in this work [42]. One strength of this approach is the large scale of the circuit that can be modeled. Another is its computational e?ciency. In principle, any transistor in the modeled circuit can be hit by a heavy ion. The biasing and loading conditions of the transistors are quite di?erent from each other. If the transient currents are based on device simulations of a struck unloaded device, the circuit simulation inherits the inaccuracy of device simulation. In practice, however, it is generally easy to identify the sensitive transistors and concentrate the analysis on those devices. Fig. 3.2 shows an example for loading the transient currents into Cadence. Transistor Q3 is chosen as the struck transistor and I CB , I CS are the two current sources representing charge 29 collection currents at CB and CS junctions. The current sources use the data files extracted from DESSIS 3-D device simulation as input files. Figure 3.2: An example of load SEE current source into circuit. Another advantage of combined mixed mode simulation is that I CB and I CS can be manually scaled to examine the LET dependence of circuit SEU qualitatively. Also, the sensitive transistor can be easily determined by simply applying I CB and I CS to di?erent transistors. In qualitative analysis, I CB and I CS can be modified manually. Meanwhile by varying the turn on time of I CB and I CS , the clock and data point dependence of digital circuit SEU can be explored. For any of the strategy above, it takes only a few seconds in Cadence. Compared to each simulation taking one or two weeks in DESSIS, it is more convenient and computationally e?cient. A natural question of practical importance is how the simulation results from true mixed mode and combined mixed mode compare with each other, which we address next in Section 3.3 for a CML circuit, a DFF. 30 3.3 Simulation Results Fig. 4.1 shows the schematic of a master-slave DFF. Simulations using true mixed mode and combined mixed mode simulation are compared. In principle, any of the transistors can be struck at any time. The two simulations compared here have Q3 struck at 3 nanosecond, which is a rep- resentative worst case as detailed in Section 4.1 In true mixed mode, Q3 is modeled in 3-D device domain, and the other transistors are modeled using GP model, e.g. "HBT" and "BJT51" in Fig. 3.1 respectively. The ion strike hits Q3 at 3 nanosecond. In combined mixed mode, current sources are added to the terminals of Q3 as shown in Fig. 3.2. The values of the current sources are calculated from base and collector transient currents using 3-D device simulation. These current sources are turned on at 3 nanosecond. ee V CS V Figure 3.3: Schematic of a master-slave DFF. 31 Fig. 3.4 compares the circuit outputs from true mixed mode simulation and combined mixed mode simulation for the circuit. Waveform Q+ represents the circuit positive output and ?M = (M+)?(M?) represents the di?erential voltage on the storage stage. The two types of simulations produce similar output waveforms. That is, for certain circuit SEU analysis, e.g. DFF, combined mixed mode simulation is su?cient, which will be applied on mechanism and regional analysis of DFF circuit SEU analysis in Chapter 4. ?1 0 0.5 ? M 2 3 4 5 6 7 ?0.4 0 0.2 Time (ns) Q+ Combined mixed mode True mixed mode ?1 ?0.7 ?0.3 0 CLK+ and D+ (a) (b) (c) LET = 0.037 pC/um D+ CLK+ Figure 3.4: Comparison between true mixed mode output and combined mixed mode output for a DFF. 32 3.4 Conclusion The advantages and disadvantages of two types of mixed mode simulation are introduced and discussed. The true mixed mode simulation using DESSIS solves device and circuit equations si- multaneously, which considers the interaction between the struck device and the left of the circuit naturally. This type of mixed mode simulation is accurate but time consuming as well as di?cult to realize. The combined mixed mode simulation models SEE of the struck device using current sources, which can be easily applied on large scale circuits, and provides qualitatively accurate sim- ulation results. The simulation results from the two types of mixed mode simulations are compared for an example circuit, a master-slave DFF. For the circuit examined, combined mixed mode is su?cient for circuit SEU analysis. 33 CHAPTER 4 MECHANISMS OF SINGLE EVENT UPSET IN DFF SiGe HBTs are robust to various types of ionizing radiation, but can be susceptible to SEU [55] [49]. At present, the SEU sensitivity is primarily attributed to the high resistivity or lightly doped substrate, and the associated large amount of both drift and di?usion charge collected by the collector through the reverse biased CS junction [46]. As a result, transistor-level hardening has focused on reducing CS junction charge collection, including the use of a dummy collector placed outside the DT isolation [3] [9], or removal of the CS junction using an SOI substrate [45]. Experi- mentally, transistor-level SEU sensitivity has been primarily characterized using the total amount of collector charge collected during an ion strike as a figure-of-merit [8] [9]. This, however, may not be accurate, as the CB junction charge collection current has recently been shown to dominate SEU in emitter followers via circuit action, despite the small collected charge involved [50]. The purpose of this chapter is to examine the di?erence in SEU of CML circuit, a master- slave DFF here, caused by CB and CS charge collection, respectively. For CS charge collection, we examine the di?erence in SEU impact between drift and di?usion charge collection. The CS junction di?usion charge is shown to have negligible impact on CML circuit SEU, despite the large amount of charge collected. The CB drift charge collection is shown to be relevant and impose the level of mitigation possible in transistor-level RHBD, (e.g, even in the extreme case of using SOI substrate) despite its small amount of charge collected. An ion track passing through the physical CS junction is found to be more e?ective in causing SEU than an ion track passing through only CS SCR but not intersecting the junction interface, because of the funneling-induced large current amplitude. 34 Implications on threshold LET, cross section, angular strike, and device hardening techniques are discussed. 4.1 Technical Approach The same CML master-slave DFF used in [56] is simulated here. Fig. 4.1 shows the circuit schematic. The switching current is 0.6 mA, and the voltage swing is 300 mV. The input data alternates between ?1? and ?0? bits at 2 Gbit/s unless otherwise specified. The simulations are first run using the combined mixed mode simulation in Section 3.2, then verified using the DESSIS mixed mode simulation in Section 3.1 that the conclusions are still valid . ee V CS V Figure 4.1: Schematic of a master-slave DFF. 35 The 3-D transistor using in this work is shown as in Chapter 2. In device simulation, the col- lector, base, and emitter nodes are grounded, and the substrate is held at -4 V. The simulated emitter current is negligible, as EB junction drift charge collection is small due to the narrow depletion layer. The base current is then mainly the CB drift current. The collector current is the sum of CB drift current, CS drift current and CS di?usion current. To mimic an ion strike, two current sources, I CB and I CS , were placed on the struck transistor, as shown in Fig. 4.2 [46] [47] [48] [49]. Here, I CB and I CS represent the ion strike induced charge collection currents at the CB and CS junctions, including both drift and di?usion currents. I CB is primarily drift dominated, while I CS hasadi?usion component for a typical deep strike. I CB is approximately equal to the ion-induced base current from 3-D device simulation. I CS is then determined from the di?erence of simulated collector and base currents. CB I CS I Figure 4.2: The equivalent circuit model used for including the charge collection currents in circuit simulation. Fig. 4.3 (a) shows a typical I CB and I CS response versus time. Fig. 4.3 (b) shows the corre- sponding integral charges Q CB and Q CS vs. time curves. Note that the final Q CB is only 0.05 pC, 36 much smaller than 0.6 pC Q CS . However, as we will show below, I CB is important for circuit SEU, despite the small Q CB . I CS is further separated into a drift and a di?usion component, I CS,drift and I CS,di? , at the point in time of drift charge saturation, as shown in Fig. 4.3 (a). CS di?usion charge is about 25% of total CS charge collection as Q CS,drift = 0.45 pC, Q CS,di? = 0.15 pC in Fig. 4.3 (b). Observe that I CS,di? is less than 0.004 mA, despite the large final charge Q CS,di? . This I CS,di? is much less than typical biasing currents used in CML gates (e.g., 0.6 mA in this work), and thus is not capable of producing circuit upset, as detailed below, even though it may last for several microseconds. ?1 ?0.5 0 0.5 1 1.5 Current (mA) 0 0.2 0.4 0.6 10 ?2 10 0 10 2 10 4 ?0.1 ?0.05 0 Time (ns) Charge collected (pC) Q CS,SEE ? Q CB,SEE I CS,SEE ? I CB,SEE 0.05pC/div 0.2pC/div (a) (b) Drift dominate Diffusion dominate Q CS,drift Q CS,total Q CS,diff LET = 0.037 pC/um I CS, diff < 0.004 mA Figure 4.3: The SEE induced CB and CS charge collection currents and the integral charges. 37 Simulations show that all eight transistors, Q1 to Q8 in Fig. 4.1, are SEU sensitive. Q12, Q13 and Q14 show less SEU sensitivity or higher threshold LET, while Q9, Q10 and Q11 show the least SEU sensitivity. For the discussions below, we will strike Q3 as an example. The excitations are turned on when Q3 is holding a "1" logic state, unless specified, as this represents a worst case for producing SEU. Fig. 4.4 shows the DFF output waveforms with I CS and I CB added to Q3 and turned on at 3 nanosecond, which is 100 picoseconds after the rising clock edge. Fig. 4.4 (a) shows ?M = (M+) ? (M?), which is the di?erential input signal to the slave stage. Q+ in Fig. 4.4 (b) is the positive output. Upset is observed at the output. An upset is also observed when the strike occurs on Q3 when Q3 holds a "0" logic state; that is, when Q3 is turned on. At the ion strike, the collector voltage becomes lower than its normal low, causing its CB junction to be forward-biased and driving the transistor into saturation. When the next "1" bit comes, if Q3 is not able to recover from saturation, the output will continue to show a "0" rather than "1", e?ectively causing an upset. 4.2 Drift vs. Di?usion Charge Collection To better evaluate the individual impact of various charge collections mechanisms, di?erent current excitations representing di?erent components of collector charge collection were simulated. Three cases were compared: 1. only drift currents, with I CB and I CS,drift turned on. Note that I CB is purely drift in origin. 2. with only di?usion current I CS,di? turned on. 3. both drift and di?usion currents turned on. 38 ?1 ?0.7 ?0.3 0 CLK+ and D+ ?1 0 0.5 ? M 2 3 4 5 6 7 ?0.4 0 Time (ns) Q+ (a) (b) LET = 0.037 pC/um Ion Strike @ "1" D+ CLK+ Figure 4.4: Output waveform from transient simulation result for the DFF. In all cases, the time axis of the original current sources obtained from device simulation was shifted to excite the circuit at the same starting time. The results are shown in Fig. 4.5. The Q+ with all currents is identical to the Q+ with drift currents alone, both showing upsets, while the Q+ with only di?usion current shows no upset. The actual simulation was performed for tens of microseconds, much longer than the di?usion charge collection time, and no upset was observed. To account for the slow nature of di?usion collection, simulations were also performed with a static clock, which holds the data in the storage cell indefinitely, as in an SRAM. The results are shown in Fig. 4.6. Still, no upset is observed for the I CS,di? only case. This is attributed to the 39 ?1 ?0.7 CLK+ ?1 0 0.5 ? M 2 3 4 5 6 7 ?0.4 0 Time (ns) Q+ 0 1 2 Ion Strike @ "1" (a) (b) I CB I CS,drift 100 x I CS,diff Currents (mA) (c) I CB +I CS,drift +I CS,diff and I CB +I CS,drift I CS,diff only LET = 0.037 pC/um Figure 4.5: Comparison of the simulated ?M and Q+, with drift and di?usion currents activated individually. current mode operational nature of CML circuits, and the small magnitude of I CS,di? (.004 mA). Since I CS,di? is much less than the biasing current, ?V = I CS,di? R C,load is on the order of 2 mV, much less than the voltage swing. Here R C,load is the load resistor at the collector of Q3. This small ?V variation is restored by the circuit itself through cross-coupling between Q3 and Q4, and no upset is produced. 40 ?1 ?0.7 CLK+ ?1 0 0.5 ? M 2 3 4 5 6 7 ?0.4 0 Time (ns) Q+ Ion Strike @ "1" (a) (b) I CS,diff only I CB +I CS,drift +I CS,diff and I CB +I CS,drift LET = 0.037 pC/um Figure 4.6: Comparison of the simulated ?M and Q+ with drift and di?usion currents activated individually, for a static clock. 4.3 CB Drift Charge vs. CS Drift Charge For the LET used, Q CB is about one tenth of Q CS,drift . However, its impact on circuit SEU is much stronger than the charge magnitude might suggest, because I CB appears in the feedback path between collector and base, where it is amplified by the transistor. This directly raises the base voltage and indirectly increases the collector current, which exponentially depends on base-emitter voltage. The process is further enhanced by the cross-coupling of Q3 and Q4. Fig. 4.7 (b) and (c) compare ?M and Q+ from simulations with I CB and I CS,drift activated individually. Both I CB and I CS,drift cause circuit upset. I CB is actually ?more e?ective? than I CS , since only very little Q CB is necessary to produce SEU. 41 ?1 ?0.7 CLK+ ?1 0 0.5 ? M 2 3 4 5 6 7 ?0.4 0 Time (ns) Q+ 0 1 2 Ion Strike @ "1" (a) (b) I CB,drift I CS,drift Currents (mA) (c) I CS,drift only I CB,drift only LET = 0.1 pC/um Figure 4.7: Comparison of the simulated ?M and Q+ with CB and CS drift currents activated individually. 4.4 Regional Charge Collection Analysis A more elaborate approach to study the di?erent charge collection mechanisms is by using selective ion track placement in di?erent regions of the SiGe HBT. Simulations were performed for the following ion track placement: 1. Ion track is placed only in the EB and CB junctions. This should produce primarily CB drift current. 42 2. Ion track is placed only in the CS junction. This should produce CS drift and di?usion currents. 3. Ion track is placed below the CS junction, but through part of its SCR. This should produce CS drift and di?usion currents. The di?erence from the previous case, however, is that the ion track does not pass through the junction interface. 4. Ion track is placed well below the CS SCR. This should produce only CS di?usion current. All of these cases are compared with placing the ion track through the whole device. A schematic illustration is given in Fig. 4.8. Fig. 4.9 (a) and (b) show the simulated I CB , I CS and the corresponding integral charge versus time, respectively. The results are close to our expectations. I CB is produced only in the two place- ments that traverse the CB junction, and I CB is primarily caused by drift. The ion track that passes the CS junction only produces only CS drift and di?usion charge collection. The ion track passing through part of CS SCR produces less drift current and charge, but about the same total collected charge. The ion track placed below the CS SCR causes only CS di?usion charge collection, and no drift charge collection, as expected. Fig. 4.10 compares the circuit output waveforms. There is no upset when the ion track passes part of CS SCR or below CS SCR. In all other cases, upset is observed. It is worth noting that the ion strike passing part of CS SCR produces 0.25 pC of drift charge, which is significant. However, the overall current magnitude is much less compared to the strike passing through CS junction, as can be seen from Fig. 4.9. The I CS peak is above 1 mA when the ion track passes through CS junction, and below 0.2 mA when the ion track does not pass through the junction. This current di?erence, rather than the drift charge di?erence, is the reason why upset is not observed with a 0.25 pC drift charge, and originates from the fact that the ion track does not pass through the CS 43 junction interface. We will further discuss this in detail below. We will see that a smaller 0.22 pC CS drift charge can actually produce upset when the ion strike passes through the CS junction. 4.5 Threshold LET and the SOI Limit Fig. 4.11 plots the CS, CB and the total drift charge versus LET for a deep strike at emitter center. When the LET is below 0.02 pC/?m, the relationship between Q drift and LET is linear. The drift current itself is also approximately linear with LET. This provides an excellent way of speeding up the process of determining threshold LET, as one can take 3-D simulation results at one LET and scale the currents continuously with LET so that threshold LET can be determined by only re-running circuit simulation (not device TCAD). The process can be automated through a parametric sweep in circuit simulators. At higher LET, the linear relationship becomes less valid. Also shown in Fig. 4.11 are the threshold LET, defined as the LET at which upset starts to be observed, and the corresponding drift charge for three cases: 1) I CB,drift only, Q drift = 0.025 pC, LET threshold = 0.02 pC/?m. 2) I CS,drift only, Q drift = 0.22 pC, LET threshold = 0.02 pC/?m. 3) I CB,drift and I CS,drift , Q drift = 0.0074 pC, LET threshold = 0.008 pC/?m, that is, 0.8 MeV?cm 2 /mg. This is consistent with the experimental result of [5] at a similar data rate. In [5], cross sections were appreciable at LET of 1.4 MeV?cm 2 /mg with C-12. Note that even though I CS,drift and I CB,drift give the same threshold LET in Fig. 4.11, this should not be generalized to all technologies. The I CB only case corresponds to the use of SOI substrate, which eliminates the CS junction. Although SOI can decrease total collector charge by 10 times, the threshold LET, however, shows much less improvement since CB charge collection is more e?ective. This suggests that the CB charge collection poses a limit to achievable device-level hardening. 44 4.6 Importance of Junction Passing and Potential Funneling Note that the CS junction drift charge at a threshold LET of 0.02 pC/?m is 0.22 pC in Fig. 4.11 for the CS drift charge only case. Recall that in the partial passing through the CS SCR case of Fig. 4.9, LET = 0.037 pC/?m, the drift charge is a higher 0.25 pC, but no upset is produced in that case. The main di?erence is that the overall current is much higher when the ion passes though the CS junction, due to potential funneling. This result suggests that the drift charge number alone cannot be used as an indicator for CML circuit upset. Whether a strike passes through the junction interface is also very important, as the current magnitude is much larger for junction passing strikes due to potential funneling. Observe that for the junction passing case, LET = 0.02 pC/?m, while for the passing CS SCR case, LET = 0.037 pC/?m. The induced I CS is much larger in the junction passing case, despite a smaller LET. The importance of potential funneling therefore not only lies in the amount of drift charge collected, which is well known, but more importantly, the high rate of charge collection or high drift current. This is particularly the case for CML circuits. For angular strikes, particularly those at a large angle, some of the ion tracks may not pass the whole CS junction, but only part of CS SCR. An extreme case would be horizontal (parallel to the surface) ion tracks below the CS junction interface. This will certainly reduce the CS drift current compared to a vertical strike. For smaller angles, the ion track still intersects with the junction, but will su?er from limited potential funneling because of the presence of the DT, and hence reduced drift current magnitude. This should make angular strikes produce less circuit SEU than predictions from traditional sensitive volume theory that only considers charge deposition in a sensitive volume, which could potentially explain the angular dependence data in [5]. 45 4.7 Error Cross Section From an error cross section standpoint, for a given transistor in the circuit, the sensitive area for a given LET should be a function of both the CB and CS sensitive areas. Fig. 4.12 shows the sensitive areas for CB and CS junction charge collection. The CB junction area is defined by the active area between STIs. The CS junction area is defined by the silicon area enclosed by the DT ring, which is typically over 10 times larger than the CB junction area. The cross section for an LET larger than the threshold LET of I CB,drift and I CS,drift case is determined by CB junction area, while the cross section for an LET larger than the threshold LET I CS,drift only case is determined by CS junction area. The error cross section can thus be reduced by using an SOI substrate, as the ion strike sensitive area is limited to CB junction area. Given the di?erent threshold LET of di?erent transistors, the overall circuit SEU cross section should increase with increasing LET. 4.8 Outside DT Charge Deposition Experimentally, outside DT deep strikes were shown to produce significant amounts of charge, and were suspected to cause digital circuit SEU [3]. The underlying physical mechanism, however, is the di?usion of charge deposited deep in the substrate. This will only contribute to I CS,di? ,but not I CB or I CS,drift , as further verified by selective ion track placement simulations. According to the new simulation results above, outside DT strikes should not produce SEU in CML circuits. Additional device simulations for outside DT strikes were performed, and the corresponding circuit simulations indeed show no circuit level upset, despite the appreciable amount of final charge collection. This observation significantly a?ects how SEU sensitive area or cross section should be calculated. The same argument applies to charges deposited outside the DT by angular ion strikes. 46 4.9 Dummy Collector Hardened SiGe HBT A dummy collector was proved to be e?ective in reducing CS junction di?usion charge col- lection using both device simulation and microbeam testing [3] [9]. As drift charge collection is responsible for SEU, we expect such hardening to be ine?ective for CML circuits. Fig. 4.13 (a) and (b) compare I CB , I CS , Q CB , and Q CS for the regular and the hardened HBT. The dummy collector is biased at +3 V. Fig. 4.14 compares ?M and Q+ for circuits using a hardened HBT and regular HBT. No SEU improvement is observed, as expected. Even though dummy collector does not improve CML circuit SEU, the removal of di?usion current on the order of?A for tens of microseconds can be significant for many analog, mixed-signal and RF circuits. Circuit topology clearly matters. 4.10 Conclusion The individual contributions of charge collection in the CB and CS junctions to SEU in SiGe HBT CML digital circuits are examined. The voltage change introduced by CS junction di?usion charge collection is negligible compared with the signal voltage swing. Such voltage change is re- stored through circuit operation, and no SEU is produced. The CS and CB drift charge collections are primarily responsible for CML SEU. The CB drift charge collection is shown to be more e?ec- tive than CS drift charge collection in producing circuit SEU, and will ultimately set the threshold LET in an SOI process. The dummy collector hardening technique shows no SEU improvement in CML circuits, as it reduces only di?usion charge collection. Using selective ion track placement, we showed that for the same amount of CS drift charge, the ion track that passes through the phys- ical junction is much more e?ective in causing SEU, due to potential funneling and the resulting 47 high current magnitude. Implications to outside DT charge deposition, angular strike, and dummy collector hardening are discussed. 48 Figure 4.8: Illustration for regional charge collection analysis. 49 ?1 ?0.5 0 0.5 1 1.5 Current (mA) 0 0.2 0.4 0.6 10 ?2 10 0 10 2 10 4 ?0.1 ?0.05 0 Time (ns) Charge collected (pC) EB CB CS junction EB CB junction CS junction Part of CS SCR Below CS SCR ? Q CB,SEE I CS,SEE ? I CB,SEE 0.05pC/div 0.2pC/div (a) (b) Drift dominate Diffusion dominate LET = 0.037 pC/um Q CS,SEE Figure 4.9: Terminal currents and charge for regional charge collection analysis. 50 ?1 ?0.7 CLK+ ?1 0 0.5 ? M 2 3 4 5 6 7 ?0.4 0 Time (ns) Q+ EB CB CS junction EB CB junction CS junction Part of CS SCR Below CS SCR Ion Strike @ "1" (a) (b) LET = 0.037 pC/um Figure 4.10: Circuit output comparison for regional charge collection analysis. 51 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0 0.1 0.2 0.3 0.4 LET (pC/?m) Drift Charge (pC) CB junction CS junction Total Collector Threshold LET Drift Charge at Threshold LET ? ? ? ? ? linear fitting Figure 4.11: The drift charge collected at CB and CS junctions, individually, and the total collector drift charge versus LET. 52 Figure 4.12: Sensitive areas for CB and CS junction charge collection in 2-D cross section illustra- tion. 53 ?0.5 0 0.5 1 1.5 Current (mA) 0 0.2 0.4 0.6 10 ?2 10 0 10 2 10 4 ?0.1 ?0.05 0 Time (ns) Charge collected (pC) Regular Hardened Q CS,SEE ? Q CB,SEE I CS,SEE ? I CB,SEE 0.05pC/div 0.2pC/div (a) (b) Drift dominate Diffusion dominate Q CS,drift Q CS,total Q CS,diff LET = 0.037 pc/um Figure 4.13: The SEE induced CB and CS charge collection currents and the integral charges for regular and hardened SiGe HBTs. 54 ?1 ?0.7 CLK+ ?1 0 0.5 ? M 2 3 4 5 6 7 ?0.4 0 Time (ns) Q+ 0 1 2 Regular Hardened Ion Strike @ "1" (a) (b) I CS (mA) (c) LET = 0.037 pC/um Figure 4.14: Comparison of the simulated ?M and Q+ with CB and CS currents from regular and hardened SiGe HBTs. 55 CHAPTER 5 SINGLE EVENT TRANSIENTS IN EMITTER FOLLOWERS This work is started to answer circuit designer?s questions on how to optimize circuit design to minimize SET in emitter followers. As the emitter current determines output, using a higher biasing emitter current seems to be a logical hardening approach. The basic idea is to make SEE induced transient emitter current smaller than the biasing emitter current. This is in fact what designers first proposed. However, our simulations show this intuitive approach is completely incorrect, as it does not consider the complex operation of the circuit during SET. Various RHBD techniques at both device and circuit levels have been developed to improve SEE [45] [44] [3] [9]. These techniques focus on collector charge collection, particularly through the reverse biased CS junction, the dominant path, and therefore apply to circuits in which the collector current determines circuit output, such as ECL circuits. However, such techniques do not apply to circuits where the emitter current determines circuit output. An example is emitter follower, which is widely used as output bu?er, unity voltage gain amplifier, dc power regulator in analog circuits, as well as level shifter in ECL circuits. This chapter investigates SET in SiGe HBT emitter followers using true mixed mode simulation, and provides hardening guidelines. This chapter is organized as follows. In Section 5.1, the 3-D simulation details and circuit topology of an emitter follower are described. Section 5.2 describes the SET simulation results in three typical emitter followers. Section 5.4 to 5.8 further examines the impact of biasing current and biasing resistance on SET individually by varying only the design parameter in question while keeping everything else the same. A critical result is that the emitter voltage SET follows the base voltage SET by the very nature of circuit operation of an emitter follower, which in turn is 56 determined by base charge collection. Section 5.9 examines the impact of ion strike position, depth, and LET. Section 5.10 examines the optimization of base biasing resistance for reduced emitter voltage SET. 5.1 Simulation Details and Circuit Topology The 3-D transistor used in this work is from the IBM 8HP SiGe HBT technology, which is from a more advanced technology compared with the device used in Chapter 2 and 4. The n-p-n-p structure is the same, but the layout of the contacts and the doping profile are di?erent. Fig. 5.1 shows the 2-D cross section of this advanced transistor. The transient simulation conditions are also a little di?erent from simulations in Chapter 2 and 4. The silicon substrate has an area of 25?m ? 25?m and a depth of 35?m. The normal deep ion strike through the emitter center has a uniform LET of 0.1pC/?m (10MeV-cm 2 /mg). The charge track was generated using a Gaussian waveform, with an 1/e characteristic time scale of 2 picosecond and an 1/e characteristic radius of 0.2 ?m. The peak of the Gaussian occurs at 6 picoseconds. Fig. 5.2 shows the circuit topology of a typical emitter follower. Unless specified, the dc power supply V CC is 3.3V. The base biasing resistance R BB , base biasing current I BB , emitter biasing resistance R EE , and emitter biasing current I EF are the design parameters. Emitter followers with multiple R BB , I BB , R EE , and I EF combinations are carefully designed and simulated to find out how to minimize duration and magnitude of emitter voltage SET. 5.2 SET in Typical Emitter Followers We first consider three emitter followers with design parameters shown in Table 5.1. I EF , R EE , I BB , and R BB are chosen such that the quiescent emitter voltage V E,Q is 2.24V for a V CC of 57 Figure 5.1: 2-D cross section of an 8HP regular HBT. Table 5.1: Design parameters for three typical emitter followers. Name R EE (?) R BB (?) I BB (?A) I EF (?A) EF1 5000 200 1300 450 EF2 2000 200 1100 1120 EF3 1000 1600 140 2200 3.3V. The base quiescent voltage V B,Q is only slightly di?erent among the three emitter followers, as I E exponentially depends on V BE . Fig. 5.3 (a) compares the output emitter voltage of the three emitter followers. The peak V E deviation is relatively close for the three designs. However, the design with highest I EF shows the longest (worst) duration. The results at least suggest that a high I EF does not guarantee reduced 58 CC V BB R BB I EE R EF I Figure 5.2: The circuit topology of a typical emitter follower. emitter voltage SET. To further clarify the impact of I EF , we will vary only I EF while keeping everything else the same in Section 5.4 to 5.8. Fig. 5.3 (b) compares the SEE induced emitter current I E,SEE for the three circuits. I E,SEE is defined as I E,SEE = ?(I E ? I E,Q ). I E and I E,Q are the transient and quiescent current flowing out of the emitter. I E,Q = I EF . The positive direction of I E,SEE is defined as entering the emitter. I E,SEE is not dominated by EB junction charge collection, which would give a positive I E,SEE , while the simulated I E,SEE is negative in all cases. It is not dominated by ion track shunt e?ect [47] either, even though the resulting I E,SEE would be negative, because V CE is the lowest for the highest I E,SEE , as shown in Fig. 5.3 (c). Instead, I E,SEE follows V E through I E,SEE = ?(V E /R EE ?I EF ). (5.1) 59 The impact of ion track shunt e?ect will be further investigated using an o?-center ion strike in Section 5.9.1. 0 50 100 150 200 250 300 0 1 V CE (V) timee (psec) ?1 0 I E,SEE (mA) 2 3.3 V E (V) EF1, R BB =200?, R EE =5k?, I EF =450?A EF2, R BB =200?, R EE =2k?, I EF =1.12mA EF3, R BB =1.6k?, R EE =1k?, I EF =2.22mA (a) (b) (c) Figure 5.3: SET on three typical emitter followers. (a) V E , (b) I E,SEE , and (c) V CE versus time. Now we have established that I E,SEE is not a result of the normal pn junction and ion track shunt charge collection. The only next possibility is that it is a result of interaction between circuit and charge collection. Fig. 5.4 (a) and (b) show the base voltage V B and the SEE induced base current, I B,SEE = I B ?I B,Q . Again, I B,SEE flowing into the base is defined as positive. V B can be determined from I B,SEE as V B = V B,Q ?I B,SEE R BB . (5.2) Observe that the V E SET waveform closely follows the V B SET waveform, which is a result of the emitter voltage following base voltage nature of the emitter follower circuit operation, despite the 60 ion strike. During the following process, V E is limited by V CC . V B follows I B,SEE according to (5.2). I E,SEE actually originated from I B,SEE and hence base charge collection. V E upset is thus mainly a result of V B upset, which then depends on I B,SEE R BB product. I B,SEE lasts longer for design EF3, because of the largest R BB in the path of CB junction charge collection. The EB junction total volume is very small compared to the CB junction volume, thus the base charge collection observed is dominated by CB junction collection. Here the collector is ac grounded, while the base node sees R BB . Fig. 5.4 (c) shows the base collected charge Q B,SEE obtained from integration of I B,SEE vs time data [42]. The final total amount of charge collected is about the same for all 3 designs, as expected. 0 50 100 150 200 250 300 ?0.08 ?0.04 0 Q B,SEE (pC) time (psec) ?2 ?1 0 I B,SEE (mA) 3 3.5 4 V B (V) EF1, R BB =200?, R EE =5k?, I EF =450?A EF2, R BB =200?, R EE =2k?, I EF =1.12mA EF3, R BB =1.6k?, R EE =1k?, I EF =2.22mA (a) (b) (c) Figure 5.4: SET on three typical emitter followers. (a) V B , (b) I B,SEE , and (c) Q B,SEE versus time. The above analysis concludes that R BB is what determines the emitter voltage SET waveform. EF1 and EF2 have identical R BB and thus the same V E SET waveforms. EF3 has a larger R BB . 61 The higher impedance slows down base charge collection, leading to the longest V E SET. V E can- not exceed V CC in this process. More mixed mode DESSIS simulations are done to examine the individual impact of design parameters in Section 5.4 to 5.8 . 5.3 Biasing Current and Resistance Dependence To examine the impact of the four design parameters, I EF , R EE , I BB , and R BB separately, the circuit topology in Fig. 5.2 must be modified slightly. For example, to investigate the impact of I EF individually, emitter followers with di?erent I EF but the same I BB , R BB , and R EE must be simulated. V B,Q are the same for the three circuits since I BB , and R BB are the same. Then, there will be a voltage shift at V E,Q , since V E,Q = I EF R EE . This, however, will cause an additional exponential change of I EF as V BE varies. An independent dc voltage source V EE , as shown in Fig. 5.5 (a), must be added to compensate the shift of V E,Q . For smaller I EF , V EE is positive, and for larger I EF , V EE is negative, since now we have V E,Q = V EE +I EF R EE . The same schematic can be used for designs with di?erent R EE . Similarly, an independent voltage source has to be used to compensate the voltage shift at V B,Q when examining the impact of I BB and R BB in singles. Fig. 5.5 (b) gives the schematic for simulations with varying I BB or R BB . A separate voltage source V BB is added. With V BB , the base biasing voltage is calculated as V B,Q = V BB ? parenleftbig I BB +I B,Q parenrightbig R BB . 5.4 Emitter Biasing Current Dependence As mentioned before, one intuitive approach to reduce emitter voltage SET is to increase the emitter biasing current I EF so that the SEE induced emitter current can be made less significant, as parenleftbig I EF +I E,SEE parenrightbig R EE determines V E . We have however shown earlier using the three typical 62 CC V BB R BB I EE R EF I EE V CC V BB R BB I EE R EF I BB V Figure 5.5: The schematic of emitter followers used to examine the impact of (a) I EF and R EE , and (b) I BB and R BB , on emitter voltage SET individually. designs that a largerI EF does not guarantee reducedV E SET. In those designs, all design parameters are varied inevitably due to circuit constraints. We now vary I EF only using the circuit shown in Fig. 5.5 (a). Three emitter followers with di?erent I EF are designed and simulated. One of them is EF2 with I EF =1.12mA. The other two emitter followers have I EF =480?A and I EF =2.2mA. V EE =1.34V for I EF =480?A, and V EE =- 2.16V for I EF =2.2mA. The three circuits have the same R BB , I BB , R EE as EF2, but a sightly di?erent V E,Q to allow the shift in V BE and then I EF . The simulation results are shown in Fig. 5.6. First, the rate, duration, and total amount of base charge collection are approximately the same for the three circuits with varying I EF , as shown in Fig. 5.6 (a) and (b). The three circuits have practically identical V E SET output as expected, which follow V B SET very well, as shown in Fig. 5.6 (c) and (d). Since R EE are the same for the three 63 circuits, I E,SEE are approximately the same, and thus are not shown here. This further confirms our earlier analysis that I EF can barely a?ect SET of emitter follower. ?0.08 ?0.04 0 Q B,SEE (pC) 0 50 100 150 200 250 300 2 3.3 V E (V) time (psec) 3 3.5 V B (V) ?2 ?1 0 I B,SEE (mA) I EF = 480?A I EF = 1.12mA (EF2) I EF = 2.2mA R BB =200?, R EE =2k?, I BB =1.1mA (a) (b) (c) (d) Figure 5.6: SET on emitter followers with di?erent emitter biasing current. (a) I B,SEE , (b) Q B,SEE , (c) V B , and (d) V E versus time. 5.5 Emitter Biasing Resistance Dependence Again, for further verification of the impact of R EE , two emitter followers with the same I EF , I BB and R BB , but di?erent R EE are compared with EF2. Here we choose to use R EE =1k? and R EE =5k?. The other design parameters are chosen to be the same as in EF2, that is, I EF =1.12mA, I BB =1.1mA, R BB =200?, V B,Q =3.08V, and V E,Q =2.24V. Recall that R EE = 2k? and V EE = 0V 64 in EF2. To achieve the same V E,Q with multiple R EE , we use V EE =1.1V for R EE =1k? and V EE =- 3.3V for R EE =5k? in the schematic of Fig. 5.5 (a). Fig. 5.7 (a) and (b) show SEE induced base current and base collected charge versus time. Neither the base current transient nor the base charge collected is dependent on R EE . Fig. 5.7 (c) shows that V E from the three circuits are practically identical. A larger R EE does lead to a lower I E,SEE , as shown in Fig. 5.7 (d), since I E,SEE = ? ((V E ?V EE )/R EE ?I EF ). (5.3) Thus, R EE has negligible e?ects on emitter voltage SET, despite its large impact on the emitter current SET. 5.6 Base Biasing Current Dependence To examine the impact of I BB on V E SET, two emitter followers with I BB =140?A and 2.2mA are simulated and compared with EF2 (I BB =1.1mA). The schematic in Fig. 5.5 (b) is used to achieve the sameV B,Q . V BB =3.11V forI BB =140?A, andV BB =3.52V forI BB =2.2mA.I EF =1.12mA, R BB =200?, R EE =2k?, and V CC =3.3V for all three circuits. As long as V B,Q is fixed, the value of I BB should have no e?ects on base charge collection and emitter voltage upset. I B,SEE and Q B,SEE in Fig. 5.8 (a) and (b) are identical for the three circuits as expected. Fig. 5.8 (c) and (d) show that the V E SET from three circuits are identical, and follow the V B SET exactly. This concludes that I BB has no e?ects on base charge collection, and then does not a?ect emitter voltage SET at all. 65 ?0.08 ?0.04 0 Q B,SEE (pC) ?2 0 I B,SEE (mA) 0 50 100 150 200 250 300 ?0.5 0 I E,SEE (mA) time (psec) 2 3.3 V E (V) R EE =1k? R EE =2k? (EF2) R EE =5k? (a) (b) (c) (d) Fixed Q?point V BE =0.84V, V CE =1.06V, I EF =1.12mA Figure 5.7: SET on emitter followers with di?erent emitter biasing resistance. (a) I B,SEE , (b) Q B,SEE , (c) V E , and (d) I E,SEE versus time. 5.7 Base Biasing Resistance Dependence For further verification and better insight into R BB ?s e?ect, we vary R BB in Fig. 5.5 (b), while keeping I EF , R EE , V B,Q , V E,Q , and V CC the same as in EF2. V BB =3.3V. To keep V B,Q the same, we choose I BB =1.1mA, 140?A, 70?A for R BB = 200?, 1.6k?, and 3.2k?, since V B,Q = V BB ? (I BB +I B,Q )R BB . The di?erence in I BB will not a?ect SET, as we have shown in Section 5.6. Fig. 5.9 (a) compares I B,SEE for di?erent R BB . A larger R BB reduces the charge collection speed, which leads to a lower charge collection current, and a longer SET duration. However, the total amount of charge collected by the base are approximately the same for di?erent R BB , as shown 66 ?2 ?1 0 I B,SEE (mA) 3 3.5 V B (V) 0 50 100 150 200 250 300 2 3.3 V E (V) time (psec) ?0.08 ?0.04 0 Q B,SEE (pC) I BB =140?A I BB =1.1mA (EF2) I BB =2.2mA Fixed Q?point V BE =0.84V, V CE =1.06V, I EF =1.12mA (a) (b) (c) (d) Figure 5.8: SET on emitter followers with di?erent base biasing current. (a) I B,SEE , (b) Q B,SEE , (c) V B , (d) V E versus time. in Fig. 5.9 (b) and expected from CB junction charge collection mechanism. The peak I B,SEE decreases as R BB increases. As R BB increases from 200? to 1.6k?, by a factor of 8, the peak I B,SEE decreases by only 4?. The SEE induced voltage change on R BB is doubled. Since I B,SEE is negative, V B for higher R BB is higher from (5.2). Fig. 5.9 (c) compares V B for di?erent R BB . The peak V B SET increases as R BB increases, until it reaches a limit of 4V. The duration increases significantly as R BB increases after V B reaches 4V. The relationship between SET duration and R BB will be further discussed in Section 5.10. The V E SET waveforms in Fig. 5.9 (d) clearly show that V E is highly R BB dependent and follows V B SET as expected. As R BB increases, the level and 67 duration of V E upset increase. The peak value of V E is limited by V CC =3.3V. V E upset and I E,SEE are not dominated by SEE induced charge collection at the emitter. Instead, V E upset simply follows the V B upset for reasons discussed above. ?0.08 ?0.04 0 Q B,SEE (pC) ?2 0 I B,SEE (mA) 3 4 V B (V) 0 50 100 150 200 250 300 2 3.3 V E (V) time (psec) R BB =200? (EF2) R BB =1.6k? R BB =3.2k? (a) (b) (c) (d) Fixed Q?point V BE =0.84V, V CE =1.06V, I EF =1.12mA Figure 5.9: SET on emitter followers with di?erent base biasing resistance. (a) I B,SEE , (b) Q B,SEE , (c) V B , and (d) V E versus time. 5.8 CB Voltage Dependence From previous analysis, V E SET is determined by base charge collection. R BB is the most important design parameter for optimizing emitter follower SET, because R BB is the impedance on base charge collection path. The higher the impedance, the lower the base charge collection 68 rate, the longer the base charge collection time. V CB is another dominant factor that a?ects base charge collection. To examine the e?ects of V CB , Two emitter followers with V CB =-0.5V and 1V are compared with EF2 (V CB =0.22V). The schematic in Fig. 5.5 (b) is used here. I EF =1.12mA, V BB =3.3V, R BB =200?, R EE =2k? for the three circuits. The other design parameters for the three circuits are: 1. I BB =1.075mA, V CC =2.58V. 2. I BB =1.1mA, V CC =3.3V (EF2). 3. I BB =1.13mA, V CC =4.08V. As V CB increases, the CB junction field increases, which should lead to a faster base charge collection. The total amount of charge collected should not change much. With increasing V CB , we observe a higher peak value and a shorter duration of I B,SEE in Fig. 5.10 (a) and the same total amount of charge collected by base in Fig. 5.10 (b), as expected. Fig. 5.10 (c) compares V B for di?erent V CB . As a consequence of the faster base charge collection at higher V CB , V B determined by I B,SEE from (5.2) has a higher peak value and a shorter duration. V E in Fig. 5.10 (d) follows V B . However, the peak of V E is still limited by V CC . It does not exceed V CC for all cases. 5.9 Ion Strike Dependence 5.9.1 Position and Depth Dependence In Section 5.2, we have shown that the ion track shunt e?ect is not important for I E,SEE , and I E,SEE is mainly a result of V E following V B . Furthermore, V B SET is primarily determined by base charge collection through the CB junction. 69 ?3 ?2 ?1 0 I B,SEE (mA) 3 3.5 4 V B (V) 0 50 100 150 200 250 300 2 2.58 3.3 4.08 V E (V) time (psec) ?0.08 ?0.04 0 Q B,SEE (pC) V CB = ?0.5V V CB = 0.22V (EF2) V CB = 1V R BB =200?, R EE =2k?, I EF =1.12mA (a) (b) (c) (d) Figure 5.10: SET on emitter followers with di?erent CB voltage. (a) I B,SEE , (b) Q B,SEE , (c) V B , and (d) V E versus time. These results can be further verified by varying the position and depth of ion strike. We choose two ion strike positions, one at the emitter center, and the other in the middle of the extrinsic base. This is illustrated in a 2-D cross section in Fig. 5.11. The ion track for the center strike, ION 1 , shunts the emitter and collector, while the o? center strike track, ION 2 , does not. A comparison of the two strikes would directly show any ion track shunt e?ect on the circuit. We also reduce the depth of the ion strike for the o? center strike such that charge deposition occurs only above the n + buried layer. As this strike does not go through the EB junction or the CS junction, the only junction 70 involved is the CB junction. This o? center shallow strike allows us to examine if CB junction is indeed the dominant charge collection path responsible for SET in emitter followers. The simulation results for EF2 are shown in Fig. 5.12 for the above three ion strikes. I B,SEE , Q B,SEE , I E,SEE and V E are approximately identical for all three ion strikes. This provides ad- ditional verification to our conclusion that the emitter voltage SET primarily originates from CB junction charge collection. From a cross section standpoint, we expect an improvement over circuits in which collector current determines output. In that case, the CS junction is the dominant charge collection path, and the area enclosed inside the DT isolation around the HBT approximately defines the area for maximum collector charge collection [43]. For emitter followers, we are concerned with the area for maximum base charge collection, which is defined by the STI [43]. This is illustrated in Fig. 5.11. When the ion strike is in between the STIs, base charge collection maximizes, and the resulting emitter voltage SET is the same. 5.9.2 LET Dependence The EF2 circuit, which shows best SET tolerance, is simulated for di?erent LETs. Fig. 5.13 (a) indicates that the higher LET, the longer it takes for the charge to be collected, even though the charge collection is faster. The total amount of charge collected increases accordingly as shown in Fig. 5.13 (b). Since base charge collection rate and time determine base voltage upset, a higher LET further leads to a worse V B upset. With increasing LET, a larger and longer V B upset is observed in Fig. 5.13 (c). Fig. 5.13 (d) compares V E under three LETs. V E follows V B , but is limited by V CC , and thus its magnitude will saturate as LET increases. Note that there is a small V CE saturation voltage di?erence between V CC and V E . 71 Figure 5.11: Illustration of the ion tracks for a center strike and an o? center strike. 5.10 Hardening Implications From previous analysis, the impedance and electric field across the CB junction dominate V E SET of an emitter follower. Therefore, R BB and V CB are the most important factors for emitter follower SET. V CB is normally limited by the supply voltage and headroom considerations. This leaves R BB the only variable to be optimized for reducing SET. To identify the relationship between R BB and V E SET, more emitter followers with R BB rang- ing from 5? to 3.2k? are designed and simulated. We note that 5? represents a low extreme, and in practice R BB is much higher. Fig. 5.14 (a) compares V E for six R BB .AsR BB decreases, V E SET is first reduced dramatically, especially the duration of V E SET. When R BB is below 50?, further decrease of R BB does not help reducing V E SET. Instead, V E SET reaches a low limit with 72 0 50 100 150 200 250 300 2 3.3 V E (V) time (psec) ?0.4 ?0.2 0 I E,SEE (mA) ?2 ?1 0 I B,SEE (mA) ?0.08 ?0.04 0 Q B,SEE (pC) ION 1 (deep) ION 2 (deep) ION 2 (shallow) (a) (b) EF2 : R BB =200?, I BB =1.1mA, R EE =2k?, I EF =1.12mA (c) (d) Figure 5.12: SET on emitter followers under ion strikes at di?erent position and with di?erent depth. (a) I E,SEE , (b) V E versus time. very short duration. However, the peak and duration of V B SET continue to decrease as shown in Fig. 5.14 (b). This indicates that V E no longer follows V B for extremely small R BB . Fig. 5.14 (c) shows that base charge collection for R BB below 50? are practically identical. V B SET reduces to a negligible short pulse because the voltage drop on R BB is very small. For comparison, we define SET duration as the time it takes for V E to drop back to a reference value V E,REF . For the waveforms shown in Fig. 5.14, a V E,REF of 2.3V is used for a V E,Q of 2.24V. Fig. 5.15 (a) shows SET duration versus R BB . Fig. 5.15 (b) shows SET duration versus 1/R BB . As R BB decreases, the duration of V E SET first decreases linearly until it reaches 44 picoseconds. 73 ?0.4 ?0.1 0 Q B,SEE (pC) ?4 ?2 0 I B,SEE (mA) 3 4 V B (V) 0 50 100 150 200 250 300 2 3.3 V E (V) time (psec) LET = 0.05pC/?m LET = 0.1pC/?m LET = 0.5pC/?m EF2 : R BB =200?, I BB =1.1mA, R EE =2k?, I EF =1.12mA (a) (b) (c) (d) Figure 5.13: SET on emitter followers under ion strikes with di?erent LET. (a) I B,SEE , (b) Q B,SEE , (c) V B , and (d) V E versus time. Approximately, the duration limit is reached at R BB =50?. We believe that the V E SET duration?s low limit is R EE dependent. No further simulation is done as this occurs only for extremely small R BB , that are not used in practical designs. Device level hardening is not e?ective for emitter followers as base charge collection is the dominant origin for typical circuits. Existing device level SiGe HBT hardening techniques focus on reducing charge collection in the CS junction by collecting part of the deposited charge in the substrate through an added back junction or a dummy CS junction [44] [3] [9]. SOI technology even completely eliminates the CS junction [45]. However, the heavily doped n + buried layer 74 0 50 100 150 200 250 300 ?0.08 ?0.04 0 Q B,SEE (pC) time (psec) 2 2.3 3.3 V E (V) 3 3.5 4 V B (V) (a) (b) R BB =3.2k? 1.6k? (EF3) 800? 200? (EF2) 50? 5? R BB =3.2k? to 5? Fixed Q?point V BE =0.84V, V CE =1.06V, I EF =1.12mA (c) 50? 5? Figure 5.14: SET on emitter followers with di?erent R BB . (a) V E , (b) Q B,SEE versus time. decouples the charge collection in the intrinsic emitter, base from those in the CS junction. The charge collected by base and emitter is nearly identical for SOI and bulk SiGe HBTs [45]. The same situation exists for SiGe HBTs hardened using back junction or dummy collector methods. This indicates that all of these device-level or technology-level hardening techniques are not e?ective for reducing SET in emitter followers and other circuits in which the emitter current is of interest. 5.11 Conclusion This chapter presents true mixed mode simulation results for multiple emitter follower designs, as well as parametric analysis. In contrast to conventional wisdom, using a higher emitter current 75 0 400 800 1200 1600 0 150 300 R BB (?) V E SET duration (psec) 0 0.05 0.1 0.15 0.2 0 200 400 1/R BB (? ?1 ) V E SET duration (psec) V E,REF = 2.3V V E,REF = 2.3V (a) (b) Figure 5.15: SET duration on emitter followers with di?erent base biasing resistance. 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