Electrical properties of MOS devices fabricated on 4H Carbon-face SiC
Except where reference is made to the work of others, the work described in this
dissertation is my own or was done in collaboration with my advisory committee. This
dissertation does not include proprietary or classifled information.
Zengjun Chen
Certiflcate of Approval:
Jianjun Dong
Associate Professor
Physics
John R. Williams, Chair
Walter Professor
Physics
Minseo Park
Associate Professor
Physics
Chin-Che Tin
Professor
Physics
George T. Flowers
Dean
Graduate School
Electrical properties of MOS devices fabricated on 4H Carbon-face SiC
Zengjun Chen
A Dissertation
Submitted to
the Graduate Faculty of
Auburn University
in Partial Fulflllment of the
Requirements for the
Degree of
Doctor of Philosophy
Auburn, Alabama
August 10, 2009
Electrical properties of MOS devices fabricated on 4H Carbon-face SiC
Zengjun Chen
Permission is granted to Auburn University to make copies of this dissertation at its
discretion, upon the request of individuals or institutions and at
their expense. The author reserves all publication rights.
Signature of Author
Date of Graduation
iii
Vita
Zengjun Chen, Son of Mantun Chen and Huyou Wang, was born on August 1st, 1978, in
Linyi, Shanxi Province, People?s Republic of China. He entered Xi?an Jiaotong University,
Xi?an, Shaanxi Province, P.R.China in September, 1996 and earned a Bachelor of Science
degree majoring in Applied Physics from Physics Department in July, 2000. He then entered
Fudan University, Shanghai, P.R.China in September, 2000. In July, 2003, he earned a
Master of Science degree majoring in General Physics from the Institute of Modern Physics
of Fudan University. He entered the graduate program in Physics Department of Auburn
University in August, 2003 and worked as a Graduate Teaching Assistant and later as a
Graduate Research Assistant in the Silicon Carbide Research Group under the supervision
of Professor John R. Williams. He married Yanling Ma in Lucheng, Shanxi Province,
P.R.China on December 25th, 2003, and his daughter, April M. Chen was born on October
2nd, 2008 in East Alabama Medical Center, Opelika, Alabama.
iv
Dissertation Abstract
Electrical properties of MOS devices fabricated on 4H Carbon-face SiC
Zengjun Chen
Doctor of Philosophy, August 10, 2009
(M.A., Fudan University, 2003)
(B.S., Xi?an jiaotong University, 2000)
143 Typed Pages
Directed by John R. Williams
Silicon-based devices are still the mainstay of the electronics industry with applications
ranging from small chips in personal computers to large, high power switching devices.
However, Si has faced grater and greater challenges for applications at high frequency, high
voltage, and in high temperature environments. In order to work under these demanding
conditions, silicon-based devices must be used with cumbersome expensive cooling systems
and electrical snubbers that add to circuit complexity for switching applications. Solutions
for these problems have been sought for years and one potential solution is the replacement
of Si with a wide band-gap semiconductor material such as silicon carbide (SiC).
It has been over 20 years since research groups started to investigate SiC as the candi-
date to replace silicon. Many advantages of SiC over silicon have been well recognized. Its
wide band-gap (3.3eV vs. 1.1eV for silicon) allows SiC to operate at higher temperature.
The high thermal conductivity (3.7W/cm-K vs. 1.5W/cm-K for silicon) can signiflcantly
reduce the amount of cooling power required in a system. In addition, SiC has a high
v
electric breakdown fleld (2.1MV/cm vs. 0.3MV/cm for silicon), which enables SiC to block
the same voltage as Si with a 7 times thinner layer, thereby providing a much lower drift
resistance for drift layer of similar doping concentration. Moreover, among the wide band
gap semiconductors, a unique property of SiC is its native oxide is SiO2, which is the same
as the native oxide of Si. This implies that the current silicon MOS device technology can
be adopted for SiC MOS device fabrication without much efiort in the development of new
processing methods.
Despite all these advantages, the realistic applications of SiC in industry have been
hindered by some of its disadvantages. Silicon carbide?s crystal quality is still not as good
as that of silicon. Defects like micropipes and dislocations contribute to less than optimum
breakdown characteristics SiC-based MOS devices. More importantly, although the bulk
electronic mobility of 4H-SiC is comparable to that of silicon (1000cm2/V-s vs. 1400cm2/V-
s), MOSFET inversion channel mobility is much lower - currently 50cm2/V-s compared to
700cm2/V-s. This low channel mobility is caused largely by a high trap density at the
4H-SiC/SiO2 interface.
With its advantages and disadvantages, SiC has been widely investigated. Among many
polytypes of SiC, 4H-SiC attracts much interest because this polytype has the largest band-
gapenergyandahighbulk, almostisotropicbulkmobility. The(000?1)orcarbon-terminated
face 4H-SiC has been much less studied than the (0001) Si-terminated face. However, the
carbon face 4H-SiC has a higher oxidation rate (?9 higher), which can signiflcantly reduce
the fabrication time for SiC MOS devices. Furthermore, Fukuda et al. reported high
vi
inversion channel mobility on the carbon face 4H-SiC?. Such characteristics would make
the carbon face 4H-SiC an ideal candidate of power MOSFETs.
In this dissertation, the basic properties of SiC will be discussed in Chapter 1. The
physics of MOS devices will be presented in Chapter 2, and the characteristics of SiC-based
MOS devices will be discussed in Chapter 3. The processes and techniques used to fabricate
SiC MOS devices will be described in Chapter 4. The results of measurements for MOS
capacitors and MOSFETs fabricated on the 4H carbon face will be presented in Chapter
5 to provide an overview of (000?1) characteristics compared to (0001). Both implanted
and epitaxial layers are used to build MOSFETs. The oxide layer is grown thermally in
furnace at 1150oC, followed by post-oxidation annealing to passivate the O-S interface.
High-purity Mo is sputtered as the gate metal, and source and drain ohmic contacts for
the lateral test MOSFETs are produced by sputtering Ni on heavily implanted regions
(nitrogen at 6?19cm?3), followed by an anneal at 950oC for 4min in Ar. Hi-lo capacitance-
voltage measurements at both 23oC and 300oC are used to obtain the interface trap density
(Dit). Current-voltage measurements at room temperature are used to collect information
about oxide leakage and breakdown fleld (Ebd). A three-probe I-V system is employed to
determine Id-Vg characteristics of the MOSFETs at room temperature, and the inversion
channel mobility (?) is extracted from these characteristics.
Results are compared for difierent post-oxidation interface passivation anneals, with
the combination of nitric oxide (NO) and H2 giving the lowest trap density Dit in the upper
half of the band gap. Wet-reoxidation plus NO passivation produces the most reliable oxide,
but the measured breakdown fleld of 6MV/cm is still approximately 2MV/cm lower than the
?K. Fukuda, M. Kato, S. Harada, K. Kojima, Mater. Sci. Forum., 527, 1043, (2006)
vii
average fleld measured for the silicon face. Compared to the values reported by Fukuda,
et al., our low fleld mobility value is not remarkable. However, the high fleld mobilities
are similar. It was observed that the presence of mobile ions can increase our low fleld
channel mobility signiflcantly. For example, after negative bias stress at 250oC to remove
possible mobile ions from the O-S interface, the mobility peak value drops from 65cm2/V-s
to 35cm2/V-s. These results suggest that the efiective channel mobility for the carbon face
may not be signiflcantly higher compared to the silicon face.
viii
Acknowledgments
The author would like to express sincere appreciation to Dr. John R. Williams, for
all his invaluable advice, guidance, and academic and moral support. His encouragement,
knowledge and enthusiasm continuously enlightened and guided him during the entire re-
search work. The author is also very grateful to all the committee members, Dr. Chin-che
Tin, Dr. Jianjun Dong, Dr. Minseo Park and Dr. Robert Nelms for their support, instruc-
tion and participation in the evaluating of his work.
In addition, the author is also deeply in debt to Dr. Ayayi C. Ahyi, for inspiration,
collaboration, attention, discussion and help that he kindly provided at all times. Special
thanks to Tamara Isaacs-Smith and Max Cichon for their valuable assistance all along, and
to Dr. Shurui Wang for her instruction and time during the early part of the work. The
author would also like to take this opportunity to thank Xingguang Zhu, Mingyu Li, all
the collaborators in the research group and the alumni in Physics Department of Auburn
University for their help and contributions during the past six years.
Last but not least, the author extends special thanks to his wife Yanling Ma for all her
patience, understanding and moral support. The author also wants to thank his daughter,
April, for bringing him so many pleasant moments. This dissertation is also dedicated to
all his family members and friends.
This work was supported by ARL under contract ARMY-W911NF-07-2-0046 and
TARDEC under contract W56H2V-06-C-0228.
ix
Style manual or journal used Bibliography follows American Physical Society (APS)
style
Computer software used The document preparation package TEX (speciflcally LATEX)
together with the departmental style-flle auphd.sty.
x
Table of Contents
Vita iv
Abstract v
Acknowledgments ix
List of Tables xiii
List of Figures xiv
1 Silicon Carbide Properties 1
1.1 Crystal Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Crystal Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Band Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Defects in the Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5 Physical and Electronic Properties . . . . . . . . . . . . . . . . . . . . . . . 11
2 Physics of Metal-Oxide-Semiconductor Devices 15
2.1 MOS-Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.1 Ideal MOS-Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.2 Real MOS-Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2 MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2.1 Device Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2.2 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3 SiC-based MOS Devices Properties 36
3.1 Oxidation of SiC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2 SiC/SiO2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2.1 Post-Oxidation Annealing . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3 Oxide Reliability on SiC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3.1 Oxide Failure Mechanism . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3.2 Time Dependent Dielectric Breakdown (TDDB) . . . . . . . . . . . 51
3.3.3 Negative Bias Temperature Instability (NBTI) . . . . . . . . . . . . 53
3.4 SiC-Based MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
xi
4 MOS Device Fabrication Techniques and Measurements 56
4.1 Oxidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.1.1 Dry Oxidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.1.2 Wet Oxidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.1.3 Post-Oxidation Annealing . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2 Lithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.3 Metal Deposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.4 Implantation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.5 Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.6 Ohmic Contact Annealing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.7 Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.7.1 BOE Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.7.2 RIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.7.3 KOH Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.8 Capacitance-Voltage Measurements . . . . . . . . . . . . . . . . . . . . . . . 71
4.9 Current-Voltage Measurements . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.9.1 TDDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.10 MOSFET Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5 Characterization of MOS Devices Fabricated on Carbon Face 4H-SiC 80
5.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.2 Oxidation Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3 (000?1)4H-SiC/SiO2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3.1 Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3.2 Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.4 Oxide Breakdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.4.1 Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.4.2 Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.5 MOSFET Channel Mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.5.1 Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.5.2 Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Bibliography 110
A Wafer Cleaning 119
B Transmission Line Measurement 121
C Metal and Metal Film Etchants 124
xii
List of Tables
1.1 Physics properties of several important semiconductors . . . . . . . . . . . . 12
5.1 The oxidation rates of (0001) and (000?1) 4H-SiC . . . . . . . . . . . . . . . 81
C.1 Metal and Metal Film Etchants . . . . . . . . . . . . . . . . . . . . . . . . . 124
xiii
List of Figures
1.1 The basic tetrahedron frame of SiC . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Stacking sequence of several SiC polytypes. . . . . . . . . . . . . . . . . . . 3
1.3 Unit cell of hexagonal structure of SiC. . . . . . . . . . . . . . . . . . . . . . 4
1.4 Stacking sequence of several SiC polytypes in (11?20) face. . . . . . . . . . . 4
1.5 Schematic diagram of Lely growth method . . . . . . . . . . . . . . . . . . . 5
1.6 Schematic diagram of seeded sublimation growth method . . . . . . . . . . 7
1.7 Relation between polytype and temperature of crystal growth . . . . . . . . 7
1.8 The band gap information of several polytypes of SiC . . . . . . . . . . . . 8
1.9 A schematic illustration of the proposed micropipe formation mechanism . . 10
1.10 Cross sectional view of a vertical difiused MOSFET . . . . . . . . . . . . . 14
2.1 A typical Metal-Oxide-Semiconductor capacitor structure . . . . . . . . . . 16
2.2 The energy band diagram of an ideal MOS-capacitor . . . . . . . . . . . . . 17
2.3 The energy band diagrams of MOS-cpacitors . . . . . . . . . . . . . . . . . 18
2.4 The capacitance of an MOS-capacitor under difierent bias conditions . . . . 20
2.5 The energy band diagram of a p-type semiconductor under the positive bias 21
2.6 The energy band diagram of a real MOS-capacitor at  at-band state . . . . 25
2.7 The structure of a lateral n-MOSFET . . . . . . . . . . . . . . . . . . . . . 29
2.8 The three working regions of MOSFETs . . . . . . . . . . . . . . . . . . . . 30
2.9 The drain current - gate voltage characteristics of an MOSFET . . . . . . . 33
xiv
3.1 Comparison of oxide thickness on (0001) and (11?20) 6H-SiC . . . . . . . . . 38
3.2 Interface state density Dit as a function of energy . . . . . . . . . . . . . . . 41
3.3 Interface state density on three difierent dielectrics . . . . . . . . . . . . . . 44
3.4 N passivation on carbon clusters . . . . . . . . . . . . . . . . . . . . . . . . 45
3.5 Schematic plot of a plasma nitridation furnace . . . . . . . . . . . . . . . . 46
3.6 Dit comparison before and after plasma nitridation . . . . . . . . . . . . . . 47
3.7 Dit after the difierent interface treatments . . . . . . . . . . . . . . . . . . . 48
3.8 Schematic of the reliability test circuit . . . . . . . . . . . . . . . . . . . . . 52
4.1 Furnace for dry oxidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2 DI-water container for wet oxidation . . . . . . . . . . . . . . . . . . . . . . 59
4.3 Schematic of a general photo-lithography process . . . . . . . . . . . . . . . 61
4.4 Mask aligner for photo-lithography . . . . . . . . . . . . . . . . . . . . . . . 62
4.5 DC/RF sputtering deposition system . . . . . . . . . . . . . . . . . . . . . . 64
4.6 Working mechanism of the sputter deposition process . . . . . . . . . . . . 64
4.7 Implant activation anneal chamber . . . . . . . . . . . . . . . . . . . . . . . 66
4.8 Sample holder carbon box for implant activation . . . . . . . . . . . . . . . 67
4.9 Ohmic contact annealing furnace . . . . . . . . . . . . . . . . . . . . . . . . 68
4.10 Equipment for reactive ion etching . . . . . . . . . . . . . . . . . . . . . . . 70
4.11 Simultaneous high-low capacitance-voltage station . . . . . . . . . . . . . . 72
4.12 A typical CV plot of MOS capacitor . . . . . . . . . . . . . . . . . . . . . . 73
4.13 Current-voltage station . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.14 TDDB measurement board . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.15 The user interface of TDDB measurement program . . . . . . . . . . . . . . 77
4.16 The three probe current-voltage measurement station . . . . . . . . . . . . 78
xv
4.17 The user interface of MOSFET measurement program . . . . . . . . . . . . 79
5.1 Capacitance v.s. gate voltage of an MOS capacitor with as-oxidized oxide . 83
5.2 Interface trap density proflle of an MOS capacitor with as-oxidized oxide . . 84
5.3 Interface trap density proflle after NO passivation . . . . . . . . . . . . . . . 85
5.4 Interface trap density proflle after H2 passivation . . . . . . . . . . . . . . . 87
5.5 Dit after NO and H2 passivation . . . . . . . . . . . . . . . . . . . . . . . . 89
5.6 Dit after wet reoxidation and H2 passivation . . . . . . . . . . . . . . . . . . 90
5.7 Dit of (000?1) 4H-SiC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.8 Dit of (0001) 4H-SiC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.9 Current-voltage measurements for carbon face 4H-SiC MOS capacitors . . . 94
5.10 IV measurements for (000?1) 4H-SiC . . . . . . . . . . . . . . . . . . . . . . 95
5.11 IV measurements for (0001) 4H-SiC . . . . . . . . . . . . . . . . . . . . . . 96
5.12 Aluminum implantation proflles on carbon face 4H-SiC . . . . . . . . . . . . 98
5.13 Nitrogen implantation proflles on carbon face 4H-SiC . . . . . . . . . . . . . 99
5.14 TLM results after Ohmic Contact Annealing . . . . . . . . . . . . . . . . . 100
5.15 The channel mobility of carbon face 4H-SiC . . . . . . . . . . . . . . . . . . 102
5.16 The channel mobility of carbon face 4H-SiC . . . . . . . . . . . . . . . . . . 103
5.17 The channel mobility of silicon face 4H-SiC . . . . . . . . . . . . . . . . . . 104
5.18 The channel mobility of carbon face 4H-SiC after negative bias . . . . . . . 106
5.19 The channel mobility of carbon face 4H-SiC after negative bias . . . . . . . 107
B.1 Schematic pattern of a transmission line measurement device. . . . . . . . . 121
B.2 Diagram of a 4-probe I-V measurement in TLM. . . . . . . . . . . . . . . . 122
B.3 Plot of resistance as a function of L . . . . . . . . . . . . . . . . . . . . . . . 123
xvi
Chapter 1
Silicon Carbide Properties
Silicon carbide (SiC), also named by moissanite[1], is a compound of silicon and carbon.
Compared to silicon, the current dominant semiconductor material in the industry, SiC has
shown signiflcant advantages in terms of the electrical properties. The wide band gap of
SiC, 3.2eV versus 1.2eV of silicon, enables it to work at higher temperature. The high
thermal conductivity of SiC, 3.7W/cm-K compared to 1.5W/cm-K of silicon, makes it an
excellent material for heat management application. The high electrical breakdown fleld
of SiC, 2.1MV/cm as opposed to 0.3MV/cm of silicon, can sustain high blocking voltage
with employing a much thinner epi-layer. 4H-SiC, one of many polytypes of SiC, has a bulk
electron mobility of 1000cm2/V-s, comparable to silicon?s bulk mobility (1350cm2/V-s),
leaving open the possibility of even high channel mobility. The native oxide of SiC is SiO2,
same as that of silicon, enabling the adoption of fabrication techniques from silicon industry.
This unique property potentially saves money and efiort for developing new procedures for
SiC applications. In this chapter, an overview of the relevant properties will be presented
and discussed.
1.1 Crystal Structure
SiC crystals exist in many polytpes, more than 250 polytypes have been reported.
All polytypes share a hexagonal frame with a carbon atom situated above the center of a
1
triangle of silicon atoms and underneath a silicon atom belonging to the next layer. This
framework is shown in flgure 1.1. The distance between any two silicon atoms is 3.08?A.
From geometrical relations, the distance between silicon atom and carbon atom is around
1.89?A.
Fig. 1.1: The basic tetrahedron frame of SiC. Dark grey balls rep-
resent silicon atoms, light grey ball represents carbon atoms. The
distance between silicon atoms and carbon atom is same.
In flgure 1.1, a plane is formed by the three base silicon atoms, above this plane,
the carbon atoms form another plane. The whole SiC crystal is constructed from silicon-
carbon planes. The stacking style of silicon-carbon planes varies, and the variation deflnes
the polytype of SiC crystal. Figure 1.2 shows the stacking sequences of several common
polytypes. A, B, and C stand for the difierent distributions of the silicon-carbon bonds.
If the stacking order is ABCABC..., the single crystal structure is named as 3C, where C
denotes the cubic structure. For 4H single crystal, the stacking order is ABACABAC..., the
H denotes a hexagonal structure. 4H-SiC will be the focus of discussion.
2
Fig. 1.2: Stacking sequence of several SiC polytypes.
To distinguish the difierent orientation of SiC crystal, miller indices are employed.
3C crystal uses 3 digits and hexagonal crystal uses 4 digits with the last one deflning the
direction of c-axis. In flgure 1.3, the top surface represents (0001) and the bottom surface
(000?1). The shadow surface is (11?20). In the surface of (11?20), the difierences of stacking
sequences of various polytypes can be seen, as shown in flgure 1.4.
1.2 Crystal Growth
The most well-known crystal growth technique today is Czochralski method[2], growth
of single crystal from the melt. Most silicon single crystal ingots are produced by this
method. In this process, a seed crystal rod is dipped into molten high-purity silicon in a
quartz crucible and then pulled up while rotating. A large diameter silicon single crystal
ingot will be produced. Single crystal SiC, however, can not be produced by Czochral-
ski method since SiC dose not melt at temperatures above 2000oC, but instead gradually
sublimes[3]. Thermodynamic analysis of the possibility of single-crystal growth from the
3
a1
a2
a3
c
Fig. 1.3: Unit cell of hexagonal structure of SiC.
Fig. 1.4: Stacking sequence of several SiC polytypes in (11?20) face.
4
melt indicated that the intrinsic melt of SiC can exist at temperatures greater than 3190oC
and pressures greater than 104 MPa, which does not allow the commonly used grow-from-
melt techniques for the production of SiC single crystals[4]. For materials with no congruent
melting temperature or at least one component having too high a vapor pressure at the
melting point, vapor phase growth methods are employed[5].
The flrst SiC was produced in 1890s by Acheson[5], who let silicon and carbon react at
temperature higher than 2500oC. It was Lely who flrst developed the sublimation method
for SiC crystal growth in 1955. The schematic diagram of Lely growth method is shown
in flgure 1.5. The temperature in the crucible is 2500-2700oC. Under the in uence of
temperature gradients, SiC or silicon and carbon penetrate through porous graphite and
form SiC crystal in the shape of boules on inner walls of graphite. These single crystals
are very pure and limited to small size. A large SiC single crystal was flnally produced in
Fig. 1.5: Schematic diagram of Lely growth method[5].
the laboratory by Tairov and Tsvetkov by using seeded sublimation growth method (also
5
known as modifled-Lely growth method)[6]. Their approach is shown in flgure 1.6. Seeded
sublimation growth places a single crystal seed inside the crucible. An advantage of seeded
sublimation growth method over Lely growth method is better control of the nucleation
process. Additionally, the crucible is fllled with Argon, which helps control the difiusion
process of Si-C gas species. The main reactions in the crucible are list below:
SiC(s) $ Si(g)+C(s) (1.1)
2SiC(s) $ SiC2g +Si(g) (1.2)
SiC(s)+Si(g) $ Si2C(g) (1.3)
Meanwhile, since the crucible is composed of graphite, the following reactions between the
silicon vapor and crucible also exist:
C(s)+2Si(g) ) Si2C(g) (1.4)
2C(s)+Si(g) ) SiC2(g) (1.5)
The letters g and s in the parenthesis stand for gas and solid, respectively. As mentioned
in section 1.1, SiC has many polytypes. During the single crystal growth, only the desired
polytype is expected to be grown. In reality, many other polytypes may be simultaneously
grown and they are considered to be defects in the host polytype semiconductor[5]. Figure
1.7 shows the relationship between the polytpe and the temperature of crystal growth.
To achieve single-polytype single-crystal growth, the seed crystal must be pure and of the
6
Fig. 1.6: Schematic diagram of seeded sublimation growth
method[5].
desired polytype with excellent surface condition. Since polytypes other than that of the
seed can easily be formed by phase transitions, the initial stage of crystal growth is critical
and very important for polytype control[5]. It has also been shown that using a seed with
a slight ofi-axis from the low-index (0001) plane and growth with a relatively slowly at
initial stage improves the polytype control[7]. Another issue in crystal growth is the control
Fig. 1.7: Relationship between the polytype and the temperature
of crystal growth[5].
7
of doping concentration. For SiC bulk doping concentration, which is generally very high,
nitrogenandaluminumareusedasn-andp-typedopantsduringthegrowth. Forlow-doping
concentration, for instance, for an epitaxial layer, precise control is required to achieve
accurate doping. Chemical vapor deposition (CVD) is commonly used as the method of
epitaxial growth[8{10]. Dopants are added during CVD and difiuse into the epitaxial layer to
obtain desired concentration. Other than CVD, molecular beam epitaxy (MBE) and liquid
phase epitaxy (LPE) are also used for epitaxial growth[11{13] of compound semiconductors.
Since difiusion in SiC is much more di?cult than in silicon, ion implantation is also employed
to dope epitaxial layer[14, 15].
1.3 Band Diagram
Fig. 1.8: The band gap information of several polytypes of SiC,
comparing to that of silicon[16].
SiC is a wide band gap semiconductor material[17, 18]. Figure 1.8 shows the band gaps
of the 4 commonly used SiC polytypes. For comparison, SiO2 and silicon are presented.
It should be noted that the band gap depends on temperature and pressure. The values
listed in flgure 1.8 are measured at liquid helium temperatures. Of the polytypes of SiC,
8
4H has the widest band gap. Due to this property, devices fabricated on 4H-SiC are able to
sustain a higher electric power. This property plus the fact that the native oxide of SiC is
silicon dioxide leads to the expectation that 4H-SiC will be a suitable substitute for silicon
in the production of power MOSFETs working in the harsh environments. Currently, the
poor quality of SiC/SiO2 interface hinders the transition from Si to SiC, which will be
discussed later in this dissertation.
1.4 Defects in the Crystal
During the crystal growth process, the most easily or commonly produced defects are
micropipes[19{22]. Micropipes are hollow tubes propagating the SiC crystal along the growth
direction, i.e. c-axis. In most cases, the micropipes appear as the super-screw dislocations
with a huge Burgers vector[23]. Putting SiC crystal in high-temperature Potassium hydrox-
ide (KOH) liquid allows for visualization of the micropipes[24]. The formation of micropipes
is shown in flgure 1.9. During the crystal growth process, impurity particles may gather
together at the surface of growing crystal, as the next SiC layer grows, the impurity par-
ticles will stop Si and C atoms from occupying their lattice sites. As more and more SiC
layers are grown, there will be a repulsive force exerted by the edge of the SiC layer on the
impurity particles. This force may lift up the impurity particles due to the weak bonding
between the impurity particles and the SiC crystal. A hollow tube may be produced under
the impurity particles. The moving process of the impurity particles may continue through
out the growth. This model explains why most micropipes are along the crystal growth
direction and have length equal to the height of the grown crystal[25].
9
Fig. 1.9: A schematic illustration of the proposed micropipe for-
mation mechanism[25].
10
The early stage of SiC crystal growth was also investigated to flnd the relationship
between seed condition and micropipe formation in crystal. The micropipes in the seed
continue to grow into the crystal, but no new micropipes would be generated[26]. If the seed
surface is disintegrated by parasitic sublimation during the preheating stage of growth,
micropipes may be generated[27, 28]. The temperature  uctuation in the growth chamber
was found to be another cause of generation of micropipes[5].
In addition to micropipes, planar defects, grain boundaries, dislocations and stacking
faults are also defects existing in SiC[24, 29{31]. Planar defects are hexagonal voids or tubelike
cavities. They are several hundreds microns in width and flve to twenty-flve microns in
thickness along the c-axis[32]. Grain boundaries occur at the places where two polytypes are
grown and they appear as line of etch pits after KOH etching. Dislocations are of importance
because they are electrically active defects signiflcantly degrading device performance. KOH
etching is also used to reveal dislocations. Stacking faults only happen when crystal is grown
perpendicularly to the c-axis and they appear as linear etch pits in the basal plane.
1.5 Physical and Electronic Properties
SiC has many excellent physical and electrical properties. Table 1.1 shows the relevant
parameters. For comparison, the same parameters of several other semiconductor materials
are provided.
From table 1.1, the following conclusions may be drawn about SiC.
1. The wide band gap is the most promising characteristics of SiC. This makes it
possible for SiC-based devices to sustain a higher working voltage, as required by power
MOSFETs.
11
Table 1.1: Physics properties of several important semiconductors
Materials Si 4H-SiC 6H-SiC GaAs GaN(Wurtzite)
Lattice fi[?A] 5.43 3.08 3.08 5.65 3.189
Lattice c[?A] - 10.07 15.12 - 5.185
Bond length[?A] 2.35 1.89 1.89 2.45 1.95
Density[gm/cm3] 2.32 3.16 3.16 5.3 6.09
Therm. cond.[W=cm?K] 1.5 3.7 3.7 0.46 2.3
Melting point[oC] 1420 2830 2830 1240 2500
Debye temperature[K] 640 1300 1200 360 600
Young?s modulus[Gpa] 47 100-750 488 85.5 330
Band gap[eV] 1.12 3.26 3.03 1.43 3.457
Bulk elec. mob.[cm2V?1S?1] 1400 1000 400 8500 500
Bulk hole mob.[cm2V?1S?1] 480 115 90 400 80
Elec. breakd. fleld[MV=cm] 0.25 2.2 2.4 0.4 -
Dielectric constant[?s=?o] 11.7 6.5-6.7 6.5-6.7 12.5 10
Satur. elec. drif. velo.[cm=s] 1x107 2x107 2x107 1x107 1x107
2. By comparing Young?s modulus, SiC is a stifier material when compared to silicon.
Considering carbon atoms are lighter than silicon atoms, it can be implied that the thermal
conductivity of SiC is higher than that of silicon[16].
3. High saturated electron drift velocity enables SiC microwave devices to operate at
higher cut-ofi frequencies[33].
4. High thermal conductivity enables devices based on SiC to transfer heat faster than
devices based on silicon, therefore reducing the cost on heat management.
5. Signiflcantly high electron breakdown fleld allows the thinner SiC power devices to
handle high blocking voltage. Figure 1.10 shows the cross sectional view of a vertical difiused
MOSFET (VDMOSFET). VDMOSFET is a type of power MOSFET, which requires to
12
handle high blocking voltage, and still have smaller power loss at the same time. A trade-ofi
exists due to the fact that higher blocking voltage needs a thicker epi-layer and lower doping
concentration. A thicker epi-layer and lower doping concentration will lead to higher drift
resistance RDr, which is one part of on-resistance when power MOSFET is working. The
total on-resistance can be approximated by the following equation: Ron ? Rch +RDr, where
Rch is the channel resistance. Although several other resistances also contribute to the total
on-resistance, for example, contact resistance and access resistance (the resistance when
current  ows out from channel and changes from horizontal direction to vertical direction),
the channel resistance and drift resistance are the two largest components. Consequently
the on-resistance will be higher. Because power loss during the operation of MOSFET is
Ploss = I2sd ?Ron, the power loss will also be higher. This trade-ofi can be changed when
SiC is used to be the substrate. Considering Ron is proportional to speciflc on-resistance
ron, and ron = V
2
blocking
?E3c , where ? is the bulk electronic mobility of semiconductor. If the
blocking voltage does not change, given that bulk electronic mobility of SiC and silicon are
comparable and electron breakdown fleld of SiC is 7 times higher than that of silicon, the
speciflc on-resistance of SiC will be 0.3% of that of silicon. This will make power loss of
MOSFET fabricated on SiC much smaller than that fabricated on silicon. This also implies
that SiC MOSFET can be much thinner than silicon MOSFET but equally safe.
6. Small dielectric constant provides low parasitic capacitance and higher operating
speed for MOS devices[34].
These attractive properties have led to rapid development of SiC as a material and
its device technology over the past 10 years[35]. For instance, Schottky diodes have been
available commercially for years[36]. According to Cree, power MOSFETs are scheduled to
13
Drain
N+ substrate
N?
P?
N+
Gate
Source Source
RCh
RDr
ISD
Fig. 1.10: Cross sectional view of a vertical difiused MOSFET.
be introduced in mid-2009. Bipolar transistors are expected to be available in the market
within three to seven years. The future of SiC power devices appears bright[36].
14
Chapter 2
Physics of Metal-Oxide-Semiconductor Devices
The metal-oxide-semiconductor or MOS structure is the most important and most
commonly used structure in modern microelectronics[37]. A more general deflnition is MIS
or metal-insulator-semiconductor. Since it is used extensively in devices and integrated
circuits, the MOS structure has been extensively studied[38]. Although the concept of
MOS was proposed in Lilienfeld?s patent in 1926[39], the flrst real working MOS device was
demonstrated by Atalla and Kahng in 1959[40, 41]. Today, the most successful, ideal and
practical MOS structure is Metal-Si-SiO2 system.
In this chapter, two important MOS devices, the MOS-Capacitor and the MOSFET
will be discussed. Ideal devices will be discussed flrst,and electronic characteristics of real
devices will be reviewed as well.
2.1 MOS-Capacitors
The MOS capacitor has been the most useful device in the study of oxide-semiconductor
surface, which is important for device reliability and stability[38].
2.1.1 Ideal MOS-Capacitors
MOS capacitors refer to the devices with oxide layer sandwiched by a metal layer and
a semiconductor layer. The structure of an MOS capacitor is shown in flgure 2.1. Another
15
Fig. 2.1: A typical Metal-Oxide-Semiconductor capacitor
structure[37]
16
metal layer, generally grounded, is put on the back of semiconductor material to be annealed
as a low resistance ohmic contact. In an ideal MOS-capacitor, the oxide layer is a perfect
insulator and has no mobile ions inside. The gate metal layer has to be thick enough to be
an equipotential surface.
Fig. 2.2: The energy band diagram of an ideal MOS-capacitor.
With no gate voltage, VG, applied, the energy band diagram of an ideal MOS-capacitor
is shown in flgure 2.2. Since the device must be in equilibrium, the Fermi energy levels of
metal layer and semiconductor have to be aligned. If VG 6= 0, Equation 2.1 can be used to
describe the relationship between Fermi energy levels of the two sides,
EF(metal)?EF(semiconductor) = ?qVG (2.1)
From Equation 2.1, if VG > 0, Fermi energy level of metal layer will be lower than that
of semiconductor; if VG < 0, Fermi energy level of metal layer will be higher than that of
semiconductor. For n-type semiconductor material, when VG > 0, the MOS-capacitor will
17
stay in the accumulation state, and MOS-capacitor will be in depletion when VG < 0. If VG
is lower than a speciflc value, holes will appear at the interface of semiconductor-oxide. This
state is called the inversion state. The situation will be opposite for p-type semiconductor
material. Energy band diagrams of the three states for both p-type and n-type materials
are shown in flgure 2.3.
Fig. 2.3: The energy band diagrams of MOS-cpacitors at (a) accu-
mulation, (b) depletion and (c) inversion regions. the upper row is
p-type material and the lower row is n-type material[38].
To understand detailed characteristics of MOS-capacitors, capacitance-voltage charac-
teristics are obtained and analyzed. The capacitance of an MOS-capacitor will change with
respect to the applied gate voltage. The frequency of an AC probe voltage added to the DC
gate voltage afiects the measured capacitance, as well. Firstly, we consider the magnitude
of the applied gate voltage. When VG is positive, the device stays in accumulation, which
18
means that electrons pile up in the semiconductor at the oxide-semiconductor interface. Be-
cause electrons are majority carriers in an n-type semiconductor, they can respond quickly
with the change of voltage. Therefore, for all applied probe frequencies, the electrons can
always follow the changing AC voltage. So the capacitance of the MOS-capacitor in accu-
mulation will be equivalent with that of a parallel-plate capacitor. Equation 2.2 gives the
capacitance expression,
Co = K0"0At (2.2)
where K0 is dielectric constant of the oxide, "0 permittivity of free space, A gate area and
t thickness of the oxide. Under depletion conditions, VG < 0, electrons disappear from the
surface region of the semiconductor near the O-S interface. This region, generally is called
depletion layer, whose width depends on how much gate voltage is applied. At the opposite
end of depletion layer, electrons will follow the varying gate voltage. The situation will then
be like two parallel-plate capacitors in series. One parallel-plate capacitor is the oxide layer,
the other is the depletion layer. Equation 2.2 is still valid for oxide layer capacitance, and
depletion layer capacitance can be described as equation 2.3,
Cs = Ks"0AW (2.3)
where Ks is dielectric constant of semiconductor and W the width of depletion layer. The
total capacitance of the device is
C = CsCoC
s +Co
= Co1+ K0W
Kst
: (2.4)
19
It is easy to flnd C is a function of width of depletion layer.
Whenann-MOS-capacitorisbiasedmorenegatively, theinversionstatecanbeachieved.
In this state, minority carriers can appear at the O-S interface. The frequency of the AC
gate voltage probe may then afiect the measured capacitance of the device. Due to the slow
response of minority carriers (holes for n-type), high-frequency gate voltage will only drive
the electrons in depletion layer, while low-frequency gate voltage will make holes respond.
The capacitance of device can be expressed as following,
C =
8
>>>>
>><
>>>
>>>:
Co ! ?! 0
Co
1+K0WKst ! ?!1
(2.5)
We use flgure 2.4 to explain the capacitance of MOS-capacitor in difierent regions.
Fig. 2.4: The capacitance of an MOS-capacitor under difierent bias
conditions.
20
Electrostatic Analysis
With a knowledge of how energy bands bend with the application of gate voltages, it
is necessary to derive the relationships among the potential distribution, the charge density
and the electric fleld inside the semiconductor.
Fig.2.5: Theenergybanddiagramofap-typesemiconductorunder
the positive bias[38].
Figure 2.5 shows the energy band diagram of a p-type semiconductor under the positive
bias. The potential ? is a function of distance x. In the semiconductor bulk away from the
interface, ? = 0. Also, in the ? at-band state?, the surface potential, ?s = ?(x = 0) = 0.
As functions of ?, the concentrations of electrons and holes can be written as the following
equations.
np = np0 exp(q?=kT) = np0 exp(fl?) (2.6)
pp = pp0 exp(?q?=kT) = pp0 exp(?fl?) (2.7)
21
In these equations, np0 and pp0 represent the equilibrium densities of electrons and holes in
the bulk, and fl ? q=kT.
With the help of Poisson?s equation, we can describe the relationship between ? and
the charge density.
d2?
dx2 = ?
?(x)
?s (2.8)
?s in above equation is the permittivity of the semiconductor material and ?(x) the charge
density, which is given as
?(x) = q(N+D ?N?A +pp ?np) (2.9)
, in which N+D and N?A are the densities of the ionized donors and acceptors. The boundary
conditions are ?(x = 1) = 0 and ?(x = 1) = 0. Therefore, when x = 1,
N+D ?N?A = npo ?ppo: (2.10)
Generally,
pp ?np = ppo exp(?fl?)?npo exp(fl?): (2.11)
The Poisson?s equation can be written as follows.
@2?
@x2 = ?
q
?s[ppo(e
?fl? ?1)?npo(efl? ?1)]: (2.12)
If we integrate the above equation,
Z @?=@x
0
(@?@x)d(@?@x) = ? q?
s
Z ?
0
[ppo(e?fl? ?1)?npo(efl? ?1)]d? (2.13)
22
we flnd the relationship between the electric fleld and the potential,
E2 = (2kTq )2(qppofl2?
s
)[(e?fl? +fl? ?1)+ npop
po
(efl? ?fl? ?1)]; (2.14)
where E = @?=@x. If we deflne two new variables:
LD ?
s
kT?s
ppoq (2.15)
and
F(fl?; npop
po
) ? [(e?fl? +fl? ?1)+ npop
po
(efl? ?fl? ?1)]1=2; (2.16)
the electric fleld will be
E = ?
p2kT
qLD F(fl?;
npo
ppo): (2.17)
Depending on the sign of ?, E will be either positive or negative. At the surface of semi-
conductor, ? = ?s, the electric fleld is
Es = ?
p2kT
qLD F(fl?s;
npo
ppo): (2.18)
The surface charge density can also be obtained by using the following equation,
Qs = ??sEs = currency1
p2kT
qLD F(fl?s;
npo
ppo): (2.19)
23
Knowing the electric fleld and the surface charge density, we can get the expression of
semiconductor capacitance
CD ? @Qs@? = ?sp2L
D
[1?e?fl?s +(npo=ppo)(efl? ?1)]
F(fl?s;npo=ppo) : (2.20)
An interesting result is when semiconductor is at  at-band condition, ?s = 0, the capaci-
tance is
CD = ?s=LD: (2.21)
We have made an assumption in above analysis that the MOS-capacitors are on silicon
substrates. For MOS-capacitors fabricated on SiC, the situation will be slightly difierent
because of SiC?s wider band gap compared with silicon. Details describing SiC-based MOS-
capacitors will be discussed in next chapter.
2.1.2 Real MOS-Capacitors
When dealing with real MOS-Capacitors, we can not avoid defects in semiconductor,
traps at O-S, mobile ions in insulator and the efiects of the gate metal.
Work Function Difierence
Since C-V characteristics has been used to describe the electrical properties of ideal
MOS-Capacitors, this method will be employed for a better understanding of real MOS-
Capacitors. In C-V measurements,  at-band voltage is an important quantity, which refers
to the voltage applied on gate to make the electrical potential at the O-S interface equal
to that of the bulk semiconductor. In other words, when  at-band voltage is applied, the
24
conduction and valence bands are horizontal on a band diagram. Theoretically,  at-band
voltage can be expressed simply by the following equation
Vfb = `ms ? 1C
ox
[QF + mQMI +QIT] (2.22)
where Vfb is  at-band voltage, `ms is the work-function difierence between gate metal and
semiconductor, Cox the oxide capacitance of insulator, QF the positive flxed charge located
near the O-S interface on the insulator side, QMI the mobile ion charge in insulator,  m a
pure number ranging from 0 to 1 for MIS at the M-O and O-S interfaces respectively, and
QIT the charges located in interface traps.
Fig. 2.6: The energy band diagram of a real MOS-capacitor at
 at-band state[37].
For the case of ideal devices, insulator layer is clean, interface quality is perfect and the
work functions of the gate metal and the semiconductor are the same. Therefore  at-band
voltage will be equal to 0. The situation, however, will be difierent for real MOS-Capacitors.
First of all, `ms 6= 0 due to the fact that the Fermi levels of semiconductor and metal must
25
be aligned in a device in equilibrium. The Fermi level of semiconductor depends on doping
and is unlikely to be at same level as that of metal. This will lead to shift of Fermi level of
the metal and to energy-band bending of the semiconductor. Figure 2.6 explains the work
function difierence in real MOS-Capacitors,
Oxide Charges
If we don?t consider charges located in device, the gate voltage will be equal to `ms
in  at-band state. The charges, however, are the most important issues in the real de-
vices. For instance, mobile ions are frequently introduced in fabrication of semiconductor
devices. The most commonly seen mobile ions are sodium ions which are introduced from
the hands of operators or materials used in fabrication process. A serious problem pro-
duced by mobile ions is the  at-band voltage will shift dramatically under electrical bias at
elevated temperature. From equation 2.6, the mobile ion concentration can be calculated
if one knows the shift of  at-band voltage and the oxide capacitance. Most semiconductor
devices need to operate at temperatures as high as 150oC, and mobile ions located in the
insulator will change the working voltage of a device, which leads to unstable operation.
Many methods have been proposed to solve the mobile ion problem. In the phosphorus
stabilization method[42], the surface of the oxide layer is infused phosphorus. Heated at
high temperature, the mobile ions in the oxide will move everywhere. Once entering the
phosphorus layer, they are trapped and immobilized. A similar approach was also used by
Miremadi[43] who used thin alumina layers and thin MoS2 fllms as protective layers.
Another method is called chlorine neutralization[44], in which people introduce a small
amount of chlorine, in the form of HCl, Cl2 or TCE, into the oxide growth chamber. A new
26
material chlorosiloxane will be produced at the O-S interface. The mobile ions in the oxide
layer will move into the new material and be trapped. Chlorosioxane is reported to have
no efiects on the electrical properties of MOS devices.
Other than mobile ions, other kinds of oxide charges exist as well. Unlike mobile ions,
these charges don?t move with bias and temperature, but rather stay very close to the O-S
interface. Because of this property of stability, they are generally called flxed oxide charges.
It has been found experimentally, flxed oxide charges don?t disappear with improvement of
fabrication environment. Furthermore, flxed oxide charges depend on semiconductor surface
orientation and oxide conditions such as temperature and gas used, but not on thickness
of oxide, semiconductor doping concentration or doping type[37]. Generally speaking, flxed
oxide charges are positive in silicon-based oxide, and are believed to result from unoxidized
silicon atoms. Based on this information, people have used post-oxidation annealing to
reduce the flxed oxide charge concentration.
Equation 2.22 has one more term afiecting  at band voltage, which is the interface trap
charge, QIT. Interface trap density, however, is the term people use more often to describe
the quality of interface of semiconductor and oxide. As an intrinsic property of an MOS
device, interface trap density plays a very important role in operating e?ciency of whole
device. As a result, it has been studied very widely, many approaches have been proposed
to improve the interface quality[45{49] by reducing the interface trap density. Currently,
the interface trap density for Si/SiO2 is around 109cm?2eV?1, while the density for 4H-
SiC/SiO2 is 1011cm?2eV?1 at best. Interface trap density for SiC/SiO2 will be discussed
in more detail in later chapters.
27
2.2 MOSFETs
The metal-oxide-semiconductor fleld efiect transistor (MOSFET) is a fundamental
semiconductor device that is widely applied in both analog and digital circuits. With
the dramatic shrinking of chip size, millions of MOSFETs can be integrated into an area as
small as 1 mm2.
2.2.1 Device Structures
Although various speciality structures can be found in the literature, the basic MOS-
FET is nothing more than an MOS-capacitor plus two p-n junctions. Figure 2.7 shows the
structure of a lateral n-MOSFET. Two N+ zones are called source and drain respectively,
where \+" means high doping. Above the oxide layer is a metal gate such as Al or Mo.
The source and drain have metal layers, as well, that are annealed at high temperature to
form ohmic (i.e., non-rectifying) contacts to the N+ regions of the semiconductor. Another
ohmic contact is also formed on the bottom side of the semiconductor. If bottom side of
semiconductor is highly doped, annealing is not necessary since the backside ohmic con-
tact is a large area contact. Besides lateral test MOSFETs, other structures are designed
for particular applications. For example, vertical geometry MOSFETs handle high power.
Lateral test MOSFETs were used in this work.
2.2.2 Device Characteristics
The working mechanism of the MOSFETs is not complicated. From flgure 2.7, it is
easy to see that, if the gate voltage is not applied, no current  ows from source to drain,
because a reversed biased p-n junction blocks any electron  ow no matter the polarity of
28
Fig. 2.7: The structure of a lateral n-MOSFET.
the source-drain voltage. However, if gate voltage is not zero, the situation will be difierent.
According to flgure 2.7, the substrate is p type semiconductor material; therefore negative
gate voltage will make holes accumulate at the O-S interface, and current cannot  ow along
the interface in the p-type semiconductor. However, when positive voltage is applied on
gate, holes are repelled from the O/S and electrons simultaneously will move up to the
interface. This movement creates a depletion layer, as described previously. With more
positive voltage applied, the surface of the semiconductor inverts to produce an n-type
channel that connects the S/D regions of the device. If a voltage exists between the source
and drain terminal, current  ow will be observed. Generally, the source terminal is grounded
and voltage is applied on drain terminal. The voltage and corresponding current are called
drain voltage and drain current, respectively, or simply VD and ID. Gate voltage is noted
by VG.
The voltage applied on the gate to create the n-channel is an important quantity, which
is called threshold voltage, VT. Simply speaking, the MOSFET will conduct if VG > VT,
29
but only when VD is small compared to VG ?VT. If VD is positive and large enough, the
channel region near the drain will see a modifled bias voltage. The result slows the rate
of increase in the current  ow. When channel near the drain is \pinched-ofi", the current
through the drain will no longer increase, but rather remain constant. Figure 2.8 depicts
the above explanation.
Fig. 2.8: MOSFET operated (a) in the linear region (low VD,), (b)
at onset of saturation, and (c) beyond saturation[38].
30
Linear and Saturation Regions
In this section, we begin by discussing the ideal MOSFET . By \ideal", we are speaking
of several conditions: (1) gate-oxide-semiconductor is similar to that of the MOS-capacitor;
(2) only drift current will be considered; (3) there exists a constant carrier mobility in the
inversion layer; (4) semiconductor is uniformly doped; (5) reverse leakage current is very
small and can be neglected; (6) the transverse fleld in the channel is much larger than the
longitudinal fleld[38]. Under these idealized conditions, the conductivity of the inversion
channel can be written as
 (x) = qn(x)?n(x): (2.23)
In the above equation, n(x) is the carrier concentration in the channel, and ?n(x) the
channel mobility. The conductance of the inversion channel will be
g = ZL
Z xi
0
n(x)dx; (2.24)
in which Z is the channel width, L the channel length and x is measured from the interface
into the semiconductor. Assuming the channel mobility is constant, the conductance will
be
g = qZ?nL
Z xi
0
n(x)dx = qZ?njQnjL ; (2.25)
in which Qn is the total charge in the inversion channel. Let us consider a small element
in the channel and assume the length of this element is dy. The voltage drop across this
element will be
dV = IDdR; (2.26)
31
and
dR = dygL = dyZ?
njQn(y)j
; (2.27)
where ID is the drain current that does not change with location in the channel. It can be
shown[38] that the inversion charge in the channel is
Qn(y) = ?[VG ?V(y)?2?B]Ci +
q
2?sqNA[V(y)+2?B]; (2.28)
where VG is the applied gate voltage, V(y) is the bias between a speciflc point y and the
source, ?B is the bulk potential, and Ci is the capacitance per unit area. If we integrate
equation 2.26 from the source to the drain, given that V(y = 0) = 0 and V(y = L) = VD,
the drain current can be expressed as
ID = ZL?nCif(VG ?2?B ? VD2 )VD ? 23
p2?
sqNA
Ci [(VD +2?B)
3=2 ?(2?B)3=2]g: (2.29)
From the above equation, we can infer important characteristics of MOSFET. When
VG is given and VD is small, by expanding in a Taylor series and keeping only the flrst-order
terms, we can get a simplifled expression for ID,
ID ?= (Z=L)?nCi(VG ?VT)VD (2.30)
for VD ? (VG ?VT) where VT is called the threshold voltage, a very important MOSFET
parameter
VT = 2?B +
p2?
sqNA(2?B)
Ci : (2.31)
32
This tells us ID ?VD is a straight line when VD is small. This region is called linear region
of the MOSFET. By taking derivative of ID with respect to VD or VG, we can obtain the
expression for the channel conductance and transconductance. They are
gD ? @ID@V
D
jVG=const = (Z=L)?nCi(VG ?VT) (2.32)
gm ? @ID@V
G
jVD=const = (Z=L)?nCiVD: (2.33)
Fig. 2.9: The drain current - gate voltage characteristics of an
MOSFET.
If VD is not small, but instead large enough that Qn(y = L) = 0, the MOSFET enters
the saturation region and the point where VD applied leads to zero charge at y = L is
called ?pinch-ofi?. At this point, we name VD and ID as VDsat and IDsat, respectively. The
33
complete drain current versus drain voltage plot is shown in flgure 2.9. Theoretically, by
solving equation for Qn(y), we can obtain the values of VDsat and IDsat.
VDsat = VG ?2?B + ?sqNAC2
i
(1?
q
1+2VGC2i =?sqNA); (2.34)
and
IDsat ?= mZL ?nCi(VG ?VT)2; (2.35)
in which m is a function of doping concentration and roughly equal to 1/2 for light doping.
VT is same as previously stated if doping is low, and the insulator is thin. However, when
these two conditions are not satisfled, VT will be a function of VG. In saturation region, the
transconductance is given by
gm = @ID@V
G
jVD=const = 2mZL ?nCi(VG ?VT): (2.36)
In real measurements, the channel mobility can be calculated using the above equation by
measuring drain current as a function of the gate voltage.
The MOSFET device characteristics we have discussed so far describe ideal devices.
In the following section, several real issues related to MOSFETs will be discussed, and
corresponding adjustments will be made to describe the real devices.
Work Function Difierence
As with MOS-capacitors, the metal gate - semiconductor work function difierence is an
unavoidable problem which requires that we introduce the term `ms and write the threshold
34
voltage as
VT = `ms +2?B +
p4?
sqNA?B
Ci : (2.37)
Fixed Oxide Charges
Considering the flxed oxide charges Qf, the threshold voltage will be
VT = `ms ? QfC
i
+2?B +
p4?
sqNA?B
Ci : (2.38)
In addition to the non-idealities discussed above, channel doping uniformity, channel length
and temperature afiect the MOSFET characterisitics, particularly the threshold voltage,
the subthreshold slope and the channel mobility.
35
Chapter 3
SiC-based MOS Devices Properties
3.1 Oxidation of SiC
The oxidation of SiC is the most important process of SiC-based MOS devices, since
the quality of the oxide layer critically determines the devices? performance[50]. Of many
oxidation processes, the thermal oxidation is the most commonly used one due to the fact
that thermal oxidation techniques of silicon can be applied directly, and yields a better
interface quality than other methods. Other methods for putting an oxide layer over SiC
include sputtering, chemical vapor deposition, and pulsed laser deposition. In this thesis,
we focus only on thermal oxidation.
ThemechanismofthermaloxidationofSiChasbeeninvestigatedboththeoreticallyand
experimentally. First-principle calculations are used to study the atomic-scale mechanisms
of the nucleation and growth of SiO2 precipitates in cubic SiC[51, 52]. In his work, Di
Ventra et al.[51] proposed the mechanisms of the oxidation process on SiC. They found
by calculation that oxygen atoms difiused onto the surface of SiC and formed an advance
interface of SiC/SiO2. The excess carbon atoms were emitted out of the system in the
form of CO, as conflrmed experimentally by Tan et al.[53]. When thicker SiO2 layer was
formed, CO had to difiuse through the oxide layer to take out carbon atoms. Through
simulation, they found CO may break up either at the interface of SiC/SiO2 or in the
36
SiC bulk. The broken oxygen atom would participate in another round of oxidation and
carbon atom would remain. This result explained why carbon clusters are found at the
interface of SiC/SiO2. Wang et al.[52] went further. When CO difiused through the oxide
layer, two or more CO molecules might interact and the result was the more complicated
structure formed. One of the consequences was the emission of CO2, not just CO. However,
no experimental evidence has been reported to support this result yet. Knaup et al.[54]
reported in their theory work that carbon interstitials and stable carbon pairs grow into
the oxide as well as CO molecules. Combined with silicon interstitials, these defects were
thought to be the sources of NIT (near-interface traps).
Shenoy et al.[55] study experimentally the efiect of substrate orientation on thermal
oxidation on SiC. They noticed the oxidation rate depended signiflcantly on the crystal
orientation of SiC. For instance, a-axis planes of SiC oxidize at rates as much as 3-5 times
faster than the Si-face c axis. Figure 3.1 shows the oxide thickness on (0001) and (11?20)
orientated 6H-SiC for three difierent oxidation times.
3.2 SiC/SiO2 Interface
Although SiC is superior to silicon in many aspects, a number of improvements need to
be made before it can replace silicon as the dominant semiconductor. The problem which
impedes the real application of SiC in MOS devices is the quality of the interface between
SiC and SiO2. Please note only the interface of SiC/SiO2 produced by thermal oxidation
is under discussion.
37
Fig. 3.1: Comparison of oxide thickness on (0001) and (11?20) ori-
ented 6H-SiC as a function of oxidation time[55].
38
In order to study the interface states of SiC/SiO2, many experimental methods have
been used. Afanasev et al.[56] determined the interface state density by admittance spec-
troscopy. McDonald et al.[57] employed SIMS(Secondary Ion Mass Spectrometry) to study
howSiCandSiO2 areconnected; Chunget al.[58] usedthesimultaneoushigh-lowcapacitance-
voltage technique to obtain the interface state density of SiC/SiO2. Bardeleben et al.[59]
studied the SiC/SiO2 interface by EPR (Electron Paramagnetic resonance) [59{61]. Other
techniquesincludeAFM(AtomicForceMicroscopy)[62], EELS(ElectronEnergyLossSpectroscopy)[63],
SER (Surface Sensitized Raman)[64], and XPS (X-ray photoelectron spectroscopy)[65]. The
efiort dedicated by the researchers has created a detailed picture of the interface between
SiC and SiO2. In the following sections, the current research on the interface of SiC/SiO2
will be reviewed and the challenges will be discussed.
IthasbeenreportedthattheinterfacetrapdensityofSiC/SiO2 rangesfrom1011cm?2eV?1
to1013cm?2eV?1[56], whiletheinterfacetrapdensityofSi/SiO2 is109cm?2eV?1. Thehigher
interface trap density results in lower inversion channel mobility of MOSFETs[66, 67]. It is
unclear whether the worse interface quality comes from the intrinsic SiC/SiO2 system or
the thermal oxidation process[68]. However, for the last 10 years, people have been flnding
a lot of useful information of the SiC/SiO2 interface[67{71].
Shenoy et al.[69] used hi-lo capacitance-voltage technique and AC conductance tech-
nique at elevated temperatures to characterize the MOS interface of p-type 6H-SiC, because
they found only by doing this can they obtain the information of the interface states beyond
0.6eV from the band edge, or the deeper levels of the band gap, which are too stable to be
charged and emitted at room temperature and low frequency. Friedrichs et al.[70] reported
the interface properties of MOS structure of n-type 6H and 4H-SiC. From both theory and
39
experiments, they showed that the SiC/SiO2 interfaces are more sophisticated than the
Si/SiO2 interfaces. Moreover, 6H-SiC showed a better interface quality than 4H-SiC did.
To study the interface state very near to the band edges, Saks et al.[67] used Gray-Brown
C-V technique to obtain proflles of Dit close to both band edges of 4H-SiC. In their work, Dit
increased rapidly close to the conduction band edge. Dhar et al.[71] used similar method to
reveal the ultrashallow defect states (EC-E?=0.05-0.2eV) at SiO2/4H-SiC interfaces. A Dit
peak at ?0.1eV below the conduction band edge is found with an energy width of ?0.2eV
and a magnitude of ? 2?1013cm?2eV?1. Figure 3.2 shows the interface trap density (Dit)
of difierent polytypes of SiC along the band gap energy[68]. Sch?orner et al.[66] found most
interface defects of SiC/SiO2 are located at around 2.9eV above the valence band. Con-
sidering the band gap information of several SiC polytypes, 4H-SiC will have more defects
in the gap rather than other polytypes like 6H- and 15R-SiC. This also explains why the
inversion channel mobility of 4H-SiC is lower than that of other polytypes.
The SiC/SiO2 interface roughness may come from the following: (1) the surface atom
density of SiC is larger compared to that of silicon, (2) a transition layer exists instead of
a perfect connection of SiC and SiO2[65], (3) carbon cluster accumulates at the interface
during the oxidation, (4) the near-interflcial oxide traps, and (5) Si- and C- dangling bonds.
While investigating the interface charges of SiO2/Si on difierent surface orientations,
Vitkavage et al.[72] found a strongly positive relationship between the silicon surface atom
density and the charge density of the Si/oxide interface. Inspired by this article, Afanasev
et al.[56] suspected the higher surface atom density of SiC contributes to the higher interface
trap density of SiC/SiO2, since a higher density of dangling bonds may be produced during
the oxidation process. In the same work, Afanasev et al. also found the dopant species
40
Fig. 3.2: Interface state density Dit as a function of energy for 3C-
SiC/SiO2 squares, black squares, 6H-SiC/SiO2 circles, bullets, and
4H-SiC/SiO2 triangles, black triangles MOS structures determined
from admittance spectroscopy fllled symbols and from constant-
capacitance deep-level transient spectroscopy open symbols[68].
41
(N, Al, B) do not afiect the magnitude and distribution of the interface trap density (Dit).
They drew the conclusion that Dit is dominated by intrinsic defects at the interface. They
also noticed the higher interface trap density of carbon face SiC/SiO2 may be attributed to
the higher surface carbon atom density of c-face SiC, as compared to Si-face SiC. ?-bonded
carbon clusters (sp2- bonded carbon units) were believed to play an important role in the
increased interface state density. Electron energy loss spectroscopy (EELS) also showed a
high-carbon concentration at the SiO2/6H-SiC(0001) interface[63]. The carbon-rich region is
10-15?A in thickness, and may be produced by the kinetically limited formation and removal
of volatile CO molecules. The C- dangling bonds were also found at the interface states
around 1.8eV above the valence band maximum (VBM) by Kobayashi et al.[73] when they
were studying the interface states at silicon face 6H-SiC/SiO2 by using x-ray photoelectron
spectroscopy (XPS). Meanwhile they found a broad interface-state peak at around 2eV
above the VBM, which they believed was attributable to Si- dangling bonds at the interface.
They also noticed that the density of the Si- dandling bonds did not depend strongly on
the oxidation temperature and atmosphere, while that of the carbon-related interface states
were strongly dependent on them.
The interface state density is also afiected by the near-interflcial oxide traps (NIT).
These traps are those oxide traps located very close to the interface and being able to trap
a charge carrier from the semiconductor or to emit it back into the semiconductor[56]. The
PST technique (photon stimulated electron tunneling) was used to detect the location of
oxide traps relative to the conduction band edge of several semiconductor materials like
silicon, 3C-SiC, 4H-SiC and 6H-SiC. It was found that the oxide traps always occur at
the same locations relative to the oxide conduction band edge, say 2.77eV below the SiO2
42
conduction band edge. For silicon, 3C-SiC, 6H-SiC, the traps are still in the oxide layer.
But for 4H-SiC, the traps are located at the interface. Therefore, the oxide traps contribute
to the interface state of SiC, especially the 4H-SiC. In theoretical work of Knaup et al.[74],
carbon pairs are believed to contribute to the NIT.
Based on the above review, it is clear that the interface quality of SiC/SiO2 plays a
very important role in the function of SiC-based MOS devices. To improve the quality of
SiC MOS devices, the flrst thing to do is improve the interface state of SiC/SiO2. Ex-
perimentally, people have found pre-oxidation ultraviolet-ozone cleaning or post-oxidation
annealing enhances the quality of the interface[34, 58, 75{77]. The latter will be discussed
mainly in this work.
3.2.1 Post-Oxidation Annealing
Post-oxidation annealing has been a main technique to enhance the interface quality
of SiC/SiO2. Varying gases may be used in this process.
Nitridation
Li et al.[77] used NO in post-oxidation annealing of 6H-SiC/SiO2 and found the interface
state density reduced dramatically. However, the use of N2O in the post-oxidation annealing
increased the interface state density. Figure 3.3 shows the interface trap density after NO
and N2O annealing. Chung et al.[58] reported the improvement of the interface quality
of 4H-SiC/SiO2 by using NO post-oxidation annealing. This improvement, however, only
occurs at the upper half of the gap. They also explained theoretically the NO efiect on
the interface in flgure 3.4, according to which, the carbon clusters will move from near the
43
Fig. 3.3: Interface state density versus gate voltage for MOS ca-
pacitors with three difierent types of dielectrics[77].
44
conduction band downward to near the valence band, and some small carbon clusters even
enter the valence band. The consequence is the interface trap density near the conduction
band is reduced dramatically. In another article, Chung et al.[78] tried another type of
gas, ammonia or NH3, in the post-oxidation annealing. Compared to control samples that
were not annealed, Dit was reduced about 85%. Moreover, NH3 can lower the flxed charge
density and efiective charges in the oxide since the anneals incorporate an extensive amount
of nitrogen throughout the oxide[78]. However, McDonald et al.[57] show that NH3 anneals
remove oxygen in the oxide, change the oxide stoichiometry, increase the dielectric constant
and decrease the breakdown fleld. They, therefore, conclude that the nitridation in NO is
a better technique to reduce the Dit in MOSFETs. Nitridation is also used to reduce the
interface state of other polytypes of SiC[79].
Fig. 3.4: (a) Energy levels for interstitial C and C clusters in SiC.
(b) C and C clusters in SiC following N passivation[58].
Although the experiments have already shown the efiectiveness of nitridation on reduc-
tion of interface state of SiC/SiO2, the mechanism for the reduction is not clear. However,
several theories have been suggested for investigation[80, 81]. X-ray photoelectron spec-
troscopy after nitridation shows the formation of Si?N bonds[82], which is also suggested by
the observation of the slower oxidation rate. The slower oxidation rate implies the reduction
45
of the carbon clusters at the interface, considering the fact that (000?1) 4H-SiC has much
higher oxidation rate than (0001) does. Gavrikov et al.[81] also proposed a mechanism of
nitridation that the introduction of N suppresses the lateral moving of the carbon atoms
and therefore reduces the possibility of formation of carbon clusters.
Fig. 3.5: Schematic plot of a plasma nitridation furnace[34].
The above reviews indicate the nitridation is an efiective tool to reduce the interface
state density of SiC/SiO2. The way they did the nitridation was introducing NO into a
heated environment in which SiC/SiO2 structure was loaded. NO post-oxidation annealing
introduces oxygen at the same time and creates new interface, which weakens some the
efiectiveness of nitridation. To solve this problem, some approaches are proposed. Plasma
nitridation is one method[34]. Figure 3.5 shows the experimental set-up used in the plasma
nitridation. In this process, N2 gas is introduced into the quartz tube and microwave
generator breaks N2 into nitrogen atoms. Nitrogen atoms at high temperature will difiuse
through SiO2 all the way to the interface of SiO2/SiC and improve the interface structure.
46
Figure 3.6 shows the change of Dit of (0001) 4H-SiC/SiO2 after plasma nitridation with
varying lengths of time[34]. Another approach is nitrogen ion implantation followed by high
temperature annealing.
Fig. 3.6: Comparison of Dit of silicon face 4H-SiC/SiO2 before and
after plasma nitridation[34].
Hydrogen Passivation
HydrogenhasbeenknownefiectivetoreducetheinterfacestatesdensitiesofSi/SiO2[83],
because silicon dangling bonds can be reconnected in the form of Si-H. A number of in-
vestigations have been conducted to see if the hydrogen passivation enhances the interface
quality of SiC/SiO2[56]. The results demonstrate no signiflcant reduction of the interface
state of SiC/SiO2. This implies that the silicon dangling bonds are not the main cause of
the interface defects and only hydrogen passivation dos not improve the interface quality
signiflcantly. The combination of nitridation and hydrogen passivation, however, yields a
47
lower Dit on SiC/SiO2 than simple nitridation does, especially at the deep level[84], as shown
in flgure 3.7. More speciflcally, Wang et al.[85] conclude that isolated carbon dangling bonds
with various backbond combinations have a level in the midgap region and can be passi-
vated by either H or H2, but the difierent local geometries of correlated carbon dangling
bonds can only be passivated by H.
Fig. 3.7: SiC/SiO2 interface state density proflles in the upper half
of the 4H-SiC band-gap for the difierent interface treatments[85].
3.3 Oxide Reliability on SiC
The native oxide of SiC is SiO2. This property makes SiC a unique compound semi-
conductor material, because the fabrication techniques on silicon can be applied on SiC and
many experiments on Si-MOS devices will also be used on SiC-MOS devices.
48
In an MOS device, the oxide is of importance. The role of the oxide is to block the
current driven by the voltage applied between the gate and the substrate. When the oxide
breaks down, the MOS device is destroyed. Oxide reliability means the ability of the oxide
to be stable under operational conditions. When a higher voltage is applied, the oxide
tends to break down. Usually, for an oxide of a speciflc thickness, breakdown electric fleld
is often used to describe the blocking strength of the oxide. To test the reliability of an
oxide, current-voltage (I-V) measurements are employed to obtain the breakdown fleld.
In the I-V measurement, applied voltage is increased from 0 to a high value, at which a
deflned breakdown current goes through the oxide. The value of the gate voltage causing
the breakdown of oxide is called breakdown voltage. By simply calculation, the breakdown
fleld can be determined from breakdown voltage.
Eox = Vg ?`mst
ox
(3.1)
where Eox is the electric fleld inside the oxide, Vg is the voltage applied on the gate, `ms
is the work function difierence of gate metal and semiconductor, and tox is the thickness of
the oxide.
3.3.1 Oxide Failure Mechanism
It is necessary to understand the physical process to determine the direction for im-
proving the reliability of the oxide. The degradation of oxide is not a short-time process in
practical environments. This process always starts with the accumulation of carriers at the
interface of oxide and semiconductor. With the presence of difierent electric flelds on oxide,
49
the carriers will obtain difierent kinetic energies for attempting to pass over the barrier
between oxide and semiconductor. The term of \injection" is used to describe the penetra-
tion of carriers. At difierent levels of electric fleld, difierent injection mechanism rules the
form of the penetration of carriers: quantum tunneling, thermionic emission, Frankel-pool
emission and Fowler-Nordheim tunneling. Of these four injections types, quantum tun-
neling and thermionic emission are two happening at all time, even without electric fleld.
They actually originate from the nature of probability and temperature, respectively. The
relationship of current density and electric fleld in thermionic emission can be written as:
JTE = A?T2 exp(?q`b ?
pqE=4??
ox
KbT ) (3.2)
, where JTE is the current density through the oxide, A? the efiective Richardson constant,
q the carrier charge, `b the barrier height, E the oxide electric fleld and T the temperature.
Frankel-pool emission refers to the current generated by electrons trapped in the oxide at
high fleld, and generally is treated as an extrinsic injection mechanism. The corresponding
J-E relationship is as follows.
J ? Eexp(?q(`B ?
pqE=??
i)
KbT ) (3.3)
, where the parameters are similarly deflned as those in thermionic emission. Fowler-
Nordheim tunneling is also called as fleld emission. It is an injection process in which
carriers tunnel into the oxide from either gate or semiconductor under the in uence of high
50
electric fleld. The F-N tunneling can be expressed by the following equation:
JFN(T) = A(T)E2ox exp(?B(T)E
ox
); (3.4)
where
A(T) = q
3m
8??hmox`b; (3.5)
and
B(T) =
4
q
2mox`3b
3q?h : (3.6)
In above equations, q is the electron charge, m and mox are the efiective electron mass
in the semiconductor and oxide, respectively, ?h is the Plank constant, Eox is the electric
fleld in the oxide, and 'b is the efiective barrier height. Since SiC has a smaller barrier
height than silicon (see flgure 1.8), it is expected that F-N tunneling is more dominant in
the injection of SiC-MOS device.
3.3.2 Time Dependent Dielectric Breakdown (TDDB)
TDDB measurement is a kind of method to test the reliability of MOS devices. In the
measurement, voltage is applied on devices to keep semiconductor at accumulation region.
Elevated temperatures might be used as well. The time it takes before the breakdown
current occurs is deflned as the lifetime of a MOS device. Tens of devices are measured at the
same time, so the statistical result of failure time can be obtained. In TDDB measurement,
the electric fleld in the oxide is generally higher than that used in practical operation, thus
51
accelerating the measurement. Elevated temperatures might be used for the same goal.
The actual lifetime of devices at low fleld can be extrapolated from the data at high fleld.
Figure 3.8 shows the schematic of a reliability test circuit. Maranowski et al.[86] found
from the TDDB measurements that n-type 6H-SiC MOS devices showed a comparable or
even better reliability at fleld lower than 4MV/cm than silicon MOS-devices, but a worse
one at high fleld like 7-9MV/cm. It was concluded that the oxide reliability precluded SiC
MOS devices from many high-temperature applications. Reliability of nitrided oxides in
4H-SiC MOS devices was investigated by Krishnaswami et al.[87], 100-year Mean Time to
Failure (MTTF) was estimated for the oxides working at 175oC and 3MV/cm.
Fig. 3.8: Schematic of the reliability test circuit[86].
Other investigations on the SiC oxide reliability have also been carried out. Alok et
al.[88] used I-V and C-V measurements to test the quality of thermal oxide grown on n-type
6H-SiC. They found a barrier height of 2.7eV by fltting with Fowler-Nordheim injection
mechanism. Combined with information about the interface quality, efiective charge density,
breakdown fleld, they concluded that 6H-SiC oxides were comparable to those grown on
silicon. Agarwal et al.[89] compared the reliability of 4H-SiC MOS devices with 6H-SiC MOS
devices. Both polytypes were n-type materials. They obtained data for current densities and
52
electric flelds, computed the efiective barrier heights of both polytypes MOS devices from
Fowler-Nordheim injection theory. 4H-SiC MOS devices showed a smaller barrier height,
which is in agreement with results from experimentalists[90, 91]. Compared with silicon MOS
devices, both polytypes did not show a better performance in reliability. P-type 4H-SiC
MOS structures were studied by Chanana et al.[92]. Fowler-Nordheim hole tunneling was
conflrmed in their measurements. Using the barrier height of 2.9eV, they obtained the
efiective hole mass which is 0.35m to 0.52m, where m is the free electron mass.
3.3.3 Negative Bias Temperature Instability (NBTI)
It has been demonstrated that a negative gate voltage would degrade channel mobility,
causing a threshold voltage shift, and reducing the drain current. NBTI occurs in silicon
industry[93], the same problem has been found in SiC-based MOS devices[94]. The investiga-
tion on both silicon and SiC MOS devices has led to this conclusion: NBTI efiect originates
from interface and oxide trap generation. Further studies show this efiect occurs only in the
presence of negative gate voltage, holes in the semiconductor, and at elevated temperatures.
3.4 SiC-Based MOSFETs
SiC, because of its high thermal conductivity, wide band gap, and native oxide of SiO2,
has been chosen as a preferable candidate for MOSFET devices, especially those working
in an extreme environment. The bulk electron mobility of 4H-SiC is as high as 1000cm2/V-
s, which is comparable to that of silicon. However, the inversion channel mobility of SiC
MOSFET is very low compared to the bulk mobility. This situation was not observed
in the case of silicon, whose typical inversion channel mobility is 800 - 1000cm2/V-s, not
53
big reduction compared to its bulk mobility of 1400m2/V-s. Much work has been done to
understand the reason for the low inversion channel mobility of SiC-MOSFET as well as a
method that improves the inversion channel mobility[45, 66, 95{97].
The low inversion channel mobility is attributed to the poor quality of interface of
SiC/SiO2. Attempts to enhance the inversion channel mobility have concentrated on reduc-
ing the interface states of SiC/SiO2. In this section, a few results concerning the inversion
channel mobility of difierent polytypes SiC MOSFETs will be reviewed.
Sch?orner et al.[66] used 4H-SiC, 6H-SiC and 15R-SiC to build MOSFETs. The low fleld
mobility is signiflcantly higher for both 6H-SiC and 15R-SiC than 4H-SiC, the corresponding
Dit of SiC/SiO2 is approximately one order of magnitude lower for 6H and 15R polytpes
than for the 4H polytype. They believed the oxide defects, which are located at 2.7eV above
the valence band, cause the bad interface quality and low channel mobility of 4H, because
4H-SiC has a band gap of 3.2eV and most defects fall in the gap. For 6H and 15R polytypes,
those defects will be at the conduction bands because of their narrow bandgap compared to
4H-SiC. Chung et al.[95] used NO to anneal the interface of 4H-SiC/SiO2 and successfully
reduced the interface trap density. They applied the same passivation process to (0001) 4H-
SiC MOSFETs and found the inversion channel mobility could be improved from 3cm2/V-s
to 35cm2/V-s[95]. It was the flrst time that the substantial improvement was observed in the
inversion channel mobility for lateral n-channel MOSFETs fabricated with standard thermal
oxidation techniques and standard 4H-SiC. A similar improvement of channel mobility on
4H-SiC n-channel MOSFET was also achieved by Sch?orner et al.[96]. The peak value of
inversion channel mobility they reported was 48cm2/V-s. An important difierence to note
it that the temperature Sch?orner et al. used to anneal the source and drain implanted
54
regions was 1700oC, 150oC higher than that typically used. The efiect of implant anneal
temperature on the inversion channel mobility was also studied by Lu et al.[45]. Only minor
in uence of temperature on the channel mobility was found. Moreover, they checked the
efiects of other process variations, such as oxidation procedure, post-oxidation annealing,
type of gate material, and ohmic contact annealing. Other than post-oxidation annealing in
NO, no process variations show signiflcant improvement to the channel mobility of silicon
face 4H-SiC MOSFETs. The roughness of the SiC/SiO2 was investigated by Fukuda et
al.[98] for improvement of the channel mobility of carbon face 4H-SiC MOSFETs. They
found the channel mobility of MOSFETs fabricated on the (000?1) 4H-SiC with 8o ofi-angle
is approximately 10% higher than that of MOSFETs fabricated on (000?1) 4H-SiC with the
vicinal (below 1o) ofi-angle, although the lower one is already above 80cm2/Vs. Considering
the higher ofi-angle gives the higher roughness, they concluded that the roughness is a main
factorafiectingthechannelmobility. TheroughnesscanberevealedfromtheDit asobtained
from C-V measurement, their conclusion is the same that the inversion channel mobility is
determined by the interface quality.
As a summary, the interface quality of SiC/SiO2 is signiflcant in determining the per-
formance of SiC-based MOSFETs. NO post-oxidation annealing not only can reduce the
interface trap density, but also improves the inversion channel mobility of MOSFETs. The
ofi-angle of substrate material can afiect the performance of MOSFETs, while other factors
do not show comparably signiflcant efiects on the channel mobility of MOSFETs.
55
Chapter 4
MOS Device Fabrication Techniques and Measurements
In this chapter, the experiment details of MOS devices fabricated on 4H-SiC will be
discussed. The performance of a device is determined by the fabrication process. Statistical
results for a set of devices depend dramatically on the consistency of the fabrication steps.
Therefore, it is very important to methodically apply the key processes of device fabrication
and strictly follow proven processing procedures. Careful characterization of the devices is
important, as well. The most commonly used measurements for characterization will also
be discussed in this chapter.
4.1 Oxidation
Oxidation is the most important step in MOS devices fabrication, since the oxide layer
is the most critical part of the devices[50]. Difierent methods of oxidation have been used to
improve the oxide reliability, as mentioned in chapter 3. Simply speaking, a layer of SiO2
will be grown on a SiC wafer during the oxidation process. SiC is the only wide band gap
semiconductor that has a tavie oxide, and thermal oxidation is the most commonly used
method for SiC MOS devices fabrication[99]. There are two types of thermal oxidation: dry
oxidation and wet oxidation. It should be noted that careful cleaning prior to oxidation is
important for the oxide?s quality. Detailed process of cleaning can be found in appendix A.
56
Fig. 4.1: Furnace for dry oxidation.
57
4.1.1 Dry Oxidation
Dry oxidation can be carried out in a quartz tube furnace, which is shown in flgure 4.1.
The oxygen gas is introduced at one end of the tube and exhausted from the other end.
The typical oxidation process is as follows:
(1) Turn on argon gas and  ush the quartz tube for 5minutes;
(2) Open the tube and load the wafer;
(3) Close the tube and hold the temperature at 900oC for 30 minutes;
(4) Increase temperature at the step of 5oC/minute to 1150oC;
(5) Switch Argon to oxygen for oxidation for desired time;
(6) Switch oxygen to Argon;
(7) Decrease temperature at the step of 20oC/minute to 900oC;
(8) Open the tube and unload the oxidized wafer;
(9) Close the tube and turn ofi Argon gas and keep Argon at atmosphere pressure in the
tube.
In step (1), Argon gas may be substituted by oxygen. The above dry oxidation process
is carried out at atmospheric pressure, but lower pressure has also been used to study the
relationship between the oxidation rate and pressure[16].
4.1.2 Wet Oxidation
The wet oxidation uses the similar facilities compared to dry oxidation. One difierence
is an additional input gas line added to introduce small  ow of oxygen which contains
moisture produced by passing the oxygen through deionized water heated to around 95oC.
Figure 4.2 shows the DI-water container. Wet oxidation is carried out at temperature of
58
950oC and atmosphere pressure. Since the introduced moisture may stay at the internal
wall of the tube and afiect future oxidation, the argon  ow is usually used to  ush the whole
system afterward for at least 30 minutes.
Fig. 4.2: Deionized water container for wet oxidation. The con-
tainer is heated and two ends are connected to input and output
gas lines.
4.1.3 Post-Oxidation Annealing
Post-oxidation annealing is an important process that is used to improve the interface
quality for SiC/SiO2. The anneal is usually performed in the same quartz tube furnace
used for oxidation. The temperature of post-oxidation annealing depends on the type
of annealing. For nitric oxide (NO) and ammonia (NH3) post-oxidation annealing, the
temperature is 1175oC and the anneal time is 2hr. For H2 post-oxidation annealing, the
temperature is 500oC for 1hr, and a thin layer of platinum is put on the surface of SiO2 to
59
act as a hot catalyst to break the H2 molecules into single atoms. It is noteworthy that H2
molecules, instead of H atoms, are used to anneal Si/SiO2 interface.
4.2 Lithography
Lithography is a method for pattern printing that has become an important step
in the micro-fabrication process. There are two types of lithography in terms of accu-
racy requirements: microlithography and nanolithography. In microlithography, photo-
lithography is the most commonly used, especially in the area of semiconductor manufac-
turing of microchips. Electron beam lithography is one of nanolithography methods. E-
beam lithography can deflne the pattern with higher resolution, but lower speed, compared
to photo-lithography. Other lithography methods include nanoimprint lithography, inter-
ference lithography, X-ray lithography, extreme ultraviolet lithography and scanning probe
lithography. Photo-lithography, the main lithography tool in laboratory, will be discussed
in the remainder of this section.
Figure 4.3 can be used to describe the general process of photo-lithography. The
equipment that is used is a mask aligner, which is shown in flgure 4.4.
There are two types of photoresist: positive photoresist and negative photoresist. The
photoresist in flgure 4.3 is a positive resist. If negative photoresist is used, the area exposed
to ultraviolet light will remain after development and other unexposed areas will be washed.
The developing solution is difierent for negative photoresist.
The photoresist is applied on the surface of sample by using spinner. The spinner
sticks the backside of the sample with vacuum and rotates with a speciflc speed(usually
4000RPM) for a time interval(usually 30 seconds). The photoresist, applied on the center
60
photoresist photoresist
photoresist
(a)
SiC
UV-light
mask
photoresist
(b)
Fig. 4.3: Schematic of a general photo-lithography process. (a)
Photoresist is applied on the SiC wafer; (b) The wafer is exposed
through a mask to UV light; (c) A chemical reaction takes place in
the exposed photoresist; (d) Photoresist after development.
61
Fig. 4.4: Mask aligner for photo-lithography.
62
of the sample, will spread out and coat the sample uniformly. The thickness of photoresist
on the sample after spinning is greater than 10000?A. If the photoresist is too thin, the lift-ofi
process might be di?cult.
The soft baking is needed after spinning to make the photoresist become light-sensitive.
The corresponding temperature is around 100oC and baking time is 60 seconds. When
exposing photoresist to UV light, it is important to make sample fully contact with the
mask. Otherwise, the edge of photoresist will not be clear and the lift-ofi process may be
afiected. The power of UV light is 160W and exposing time is 30 seconds.
In the process of development of pattern, avoiding over-development is very important.
Itisagoodhabittocheckthepatternwithmicroscopeseveraltimesduringthedevelopment.
If the edge of photoresist is clear and sharp, it means the development is flne.
Double exposing is required when inverse lithography is needed. Between the two
exposing processes, there is another baking at the temperature of a little higher than 100oC
for 60 seconds. The second exposing process will last 60 seconds and no mask is applied.
4.3 Metal Deposition
Metal deposition can be accomplished by various methods. Sputtering deposition is
one of them and this technique is used in our laboratory. The sputtering system is shown
in flgure 4.5 and the working mechanism is explained by flgure 4.6.
The sputtering system is usually maintained at high vacuum. When samples are to
be coated with a thin fllm, nitrogen gas is used to flll the chamber atmospheric pressure
(760Torr). The samples are held by screws on the underside of substrate mounting plate,
which can be rotated when multiple sputter targets are used. Four targets can be installed
63
Fig. 4.5: DC/RF sputtering deposition system.
ArsuppressGas
Sputteringsuppresstarget
Substratesuppressforsuppressdeposition
Ar+
Fig. 4.6: Working mechanism of the sputter deposition process.
64
in the vacuum chamber at one time. The target to be used will be covered with an open
glass chimeny to keep sputtered materials moving only vertically. Each chimney is only
used for speciflc target to avoid cross contamination. When a sputter target is changed, the
cooling water to the gun head must be shut ofi to prevent any water getting into the vacuum
chamber. To avoid contamination, high vacuum must be obtained before sputtering. The
usual achieved pressure is 4?10?7Torr. The sputter gas is Argon.
4.4 Implantation
In order to dope a semiconductor sample, thermal difiusion and ion implantation can
be used. For SiC however, the difiusion coe?cients of most dopants are too low to get ap-
preciable difiusion into crystal except at temperatures approaching the growth temperature
of the material. Doping by ion implantation, therefore, has been widely adopted. A  ux of
ions with certain a energy penetrate to some depth below the SiC surface. Considering the
energy loss of ions, the distribution of the single energy dopants in the sample wafer is a
near-gaussian curve that has a trailing edge towards the surface of the sample. If a square
doping proflle is desired, ions with several energies can be implanted. With the help of the
simulation software, SRIM, suitable energies and doses can be determined for the proflle.
4.5 Activation
Implantation put dopants at the desired depth in a sample. However, the dopants
remain primarily at interstitial site in the crystal until a high temperature activation anneal
is performed. The process of activation will heal implant damage and reorganize the lattice
structure of the crystal with implanted dopants moving from interstitial to lattice sites
65
where they become electrically active. Figure 4.7 shows the chamber used to carry out
the activation anneal. In the chamber, two parallel carbon sesistive heaters are installed
horizontally and connected to a DC power source. A round carbon box (Figure 4.8) is
located between the carbon strips. Samples are located inside the carbon box during the
process of activation. A temperature of 1550oC is used to activate nitrogen dopants, and
1650oC is used to activate aluminum dopants. In order to avoid the loss of Si from the SiC
surface during the activation anneal, a carbon cap is used to cover the implanted surface.
The cap is formed by coating photoresist on the surface of SiC followed by 30min anneal in
Argon at 600oC. During the activation anneal, Argon gas at 1atm is  owing through the
chamber at all time.
Fig. 4.7: Implant activation anneal chamber.
66
Fig. 4.8: Sample holder carbon box for implant activation.
4.6 Ohmic Contact Annealing
During the fabrication of MOSFETs, the source and drain regions are heavily doped,
and Ni is used to make ohmic contacts to the S/D regions. However, the as-deposited
metal/semiconductor structure yields a Schottky contact, which is transformed to an ohmic
contact with a linear current-voltage characteristic using a short, high temperature anneal.
Basedonexperience, anoptimizedtemperatureforourMOSFETsis?900oC/4min/Ar(1atm).
Figure 4.9 shows the ohmic contact annealing equipment in our laboratory.
4.7 Etching
Etching processes are required im many of the steps for MOSFET fabrication. For
instance, a bufiered oxide etchant (BOE) is used to etch SiO2 and NF3 is used to reactively
ion etch SiC. The choice of etching method is important in order to selectively remove layers
(oxide, metal, SiC, etc.) during the fabrication process.
67
Fig. 4.9: Ohmic contact annealing furnace.
68
4.7.1 BOE Etching
Bufiered oxide etchant (BOE) is an excellent etchant for SiO2. BOE does not react
with SiC or silicon, and at room temperature, the etch rate of SiO2 by BOE is around
1000?A/min. To protect SiO2, baked or carbonized photoresist is used as the mask. Since
the sample must be dipped into the BOE solution during the etching process and the etching
is isotropic, the time of etching must be set as precisely as possible to avoid unwanted lateral
etching after the SiO2 layer is etched through to the SiC substrate.
4.7.2 RIE
RIE is an acronym for reactive ion etching. Figure 4.10 shows the RIE equipment that
is used in our laboratory. The plasma is created in a closed chamber fllled with a speciflc
gas (e.g., NF3 or SF6). The ions created in the RF plasma can react chemically with the
substrate material we wish to remove. Masks have to be used to protect the regions we
wish to be keep unetched. In the fabrication of a MOSFET, active areas are protected with
nickel, and the devices are fabricated on an isolation mesa with sides etched down a few
hundred nanometers using an NF3 plasma.
4.7.3 KOH Etching
Another method for etching SiC wafer is KOH etching. The KOH is heated to a molten
state, at around 550oC. This etching is commonly used to enlarge and observe the defects
in a SiC wafer. The KOH technique is very useful when studying the relationship between
oxide breakdown and substrate defect density.
69
Fig. 4.10: Equipment for reactive ion etching.
70
4.8 Capacitance-Voltage Measurements
In order to understand the electrical properties of MOS devices, especially interface
characteristics, capacitance-voltage measurements are employed. The C-V measurements
in our laboratory are made with Keithley 595 analyzer and a Keithley 590 CV meter,
shown in flgure 4.11. The Keithley 595 analyzer measures the high-frequency capacitance,
and 590 CV meter measures the quasi-static capacitance. Both measurements are made
simultaneously.
A typical high-low CV curve for an n-type MOS capacitor is shown in flgure 4.12.
In the flgure, the red curve represents the quasi-static capacitance, and the black curve
represents the high frequency capacitance. The high frequency curve does not re ect the
efiects of interface defects because the defects - as they flll an empty - cannot follow the high
frequency signal. However at room temperature, the interface traps with energies between
EC and approximately EC-0.6eV do follow the much slower quasi-sttic signal as they trap
and emit electrons. This additional charge motion contributes to the measured capacitance,
making the quasi-static capacitance higher than the high-frequency capacitance for a given
bias voltage. The energy level of a trap in the band gap is determined by the position of
the Fermi level at the SiC surface for a given bias voltage. The difierence between CQS and
CHF is used to calculate the defect state density at a speciflc energy level.
For CV measurements, temperature has an important efiect on the results. Since SiC
is a wide gap semiconductor material, the defects states which are at deep energy levels
(?EC-0.6eV to mid-gap)can not respond to quasi-static bias changes at room tempera-
ture. Therefore, to obtain the defect state density between the conduction band edge and
71
Fig. 4.11: Simultaneous high-low capacitance-voltage station.
72
s48 s53 s49s48
s48s46s48
s48s46s50
s48s46s52
s48s46s54
s48s46s56
s49s46s48
s32
s32
s67
s47
s67
s111
s120
s71 s97s116s101s32s86s111s108s116s97s103s101s32s40s86s41
s32s72 s105s103s104s32s102s114s101s113s117s101s110s99s121
s32s81 s117s97s115s105 s32s115s116 s97s116s105s99
Fig. 4.12: A typical plot of capacitance v.s. gate voltage of n-type
MOS capacitor with a thermal oxide annealed in NO.
73
mid-gap, difierent CV measurements are normally made at 23oC and 300oC. The 300oC
measurements are used to measure defects states 0.6eV?1.6eV below the conduction band
edge. Sometimes, to make the two regions connect smoothly, one extra measurement will
be made at 150oC.
Measurements with N-type material only give trap densities in the upper half states of
the band gap. P-type material can be used to obtain trap densities in the bottom half of
the gap.
4.9 Current-Voltage Measurements
Current-voltage (I-V) measurements are used to obtain breakdown information for the
oxides in MOS devices. The voltage is applied on the gate of the devices, and the current
 owing through the oxide layer is detected. When a preset limit for current is achieved, the
test is usually stopped in order to prevent catastrophic oxide breakdown.
I-V measurements can be made not only at room temperature, but also at high tem-
perature for the purpose of accelerated reliability testing. Figure 4.13 shows the I-V mea-
surements station.
4.9.1 TDDB
Time Dependent Dielectric Breakdown (TDDB) measurements are used to test the
reliability of devices. Compared to anticipated operating conditions, devices are subject to
higher temperature and higher voltage (i.e., higher oxide fleld) in order to shorten the testing
time. Figure 4.14 shows the measurement board layout, which allows 36 MOS capacitors
74
Fig. 4.13: Current-voltage station.
75
to be monitored simultaneously with software programed in Labview. The Labview user
interface is shown in flgure 4.15.
Fig. 4.14: TDDB measurement board.
4.10 MOSFET Measurements
MOSFET devices have gate, source and drain contacts. Therefore, three probes are
needed for characterization measurements. The efiective channel mobility is usually mea-
sured by setting a constant source-drain voltage (typically 25mV) and measuring the source-
drain current as a function of gate voltage. Figure 4.16 shows the station that used for these
measurements,and flgure 4.17 shows the user interface of MOSFET measurement program.
As mentioned, a small voltage is applied between the source and drain contacts, and
the gate voltage is stepped during the measurement. The gate current is monitored while
the source-drain current is measured. Since Vd (drain voltage) is small compared with Vg,
the linear model can be used to describe operation of the MOSFET. According to chapter
76
Fig. 4.15: The user interface of TDDB measurement program.
2, the mobility can be evaluated as a function of Vg. Simply speaking, the peak value of
mobility will occur when the slope of Id (drain current) versus Vg has the maximum value.
It should be noted that the gate current should be kept small (?10?10A or less), otherwise
current leakage through the oxide of the oxide layer will be a concern.
77
Fig. 4.16: The three probe current-voltage measurement station
consisting of a KI-2400 source meter, a KI-2410 source meter, a
microscope and a sample holder.
78
Fig. 4.17: The user interface of MOSFET measurement program.
79
Chapter 5
Characterization of MOS Devices Fabricated on Carbon Face 4H-SiC
In this chapter, MOS capacitors and MOSFETs built on carbon face 4H-SiC will be
discussed. High-low capacitance-voltage measurements and current-voltage measurements
are used to study the properties of carbon face 4H-SiC/SiO2: interface trap density, oxide
breakdown fleld and inversion channel mobility. Several difierent oxidation processes are
used to grow SiO2 on SiC wafer and improve the interface quality of SiC/SiO2. The results
are discussed and compared to the case of the silicon face.
5.1 Background
From the previous chapters, it has been shown that SiC has a higher thermal conduc-
tivity, wider band gap, and higher critical breakdown fleld than silicon. 4H-SiC also has
comparable bulk electronic mobility to silicon. All of these properties make SiC an excellent
candidate for power MOSFET construction. However, the channel mobility of SiC is sig-
niflcantly lower than that of silicon and many people believe it is because the interface trap
density of SiC/SiO2 is high[63, 100, 101]. In order to improve the channel mobility of SiC, as
well as the interface quality, much work has been done on various polytypes and difierent
orientations[58, 95, 100, 102{104]. The carbon face 4H-SiC has a higher oxidation rate than the
silicon face. The higher oxidation rate will save time during MOS devices fabrication and
lead to potentially large savings in cost. The carbon face 4H-SiC also has been reported to
80
Table 5.1: The oxidation rates of (0001) and (000?1) 4H-SiC
O2 NO
(0001) 4H-SiC 80?A/hr 6?A/hr
(000?1) 4H-SiC 730?A/hr 50?A/hr
have high channel mobility[98]. Therefore much interest has been attracted in the carbon
face 4H-SiC.
5.2 Oxidation Rate
The oxidation rate on difierent orientations of 4H-SiC is studied. The carbon terminal
and the silicon terminal are compared for the speed of oxidation. For sake of simplicity, the
carbon terminal will be written as (000?1) and the silicon terminal will be written as (0001).
The results are shown in table 5.1.
The growth rate of oxide on the carbon face 4H-SiC is approximately 9 times higher
than that on the silicon face.
5.3 (000?1)4H-SiC/SiO2 Interface
5.3.1 Experiments
In order to investigate the interface issue of carbon face 4H-SiC/SiO2, MOS capacitors
were fabricated as test devices. The experiments started with 4H-SiC wafers bought from
Cree. Diced into 5mm?5mm pieces, wafers were cleaned with organic cleaning and RCA
cleaning (see appendix A for details on cleaning). An oxide layer with the thickness of
?75nm was grown on the surface of SiC in 1150oC furnace, followed by post-oxidation
annealing. Nitric oxide (NO) post-oxidation annealing was done for 2hr at a temperature
81
of 1175oC, while H2 annealing was done at 500oC for 1hr with a thin layer of platinum
coating on the surface of SiO2. Photo-lithography was then used to deflne the pattern of
MOS capacitors on the oxide layer. High purity Mo was deposited as the gate metal by
sputtering. Another thin layer of oxide was usually grown on the backside of SiC at the
time of oxidation, must be removed by bufiered oxide etchant (BOE) to make ohmic like
contacts. Silver paste was flnally used to attach the MOS capacitor sample to Au-coated
ceramic prior to measurement.
5.3.2 Results and Analysis
Room temperature (23oC) and High temperature (300oC) hi-lo CV measurements are
employed to collect capacitance versus gate voltage of MOS capacitor devices. Figure 5.1
shows the room temperature CV curves of an MOS capacitor with as-oxidized oxide. The
difierence between high frequency and quasi-static curves is large, and this implies that the
interface trap density Dit at the near end of the conduction band is high. The Dit proflle
is shown in flgure 5.2. Since the oxide is \weak", it is di?cult to make the device stay at
accumulation. Therefore it is di?cult to get an accurate interface trap density proflle. It
should be noted that the high temperature CV measurements could not be performed due
to the same reason. Thus, it is reasonable to imply that Dit of as-oxidized sample is very
high and it is not necessary to discuss as-oxidized method later in this chapter.
NO Passivation
To improve the interface quality or decrease the defects states density in the band
gap, post-oxidation annealing must be carried out. Since NO has been proved efiective
82
s48 s53 s49s48 s49s53 s50s48 s50s53 s51s48
s48s46s48
s48s46s50
s48s46s52
s48s46s54
s48s46s56
s49s46s48
s49s46s50
s32
s32
s67
s47
s67
s111
s120
s71 s97s116s101s32s86s111s108s116s97s103s101s32s40s86s41
s32s72 s105s103s104s32s102s114s101s113s117s101s110s99s121
s32s81 s117s97s115s105 s32s115s116 s97s116s105s99
Fig. 5.1: Capacitance v.s. gate voltage of an MOS capacitor with
as-oxidized oxide.
83
s48s46s49 s48s46s50 s48s46s51 s48s46s52 s48s46s53 s48s46s54
s49s48
s49s50
s49s48
s49s51
s49s48
s49s52
s32
s32
s68
s105
s116
s40
s99s109
s45
s50
s101
s86
s45
s49
s41
s69
s99
s45s69
s105s116
s32s40s101s86 s41
Fig. 5.2: Interface trap density proflle of an MOS capacitor with
as-oxidized oxide.
84
for enhancing the silicon face 4H-SiC/SiO2 interface[58], it was used in the post-oxidation
annealing for the carbon face 4H-SiC/SiO2. The capacitance versus gate voltage plot of
the carbon face MOS capacitor is shown in flgure 4.12. It is interesting to compare flgure
5.1 and flgure 4.12. After NO annealing, high frequency and quasi-static curves are much
closer. Moreover, a more stable accumulation region exists. Figure 4.12 suggests that the
interface defects states are reduced dramatically and the oxide is \stronger" compared to
the as-oxidized sample. From flgure 4.12, the interface trap density can be estimated, as
shown in flgure 5.3. Both shallow levels and deep levels are presented. It should be noted
that NO creates a new thin layer of oxide over the original oxide.
s48s46s49 s48s46s50 s48s46s51 s48s46s52 s48s46s53 s48s46s54 s48s46s55 s48s46s56 s48s46s57 s49s46s48 s49s46s49 s49s46s50 s49s46s51 s49s46s52 s49s46s53 s49s46s54
s49s48
s49s48
s49s48
s49s49
s49s48
s49s50
s32
s32
s68
s105
s116
s40
s99s109
s45
s50
s101
s86
s45
s49
s41
s69
s99
s45s69
s105s116
s32s40s101s86 s41
Fig. 5.3: Interface trap density proflle of an MOS capacitor with
NO passivated oxide.
85
The efiectiveness of NO passivation on enhancement of interface quality for other poly-
types of SiC has also been reported[57, 58, 77]. It is suggested that the carbon clusters pro-
duced during the oxidation are passivated by nitrogen atoms and, as a result, lead to the
lower interface states density. In the case of the carbon face 4H-SiC, carbon clusters are the
main cause of the interface defects[56]. Therefore, it is not surprising that NO passivation
has a signiflcant efiect on reduction of interface defects of the carbon face 4H-SiC.
H2 Passivation
H2 passivationhasbeenshowncapablereducingtheinterfacedefectsstatesforSi/SiO2[83].
H2 was also tried to improve the interface of the silicon face 4H-SiC/SiO2[56], but the results
were not as good as on Si/SiO2. In the research on the carbon face 4H-SiC, H2, cracked
by platinum into atoms, is used again to test the efiectiveness on improvement of interface.
Figure 5.4 shows the interface defects states density after H2 passivation. Comparison with
the interface defects states density of as-oxidized oxide shows that H2 passivation does not
yield much improvement. This means that using only H2 in the passivation can not im-
prove the interface of the carbon face 4H-SiC enough. Since H2 can efiectively passivate
slicon-related defects[56], it is suggested that the main defects at the interface of 4H-SiC,
both the silicon face and the carbon face, are not silicon-related.
Wet Re-oxidation
An alternative approach to introduce H atoms into the interface of SiC/SiO2 is the
wet re-oxidation. The experiment details have been discussed in Chapter 4. With similar
results to platinum H2 passivation, this method does not enhance signiflcantly the carbon
86
s48s46s49 s48s46s50 s48s46s51 s48s46s52 s48s46s53 s48s46s54 s48s46s55 s48s46s56 s48s46s57 s49s46s48 s49s46s49 s49s46s50 s49s46s51 s49s46s52 s49s46s53 s49s46s54
s49s48
s49s49
s49s48
s49s50
s49s48
s49s51
s49s48
s49s52
s32
s32
s68
s105
s116
s40
s99s109
s45
s50
s101
s86
s45
s49
s41
s69
s99
s45s69
s105s116
s32s40s101s86 s41
Fig. 5.4: Interface trap density proflle of an MOS capacitor with
Pt-H2 passivated oxide.
87
face 4H-SiC/SiO2 interface[58]. Similar as NO passivation, this process will grow another
layer of oxide and growth rate is even higher than dry oxidation.
Combination of NO and H2 Passivation
Although pure H2 passivation does not work successfully to enhance the interface of
SiC/SiO2, the combination of NO and H2 passivation has been found efiective in reducing
the interface defects states density of the silicon face 4H-SiC/SiO2[85]. In case of the carbon
face, this combination also works. In this approach, H2 passivation is performed after NO
treatment. Figure 5.5 shows the interface trap density of the carbon face 4H-SiC/SiO2
after NO and H2 post-oxidation annealing. For both shallow levels and deep levels, the trap
densities are apparently lower than only NO annealing. At 0.2eV below the conduction
band, the Dit is approximately 5?1011cm?2eV?1.
Wet Re-oxidation Followed by NO Passivation
When NO passivation is performed after wet re-oxidation, the interface quality of the
carbon face is better than only NO treatment. Figure 5.6 shows the results.
In summary, the Dit of the carbon face 4H-SiC/SiO2 proflles for difierent post-oxidation
annealing methods are shown in flgure 5.7. For comparison, the silicon face Dit is shown in
flgure 5.8. Clearly, the combination of NO and H2 passivation results in the best interface
quality for the carbon face 4H-SiC/SiO2. However, it is still worse than the best silicon face
interface which is also passivated by NO and H2.
88
s48s46s49 s48s46s50 s48s46s51 s48s46s52 s48s46s53 s48s46s54 s48s46s55 s48s46s56 s48s46s57 s49s46s48 s49s46s49 s49s46s50 s49s46s51 s49s46s52 s49s46s53 s49s46s54
s49s48
s49s48
s49s48
s49s49
s49s48
s49s50
s32
s32
s68
s105
s116
s40
s99s109
s45
s50
s101
s86
s45
s49
s41
s69
s99
s45s69
s105s116
s32s40s101s86 s41
Fig. 5.5: Interface trap density proflle of an MOS capacitor with
NO and Pt-H2 passivated oxide.
89
s48s46s49 s48s46s50 s48s46s51 s48s46s52 s48s46s53 s48s46s54 s48s46s55 s48s46s56 s48s46s57 s49s46s48 s49s46s49 s49s46s50 s49s46s51 s49s46s52 s49s46s53 s49s46s54
s49s48
s49s49
s49s48
s49s50
s32
s32
s68
s105
s116
s40
s99s109
s45
s50
s101
s86
s45
s49
s41
s69
s99
s45s69
s105s116
s32s40s101s86 s41
Fig. 5.6: Interface trap density proflle of an MOS capacitor with
wet re-oxidation and Pt-H2 passivated oxide.
90
s48s46s50 s48s46s52 s48s46s54 s48s46s56 s49s46s48 s49s46s50 s49s46s52 s49s46s54 s49s46s56
s49s48
s49s48
s49s48
s49s49
s49s48
s49s50
s49s48
s49s51
s50s51
s111
s99
s32
s32
s32s79
s50
s43s78s79s32s40s55s53s110s109s41
s32s79
s50
s43s72
s50
s32s40s52s53s110s109s41
s32s79
s50
s43s87 s101s116s45s82s101s79s43s78s79s32s40s54s57s110s109s41
s32s79
s50
s43s78s79s43s72
s50
s32s40s54s48s110s109s41
s68
s105
s116
s40
s99
s109
s45
s50
s101
s86
s45
s49
s41
s69
s99
s45s69s40s101s86s41
s51s48s48
s111
s99
Fig. 5.7: Interface trap density proflles of carbon face 4H-SiC/SiO2
with difierent interface treatments.
91
s48s46s50 s48s46s52 s48s46s54 s48s46s56 s49s46s48 s49s46s50 s49s46s52 s49s46s54 s49s46s56
s49s48
s49s48
s49s48
s49s49
s49s48
s49s50
s32
s32
s32s65s108s117s109 s105s110s117s109 s32s69s110s104s97s110s99s101 s100s32s79 s120s105s100s101
s32s79
s50
s32s79
s50
s47s78 s79
s32s65s108s117s109 s105s110s117s109 s32s69s110s104s97s110s99s101 s100s32s79 s120s105s100s101s47s78 s79
s32s79
s50
s47s78 s79 s47s72
s50
s68
s105
s116
s40
s99
s109
s45
s50
s101
s86
s45
s49
s41
s69
s99
s45s69
s105s116
s40s101s86s41
Fig. 5.8: Interface trap density proflles of silicon face 4H-SiC/SiO2
with difierent interface treatments.
92
5.4 Oxide Breakdown
5.4.1 Experiments
In order to test the reliability of oxide layer, I-V measurements were performed. In I-V
measurements, voltage was applied on the gate of a MOS capacitor and scanned from 0 to a
high value at which the breakdown of the oxide occurred. Given the thickness of the oxide
and the interface information, the breakdown voltage can be converted into breakdown fleld
(see equation 3.1).
5.4.2 Results and Analysis
Similar as in the section of the interface, difierent oxidation methods are investigated
in oxide breakdown experiments. Figure 5.9 shows the I-V curves of these MOS capacitors.
From flgure 5.9, all oxides perform similarly at high fleld. If breakdown current density
is set to be 1?10?4A/cm2, then all oxides will breakdown at nearly the same breakdown
fleld (?5.5MV/cm). At low fleld, difierent behaviors are shown for difierent oxide growth.
The oxide with wet re-oxidation and NO passivation maintains a low current density until
4MV/cm, while other oxides show slight leakage at low fleld.
Two difierent types of gate materials are used in the MOS capacitors. The comparison
results are shown in flgure 5.10, which suggests that the gate materials do not have obvious
efiect on the breakdown of the oxide. However, at the low fleld, the leakage of the oxide
passivated by H2 is higher compared to other oxides. This is likely because the deposition
and removal of platinum may damage the oxide.
93
s48 s49 s50 s51 s52 s53 s54 s55 s56 s57
s49s69s45s49s48
s49s69s45s57
s49s69s45s56
s49s69s45s55
s49s69s45s54
s49s69s45s53
s49s69s45s52
s49s69s45s51
s48s46s48s49
s48s46s49
s49
s32
s32
s32s79
s50
s47s78s79s47s72
s50
s32s79
s50
s47s87 s101s116s45s114s101s111s120s105s100s97s116s105s111s110s47s72
s50
s32s78s79
s32s79
s50
s47s78s79
s67
s117
s114
s114
s101
s110
s116
s32
s68
s101
s110
s115
s105
s116
s121
s32
s40
s65
s47
s99
s109
s50
s41
s69s108s101s99s116s114s105s99s97s108s32s70s105s101s108s100s32s40s77s118s47s99s109 s41
Fig. 5.9: Current-voltage measurements for carbon face 4H-SiC
MOS capacitors.
94
s48 s49 s50 s51 s52 s53 s54
s49s69s45s49s48
s49s69s45s57
s49s69s45s56
s49s69s45s55
s49s69s45s54
s49s69s45s53
s49s69s45s52
s49s69s45s51
s48s46s48s49
s32
s32
s32s79
s50
s47s78s79s47s72
s50
s32s77s111
s32s79
s50
s47s78s79s47s72
s50
s32s80s111s108s121s115s105s108s105s99s111s110
s32s79
s50
s47s87 s101s116s45s114s101s111s120s105s100s97s116s105s111s110s47s72
s50
s32s77s111
s32s79
s50
s47s87 s101s116s45s114s101s111s120s105s100s97s116s105s111s110s47s72
s50
s32s80s111s108s121s115s105s108s105s99s111s110
s67
s117
s114
s114
s101
s110
s116
s32
s68
s101
s110
s115
s105
s116
s121
s32
s40
s65
s47
s99
s109
s50
s41
s69s108s101s99s116s114s105s99s97s108s32s70s105s101s108s100s32s40s77s118s47s99s109 s41
Fig. 5.10: Current-voltage measurements for carbon face 4H-SiC
MOS capacitors with difierent gate metals.
95
The I-V measurements for the silicon face 4H-SiC MOS capacitors are shown in flgure
5.11. Apparently, the best silicon face MOS capacitor has a breakdown fleld 2MV/cm higher
than that of the carbon face. This means the silicon face oxide has better oxide quality
than the carbon face oxide.
s48 s49 s50 s51 s52 s53 s54 s55 s56 s57 s49s48
s49s48
s45s55
s49s48
s45s54
s49s48
s45s53
s49s48
s45s52
s49s48
s45s51
s49s48
s45s50
s49s48
s45s49
s32
s32
s32s79
s50
s47s78s79
s32s79
s50
s47s78s79s47s72
s50
s32s119s105s116s104s111s117s116s32s80s116
s32s79
s50
s47s78s79s47s72
s50
s32s119s105s116s104s32s80s116
s67
s117
s114
s114
s101
s110
s116
s32
s68
s101
s110
s115
s105
s116
s121
s32
s40
s65
s47
s99
s109
s50
s41
s69s108s101s99s116s114s105s99s97s108s32s70s105s101s108s100s32s40s77 s118s47s99s109 s41
Fig. 5.11: Current-voltage measurements for silicon face 4H-SiC
MOS capacitors with difierent gate metals.
5.5 MOSFET Channel Mobility
5.5.1 Experiments
The fabrication process for MOSFETs is more complicated than that of MOS capac-
itors. Each sample was 5mm?5mm in size. The substrate was the p-type carbon face
96
4H-SiC. Two kinds of substrates were used. One was p-implanted material with the im-
plant concentration of 2?1017cm?3, which was formed by implanting Al+ into the n-type
carbon face 4H-SiC at 700oC. The other, bought from Cree, was p-epi material with doping
concentration of 5?1015cm?3. The source and drain regions were 4000?A in depth, formed
by N implantation at 700oC with the implant concentration of 6?1019cm?3. Figure 5.12
and flgure 5.13 show the N and Al implantation proflles simulated by SRIM. The activa-
tion temperatures after implantations were 1550oC and 1650oC for N implantation and Al+
implantation, respectively. During the activation, the surface of sample was covered with
carbon cap, which was carbonized photo-resist, in order to avoid out- ow of silicon atoms
from SiC surface. The carbon cap was removed afterward by reactive ion etching (RIE) in
oxygen environment. A layer of sacriflcial oxide was grown on the surface of sample and
then removed to reduce the efiect of surface roughness on the device. The gate oxide with
the thickness ranging from 40nm to 75nm was grown under the same conditions as used
when the oxide of MOS capacitor was grown. BOE was used to open windows in the oxide
above source and drain regions. Nickel was sputtered onto the source/drain regions prior
to ohmic contact annealing. Optimized conditions for ohmic contacts formation were found
to be 950oC for time of 4min. Figure 5.14 shows the measurement results of a TLM sample
after ohmic contact annealing (see Appendix B for details of TLM measurements). After
ohmic contact annealing was complete, high purity Mo was sputtered as the gate metal.
The MOSFET devices had a channel length of 150?m and a channel width of 290?m.
97
s48 s50s48s48s48 s52s48s48s48 s54s48s48s48 s56s48s48s48 s49s48s48s48s48 s49s50s48s48s48
s48
s49s120s49s48
s49s55
s50s120s49s48
s49s55
s51s120s49s48
s49s55
s52s120s49s48
s49s55
s53s120s49s48
s49s55
s54s120s49s48
s49s55
s32
s32
s67
s111
s110
s99s101
s110
s116
s114
s97
s116
s105
s111
s110
s32
s40
s99s109
s45
s51
s41
s68s101s112s116s104s32s40s65s41
s32s49s48s48s107s101s86s32s52s69s49s50
s32s50s48s48s107s101s86s32s51s69s49s50
s32s51s53s48s107s101s86s32s51s46s54s69s49s50
s32s53s53s48s107s101s86s32s51s46s54s69s49s50
s32s55s53s48s107s101s86s32s51s46s54s69s49s50
s32s57s53s48s107s101s86s32s52s69s49s50
s32s83s85s77
Fig. 5.12: Aluminum implantation proflles on carbon face 4H-SiC.
SiC layer starts from 1200?A.
98
s48 s50s48s48s48 s52s48s48s48 s54s48s48s48 s56s48s48s48 s49s48s48s48s48 s49s50s48s48s48
s48
s49s120s49s48
s49s57
s50s120s49s48
s49s57
s51s120s49s48
s49s57
s52s120s49s48
s49s57
s53s120s49s48
s49s57
s54s120s49s48
s49s57
s55s120s49s48
s49s57
s56s120s49s48
s49s57
s32
s32
s67
s111
s110
s99s101
s110
s116
s114
s97
s116
s105
s111
s110
s32
s40
s99s109
s45
s51
s41
s68s101s112s116s104s32s40s65s41
s32s49s48s48s107s101s86s32s52s46s57s53s69s49s52
s32s49s53s48s107s101s86s32s52s46s57s53s69s49s52
s32s50s48s48s107s101s86s32s51s46s48s50s53s69s49s52
s32s50s53s48s107s101s86s32s53s46s55s55s53s69s49s52
s32s51s53s48s107s101s86s32s55s46s57s55s53s69s49s52
s32s52s53s48s107s101s86s32s54s46s54s69s49s52
s32s83s85s77
Fig. 5.13: Nitrogen implantation proflles on carbon face 4H-SiC.
SiC layer starts from 1800?A.
99
s52s46s48s120s49s48
s45s52
s56s46s48s120s49s48
s45s52
s49s46s50s120s49s48
s45s51
s49s46s54s120s49s48
s45s51
s51s53
s52s48
s52s53
s53s48
s53s53
s54s48
s54s53
s55s48
s70s105s116s32s101s113s117s97s116s105s111s110s32s58s32s89s61s51s55s46s54s54s120s43s49s55s50s54s49
s67 s97s108s99s117s108s97s116s101s100s32s114
s99
s61s52s46s49s49s88 s49s48
s45s52
s47s99s109
s50
s32
s32
s32s65 s118s101s114s97s103s101
s32s76s105s110s101s97s114s32s70s105s116
s82
s101
s115s105
s115s116
s97
s110
s99s101
s32
s40
s41
s71 s97s112s32s83 s112s97s99s105s110s103s32s40s99s109 s41
Fig. 5.14: TLM measurements results for doping concentration of
1E20cm?3after Ohmic Contact Annealing at 850oC for 4-minute.
100
5.5.2 Results and Analysis
Three-probe I-V measurements were used to study the source-drain current Id as gate
voltage Vg scans from ofi-state to on-state. The voltage between the source and the drain
(Vd) was flxed to be 0.025v, which is smaller compared to Vg. The channel mobility can
be simply estimated by using the surface-channel device formula.[105].
? = @Id@V
g
L
W
1
Cox (5.1)
Here, ? is the channel mobility, W is the channel width, L is the channel length, and Cox is
the capacitance per unit area. Cox can be determined by ?0?rA=d, where ?0 is permittivity
of free space, ?r is relative dielectric constant of silicon dioxide, A is unit area, and d is the
thickness of the oxide.
The channel mobility plots may be classifled into two groups. Figure 5.15 shows the
flrst group, in which the channel mobility increases slowly before arriving the highest point
and maintains peak mobility for a wide range of flelds without signiflcant change. In this
group, P-epi materials seem to have higher channel mobilities than P-implanted materials.
Two possible reasons are: the doping concentration of the P-epi material is 5?15cm?3, 1
order of magnitude lower than that of P-imp material, and the P-epi material should have
better crystal quality than the P-implanted material since the damage produced by the
implantation process may not be recovered completely by the activation process. However,
with optimized oxidation techniques, the P-implanted MOSFETs have comparable channel
mobilities to that of P-epi MOSFETs. As shown in flgure 5.15, the wet re-oxidation plus
NO passivation leads to the highest channel mobility, 40cm2/V-s, on P-implanted materials.
101
Since the interface quality of SiC/SiO2 has been believed to be the main reason for the low
channel mobility of SiC MOSFETs, the lower interface trap density is expected to result
in the higher channel mobility. But the NO and H2 post-oxidation passivation, giving
the best interface quality, does not yield the highest channel mobility. This implies the
MOSFET fabrication process is much more complicated and there must be existing other
factors in uencing the channel mobility. Although the H2 passivation enhances the interface
quality, it may simultaneously hurt the performance of other parts of MOSFETs, and the
whole efiect of the passivation may not beneflt the channel mobility.
s48 s50 s52 s54 s56 s49s48 s49s50 s49s52 s49s54 s49s56 s50s48 s50s50
s48
s50s48
s52s48
s54s48
s56s48
s32
s32
s32s80 s45s105s109 s112s32s78 s79
s32s80 s45s105s109 s112s32s79
s50
s47s87 s101s116s45s114s101s111s120s105s100s97s116s105s111s110s47s78 s79
s32s80 s45s105s109 s112s32s79
s50
s47s78 s79 s47s72
s50
s32s80 s45s105s109 s112s32s79
s50
s47s78 s79
s32s80 s45s101s112s105s32s79
s50
s47s78 s79
s67
s104
s97
s110
s110
s101
s108
s32
s77
s111
s98
s105
s108
s105
s116
s121
s40
s99
s109
s50
s47
s86
s46
s83
s41
s71 s97s116s101s32s86 s111s108s116s97s103s101s32s40s86 s41
Fig. 5.15: The channel mobility of carbon face 4H-SiC.
The second group of channel mobilities behave much difierently, as shown in flgure
5.16. One obvious property is the threshold voltage is very close to zero, and low threshold
102
voltage will hurt the operating stability of MOSFET devices. When the devices are turned
on, the channel mobility increases very quickly to a peak, usually much higher than the
peak value of the flrst group, and then drops fast after the peak value depending on the
fleld. This behavior has been observed only on P-epi materials. Common on both of these
groups are the similar channel mobilities at high fleld. It should be noted that the similar
results have been reported previously[98, 106].
s48 s50 s52 s54 s56 s49s48 s49s50 s49s52 s49s54 s49s56
s48
s50s48
s52s48
s54s48
s56s48
s49s48s48
s32
s32
s32s80s45s101s112s105s32s79
s50
s47s78 s79
s32s80s45s101s112s105s32s78 s79
s67
s104
s97
s110
s110
s101
s108
s32
s77
s111
s98
s105
s108
s105
s116
s121
s40
s99
s109
s50
s47
s86
s46
s83
s41
s71 s97s116s101s32s86s111s108s116s97s103s101s32s40s86s41
Fig. 5.16: The channel mobility of carbon face 4H-SiC.
For comparison, the channel mobility of (0001) 4H-SiC is shown in flgure 5.17. It
should be noted that all (0001) 4H-SiC are p-epi materials. The best channel mobility is
obtained on MOSFETs treated by NO and H2 post-oxidation passivation. At low fleld,
(000?1) 4H-SiC yields higher channel mobility than (0001) 4H-SiC, but (0001) 4H-SiC shows
103
a slightly better performance on stability and value of the channel mobility at high fleld.
This is probably because most carriers (electrons) in the channel have to move closer along
the interface at high fleld and the better interface quality of (0001) 4H-SiC reduces the
numbers of scattering and leads to a higher mobility. It should also be noted that the
channel mobilities on (000?1) 4H-SiC show a wide range of values (60cm2/V-s ? 120cm2/V-
s). The large difierence of the channel mobilities suggests the performance of the carbon
face 4H-SiC MOSFETs is more sensitive to the fabrication process.
s48 s53 s49s48 s49s53 s50s48
s48
s49s48
s50s48
s51s48
s52s48
s53s48
s54s48
s32
s32
s32s79
s50
s32s79
s50
s47s78 s79
s32s79
s50
s47s78 s79 s47s72
s50
s67
s104
s97
s110
s110
s101
s108
s32
s77
s111
s98
s105
s108
s105
s116
s121s32
s40
s99s109
s50
s47
s86
s46
s83
s41
s71 s97s116s101s32s86 s111s108s116s97s103s101s40s86 s41
Fig. 5.17: The channel mobility of silicon face 4H-SiC.
The reason of the high channel mobilities on the carbon face 4H-SiC MOSFETs was
also investigated. Gudjonsson et.al[106] have shown that mobile ions (mostly sodium) at
104
interface are able to apparently increase the channel mobility. In the MOSFETs? fabrication
processes, sodium could be introduced into the devices. In order to verify the efiect of the
mobile ions, which also result in the shift of the threshold voltages of MOSFET devices,
bias at temperature stressing (BTS) was used. When negative bias is applied on the gate at
high temperature (250oC), the mobile ions (carrying positive charges) will be attracted by
the electric fleld in the oxide and move away from the SiC/SiO2 interface to the SiO2/metal
interface. The devices were measured again after BTS and the results are shown in flgure
5.18. Thepeakvalueofchannelmobilitydropsfrom65cm2/V-sto35cm2/V-s, andtheshape
of the curve resembles that of the flrst group. This suggests that the mobile ions could be
the reason for the high low-fleld channel mobilities. Meanwhile, since the introduction of
the mobile ions depends strongly on the fabrication procedures, the amount of the mobile
ions introduced at the interface varies. Therefore, the loose distribution of the mobility
values can also be explained. If BTS is done on the flrst group of devices, the results can
be seen in flgure 5.19, showing that the oxide is \clean".
As shown above, to obtain a real channel mobility, the mobile ions need to be reduced
as much as possible during the fabrication processes. The ohmic contact anneal is a very
important step. BTS on MOS capacitors demonstrated sodium contaminations occurred
during this step before employing low sodium quartz. It should be also noted that the nickel
deposition step is critical for the reduction of the mobile ions. The pressure of sputtering
system needs to be as low as possible before the deposition operation. This can reduce the
possibility of sodium contamination in the nickel, as well as amount of oxygen, which may
damage the ohmic contacts by forming nickel oxide during the ohmic contact annealing
process.
105
s48 s50 s52 s54 s56 s49s48 s49s50 s49s52 s49s54 s49s56 s50s48
s48
s49s48
s50s48
s51s48
s52s48
s53s48
s54s48
s55s48
s32
s32
s32s79
s50
s47s78 s79 s47s77 s111s32s52s53s110s109 s83 s105s79
s50
s32s79
s50
s47s78 s79 s47s77 s111s32s65 s102s116s101s114s32s78 s101s103s97s116s105s118s101s32s66 s105s97s115
s67
s104
s97
s110
s110
s101
s108
s32
s77
s111
s98
s105
s108
s105
s116
s121
s32
s40
s99
s109
s50
s47
s86
s46
s83
s41
s71 s97s116s101s32s86 s111s108s116s97s103s101s32s40s86 s41
Fig. 5.18: The channel mobility of carbon face 4H-SiC after nega-
tive bias.
106
s48 s50
s48
s50s48
s32
s32
s32s112s45s105s109 s112s45s79
s50
s47s78 s79 s47s72
s50
s32
s32s112s45s105s109 s112s45s79
s50
s47s78 s79 s47s72
s50
s32s65 s102s116s101s114s32s78 s101s103s97s116s105s118s101s32s66 s105s97s115s32
s67
s104
s97
s110
s110
s101
s108
s32
s77
s111
s98
s105
s108
s105
s116
s121
s32
s40
s99
s109
s50
s47
s86
s46
s83
s41
s79 s120s105s100s101s32s69 s108s101s99s116s114s105s99s32s70s105s101s108s100s32s40s77 s86 s47s99s109 s41
Fig. 5.19: The channel mobility of carbon face 4H-SiC after nega-
tive bias.
107
5.6 Conclusions
In this chapter, MOS capacitors and MOSFETs fabricated on the 4H carbon face SiC
are investigated to provide a comprehensive view of the material. Both implanted and
epitaxial layers are used to build MOSFETs. The oxide layer is grown thermally in furnace
at 1150oC, followed by post-oxidation annealing. High-purity Mo is sputtered as the gate
metal, and silver paste is used as a broad area back contact for all measurements. The
source and drain ohmic contacts of the lateral test MOSFETs are produced by sputtering
Ni on heavily doped implanted regions (6?1019/cm3), followed by an anneal at 950oC
for 4min. Hi-lo capacitance-voltage measurements at both 23oC and 300oC are used to
obtain the interface trap density (Dit). Current-voltage measurements at room temperature
are used to collect information about oxide leakage and breakdown fleld (Ebd). A three-
probe I-V system is employed to determine Id-Vg characteristics of the MOSFETs at room
temperature, and the inversion channel mobility (?) is extracted from these characteristics.
Results are compared for difierent post-oxidation interface passivation anneals. As
shown in flgure 5.7, the combination of NO and H2 annealing gives the best Dit (?2?10?11
cm?2eV?1 atEc-E=0.2eV).Wetre-oxidationplusNOpassivationproducesthemostreliable
oxide, but the measured breakdown fleld of 6MV/cm is still approximately 2MV/cm lower
than the average fleld measured for the Si-face. Compared with the value reported by
Fukuda, et al.[98], the low fleld mobility value is not remarkable. However, the high fleld
mobilities are similar. It was observed that the presence of mobile ions may increase the
low fleld channel mobility. However, after negative bias stress at temperatures as high as
250oC, the mobility peak value drops from 65cm2/V-s to 35cm2/V-s. These results suggest
108
that the efiective mobility for carbon face may not be signiflcantly higher compared to the
Si face.
109
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118
Appendix A
Wafer Cleaning
All devices start with 4H-SiC wafers. The wafers were cut into small pieces in size
of 5mm?5mm in our laboratory. To have better quality on the flnal devices, the cleaning
process was executed prior to other steps. Usually, our cleaning process includes two parts:
organic cleaning and RCA cleaning. The details of these two parts can be described as
follows.
(1) Acetone cleaning for 5minutes in ultrasound;
(2) TCE cleaning for 5minutes in ultrasound;
(3) Acetone cleaning for 5minutes in ultrasound;
(4) Methanone cleaning for 5minutes in ultrasound;
(5) Methanone cleaning for 5minutes in ultrasound;
(6) Deionized water cleaning for 5minutes in ultrasound;
(7) BOE soak for 5minutes;
(8) Rinse in Deionized water for 5minutes;
(9) Soak in the solution (H2SO4:H2O2=1:1) for 15minutes;
(10) Rinse roughly in Deionized water;
(11) BOE soak for 1 minutes;
(12) Rinse roughly in Deionized water;
(13) Soak in the boiling solution (H2O:NH4OH:H2O2=3:1:1) for 15minutes;
119
(14) Rinse roughly in Deionized water;
(15) BOE soak for 1 minutes;
(16) Rinse roughly in Deionized water;
(17) Soak in the boiling solution (H2O:HCl:H2O2=3:1:1) for 15minutes;
(18) Rinse roughly in Deionized water;
(19) BOE soak for 1 minutes;
(20) Rinse roughly in Deionized water;
(21) Dry with N2.
Sometimes, small dusts can be observed on the surface of wafer before cleaning and could be
removed by acetone. The microscope check after cleaning is necessary. The extra cleaning
with step (17) through (21) might be performed again if needed.
120
Appendix B
Transmission Line Measurement
The transmission line measurement(TLM) is a convenient way to determine how well
the ohmic contact annealing is done. It was originally proposed by Shockley[107]. To make
TLM, a speciflc device must be fabricated, named by TLM device, which can be shown in
flgure B.1.In this device, there are several strips of pads. In one strip, each two neighboring
1
2
3
4
5 W
L
Fig. B.1: Schematic pattern of a transmission line measurement
device.
pads are separated by varying distances(L). The smallest value of L is around 2?m and
the largest one is around 16?m. The resistance between each two pads in one strip can
be determined by using 4-probe I-V measurement, as shown in flgure B.2. A constant
current(I)  ows through two probes and the corresponding voltage(V) is measured by
the other two. The two probes contacting with the same pad don?t have to be close, if
121
R C R C
R bul k
I
V
Fig. B.2: Diagram of a 4-probe I-V measurement in TLM.
the condition that each pad is at equal potential is satisfled. Deposition of gold on the
pads is generally used to meet this condition. The resistance calculated from Ohm?s law,
R = V=I, consists of contact resistances of two pads and bulk resistance between these two,
R = 2RC+RS. RS = RshL=W, where Rsh is the sheet resistance, L is the distance between
two pads, and W is the width of each pad. In this equation, It has been assumed that
the contact resistances for all pads are equal. After knowing all resistances and distances
between every two pads, a plot of resistance v.s. distance can be made, as shown in flgure
B.3.
In flgure B.3, the slope of the line is
Slope = Rsh=W: (B.1)
122
X
Y
O
2R C
2L T
slop e=R sh /W
Fig. B.3: Plot of total contact to contact resistance as a function
of L to obtain transfer length and contact resistance values.
The y-axis intercept is 2RC, and x-axis intercept(the transfer length(2LT)) is 2RCW=Rsh.
Because speciflc contact resistance(rc) is deflned as rc = RshL2T,
rc = R
2CW2
Rsh : (B.2)
In practical measurements, RC and Rsh can be determined from the fltting linear
equation of TLM plot. To get more accurate parameters, the distances between two pads
must be measured individually, because although the same mask is used to fabricate the
TLM devices, such errors as misalignments and overdevelopment still can afiect the gaps
between pads.
123
Appendix C
Metal and Metal Film Etchants
Table C.1:
Metal Composition (volume Ratio) Comments
Ag NH4OH:H2O2=1:1
Al (1) HNO3:CH3COOH:H3PO4:H2O=5:5:85:5
at 40-45oC
(2) NaOH:H2O=1:5
(3) Hot H3PO4 Photoresist safe
Rinse in deionized water fol-
lowed by HCl:H2O=1:3 to re-
move phosphorus.
Not recommended for produc-
tion use when Na contamina-
tion is of concern.
Au HNO3:HCl=3:1 1000-1200?A/S
Bi HCl:H2O=1:10
124
Metal Composition (volume Ratio) Comments
Co (1) HNO3:H2SO4:CH3COOH:H3PO4=3:1:5:1
(2) HNO3:H2O=1:1
(3) HCl:H2O2=3:1
Cr (1) HCl:H2O=3:1
(2) HCl:glycerin=1:1
(3) KMnO4:NaOH:H2O=8:4:100 by weight
Cu (1) HNO3H2O=5:1
(2) (NH4)2S2O8
(3) CH2O2:H2O2:H2O=6:1:3
Fe HCl:H2O=1:1
Hf HF:H2O2:H2O=1:1:20
In HNO3:HCl=1:3 at 40oC
Ir HNO3:HCl=1:3 at 40oC
Mg NaOH:H2O=1:1 by weight followed by
CrO3:H2O=1:5 by weight
125
Metal Composition (volume Ratio) Comments
Mo (1) H3PO3:CH3COOH:HNO3:H2O=85:5:1:5
followed by HCl:H2O=1:3
(2) H2SO4:HNO3=1:4 (dry)
(3) H2SO4:HNO3:H2O=1:1:2
at 40oC.
A slow etch for patterning use.
A fast etch for non patterning.
Nb HNO3:HF=1:1
Ni (1) FeCl3 40%
(2) HNO3:HCl=1:5
(3) CH3COOH:HNO3:HCl=150:50:3 at 70oC
NiCr (1)HNO3:HCl:H2O=1:1:3
(2)FeCl3:HCl(37%)=3:20 on Ta thin fllm cir-
cuits
Pb CH3COOH:H2O2:H2O=4:4:10
Pd HNO3:HCl:H2O=1:3:4
Pt (1) HNO3:HCl:H2O=1:3:4
(2) HNO3:HCl=1:8
At 95oC
Age 1 hour etch at 70oC
Rh HBr (62%) At 100oC
126
Metal Composition (volume Ratio) Comments
Ru Anode in HCl or H2SO4 (A.C.)
Sb HNO3:HCl:H2O=1:1:1
Sn (1) HCl:H2O=1:4
(2) HF:HCl=1:1
Ta HNO3:HF:H2O=4:4:10
TaSi2 HNO3:BHF(7:1 dilution)=4:6
Ti (1) H2SO4:H2O=1:1
(2) HF:H2SO4:H2O=1:30:69
(3) H2O2:EDTA=1:2
At 115-120oC in ultrasonic
At 65oC
At 70oC
V HNO3:HF:H2O=1:1:1
W (1) KH2PO4:KOH:K3Fe(CN)6=0.25:0.24:0.1
(2) HNO3:HF=1:1
(3) H2O2:EDTA=1:2
Zr HNO3:HF:H2O=1:1:50
Polysilicon HNO3:H2O:HF=50:20:1 At 25oC
127