BuiltIn SelfTest for the Analysis of MixedSignal Systems
By
George Joseph Starr
A thesis submitted to the Graduate Faculty of
Auburn University
in partial fulfillment of the
requirements for the Degree of
Master of Science
Auburn, Alabama
May 14, 2010
Keywords: BuiltIn SelfTest, MixedSignal, Selective Spectrum Analysis, Multiplier,
CORDIC, Test Pattern Generator, Output Response Analyzer
Copyright 2010 by George Joseph Starr
Approved by
Charles E. Stroud, Chair, Professor of Electrical and Computer Engineering
Victor P. Nelson, Professor of Electrical and Computer Engineering
Foster F. Dai, Professor of Electrical and Computer Engineering
ii
Abstract
A new BuiltIn SelfTest technique called Selective Spectrum Analysis has been
developed for the measurement of analog characteristics in mixedsignal circuits. This
design utilizes digital components to generate and collect analog waveforms to measure
both signal strength and phase shift through an analog circuit. These measurements can
be used to determine the performance of the analog circuit. However, this design still
requires a practical approach to be able to quickly and accurately obtain measurements
onchip.
This thesis proposes improvements to the implementation of this BuiltIn Self
Test design. These improvements allow for the calculation of the results of these analog
measurements onchip. This thesis also introduces a program to automatically generate
the hardware description language model required to fully implement this design in any
Application Specific Integrated Circuit or Field Programmable Gate Array.
iii
Acknowledgements
I would like to thank Dr. Charles Stroud for his constant support and advice
throughout my Master's studies. His guidance helped me become a better engineer by
teaching me how to logically analyze an unknown behavior and turn it into a known
behavior. The knowledge he imparted to me will be invaluable in my future career and
for this, I am most grateful. I would also like to thank Dr. Nelson for his instruction in
digital design and ASIC fabrication. I would like to thank Dr. Dai for his support in this
project and his expertise in the field of analog electronics. I would like to thank these
three professors for serving as my committee members. Without their contributions, the
work like that presented in this thesis would not be possible.
I would also like to especially acknowledge my colleague Jie Qin whose
continued research in BuiltIn SelfTest acts as a pillar of inspiration to future BIST
researchers. I would also like to thank Bradley Dutton and Joseph Cali for their
assistance with both the realization of this research and their support throughout my
Masters degree. I would also like to thank Mary Pulukuri for her experience in BIST
research. I would also like to thank our undergraduate researchers Neil, Alex and Eric for
their contributions to my research. Most of all, I would like to thank my wife, Kim,
whose constant support, sacrifice and encouragement allowed me realize a dream and
pursue graduate school.
iv
Table of Contents
Abstract ............................................................................................................................... ii
Acknowledgements ............................................................................................................ iii
List of Figures .................................................................................................................... vi
List of Tables ..................................................................................................................... ix
List of Abbreviations ...........................................................................................................x
Introduction ..........................................................................................................................1
1.1 BuiltIn SelfTest .....................................................................................................2
1.2 BuiltIn SelfTest for Analog Components in MixedSignal Systems ....................3
1.3 Selective Spectrum Analysis....................................................................................6
1.4 Thesis Statement ......................................................................................................7
Theory of Operation and Background .................................................................................9
2.1 Analog Characteristics .............................................................................................9
2.2 BuiltIn SelfTest Using Selective Spectrum Analysis ..........................................13
2.2.1 Test Pattern Generator .................................................................................15
2.2.2 Output Response Analyzer ..........................................................................18
2.2.3 Analog Functional Measurements Approach...............................................25
2.3 Multipliers ..............................................................................................................29
2.4 Coordinate Rotation Digital Computing Algorithm ..............................................32
2.5 Thesis Restatement ................................................................................................36
v
MixedSignal BuiltIn SelfTest Implementation ..............................................................37
3.1 Program Generation ...............................................................................................38
3.1.1 Test Pattern Generator ..................................................................................42
3.1.2 Output Response Analyzer ...........................................................................50
3.2 BuiltIn SelfTest Test Results...............................................................................55
InCircuit Calculations of Analog Characteristics .............................................................63
4.1 BuiltIn SelfTest OnChip Calculation Circuit .....................................................63
4.1.1 Coordinate Rotation Digital Computing Calculation Unit ...........................68
4.1.2 Translation of Magnitude Value to Decibels ................................................76
4.2 BuiltIn SelfTest Implementation Test Results ....................................................80
Summary and Conclusions ................................................................................................86
5.1 MixedSignal BuiltIn SelfTest Improvements ....................................................86
5.2 MixedSignal BuiltIn SelfTest Additions ...........................................................88
5.3 Areas for Future Research and Development ........................................................89
Bibliography ......................................................................................................................91
vi
List of Figures
Figure 11: Basic BIST Architecture [3] .............................................................................3
Figure 12: DDSbased Analog Test Pattern Generator [17] ...............................................5
Figure 13: MACbased Analog Output Response Analyzer Approach .............................6
Figure 21: Illustration of Analog Distortion from Two Tone Input [6] ...........................10
Figure 22: Illustration of Frequency Response Plot Showing the Magnitude Response [8]
............................................................................................................................................11
Figure 23: Illustration of SNR, THD, and SINAD Measurement Points in Frequency
Sweep .................................................................................................................................13
Figure 24: Illustration on MixedSignal BIST Architecture [11] .....................................15
Figure 25: NCO Used in MixedSignal BIST Design [4] ................................................17
Figure 26: DC1 and DC2 Versus Time [11] ....................................................................23
Figure 27: IMP Detection Circuit for Single Tone Measurement [6] ..............................24
Figure 28: Illustration of Fundamental Tone Compared to IM3 Tone in IP3 Test [6] .....27
Figure 29: Illustration of Rearranging Partial Product to Decrease Worst Case Path ......32
Figure 210: Illustration of CORDIC Rotational Procedure ..............................................34
Figure 31: Screenshot from Automated Program to Generate MixedSignal BIST Model,
MSBISTGen.exe .................................................................................................................39
Figure 32: Hierarchical Tree of Files Generated for MixedSignal BIST Model ............41
Figure 33: Illustration of Quarter Wave Table .................................................................45
Figure 34: Illustration of Repeating Quarter Wave Table to Form Full Wave Table ......45
vii
Figure 35: Illustration of Modified NCO model to include reduced LUT. ......................46
Figure 36: Block Diagram of Nicholas Modified Phase Accumulator [17] .....................47
Figure 37: Spurious Free Dynamic Range of 55.169 dBc in a 14.4 kHz Tone Generated
and by the MixedSignal BIST Without Nicholas Modified Phase Accumulator .............49
Figure 38: Spurious Free Dynamic Range of 57.959 dBc in a 24.4 kHz Tone Generated
by the MixedSignal BIST With Nicholas Modified Phase Accumulator .........................49
Figure 39: The Logical Addition of the Two?s Complement Term with Partial Products.
The First Row Represents the Correction Factor While Each Additional Row Represents
the Partial Products Rows. .................................................................................................52
Figure 310: The Two Possible Outcomes for Each Stage of Reduction ..........................52
Figure 311: The Logical Addition of Offset Term with First Negative Partial Product.
The Highlighted Area Represents the Next Area to Be Reduced. .....................................52
Figure 312: The Logical Addition of Offset Term with Second Negative Partial Product.
The Highlighted Area Represents the Next Area to Be Reduced. .....................................53
Figure 313: The Logical Addition of Offset Term with Third Positive Partial Product.
The Highlighted Area Represents the Next Area to Be Reduced. .....................................53
Figure 314: The Logical Addition of Offset Term with Final Negative Partial Product. 53
Figure 315: Image of Completed Analog Testing Printed Circuit Board Connected to the
Spartan3 FPGA. ................................................................................................................56
Figure 316: Frequency Response Measurement of the DUT from by the MixedSignal
BuiltIn SelfTest ...............................................................................................................58
Figure 317: Linear Response from DUT Measured by the MixedSignal BIST..............59
Figure 318: NonLinear Response from DUT Measured by the MixedSignal BIST .....59
viii
Figure 319: Signal to Noise Ratio Measurement from Data Collected from the Mixed
Signal BIST. .......................................................................................................................62
Figure 41: Complete InCircuit Test Calculator Using CORDIC Calculation Unit ........67
Figure 42: CORDIC Relationship on Unit Circle ............................................................69
Figure 43: Illustration of CORDIC Rotational Procedure Minimizing YAxis Value to
Maximize Xaxis Value .....................................................................................................70
Figure 44: Illustration of Circular CORDIC Calculation Unit .........................................74
Figure 45: Illustration of Logarithmic Translation Unit ...................................................79
Figure 46: Plot of Frequency Response Using OnChip and OffChip Calculations for
Magnitude ..........................................................................................................................81
Figure 47: Plot of Linearity ?P Results for OnChip and OffChip Test Calculations ....83
ix
List of Tables
Table 21: Relationship Between ??(?) and ??O? [4] ..................................................20
Table 22: Booth Recoding Bits Decoded ........................................................................31
Table 31: Description of Generated Files ........................................................................41
Table 32: Decode Top Bits of Quarter Wave Phase Accumulator ..................................45
Table 33: Linearity Measurement Comparison of MixedSignal BIST Model and
Spectrum Analyzer.............................................................................................................60
Table 34: SNR Measurement Comparison of MixedSignal BIST Model and Spectrum
Analyzer .............................................................................................................................62
Table 41: CORDIC Calculation Unit Phase Bits Weight for First Ten Phase Bits .........73
Table 42: Small Value Measurements on the Input of the Logarithmic Translation Unit
............................................................................................................................................84
x
List of Abbreviations
ADC Analog to Digital Converter
ASIC Application Specific Integrated Circuit
ATE Automated Test Equipment
BIST BuiltIn SelfTest
CCU Coordinate Rotation Digital Computer Calculation Unit
CORDIC Coordinate Rotation Digital Computer
DAC Digital to Analog Converter
DDS Direct Digital Synthesis
DFT Design For Testability
DUT Device Under Test
FFT Fast Fourier Transform
GCD Greatest Common Denominator
HDL Hardware Description Language
IC Integrated Circuit
IIP3 Input Referred I Third Order Intercept Point
IM3 Third Order Intermodulation
IMD Intermodulation Distortion
IMP Integer Multiple Period
IP3 Third Order Intercept Point
LSB Least Significant Bit
xi
LUT LookUp Table
MAC Multiplier Accumulator
MSB Most Significant Bit
NCO Numerically Controlled Oscillator
NF Noise Figure
OIP3 Output Referred Third Order Intercept Point
ORA Output Response Analyzer
PAC Phase to Amplitude Converter
PCB Printed Circuit Board
SINAD Signal to Noise and Distortion
SNR Signal to Noise Ratio
SSA Selective Spectrum Analysis
THD Total Harmonic Distortion
TPG Test Pattern Generator
VHDL Very High Speed Integrated Circuit Hardware Description Language
1
Chapter One
Introduction
The construction of high frequency analog circuits is riddled with difficulties.
There are a variety of factors that can determine the quality of an analog Integrated
Circuit (IC). These factors can include defects and nonuniform densities in the silicon
wafer that cause transistors to operate differently as well as poor design and component
choice [1]. Only some of these factors are predictable, therefore there is a need to test the
specification of an analog IC to guarantee that it will operate as expected [2].
In digital electronics, there is an expanding field of techniques dedicated to
developing selftesting and selfcorrecting algorithms for digital devices. The most
effective of these derived methods is a technique known as BuiltIn SelfTest, where the
testing components are located onchip, eliminating the need for bulky and expensive test
equipment [3]. A mixedsignal BuiltIn SelfTest approach has been proposed to measure
the analog characteristics of a circuit [4][12]. This technique utilizes Direct Digital
Synthesis (DDS) to generate test patterns and Selective Spectrum Analysis to collect
measurement results. Discussed in this thesis are additions and improvements to this
BuiltIn SelfTest (BIST) approach to measure the characteristics of an analog circuit
incorporated within a mixedsignal design.
2
1.1 BuiltIn SelfTest
To keep up with the ever increasing complexity of electronics, the field of circuit
testing has had to evolve. Design for Testability (DFT) techniques were developed ?to
improve the testability of a circuit by including additional circuitry that improves
controllability and observability of the circuit under test? [3]. Traditionally, circuits were
tested using Automated Testing Equipment (ATE) which would apply a series of inputs
to the IC?s pins and monitor the output pins for the correct response. This technique of
fault testing limits the observable faults to only those that can be directly stimulated from
the IC?s pins. This shortcoming led to the idea of placing the testing equipment within the
silicon device to perform a more thorough and sometimes shorter test sequence [3].
BuiltIn SelfTest (BIST) is any method for a circuit to test itself to detect faults
or invalid responses without the use of external test equipment [3]. The typical BIST
architecture contains two essential components used for testing and two additional
features used to facilitate testing. The two essential components are the Test Pattern
Generator (TPG) and the Output Response Analyzer (ORA). The TPG produces a
sequence of test patterns to stimulate the Device Under Test (DUT). The ORA collects
the output response of the DUT and translates it into a pass/fail indication [3]. The two
secondary components used to facilitate testing are the BIST controller and isolation
circuitry. The BIST controller acts to orchestrate the testing procedure by controlling the
testing sequence. The isolation circuitry is used to isolate the DUT from the normal
inputs so that the TPG can stimulate the DUT with a specific test sequence [3]. This
approach is illustrated in Figure 11.
3
Figure 11: Basic BIST Architecture [3]
1.2 BuiltIn SelfTest for Analog Components in MixedSignal Systems
A mixedsignal IC allows developers to combine many different analog and
digital systems into one IC. This increases the simplicity of integrating the original
design, but the DFT process becomes more difficult. More components are being placed
on ICs as the area required for circuit design is shrinking due to improved fabrication
techniques, but each added component may require a different DFT technique to verify
functionality [1]. These difficulties become even more exaggerated when one considers
the introduction of mixedsignal architecture into the IC design. Traditional digital BIST
architectures are designed to generate test patterns of distinct ones and zeros to apply to
the inputs of the DUT. The output of the circuit is then monitored and compared to the
expected digital result [3]. Analog circuits do not operate under such simplified binary
principles; therefore a modified approach is required to verify the proper operation of the
device.
System
Inputs
BIST
Controller
Device Under
Test (DUT)
Output Response
Analyzer (ORA)
Test Pattern
Generator (TPG)
Input
Isolation
Circuitry
System
Outputs
4
To perform the test procedure, a TPG is used to produce a series of test patterns
that are applied to the DUT. These test patterns are designed to exercise specific aspects
of the DUT to test for fault conditions [3]. When testing an analog circuit, the TPG needs
to be able to create an analog waveform to test the analog characteristics of a circuit. One
method for easily achieving this waveform is a procedure called Direct Digital Synthesis
(DDS) [17].
In DDS, a Numerically Controlled Oscillator (NCO) is used in conjunction with a
Digital to Analog Converter (DAC) to generate a waveform from a frequency control
value and starting phase. The NCO consists of a phase accumulator and a Phase to
Amplitude Converter (PAC) [17]. The phase accumulator continuously accumulates the
frequency control value at a periodic interval defined by a system clock frequency. This
accumulated value is passed to the PAC, which converts the accumulator value to a
magnitude value that corresponds to a phase location in the sinusoidal waveform. The
output of the PAC is then transmitted to the DAC to generate the analog waveform for
testing. Since the phase information is updated every clock cycle, the waveform will
appear quantized. An additional filter is needed to smooth this quantized waveform. The
illustration in Figure 12 shows a visual representation of how a TPG is formed using this
method [17]. An illustrated example of the output of each stage is also represented in this
figure.
5
Figure 12: DDSbased Analog Test Pattern Generator [17]
The goal of the ORA is to collect the response from the DUT after it has been
stimulated with the output of the TPG. After the response has been collected, it can be
interpreted into a pass/fail indicator [3]. For analog BIST measurements however, the
results will not be identical with every test. Noise, temperature, humidity, and external
electromagnetic radiation sources will affect the performance and response of an analog
system [20]. Therefore it becomes necessary to interpret the results and compare these
observed measurements to a goal rather than a distinct binary response to determine a
pass/fail indicator.
To convert this analog waveform into a digital signal, an Analog to Digital
Converter (ADC) can be used. To collect the data points from the digitized input, the
ORA implements two multiplier/accumulators (MAC) pairs. These two MACs can be
Output
Waveform
Test Pattern Generator
Freq
Value
System Clock
Digital
to
Analog
Converter
Phase Accumulator
Output
Phase to
Accumulator
Converter Output
Digital to Analog
Converter Output Filter Output
Filter Phase
Accumulator
Phase to
Amplitude
Converter
Freq
Value
Clock
6
used to extract the inphase and outofphase components of a single frequency within
this measured signal [4]. Once this data has been collected, the result can be compared to
a set of specifications for that test to generate a pass/fail indicator. This approach to the
ORA is illustrated in Figure 13.
Figure 13: MACbased Analog Output Response Analyzer Approach
1.3 Selective Spectrum Analysis
To perform a test on an analog circuit, a tone must be driven into the circuit and
the response measured. To measure this response, a traditional spectrum analysis can be
performed by a Fast Fourier Transform (FFT) processor [18]. These FFT engines capture
a large amount of data points to perform analysis on a broad frequency spectrum to
calculate the phase and magnitude for many distinct frequencies simultaneously using a
derivative of the Fourier Transform algorithm [18]. These FFT processors require a large
amount of area overhead and power consumption to implement [5]. This is not desirable
for a BIST approach where the goal is to use minimal overhead to test.
As an alternative solution, this BIST model applies a different approach to
measure the phase and magnitude response of the DUT. Once the analog waveform
generated by the TPG has stimulated the DUT, the DUT?s response is collected by the
ORA. To collect the spectral content, the ORA employs two pairs of MACs to capture
Pass/Fail
Output Response Analyzer
Analog to
Digital
Converter
MACbased
Measurement
Collection
Analog Waveform
Results
Calculation
& Criteria
Comparison
7
and accumulate the results. The MAC acts to filters out a single frequency of interest
from the measured response. In this BIST approach, only one frequency can be analyzed
at a time, rather than a broad spectrum approach performed by the FFT processor [5].
This allows a circuit with lower area overhead and faster calculation time to be
developed. This process of measuring one exclusive frequency at a time is referred to as
Selective Spectrum Analysis (SSA).
This SSA approach is not without limitations. To implement this circuit still
requires resource overhead to generate tones and collect the DUT response; though the
required area is a minimal when compared to that implemented by traditional FFT
processors [5]. In addition, the test time to obtain accurate measurements is a function of
the frequency words used and how many data points are collected. Therefore, a poor
choice in frequency words or performing a test that involves the capturing of multiple
frequency points can potentially result in a long test time. This proposed BIST approach
includes a mathematical basis for calculating the phase and magnitude from the output of
the ORA, but does not include a practical implementation for this design [4][5].
1.4 Thesis Statement
The goal of this thesis is to present additions and improvement to the design for the
SSA BuiltIn SelfTest model for mixedsignal systems presented in [4][12]. This thesis
will present a method for performing common analog tests onchip. In addition, this
thesis will also present improvements to the MACbased ORA by introducing an
improved multiplier design. This thesis will also present a technique for automatically
generating the complete hardware descriptive model for multiple platforms of
implementation.
8
Chapter 2 will present a detailed overview of the BuiltIn SelfTest model for mixed
signal systems. Background mathematics and procedures of measurement will also be
elaborated upon. Chapter 3 will present the work completed to obtain an automated
implementation of the BuiltIn SelfTest mixedsignal design. This includes
improvements in the TPG using minimized NCOs and the ORA using an improved
multiplier. Chapter 4 will discuss the improvements to the overall approach with the
addition of onchip interpretation of the ORA measurements. The thesis will be
summarized in Chapter 5 and provide suggestions for future areas of research and
development.
9
Chapter Two
Theory of Operation and Background
Complex mixedsignal electronic systems are being extensively developed.
Consequently, the increasing cost associated with testing these complex systems has
motivated research efforts to explore more efficient testing methodologies. This chapter
will present an introduction to BuiltIn SelfTest using Selective Spectrum Analysis to
evaluate the performance of analog devices in mixedsignal systems. This will cover the
mechanisms of measurement which are used to collect test information. In addition, a
description of previous analog testing techniques will also be presented. This chapter will
also cover a brief overview of multiplier architectures and the Coordinate Rotation
Digital Computing algorithm as an introduction to improvements to this existing BuiltIn
SelfTest approach. Finally, this chapter concludes with a restatement of the thesis goals.
2.1 Analog Characteristics
In the measurement of electronic circuits, there are key performance parameters
that can be used to determine if the circuit has met design specifications. Critical
parameters that define an analog circuit include its response to direct stimulus, distortion
from the input waveform, and noise within the system. To measure each of these
characteristics, the presented mixedsignal BIST model is capable of measuring linearity,
frequency response, and a variety of noise measurements for an analog circuit [7].
10
Linearity is a very important characteristic of electronic amplifiers and filters.
Linearity refers to the characteristic behavior of a device to have an output which is
linearly proportional to the input [20]. This is considered synonymous with having low
distortion and preserving the fidelity of analog signals. When two tones are applied to the
input of an analog circuit which exhibits a poor linearity response, the output of the
circuit experiences Intermodulation Distortion (IMD). This results in the formation of
frequencies which are not integer multiple harmonic frequencies of the originally applied
two tones [21]. IMD represents a serious hindrance to circuit performance as these
unintentionally generated tones may result in signals which prove extremely difficult to
filter out by normal means, causing an indeterminate response from the circuit. Illustrated
in Figure 21 is an example of IMD. Two tones at frequencies 7 and 8 are supplied to an
analog amplifier. If this amplifier was linear, the output would contain spectral content at
only the two input tones and harmonics. Because this amplifier is nonlinear, the output
contains the original frequencies, harmonics of the input tones, and intermodulation
between the original frequencies and harmonics tones [6].
Figure 21: Illustration of Analog Distortion from Two Tone Input [6]
Frequency response is another important measurement when attempting to
characterize an analog system [7]. Frequency response can be defined as the comparison
between a system?s output response and an input signal. Frequency response can be
separated into two separate types of measurements: magnitude and phase response.
11
Magnitude response is the difference between the magnitudes of the incident waveform
into the device and the magnitude of the output waveform. This is usually expressed
graphically against the frequency of that waveform. This is illustrated in Figure 22,
where the magnitude is recorded as the frequency is swept from low to high. Magnitude
response is useful when characterizing the gain delivered by an amplifier or the cutoff
point and slope of a filter [8]. Phase response serves an equally important role in
characterizing the analog circuit. Phase response measures the phase delay of the output
waveform which occurs due to the analog circuit.
Figure 22: Illustration of Frequency Response Plot Showing the Magnitude Response [8]
In any electronic circuit, noise plays a considerable factor in determining the
quality of the circuit. There are many sources which may generate noise in analog circuits
including thermal noise, shot noise, flicker noise, and avalanche noise [20]. This noise
appears in tandem with the signal of interest, thus excessive noise increases the difficultly
of accurately interpreting the signal. This makes preserving the signal clarity a priority in
analog design and testing. To characterize the noise within a system there are two
important parameters. The first is the signal to noise ratio (SNR). This measurement is a
Sweeping Frequency
Te
st
To
ne
12
direct comparison between the power within the signal of interest and the noise generated
by the system [9]. This is defined as
??? = ?????? ???????????? ????? ????? (?????? ????????? ?????? ???) (21)
The noise power within an SNR measurement must be defined to a particular
bandwidth of interest to contain statistically significant information. SNR can be further
subdivided into three equally important measurements based on how the noise power
bandwidth is defined. The first subdivision is known as Total Harmonic Distortion
(THD) [20]. In a THD measurement, the noise in question is only measured at
frequencies where harmonic tones of the original signal exist. This gives a direct
comparison between the signal of interest and the generated harmonics of that signal. The
next subdivision of noise bandwidth measurement involves measuring only background
noise while avoiding all harmonic tones in the measurement. This is how the traditional
SNR measurement is performed. The final form of SNR subdivision is known as the
Signal to Noise and Distortion (SINAD). The SINAD measurement is a combination of
the previous two measurements where both background noise and harmonic distortion are
combined as noise and compared to the signal of interest [20]. All three of these noise
measurement techniques are illustrated in Figure 23. In this illustration each bullet
represents a point of measurement.
13
Figure 23: Illustration of SNR, THD, and SINAD Measurement Points in Frequency
Sweep
The second critical parameter when measuring noise is called the Noise Figure
(NF). This parameter is defined as the ratio between the SNR before the influence of the
DUT and the SNR after the DUT has processed the signal [9]. This characteristic is
important as it represents the degradation of the SNR due to interference within the DUT
[20]. The formal definition for NF is shown in Equation 22.
OUT
INSNRSNRNF ? (22)
2.2 BuiltIn SelfTest Using Selective Spectrum Analysis
Analog performance testing is a challenging task even when performed by an
experienced engineer with the correct equipment. After the test data is collected, the test
results of an analog circuit are then compared to a given set of system specifications to
SINAD = SNR+THD Fundamental Tone DC Component
Harmonic Distortion Points
SNR 0 1 2 3 4 5 6 7
Frequency (MHz)
14
verify performance [3]. In order to perform a myriad of analog tests such as linearity,
frequency response, and noise measurements within a mixedsignal IC, it becomes
necessary to implement a BIST approach. This allows for specification testing without
the use of expensive and bulky external equipment.
To obtain analog measurements within this application, the BIST needs to collect
the frequency spectrum content coming from the DUT. To collect this data, the BIST
implements an ORA. Many techniques have been proposed to implement an ORA for
analog testing in [21][25], but these designs, unfortunately, are incapable of measuring
each of the desired analog characteristics of linearity, frequency response, and noise
measurements within one unified model. Some designers utilize FFT to perform broad
spectrum signal analysis, but the overhead requirements of these techniques limit their
utilization in commercial applications [18].
A solution to this overall BIST approach was originally proposed in [6]. Within
this design is a digital TPG that is constructed utilizing DDS to generate the tones
required for stimulating the DUT and internal reference. The response of the DUT is
collected by a digital ORA. To capture these measurements, this ORA will implement
two pairs of multipliers/accumulators [4].
15
Figure 24: Illustration on MixedSignal BIST Architecture [11]
This mixedsignal BIST architecture, illustrated in Figure 24, is capable of
performing measurements on the DUT depicted in the illustration. In addition, this
approach utilizes an analog multiplexer, depicted as MUX3, which allows the DUT to be
bypassed and the performance of the remaining system elements to be measured. The
BIST method for analog measurement relies primarily on two elements to test an analog
DUT. These are the DDSbased TPG and the MACbased ORA [4].
2.2.1 Test Pattern Generator
As shown in Figure 24, the DDSbased TPG of is made of three numerically
controlled oscillators (NCOs). In this design, each NCO consists of a phase accumulator,
phase truncation stage, and phase to amplitude converter. The phase accumulator is
capable of accepting both a frequency control word and a starting phase word. In the
phase accumulator, the frequency control word, f, is continuously accumulated. This acts
to control the frequency of the generated waveform. The phase word, ?, is used to define
a starting offset for the accumulator, which will correspond to a phase offset for the
16
generated waveform. The phase truncation stage removes unused Least Significant Bits
(LSBs) and formats the data so that it will properly interact with the PAC. This allows
for a large accumulator to accumulate precise phase information but implement the
conversion between phase and amplitude with a less precise PAC to reduce area overhead
[4]. The PAC design is usually achieved using a LookUp Table (LUT). The output of the
LUT represents the magnitude component of a sinusoidal waveform and can be converted
to an analog signal with a DAC or used as a digital reference tone [17]. The resulting
waveform and frequency from each NCO are expressed in Equations 23 through 25.
?? = ??????2? (23)
?? = ??2?2? (24)
??? = sin?(2? ? ???? ????? + ??) (25)
In these equations, the frequency control word and phase control word are
represented by ? and ?, respectively. The size of the phase accumulators in which these
control words are accumulated, can be represented as Nbits wide. Finally the rate of
accumulation can be represented as the system clock frequency, ?CLK =1/TCLK . The
accumulator effectively acts to divide ???? by 2N/?, creating the observed frequency and
phase of ?? and ?? [4]. The final waveform output is expressed in Equation 25 where
variable n is equivalent to the number of clock cycles which have elapsed. This NCO
design within the TPG of this BIST is illustrated in Figure 25.
17
Figure 25: NCO Used in MixedSignal BIST Design [4]
In the BIST architecture in Figure 24, NCO1 and NCO2 are used to generate the
test pattern waveform [4]. Through the multiplexer labeled MUX1, the model is capable
of selecting a waveform generated by NCO1 or the combination of NCO1 and NCO2.
This allows either a onetone or twotone waveform to be generated. The output of this
multiplexer is connected to the DAC. By combining the NCOs with the DAC, the DDS
model is completed, and it becomes possible to generate one or twotone analog
waveforms. The output of the multiplexer MUX1, which contains the test pattern, is also
attached to the input of the ORA by multiplexor MUX4 [4]. This allows the BIST to
bypass all analog components and test the functionality of the digital components. To
capture each measurement, the ORA requires reference tones. These can be generated
from additional NCOs in the TPG [11].
This TPG approach has two disadvantages due to using DDS to generate
waveforms. The first problem with using DDS is the generation of image tones around
the clock frequency. The lower half of the frequency band, 0Hz to ????/2, contains the
tones producible by the DDS, while the upper half of the frequency band, ????/2 to ????,
contains images of these tones centered around ???? [17]. This divides the usable
18
spectrum in which the DDS can generate tones to half the system clock frequency to
avoid these image tones. The second disadvantage occurs as the DDS generates tones
close to the Nyquist bandwidth of half the clock frequency, ????/2. At this point, the tone
generated, ?, and the tone?s image around the clock, ???? ??, will appear very close to
each other. This case also results in stronger image tones as quantization effects become
more pronounced when the phase accumulator uses larger increments. This results in
difficulties distinguishing the tone from the image. To reduce these images, sharp filters
are typically applied to remove frequency components at and above ????/2. This reduces
the strength of images and quantization noise, but also limits the usable range of the DDS
to less than 40 percent of ???? [17].
2.2.2 Output Response Analyzer
The second essential element of the mixedsignal BIST approach is the MAC
based ORA. Its function is to collect the response signal of the DUT. The ORA operates
on the principle of SSA, where the objective is to measure the magnitude and phase of
one specific tone.
The principles of operation for this ORA are straightforward. The ORA consists
of two pairs of MACs. Each multiplier has one input attached to the multiplexer MUX4,
which selects the source of the test data as shown in Figure 24. When undergoing a test,
the waveform being sampled by the ADC can be represented as ?(?????) [11]. The
second input on each multiplier, signals ?1 and ?2, connect to a digital NCO which is
generating a reference waveform. If signals ?1(?????) and ?2(?????) are set to
19
cos(??????) and sin(??????) respectively, then the resulting values of DC1 and DC2,
which represent the results of each MAC, are as shown in Equations 26 and 27 [4].
Equations 26 and 27 show that DC1 and DC2 each represent the inphase and
outofphase components of ?(?????) at frequency ?. By substituting Equations 26 and
27 for the inphase and outofphase components of the Fourier transformation
equation ?(?), the resulting identity can be obtained [4].
Equation 28 shows that the frequency content of the sampled waveform can be
expressed by the inphase and outofphase components DC1 and DC2, respectively. To
selectively examine a single frequency component of the response waveform, the
reference tones being mixed with the sampled waveform need to be modified to the
desired test frequency in this MACbased ORA design. To obtain the magnitude and
phase of each frequency component, it becomes convenient to express the frequency
measurements as shown in Equation 29 [4].
? ? = ??1 ? ?? ???2 ? = ?(?)?+???(?) (29)
In this representation of ? ? , the component ? ? represents the magnitude of
the measurement for frequency ?. The second component ?? ? represents the relative
(28) ?(?) = ? ????? ????? ???? = ??1(?) ?? ???2(?)
?
(26)
(27)
??1(?) = ?(?????) ? ???(??????)
?
??2(?) = ?(?????) ? ???(??????)
?
20
phase delay of the signal of frequency ? with respect to the phase of the reference tones.
These two parameters, ? ? and ?? ? , are used to determine the results of each of the
analog test measurements. The measurement of the relative phase shift can be
represented as shown in Equation 210 [4].
?? ? = ????1( ??2??
1
) (210)
This represents phase measurement only within the limited output of the
arctangent range of 90? to +90?. To express the absolute phase shift (??? ? ), the
magnitude and sign convention of DC1 and DC2 must be factored into the measurement.
This measurement of absolute phase is summarized in Table 21.
Table 21: Relationship Between ??(?) and ??O ? [4]
DC1>DC2 DC1<DC2
DC1>0, DC2>0 ??(?) = ??? ? ??(?) = 90?  ??? ?
DC1>0, DC2<0 ??(?) = 360?  ??? ? ??(?) = 270? + ??? ?
DC1<0, DC2>0 ??(?) = 180?  ??? ? ??(?) = 90? + ??? ?
DC1<0, DC2<0 ??(?) = 180? + ??? ? ??(?) = 270?  ??? ?
To solve for the ? ? parameter, three approaches are suggested in [4]. The first
approach demonstrates that it is possible to adjust the phase of the testing waveform used
to stimulate the DUT, such that the DUT response becomes inphase with the reference
tone. If the device is stimulated and the phase shift is measured, the inverse of this phase
shift can be applied to the reference source in the TPG. This will shift the inphase
measurement to match the DUT phase response. Therefore the value within the inphase
MAC will directly represent the magnitude of the measurement, while the outofphase
MAC will contain a value of zero. This magnitude is expressed in Equation 211 [4].
21
? ? = ? ? ????? ?
= ? ????? ??[?????? ??? ? ]?
= ? ????? cos?(?????? ??? ? )?
(211)
This is very beneficial as there is no calculation circuitry need to directly obtain
? ? from DC1 and DC2. However circuitry would be need to obtain the phase delay and
rerun the test with the modified phase to obtain a measurement. This approach would not
be valid if measuring noise since the noise phase could change for each subsequent
measurement [4].
The second approach to obtaining magnitude relies on factoring the phase out
from the observed measurement. If the phase shift of the observed waveform can be
obtained, then it can simply be divided out of either the inphase or outofphase
component of measurement as shown in Equation 212 [4].
? ? = ??1cos ?( ?? ? ) = ??2sin ?( ?? ? ) (212)
Unlike the first approach, this approach does not require the test to be rerun to
calculate the magnitude; therefore it can be used to perform noise measurements.
However, there is additional hardware required to calculate phase, convert the phase shift
through a cosine or sine LUT, and perform the division [4].
There is one common factor between the first two approaches. Both approaches
utilize phase shift to calculate magnitude. The third approach does not utilize phase shift
to calculate the magnitude, but instead relies on the values of DC1 and DC2 directly. The
third option presents the most direct method to implement as it only depends on the raw
values of DC1 and DC2. This is described in Equation 213 [4].
? ? = ??12 + ??22 (213)
22
Each of these three options represents a valid method of calculating the magnitude
for the SSA response in this MACbased ORA. Now that the ORA is capable of
collecting phase and magnitude utilizing two pairs of MACs, it requires a method for
controlling the length of accumulation, N. When the ORA is attempting to accumulate the
response of a single tone from the DUT, the accumulator outputs DC1 and DC2 are
expressed as shown in Equations 214 and 215 [4].
DC1 and DC2 contain the inphase and outofphase components necessary for
calculation, represented as ?? cos ?? and ?? sin ?? , respectively. An additional
component of ?2 is factored into the result as a component of accumulation. Because this
component exists equally in both DC1 and DC2 it can be factored away if the number of
accumulation cycles is known. Unfortunately, these terms also contain a summation of
cosine and sine which act to skew the correct answer based on when the accumulation is
halted. The resulting DC1 and DC2 terms will accumulate over time as shown in Figure
26 [4].
??1(?) = ????(2??????? + ??) ? cos?(
?
?=1
2???????)
= ??2 cos ?? + ?2 ???(4??????? + ??)
?
?=1
??2(?) = ????(2??????? + ??) ? sin?(
?
?=1
2???????)
= ??2 sin ?? + ?2 ???(4??????? + ??)
?
?=1
(214)
(215)
23
Figure 26: DC1 and DC2 Versus Time [11]
The slope of each line represents the DC1 inphase accumulated value of
??
2 cos ?? and the DC2 outofphase accumulated value of
??
2 sin ?? . The oscillation
in each waveform is a result of the additional erroneous sinusoidal component. In order to
obtain the correct measurement, this term must be negated from the calculations. One
method for removing this term is to utilize the identity that the summation of all points in
the unit circle will equate to zero as shown in Equation 216. Therefore, there must be a
number of discrete summations N of this sinusoidal error factor which result in canceling
out this term from both DC1 and DC2.
0 = ?????? ? ?? =2?0 ???? ? ??2?0 (216)
24
The number of samples N which relates to the canceling of this term occurs at the
Integer Multiple Period (IMP) of the waveform. This IMP occurs when the waveform
crosses the axis after each period. The waveforms are generated using NCOs in the TPG
which utilize a phase accumulator. When these accumulators reach their limit and
overflow the waveform crosses the origin. The point where the waveform crosses the
origin corresponds with an IMP [630]. However, if an overflow occurs and the
accumulator contains any value other than zero, then the discrete measured value will
contain a measurement past the origin instead of at the origin. The overflow flag of the
accumulator as well as the value of zero within the accumulator can be used to signal that
an IMP has occurred; a simple circuit can be constructed as shown in Figure 27.
Figure 27: IMP Detection Circuit for Single Tone Measurement [630]
For tests that require two tones, a slightly modified approach must be taken to
obtain the IMP. In a two tone measurement, the results stored in DC1 and DC2 contain
error based on both the fundamental waveforms and the intermodulation of these
waveforms. Therefore the true IMP which will cancel out these terms will occur only
when the IMPs of both the fundamental and intermodulation tone occur simultaneously
[30].
Carry Out & D=0
25
2.2.3 Analog Functional Measurements Approach
This BIST architecture, utilizing a DDSbased TPG and MACbased ORA, is
capable of performing linearity, frequency response, and noise measurements. These tests
allow the performance of the analog circuit to be characterized and compared to design
specifications [6]. An overview of how these measurements are conducted within the
BIST circuitry is given within this section.
The first of these testable measurements is linearity. The linearity response of a
real system is defined by severity of nonlinearity, as all real devices inherently contain
some degree of nonlinearity. The test for linearity involves measuring the Third Order
Intercept Point (IP3) under a two tone test input [6]. This product is generated from
higher order harmonics of the input tones intermodulating with the original tones to
create new frequency content. This is illustrated in the Figure 21. Specific points of
interest are the frequencies 2?2?1 and 2?1?2. These represent the two artificially
generated products of the IMD which appear closest to the original tones. These two
tones in particular are known as the Third Order Intermodulation (IM3) components [4].
The IM3 tones are chosen to define linearity because their proximity to the fundamental
tones makes them extremely difficult to filter away. Using these IM3 terms, the Input
Referred Intercept Point (IIP3) is defined by Equation 217 [4].
???3 ??? = ?? ?? 2 + ???[???] (217)
The ?P term represents the difference in power between these IM3 tones and the
fundamental tones, and Pin is the signal power at the input of the device. The
intermodulation components of this device can be theoretically calculated using the
26
Taylor Series approximations. Given that the linearity of interest is that of a nondynamic
input, Taylor Series approximation becomes an ideal representation for nonlinear time
invariant systems. Using the Taylor Series method, the input to analog system, x(t), and
the transfer function of the system, y(t), are represented as shown in the following two
Equations 218 and 219 [6].
? ? = ?1 cos ?1? + ?2 cos ?2? (218)
? ? = ?0 + ?1? ? + ?2? ? 2 + ?3? ? 3 + ? (219)
In this case, A1 and A2 represent the magnitude of the tones while ?1 and ?2
represent the two separate frequencies. The symbols ?# represent the timeinvariant
coefficients of the Taylor Series expansion [4].
? ? = 12 ?2 ?12 + ?22
+ ?1?1 + 34 ?3?1 ?12 + 2?22 cos ?1?
+ ?1?2 + 34 ?3?2 2?12 + ?22 cos ?2?
+ 12 ?2 ?12cos?(2?1?) + ?22cos?(2?2?)
+?2 ?1?2 cos ?1 + ?2 ? + cos ?1 ??2 ?
+ 14 ?3 ?13cos?(3?1?) + ?23cos?(3?2?)
+ 34 ?3 ?1
2?
2 cos 2?1 + ?2 ? + cos 2?1 ??2 ?
+?1?22 cos 2?2 + ?1 ? + cos 2?2 ??1 ?
(220)
After solving this expression for the component of the fundament term at ?2 and
the IM3 term at 2?2 ??1 and assuming that A1=A2, then the IIP3 and Output Referred
Intercept Point (OIP3) can be obtained from the Taylor Series variables as shown in
Equations 221 and 222 [6].
IIP3 ? 43 ?1?
3
, when ?1 ? 94 ?3?2 (221)
OIP3 ? ?1???3 (222)
27
This technique of measuring linearity relies on the assumption that the test tones
and output of the device are relatively small in magnitude such that the device does not
become damaged or desensitized [6]. The illustration below in Figure 28 shows the
relationship between the fundamental tone, IM3 point, and ?P.
Figure 28: Illustration of Fundamental Tone Compared to IM3 Tone in IP3 Test [6]
The frequency response is obtained by forcing the TPG to generate a single tone
and pass that tone through the DUT. The ORA will then measure the magnitude and
phase of the resulting waveform at the frequency of the generated tone. However, this
measurement includes the response of not only the DUT, but every component in the
measurement path. To negate the effects of the additional components, the test tone is
measured a second time. In the second measurement, the DUT is bypassed using an
analog multiplexer and the waveform is remeasured. This represents the resulting
magnitude and phase from the interaction with all other components within the
measurement path. This includes the DAC, smoothing filter, analog multiplexer, and
ADC. The resulting difference between these two measurements will represent the
frequency response of only the DUT [7]. This procedure can be repeated for different
28
frequencies by sweeping the generated tone and measured tone together. This is
illustrated in Figure 22. This allows for a measurement of the response over a range of
possible frequency values.
Each noise measurement test begins by forcing the TPG to generate a single tone
and passing that waveform through the DUT. The ORA will then calculate a
measurement of the signal strength at the fundamental tone [4]. At this point, the test
varies based on which of the four noise measurements is being performed. To obtain
THD, the ORA will measure the magnitude of harmonic tones which occur at integer
frequencies of the fundamental tone, while the TPG continues to generate the fixed
fundamental tone. Each of these integer multiple frequencies of the fundamental tone
represents a harmonic [20]. The THD can be obtained by taking the ratio of the
fundamental tone signal strength to the average of these harmonic noise measurements.
To obtain SNR, the ORA will measure the magnitude of frequencies that are not integer
multiples of the fundamental tone, while the TPG continues to generate a fixed
fundamental tone. This will collect the spectral content of the noise which is not a
function of fundamental tone [4]. By averaging these collected noise measurements we
obtain the average background noise of the system. The ratio between the signal strength
of the fundamental tone and this background noise measurement will be the result of the
SNR [20]. The measurement of SINAD, involves the combination of the tests for SNR
and THD. Rather than selectively choosing measurement points which contain only a
certain type of noise, SINAD selects all measurement points to include in the noise
calculation with the exception of the fundamental tone. The SINAD can be obtained by
taking the ratio of the fundamental tone signal strength to the average of the noise
29
measurement points [20]. An illustration of SNR, THD and SINAD can be seen in Figure
23.
The NF measurement represents a very important measurement to the device.
Measurements of SNR, THD, and SINAD represent the ratio of signal strength to noise
strength of the entire measurement path which includes the DAC and ADC. The NF
measurement represents the degradation in SNR due to the DUT alone [20]. The NF test
represents the longest of the noise tests, because this test requires the SNR to be
measured twice. The first SNR measurement is of the DUTs output response. This
represents the SNR of the complete path including the DUT. The second SNR
measurement involves bypassing the DUT in the measurement path [4]. This can be
performed using the analog multiplexor, MUX3, as illustrated in Figure 24 to bypass the
DUT. By taking the ratio of these two measurements as described in Equation 22, the
NF can be obtained [24].
2.3 Multipliers
Multipliers make up the core of the ORA. A multiplier is a binary circuit which
utilizes a combination of logic elements and adder units to implement a multiplication
operation on two binary numbers called the multiplier and multiplicand. The basic
construction of a multiplier has two parts. The first stage is the generation of the partial
products. The second stage is the summation of these partial products to produce the final
result [29]. Multipliers are typically differentiated by their implementation of the first
stage.
There are many common types of multiplier designs. Array multipliers represent
the simplest class of multipliers consisting of a simple array of logical AND gates to
30
generate the partial products and full adders to implement the addition of each partial
product row [29]. The fundamental shortcoming of this multiplier is that it is intended for
unsigned multiplication. A simple modification is required to transform this multiplier for
signed mathematics. By negating the upper most significant bits (MSB) of each partial
product and the highest order partial product, the array multiplier is transformed into a
BaughWooley multiplier capable of signed multiplication [29]. These two multipliers
represent the simplest designs, but both multipliers suffer from long calculation time and
high area overhead. These two multipliers have been superseded by an improved
multiplier known as the ModifiedBooth multiplier.
The ModifiedBooth multiplier seeks to reduce the overall size of the multiplier
by exploiting patterns in the multiplier and multiplicand inputs to generate half the
number of partial products as the BaughWooley multiplier. The ModifiedBooth
algorithm is based on the fact that a radix4 multiplier will require half the number of
partial product stages as a radix2. The Booth algorithm examines the contents of the
multiplier register input and seeks to reduce the number of partial product rows required
by logically combining partial products before they are generated [28]. Within the partial
products of a standard signed multiplier, each partial product row can have only one of
two possible values. These two values are either the multiplicand or all zeros. The Booth
algorithm encodes possible radix4 combinations in an entity called the Booth recoder
[28]. This coded instruction is then applied to these reduced partial products as shown in
Table 22.
31
Table 22: Booth Recoding Bits Decoded
Multiplier bits Booth Code Instruction
X2N+1 X2N X2N1 S M2 M1 Value of Partial Product
0 0 0 0 0 0 Multiplicand x 0
0 0 1 0 0 1 Multiplicand x 1
0 1 0 0 0 1 Multiplicand x 1
0 1 1 0 1 0 Multiplicand x 2
1 0 0 1 1 0 Multiplicand x 2
1 0 1 1 0 1 Multiplicand x 1
1 1 0 1 0 1 Multiplicand x 1
1 1 1 1 1 1 Multiplicand x 0
The Booth recoder then takes these coded bits, and uses a binary shift and invert
operation to reconstruct the partial products. After the Booth algorithm is complete, there
are only half the original partial products [28].
The ModifiedBooth multiplier modifies the number of partial product bits to
improve the performance of the multiplier, but this is not the only method to improve
performance. The next technique is known as Wallace tree reduction. The Wallace tree
reduction method relies on cleaning up the inefficiency when adding partial product bits
to improve calculation speed [28]. In a serial arrangement of accumulation of the partial
products, each partial product is serially added to the next partial product after it. This
results in N partial products consuming N1 addition stages. Wallace tree reduction
attempts to reduce the long computation time of accumulating these partial products by
adding multiple partial product factors together simultaneously rather than sequentially.
The Wallace tree reduction method is designed to reduce the number of partial products
to two final rows. These two remaining partial products can then be summed together
using any number of fast adder approaches [28]. Illustrated in Figure 29 is an example of
how rearranging partial product addition stages can reduce the calculation time. Figure
32
29 (a) shows a serial summation of products resulting in a worst case path of three
adders, but Figure 29 (b) rearranges these adders to result in a worst case path of two
adders.
Figure 29: Illustration of Rearranging Partial Product to Decrease Worst Case Path
2.4 Coordinate Rotation Digital Computing Algorithm
The Coordinate Rotation Digital Computer (CORDIC) algorithm is a well known
iterative approximation technique to perform various arithmetic operations. The
algorithm is very simple to implement in hardware, because it uses only shiftandadd or
shiftandsubtract operations to perform vector rotation in a two dimensional plane [29].
By using successive approximation the CORDIC algorithm can approximate the most
basic mathematical functions. The most common use of the CORDIC algorithm is in
approximating trigonometric functions [28]. The CORDIC algorithm can be broken into
three distinct groups. The distinguishing factor of each group is how the CORDIC
successive approximation function is implemented [29].
? Linear CORDIC ? This CORDIC design is capable of expressing linear functions
such as multiplication, division, addition, and subtraction. In this method the
correction factor that is applied to each successive approximation remains
constant. This allows it to be able to express linear operations [28].
A B C D
SUM
A SUM
B C D
(a) (b)
33
? Circular CORDIC ? This CORDIC design is capable of expressing trigonometric
functions which can be expressed around the unit circle. Functions such as sine,
cosine, tangent, arctangent, arcsine, arccosine, and square root can be expressed.
In this method, the successive approximation is a factor of the arctangent
function. This allows for circular functions to be expressed [28].
? Hyperbolic CORDIC ? This CORDIC design is used for representing hyperbolic,
logarithmic, and exponential functions. The hyperbolic CORDIC utilizes an
inverse hyperbolic tangent function when performing a successive approximation.
This allows for the expression of exponential and logarithmic based operations
[28].
The basic operational theory of the CORDIC algorithm is that the CORDIC will
approximate a two dimensional vector. To obtain this vector, the CORDIC will start at 0
degrees rotation and attempt to reach a goal of either phase or magnitude. Before each
rotation, the CORDIC will be able to measure if it overshot or has not yet reached its goal
[29]. Depending on this, it will either add or subtract the next rotation information from
the current approximation. Each successive approximation in the circular CORDIC
algorithm rotates by:
???????? ????? ? = tan?1( 2?? ) (223)
In this estimation, the variable N represents Nth rotation in the series. As evident
by this formula, as the number of rotations is increased, the step size of the higher order
rotations represents a decreasing amount of change. The illustration in Figure 210
represents the CORDIC algorithm attempting to reach a phase of 65 degrees.
34
Figure 210: Illustration of CORDIC Rotational Procedure
In this example, the red arrow illustrates the fixed goal of 65 degrees, while the
green represents the current CORDIC estimation. On the first attempt in Figure (a), the
CORDIC begins at 0 degrees. The CORDIC is able to ascertain that it has not yet reached
the goal of 65 degrees, so it adds the first rotational increment of 90 degrees shown in
Figure (b). This estimate overshoots the goal of 65 degrees. Because the CORDIC has
passed the goal, it must now take measures to change the direction of the next phase
increment. This causes the CORDIC to subtract the next phase rotation of 45 degrees
shown in Figure (c). This process is repeated in Figure (d) where it adds the third
rotational phase giving it a current phase of 71 degrees. This process will continue to
become more accurate as it successively approximates the measurement until a fixed
number of rotations has been achieved by the CORDIC.
The CORDIC algorithm for linear, circular, and hyperbolic functions can all be
combined into the unified CORDIC model [29]. In the unified CORDIC model, the
approach is simplified into one vector V with three components X, Y, and Z. The vector
components X and Y represent the projection of the vector V into the two dimensional xy
plane. The third component, Z, represents the angle of the vector with respect to the X
(a) (b) (c) (d)
35
axis. For each successive approximation, the value of these components can be expressed
as shown in Equation 224 [29].
??+1 =
??+1 = ?? ????2??(?,?)??
??+1 = ?? + ??2??(?,?)??
??+1 = ?? ?????,?
For each of the three CORDIC models, the CORDIC mode parameter m,
rotational direction ??, shift sequence ?(?,?) , and rotational angle ??,? used in the
definition of the unified CORDIC algorithm can be expressed as shown in Equations 2
25 through 228 [29].
? =
0
1
?1
?? = ????(??)????(?
? + ??)
?(?,?) =
0,1,2,3,4,5,?
1,2,3,4,5,6,?
1,2,3,4,4,5,?
??,? = 1 ? arctan?( ? ? 2?? ?,? )
Using these equations, the unified CORDIC model can be completely constructed
for either the linear, circular, or hyperbolic model. The CORDIC algorithm however has
three major disadvantages. The first disadvantage is the speed of calculation. The
CORDIC relies on a method of successive approximation. After each pass through the
CORDIC calculation, the results become more accurate [29]. Unfortunately, it requires
For Linear CORDIC
For Circular CORDIC
For Hyperbolic CORDIC
(228)
(224)
For Linear CORDIC
For Circular CORDIC
m=1
m=0
m=1 repeated at 3?+2?12
(227)
(226)
(225)
36
multiple iterations until the output of the CORDIC calculation begins to approximate the
correct value within a reasonable margin of accuracy. The second disadvantage also
occurs due to the successive approximation. This method will continuously approach the
correct value, but never obtain the true value [29]. The third disadvantage in the CORDIC
approach appears because of the successive shifting vector rotation. With each rotation, a
successively decreasing amount of error is added to the result. This error is based solely
on the number of rotations taken to achieve the result. This error can be expressed as
shown in Equation 229, where N represents the number of rotations [28].
2.5 Thesis Restatement
This chapter has presented previous work on mixedsignal BIST using SSA [4]
[12]. This will become the foundation for the topic of this thesis, which includes the
implementation of onchip measurement techniques within the mixedsignal design and
the automated generation of this BIST approach.
To achieve these ends, this thesis will focus on the design of the model required to
produce these measurements. This thesis will present a new multiplier model which will
reduce the size from conventional multipliers as well as increase the speed of calculation.
Another goal of this thesis will be to introduce a technique to automatically generate a
hardware description language for this mixedsignal BIST design. Finally, this thesis will
present a method for calculating onchip the results of the tests listed in this chapter
utilizing a CORDIC based calculation unit.
(229) ?????(?) = 1 + ???22?2??(?,?)
?
?=0
37
Chapter Three
MixedSignal BuiltIn SelfTest Implementation
Implementing this mixedsignal BuiltIn SelfTest design requires the conceptual
design to be capable of being expressed in hardware. This is usually achieved using a
Hardware Description Language (HDL), which is a language that can be used to express
hardware circuit elements for simulation and physical realization of the circuit. One of
the most common forms of HDLs is known as Very High Speed Integrated Circuit
Hardware Description Language (VHDL). Once this mixedsignal BuiltIn SelfTest
design has been physically implemented from the VHDL, it can then be integrated with
the intended analog components and the analog circuit to be tested.
This chapter will discuss the improvements to the implementation of the mixed
signal BuiltIn SelfTest for analog circuits. The topics covered include automatically
generating the hardware descriptive model based on userdefined system performance
parameters, producing sinusoidal waveforms in a digital core using a hardware
description language which lacks trigonometric operators, and constructing an Output
Response Analyzer using an improved multiplier design.
38
3.1 Program Generation
This mixedsignal BIST approach can be utilized in multiple applications;
therefore there is a need to develop a method to generalize the model so that it can be
implemented to fit multiple instances with differing requirements. In most HDLs, some
form of parameterization is possible. This allows for HDL structures to be reconfigured
based on the requirements of the application. However, some HDL structures prove too
complex to be completely parameterized for all applications. Attempting to parameterize
these complex models can result in a hardware description that is too difficult to verify
proper operation due to the large number of conditional synthesis statements required to
create a universalized model.
This thesis proposes a solution to the potential complexity of parameterizing this
mixedsignal BIST approach by implementing a customized program designed to
automatically generate the hardware description model given a set of userdefined system
parameters. This program, MSBISTGen.exe, written in the C programming language is
capable of generating the required VHDL models to implement the digital portion of
mixedsignal BIST design; this includes the Test Pattern Generator, Output Response
Analyzer, and test controller of the BIST design. Given userdefined requirements for the
implementation of the design, this C program is also capable of generating the VHDL
model to meet these design goals.
The mixedsignal BIST approach described in this thesis can be utilized in many
applications, but the components which comprise the hardware model will remain
relatively similar within each instance of this BIST model. The design will contain
multiple NCOs for the TPG, multipliers and accumulator for the ORA, and multiplexers
39
to control the datapath as shown in Figure 24. However, based on the intended
application, priority of the hardware implementation of this BIST design may focus on
runtime of the tests, precision of measurements, or area resource consumption.
Maximizing these design requirements can be achieved by altering key attributes such as
the resolution of the DDSbased TPG or implementation of the Multiplier Accumulator
pairs which comprise the ORA. However, by exploiting the fact that the majority of these
components remain unchanged between implementations, we can use exact models for
these unchanged elements in each design using this mixedsignal BIST. For those
components to be altered based on specific system characteristics or other user
parameters, the customized program can be used to insert, remove or modify portions of
the hardware description to accommodate any changes.
Figure 31: Screenshot from Automated Program to Generate MixedSignal BIST Model,
MSBISTGen.exe
40
This program prompts the user to define the set of model parameters to be used to
generate the VHDL model as shown in Figure 31. These options include key design
parameters for the DDSbased TPG such as the size of the phase accumulator, and
LookUp Table used to generate the waveform. There are also additional options to
format the output of the TPG to interface with varying sizes and formats of DACs. The
ORA can also be customized to accommodate varying sizes of the ADCs. In addition, the
type of multiplier and size of accumulator which compose the MAC can be selected.
The program takes each user input and interprets these choices into software flags
which will correspond to hardware implementation decisions. After all decisions have
been evaluated by the program, it will generate the hardware model in a VHDL file
format and save the resulting model within its own project directory. To generate the
VHDL files, the createfile function within the standard C library is invoked to generate
each VHDL file. Then using the fprintf function, the VHDL formatted model is generated
based on the user defined parameters and copied into each file. The structure of the
generated model can be seen in Figure 32. Detailed information on the content of each
generated file can be found in Table 31.
41
Table 31: Description of Generated Files
Filename Description
top.vhd This generated file contains the top level entity of the mixed
signal BIST model. The TPG, ORA, and Test Controller are
interconnected on this level.
tpg.vhd This generated file contains the DDSbased Test Pattern
Generator model which instantiates each NCO.
ora.vhd This generated file contains the SSAbased Output Response
Analyzer model which instantiates both MACs.
testcontroller.vhd This generated file contains the test controller entity used to send
and retrieve results of the test.
nco.vhd This generated file contains the definition for the NCO.
accum.vhd This file contains the accumulator used to accumulator the phase
information.
pac.vhd This file contains the Phase to amplitude converter which uses
the reduced sinwave LookUp Table discussed in this chapter as
well as any signal processing necessary to properly format the
LUT output.
sinlut.vhd This generated file contains the custom created LookUp Table to
implement the conversion between linear accumulation and
sinusoidal output
spi.vhd This file contains the serial peripheral used to serialize
information to be passed in and out
Top Level Integration
(top.vhd)
Test Pattern Generator
(tpg.vhd)
Output Response Analyzer
(ora.vhd)
Test Controller
(testcontroller.vhd)
Numerically
Controlled Oscillator
(nco.vhd)
Phase Accumulator
(accum.vhd)
Serial Peripheral
Interface
(spi.vhd)
Phase to Amplitude
Converter
(pac.vhd)
Sinwave LookUp
Table
(sinlut.vhd)
Figure 32: Hierarchical Tree of Files Generated for MixedSignal BIST Model
42
3.1.1 Test Pattern Generator
At the heart of any BuiltIn SelfTest technology is a Test Pattern Generator.
Unlike the traditional digital TPG design, a mixedsignal TPG requires a slightly
different approach. The goal of the mixedsignal TPG is to create an analog waveform to
stimulate the Device Under Test. As discussed in Chapter 2, this can be performed
utilizing a DDSbased approach to generate either one or two tones. To achieve this we
can simply utilize a linear accumulator in series with a LookUp Table to convert these
linear increments into a sinusoidal pattern [17]. When combined, these elements produce
a Numerically Controlled Oscillator. Unfortunately the conversion from linear to
sinusoidal notation cannot be easily performed in the hardware description languages of
VHDL or Verilog, because these languages lack the standardize trigonometric functions
necessary to perform a sinusoidal conversion. This leads to the problem of how to create
a parametizable sinusoidal conversion LUT using HDL.
However, not all computer languages lack the trigonometric function. It is very
common to find trigonometric and other complex mathematic operators builtin as
standard libraries for more common computing languages. These programming languages
typically also support functions to export strings to files. Therefore it is possible to write
a software script which can solve mathematical equations and convert the results to
strings in the form of HDL statements and export the HDL to files. When these files are
synthesized for hardware development, it will appear as though the mathematical
equation was implemented directly in hardware. This allows users to integrate tools,
libraries, and features that common computer programming languages such as C, C++,
JAVA, or PERL have been able to take advantage into less robust hardware languages.
43
The purpose of the NCO is to generate a sinusoidal waveform. By utilizing the
SIN function from the standard C programming libraries we can generate exact values to
be placed in a LUT in our NCO model to translate our linear accumulation to sinusoidal
phase. By allowing the program to compute the answer to Equation 31, we can obtain
the value of each entry in the table. In this equation the integer solution TableEntry
represents the integer value to be placed in the LUT. The term Amplitude acts as a scalar
multiplier to stretch the normally 1 to 1 value of the SIN function to a large integer
range. The value of Amplitude will be used to determine the magnitude of the LUT
output. Larger DACs will be able to accommodate a larger Amplitude value. Increasing
the Amplitude term by a power of two, results in a linear increase in the size of the LUT.
The value of ? represents the maximum possible integer input value to this table. Unlike
the Amplitude term, doubling the ? term will result in doubling the size of the resulting
LUT. The final variable, Input, represents the value that would be seen on the input to the
LUT and ranges from 0 to ?.
?????????? = ????????? ? sin ???????2?? (31)
????????? = 2?????? ?? ?????2 (32)
After the C program has computed the answer to each possible input to this
equation, it can place these inputs within a VHDL casewhen statement to ensure that the
synthesis tool which interprets the VHDL model will treat these elements as values for a
LUT. To further reduce the area coverage from the LUT, only a portion of the SIN
function needs to be stored within the LUT. In the Equation 31, we store only one
44
quarter of the complete waveform and exploit the repetition which occurs every 90? in the
sinusoidal function. This now means that additional logic is required to format the input
to and output from this table to be directly compatible with a DAC, but the overhead
required to implement this additional logic is minimal when compared to the size of the
LUT overhead.
The LUT entries stored in the Equation 31 can be visually represented as shown
in Figure 33. In this illustration, the term Amplitude is expressed as the maximum
magnitude output from the LUT and ? is inversely proportional to the phase step
resolution in the LUT. To create the full waveform of 360?, the quarter waveform table,
which represents only one quadrant of the waveform, will need to be repeated four times.
The logical repetition of this LUT is visually illustrated in Figure 34. This figure shows
how an accumulation in the quarter wave LUT can be used to express the full sinusoidal
waveform. In addition, the upper two Most Significant Bits (MSB) of the phase
accumulator can be used to decode which quadrant of the full waveform the LUT is
currently expressing. This relationship is shown in Table 32.
45
Figure 33: Illustration of Quarter Wave Table
Figure 34: Illustration of Repeating Quarter Wave Table to Form Full Wave Table
Table 32: Decode Top Bits of Quarter Wave Phase Accumulator
Expressed Range MSB MSB1 Direction Output Sine Value
0?  90? 0 0 Bottom to Top NonInverted
90?  180? 0 1 Top to Bottom NonInverted
180?  270? 1 0 Bottom to Top Inverted
270?  360? 1 1 Top to Bottom Inverted
Amplitude
B1
90:
0:
270:
180:
360 :
Negative
Domain
Positive
Domain
Negative
Domain
Positive Amplitude
Negative Amplitude
0:
Positive
Domain
90:
46
This single quarter wave encoded LUT is capable of expressing the entire range
of output values in the sinusoidal waveform. However this output must be modified to do
so. As shown in Table 32, by examining the top two MSBs of the phase accumulator, the
quadrant position of the output waveform can be determined. Using this quadrant
information, the direction the LUT is incremented, as accumulation continues, can be
determined. This quadrant information also determines whether the output of the LUT
needs to be expressed as a positive or negative result. This reduction results in a new
version of the NCO model which relies on modifying the output of the LUT with
generated bits which correspond to the current quadrant of the sine wave, rather than
encoding these bits directly into the LUT. This is shown in Figure 35.
.
This reduction of the NCO provides for a smaller DDSbased TPG with no loss in
resolution of the output waveform when compared to the originally purposed TPG.
However there is an additional component which can be added to the NCO in the TPG to
further improve resolution of measurement. As mentioned in Chapter 2, the DDS
approach to generating tones has some drawbacks. The most notable is the generation of
image tones and spurs resulting from the quantization of the signal, phase truncation, and
harmonics of the generated tone. One method for reducing the presence of these spurious
Phase to Amplitude Converter
Figure 35: Illustration of Modified NCO model to include reduced LUT.
M
??1
M
M
M f
??
M
N M M? Sin/Cos
LUT
Quadrant
Sine
extension
N?
Quadrature
Assignment
& Phase
Truncation
47
tones is the Nicholas modified phase accumulator [17]. This component replaces the
traditional phase accumulator used in the NCO. The Nicholas modified phase
accumulator is not capable of removing the error which results from the DDS process,
but instead redistributes the power spectrum of the spurious tones [17]. This results in
many small spurious tones rather than one large tone in the DDS output.
The construction of the Nicholas modified phase accumulator utilizes one
additional D Flipflop set to toggle the input of the phase accumulator adder every other
clock cycle and is illustrated in Figure 36. This does not affect the frequency word being
added to the accumulator directly, but adds an additional component into this
accumulator that acts to dither the value coming from it.
The Nicholas modified phase accumulator reduces spurious tones that are
generated in the DDS output, but this approach has two drawbacks. The first hindrance is
that this technique introduces a fractional offset to the signal, represented as shown in
Equation 33 [17]. In this equation, M represents the length of the phase accumulator.
This frequency offset is smaller than the resolution of the DDS making it extremely
difficult to detect.
Figure 36: Block Diagram of Nicholas Modified Phase Accumulator [17]
M Phase
Register
Ad
de
r Frequency
Word
Register f
CLK
R Q
Q D
M
Ha
rdwa
re
M
odifica
tio
n
To
Ca
rry
Inp
ut
Phase
Truncation
N
48
??????? = ????2?+1 (33)
The second disadvantage of the Nicholas modified phase accumulator is that it is
possible the dithering process will introduce a small amount of error. If there is no phase
truncation error in the samples, then the Nicholas modified phase accumulator will add an
unnecessary dithering factor into the accumulation and introduce a small amount of
unnecessary noise into the generated tone [17]. By utilizing an external program to
generate this model, the user can determine if tradeoffs of this dithering tool represent
significant improvement to that particular instantiation of the BIST model and should be
included.
Shown in Figure 37 is the resulting testing waveform generated by the DDS
based TPG of this mixedsignal BIST design and captured by a spectrum analyzer. In the
center of this image is the generated single tone produced by the TPG at 14.4 kHz.
Captured along with this main tone are four spurious tones generated due to the phase
truncation stage within each NCO. These are the spurious tones which the Nicholas
modified phase accumulator is designed to reduce. Shown in Figure 38 is the same tone
generated by the mixedsignal BIST with the exception that Nicholas modified phase
accumulators are used in the NCOs of the TPG rather than traditional accumulators. The
four sharp spur tones which are present in Figure 37 have been broken into many less
intense tones in Figure 38 due to the modification to the phase accumulator which
minimizes the strength of the worst case spur. Shown in the top right corner of both
figures is the measurement of the signal strength difference between the main tone and
the strongest spurious tone. In the example implementation of the Nicholas modified
phase accumulator, an improvement of 2.79 dB spurious free range was achieved.
49
Figure 37: Spurious Free Dynamic Range of 55.169 dBc in a 14.4 kHz Tone Generated
and by the MixedSignal BIST Without Nicholas Modified Phase Accumulator
Figure 38: Spurious Free Dynamic Range of 57.959 dBc in a 24.4 kHz Tone Generated
by the MixedSignal BIST With Nicholas Modified Phase Accumulator
50
3.1.2 Output Response Analyzer
The Output Response Analyzer is responsible for measuring the response from
the DUT and calculating the results of the test. In the discussed model, the ORA achieves
this calculation by using only two multiplier/accumulator (MAC) pairs to calculate the
DC1 and DC2 terms, which represent the complex terms of magnitude and phase of the
measured signal. To implement this we need a multiplier model fast enough to be able to
handle high speed signals, yet small enough that it won?t become a burden on the area
overhead.
The multiplier suggested in this thesis is a modern variant of classic multiplier
design. The most common multiplier models are the array multiplier, BaughWooley
multiplier and Booth multiplier. Background on these can be found in Chapter 2. When
the Wallace tree reduction algorithm is combined with the ModifiedBooth algorithm, the
result is a fast and efficient signed multiplier which utilizes only half the typical number
of partial product summations. By using enhancement and reduction techniques, it is
possible to compress the size of this multiplier to an even greater extent. The first step in
modifying this multiplier is to enhance its speed of calculation by pipelining each stage
within the multiplier. The key points to pipeline would be between each stage of partial
product addition and after the calculation of Booth encoded partial products. The next
stage of modification involves a novel reduction technique.
This reduction technique is centered around the axiom that any two?s complement
number added to its negative equivalent will equate to zero. Therefore, adding a number
and its two?s complement, along with the partial products normally found in the
multiplier will be equivalent to just adding the partial products. But these additional bits
51
from the additional negative two?s complement number will allow a logical reduction of
partial product bits. The negative number, 2N+1, can be logically added to the generated
partial products that come from the ModifiedBooth algorithm, where N represents the
size of the multiplicand in a two?s complement format. This number will appear as all
ones at and above the position N+1 and all zeros below.
The first step in reduction is to take the 2?s complement number and add it to the
padding that exists in each partial product row. Any positive signextended number in the
multiplier will normally be padded with zeros. Adding this padding of all zeros to a
number of all ones will result in all the padding bits and the sign bit becoming all ones.
Conversely any multiplier partial product which happens to be negative will be padded
with ones. If this number of all ones is added to the negative padding of all ones, the
result will be that all the padding bits will still be all one, but the lowest order sign bit
will have inverted from one to zero. If we keep the sign bit and the first padded bit from
each stage in this process, then this algorithm can be simplified. This summation of each
reduction phase is illustrated in the Figures 39 through 314. Figure 39 illustrates the
overall logical combination of the reduction factor with the partial products rows. Figure
310 shows the only two possible outcomes for each stage of reduction. Figure 311
through Figure 314 individually illustrate the reduction which takes place on each partial
product?s sign extension bits. The highlighted area in these illustrations represents the
area that will be reduced in the following illustration.
52
Figure 39: The Logical Addition of the Two?s Complement Term with Partial Products.
The First Row Represents the Correction Factor While Each Additional Row Represents
the Partial Products Rows.
Figure 310: The Two Possible Outcomes for Each Stage of Reduction
Figure 311: The Logical Addition of Offset Term with First Negative Partial Product.
The Highlighted Area Represents the Next Area to Be Reduced.
53
Figure 312: The Logical Addition of Offset Term with Second Negative Partial Product.
The Highlighted Area Represents the Next Area to Be Reduced.
Figure 313: The Logical Addition of Offset Term with Third Positive Partial Product.
The Highlighted Area Represents the Next Area to Be Reduced.
Figure 314: The Logical Addition of Offset Term with Final Negative Partial Product.
54
In this new model the MSB, the sign bit, of each partial product is inverted and a
binary one is added to the MSB+1 position. All higher order bits that were used for sign
extension can be modified to zero. As adding zeros will always yield zero, we can now
logically remove this extra adder logic from the circuit. This takes what would have been
a long partial product with sign extension bits up to N+M bits long and reduces each
partial product down to a fixed N+2 bits. The two MSB can be expressed as shown in
Equations 34 and 35.
)( M S BM S B XnotX ? (34)
11 ??MSBX (35)
In an 8x8 bit modified Booth multiplier, this can remove twelve no longer needed
adder units from the partial products adding phase. Larger multipliers will see an even
larger reduction in sign extension bits. For example, a 25x25 bit modified Booth
multiplier will be reduced by one hundred and fortyfour bits. This represents
approximately a 22% reduction in partial product bits from the original modified 25x25
Booth model. For symmetric multipliers, the number of reduced partial product bits is
expressed Equation 36.
??????? ???? = ?????????? ????2 ? 2?
?????????? ????
2
?=1 (36)
Table 33. Reduction in Partial Product Bits by Size of Modified Booth Multiplier
Size of N in NxN 8 9 10 11 12 13 14 15 25 500
Original Number of Bits 76 95 115 138 162 189 217 248 663 250250
Reduced bits 12 16 20 25 30 36 42 49 144 62250
Percent Reduction 16% 17% 17% 18% 19% 19% 19% 20% 22% 25%
55
This reduction in size of the partial product terms comes at a price. To reduce
these higher order sign extension bits, we must add one more number to the partial
product to compensate for adding in this previous value. This new number is simply the
two?s complement of the previous value. This will always be a power of two with the
value of 2N+1 in the ModifiedBooth model. The solution to resolving this issue is to add
this partial product within the Wallace tree structure as a carry in bit. This will result in
simply converting one halfadder into a fulladder. This has the added benefit of
requiring no additional partial product stages.
These improvements represent a significant size reduction for large MACs in the
ORA. However, size reduction is not the only benefit of these MACs. This design can be
further sped up by utilizing registers between each partial product addition stage to
pipeline the multiplication. This will result in a faster multiplier, but multiple clock
cycles will be required until the output is valid. This will cause an initial latency, but high
overall bandwidth is achieved. Because this multiplier utilizes the Booth architecture to
generate partial products, only half the partial products stages of a normal multiplier are
needed. This will result in half the number of pipelining registers when compared to a
traditional multiplier.
3.2 BuiltIn SelfTest Test Results
To verify that this program operates properly and to obtain a measurement from
this mixedsignal BIST model, this design needed to be implemented in hardware. To
achieve this, the digital portion of the BIST was generated using the C program,
56
MSBISTGen.exe, discussed in this chapter. This digital portion of the BIST was then
synthesized within a Spartan3 Field Programmable Gate Array (FPGA) manufactured by
Xilinx. However, these FPGAs lack any analog components making it impossible to
implement the complete BIST in one digital IC. Because the FPGA contains only the
digital portion of the BIST design, a Printed Circuit Board (PCB) was developed
containing the necessary analog components including the DAC, ADC, analog
multiplexor, and sample DUT to interface to the FPGA. The completed mixedsignal
BIST assembly is shown in Figure 315.
Figure 315: Image of Completed Analog Testing Printed Circuit Board Connected to the
Spartan3 FPGA.
Spartan  3 FPGA Board Analog Testing Board
57
This completed assembly was then used to test the performance of the sample
DUT located on the PCB. This DUT consisted of two separate parts. The first element in
the DUT was that of a tunable lowpass filter, where the cutoff point can be modified. The
second element was a tunable common collector amplifier where supply voltage can be
modified to clip the peaks of the waveform and introduce signal distortion. The original
design goal of this mixedsignal BIST was to be able to measure the frequency response,
linearity, and noise margins of an analog device. Using these two tunable parts of the
DUT, it is possible to compare each of these measurements taken by the mixedsignal
BIST to those expected by simulation and measurement with external equipment.
To communicate with the mixedsignal BIST, the MSBISTGen.exe program
placed a Serial Peripheral Interface (SPI) bus within the model to serially stream results
out of the BIST circuit and test setup information into the BIST circuit. Using this SPI
interface and a computer which can communicate over this interface, a simple program
was written to serially stream test information and collect test results for this BIST.
The first of these desired tests is that of the frequency response. Of the two parts
of the DUT on the analog PCB, the tunable first order low pass filter has a known
frequency response. Using the mixedsignal BIST to measure a range of distinct
frequency points, the frequency response of the DUT was measured for different cutoff
points of the tunable filter. The results of this measurement are shown in Figure 316.
Ten frequency response plots obtained from the measurements by the mixedsignal BIST
model are superimposed in this figure. These results show that as the cutoff point is
moved to a higher frequency in each successive test, the mixedsignal BIST accurately
58
detects the change in response. In addition, these response curves match the expected
response from simulation with a 20dB/decade slope after the cutoff point.
Figure 316: Frequency Response Measurement of the DUT from by the MixedSignal
BuiltIn SelfTest
The second measurement of interest for the mixedsignal BIST is that of the
linearity measurement. To obtain the linearity measurement, the BIST model will
generate two tones through the DUT, specifically a common collector amplifier, which is
designed to cause distortion. The BIST will then measure the signal strength of one of the
two generated tones and the signal strength at the third order intermodulation frequency.
The difference between these two tones represents the ?P component in the linearity
measurement. Using the tunable amplifier, the linearity of the device was swept between
the extremes of very linear to nonlinear. These measurements can be observed in Figures
317 and 318, respectively.
Mag
nitu
de
(dB)
Frequency (Hz)
59
Figure 317: Linear Response from DUT Measured by the MixedSignal BIST.
Figure 318: NonLinear Response from DUT Measured by the MixedSignal BIST
Fundamental Tone f2 Fundamental Tone f1
f1+ f2
Background
Noise
Intermodulation
Distortion
f2 f1
Intermodulation
Distortion
Mag
nitu
de
(dB)
Mag
nitu
de
(dB)
Frequency (Hz)
Frequency (Hz)
60
In Figure 317, a linearity measurement is observed through the DUT. In this plot,
the two generated tones, f1 and f2, can clearly be observed in the center of the image. The
next strongest observable point is the frequency at the summation the summation of these
two tones, f1+f2. No observable Intermodulation Distortion is seen in this plot. Figure 3
18 represents a measurement through a nonlinear DUT. In this measurement, signals f1
and f2 can still be seen in the plot; however, the plot is saturated with distortion at the
points of intermodulation between the fundamental tones. The mixedsignal BIST model
was used to sample many varying degrees of nonlinear by measuring the difference in
signal strength between the fundamental and third order intermodulation term. Table 33
shows a sampling of these measurements. To verify that these measurements were
accurate, these tests where simultaneously measured using an Agilent 4395A spectrum
analyzer.
Table 33: Linearity Measurement Comparison of MixedSignal BIST Model and
Spectrum Analyzer
Sample # BIST Measurement Spectrum Analyzer Measurement Difference
1 13.033 dB 13.08 dB 0.047 dB
2 13.110 dB 13.14 dB 0.03 dB
3 13.365 dB 13.4 dB 0.035 dB
4 13.845 dB 13.87 dB 0.025 dB
5 14.590 dB 14.55 dB 0.04 dB
6 16.103 dB 16.12 dB 0.017 dB
7 19.083 dB 19.07 dB 0.013 dB
8 24.219 dB 24.15 dB 0.069 dB
9 27.217 dB 27.01 dB 0.207 dB
10 30.321 dB 29.8 dB 0.521 dB
11 31.950 dB 31.25 dB 0.7 dB
12 36.024 dB 34.9 dB 1.124 dB
61
The final measurement of interest for the mixedsignal BIST is that of the Signal
to Noise Ratio (SNR) and the Noise Figure (NF). To produce this test a single fixed tone
was generated and the mixedsignal BIST measured the signal strength at many noise
points and again at the generated tone. By taking the difference in the generated tone and
average noise measurement, the SNR can be obtained. If this SNR measurement is also
performed while bypassing the DUT, the NF can be obtained from the difference between
the two SNR measurements. In Figure 319, an SNR measurement obtained from data
collected from the ORA of the BIST shows a 44dB SNR measurement was obtained
during the measurement of the DUT. Additionally, the mixedsignal BIST was used to
perform multiple SNR measurements. Each measurement was recorded and compared to
an SNR measurement obtained from an Agilent 4395A spectrum analyzer. The
comparison between these measurements can be seen in Table 34.
62
Figure 319: Signal to Noise Ratio Measurement from Data Collected from the Mixed
Signal BIST.
Table 34: SNR Measurement Comparison of MixedSignal BIST Model and Spectrum
Analyzer
Sample # BIST Measurement Spectrum Analyzer Measurement Difference
1 32.45 dB 32.78 dB 0.33 dB
2 34.57 dB 34.97 dB 0.4 dB
3 36.98 dB 36.15 dB 0.83 dB
4 38.91 dB 38.21 dB 0.7 dB
5 41.34 dB 40.38 dB 0.96 dB
44 dB
Generated
Tone
Background
Noise
Frequency (Hz)
Mag
nitu
de
(dB)
63
Chapter Four
InCircuit Calculations of Analog Characteristics
The primary purpose of a BuiltIn SelfTest system is to test a circuit component
for faults to verify that the device is operating properly. This chapter focuses on additions
to the originally proposed mixedsignal BuiltIn SelfTest model to further aid in
performing fault testing onchip. These additions include the development of digital
components to interpret the accumulated results of the Output Response Analyzer into a
magnitude and phase measurement as well as perform analog measurements onchip.
These new designs were implemented mainly to provide a rapid analysis of onchip
analog measurements within the mixedsignal BuiltIn SelfTest model. A secondary goal
of these designs was to provide a flexible model that can easily be parameterized.
4.1 BuiltIn SelfTest OnChip Calculation Circuit
In the current mixedsignal BIST model, the ORA captures results from each
measurement by multiplying the measured waveform by the inphase and outofphase
waveform components of the frequency of interest and then accumulates the results. This
obtains the accumulated values of the inphase and outofphase components of a given
frequency within the originally measured waveform. These values contain the relative
phase and magnitude information necessary to evaluate tests such as linearity, noise
64
measurement, and frequency response. However, the form they are in at the output of the
ORA does not allow these measurements to be directly evaluated for these tests. To
obtain magnitude and phase information from these two extracted ORA components, DC1
and DC2, an additional component in the BIST architecture will be necessary.
Presented in Chapter 2 are three methods to calculate the magnitude from the
ORA?s results. Of these three methods, this thesis utilizes the approach for calculating the
magnitude using the square root of the summation of the squares of the inphase and out
ofphase components to obtain the magnitude of the measured signal strength. To
perform the calculation, an additional circuit component which utilizes the Coordinate
Rotation Digital Computing (CORDIC) algorithm was designed. This CORDIC
technique can be used to calculate a variety of mathematical operations, including the
square root of the summation of squares. To perform each computation the CORDIC
approach utilizes a system of shift and add or shift and subtract operations to calculate the
result of the operation in accordance with the unified CORDIC model. Additionally the
CORDIC approach can be used to extract the relative phase measurement of the
measured waveform in a method similar to how the magnitude is extracted from the in
phase and outofphase components.
Once the CORDIC Calculation Unit (CCU) has extracted the magnitude
information from the DC1 and DC2 terms, the resulting magnitude can be used to
calculate the results of a variety of analog tests. The primary tests of interest in this
mixedsignal BIST design are linearity, noise, and frequency response.
To perform a linearity test, two tones are generated simultaneously, and the
Intermodulation Distortion (IMD) between these tones is measured. To measure the IMD,
65
the signal strength between one of the fundamental tones, f2, is compared to that at the
Third Order Intermodulation (IM3) point at 2f2f1. The ratio of these two signal strengths,
?P, represents our measurement of linearity. From this measurement, a variety of
abstractions about the linearity of the system, as shown in Chapter 2, can be derived. To
implement this mathematical comparison in hardware, it is necessary to divide the signal
strength of the fundamental tone by that of the IM3 tone to obtain ?P. To express ?P in
decibel, as it is usually shown, the result can be expressed as shown in Equation 41.
??(??) = 20 ? log10 ?????? ????????(?2)?????? ???????? (2?
2 ??1)
To perform a noise measurement, a single tone is generated and passed through
the DUT. The signal strength of the tones in the noise regions can then be extracted using
the CCU and averaged. To average these signals an accumulator can be used to collect
each measurement, and a divider can be used to divide by the number of samples
collected from this accumulated value. The next step in obtaining a noise measurement is
to measure the signal strength of the originally generated tone. This is achieved using the
CCU to interpret the response from the ORA. By taking the ratio between the power in
the fundamental tone and the average power in the noise measurements, the Signal to
Noise Ratio (SNR) can be obtained. This is expressed in Equation 21.
To perform the frequency response test for either phase or magnitude, the
frequency of interest must be swept over multiple tones, making multiple measurements.
Unlike linearity and SNR measurements, there is no single answer to frequency response.
Instead the result is a list of distinct measurements typically expressed as a plot. To that
end, the CCU is capable of extracting the relative phase and magnitude from each ORA
66
measurement for the generated signal strength. Each measurement can then be collected
from the CCU individually for either phase response or magnitude response of the DUT.
This entire approach can be summarized into one digital model. This can be
constructed using a single divider, two accumulators, and two multiplexers in conjunction
with the CCU. This model is illustrated in Figure 42. The divider provides two main
functions. The first operation the divider can perform is to divide a current magnitude
measurement from the CCU by a previous measurement. This is essential to perform a
comparison between tones in the linearity test, SNR measurement, and magnitude
response. The second operation the divider provides is the ability to average the noise
measurements in the SNR test by dividing the accumulated noise by the number of noise
samples collected. The first accumulator accumulates each noise measurement magnitude
as well as any past magnitude measurements, while the second accumulator records the
number of noise samples collected. However, unlike the magnitude value, obtaining a
summation of the noise phase has little statistical information about the performance of
the system. Therefore, it is not necessary to perform the heavy calculations to obtain
average noise phase as the proposed circuit does for magnitude. The extracted phase
information is, however, necessary for finding the phase of a specific signal of interest.
The remaining multiplexors can be used for controlling the data path. An additional
component, the Logarithmic Translation Unit, is used to express the final test results in
decibels.
67
Figure
4
1: C
ompl
ete I
nC
irc
uit
Te
st C
alcula
tor U
sing C
ORDI
C C
alcula
tion Unit
MULTIPLEXER
CORDI
C
Ca
lcula
tion
Unit
(CCU)
DC
1
DC
2
DIVIDER
Te
st C
ount
Ac
cumul
ator
Pha
se
Magn
itude
MULTIPLEXER
?1?
Loga
rithm
ic
Tr
anslati
on
Unit
TC
TC
TC
Re
sult
Ac
cumul
ator
TC
MULTIPLEXER
TC
Te
st
Re
sult
Te
st
Re
sult
(dB)
TC
68
4.1.1 Coordinate Rotation Digital Computing Calculation Unit
The general relationship between the values in the ORA and desired magnitude
and phase measurement can be summarized as shown in Equations 42 through 44.
??? ?????? = ??1 + ???2 = ??2 cos ? + ??2 sin?(?)
????????? = ??12 + ??22
????? = tan?1 ??2??
1
Performing these operations in hardware can prove to be a difficult challenge,
especially for models that can be parameterized or utilize large signals. Even
implementing an inverse tangent LookUp Table (LUT) for two 32bit DC terms would
consume a very large amount of area overhead. Therefore, an alternative to traditional
implementation methods is needed to efficiently calculate the magnitude and phase.
The Coordinate Rotation Digital Computing (CORDIC) algorithm is used in
many applications to perform basic mathematical functions and has been used in many
pocket calculators since the Hewlett Packard HP 35 and within processors since the Intel
8087 [29]. In this thesis, the CORDIC algorithm will find a different application in signal
processing. The CORDIC algorithm will be used to construct a physical circuit to
transform the output of the Selective Spectrum Analysis (SSA) based ORA into the
magnitude and phase measurements required to evaluate the results of the three desired
analog tests: linearity, frequency response, and noise measurement.
This relationship between the ORA outputs, magnitude, and phase can be
represented graphically as depicted in Figure 42. DC1 and DC2 can be depicted on the
unit circle as two orthogonal vectors. The vector addition of these two DC terms will
(42)
(43)
(44)
69
result in a new composite vector. The length of this new vector represents the magnitude,
while the phase is depicted as the angle from DC1?s vector to the composite vector.
Because these values can be expressed in terms of the unit circle, the circular CORDIC is
able to convert between these expressions for the DC terms, magnitude, and phase.
To transform the inphase and outofphase components, DC1 and DC2
respectively, of the ORA into the magnitude value shown in Equation 43, the square root
of the summation of squares operation needs to be applied to the values of DC1 and DC2.
To achieve this operation the circular CORDIC needs to be modified slightly from the
example listed in Chapter 2. Rather than attempting to find the magnitude for a fixed
angle, the square of the sum of squares circular CORDIC will allow variable values to be
loaded into the two XY coordinates so the starting angle is set. Then the component
DC1
DC2
Phase
Magnitude
Figure 42: CORDIC Relationship on Unit Circle
70
values will be rotated in the CORDIC model until the Yaxis value approximates zero.
This leaves the Xaxis value as the approximation of the magnitude.
As observed in Figure 43, the red line represents true magnitude of the Xaxis
value and Yaxis value together. As the Yaxis value, represented by the blue line, begins
to shrink away, the Xaxis value has to grow to keep a constant magnitude. When the Y
axis value become significantly small, the Xaxis value can be said to approximate the
actual magnitude.
The first step in the square of the sum of squares CORDIC is to load the starting
values of DC1 and DC2 into two registers within the model. Based on the sine values of
DC1 and DC2, the quadrant of the unit circle which the vector answer will be in can be
established. However, this circular CORDIC algorithm requires that vector rotation
begins at angle 0?. Therefore to rotate the vector to the correct starting place, the
Register I and Register Q are loaded under the given conditions shown in Equations 45
and 46.
Figure 43: Illustration of CORDIC Rotational Procedure Minimizing YAxis Value
to Maximize Xaxis Value
71
???????? ? = ??1, ?? ??2 ?? ???????????
1, ?? ??2 ?? ????????
???????? ? = ???2, ?? ??2 ?? ??????????
2, ?? ??2 ?? ????????
Once the registers have been loaded, the CORDIC will begin the successive
approximation process to obtain the correct magnitude. For the first iteration of this
approximation Register I will have the absolute value of Register Q added to it, while
Register Q will be updated to contain the absolute value of Register Q with the value of
Register I subtracted away. Because of the conditional loading in the first step of this
CORDIC calculator, the value in Register I now contains the magnitudes of DC1 +DC2
added together. This is however not the square root of the sum of squares, but the
CORDIC?s first approximation towards that goal. On the following iterations, the values
of Register Q and Register I are combined again to their complement register, however
the values to be added are shifted right by N1 bits before the addition, where N
represents the iteration number in the CORDIC model. These iterative steps will follow
the form in Equations 47 and 48. For each successive iterative step, the value in
Register I will always be positive and continue to increase as it begins to approximate the
value of the square root of the sum of squares. The value in Register Q represents the
relative overshoot in the CORDIC calculation. For each iteration, the magnitude of the
value in Register Q will continue to decrease toward zero as Register I becomes more
precise.
???????? ? = ???????? ? + ??? ???????? ? ? [? ? 1]
???????? ? = ???(???????? ?) ? ???????? ? ? [? ? 1]
(45)
(46)
(47)
(48)
72
The end result is an approximation of the square root of the sum of squares of
DC1 and DC2 stored in Register I. This resolves the issue of generating the magnitude;
however, another needed calculation is the phase of the signal. In reality, the calculation
through the CORDIC process to obtain the magnitude coincidently generates the phase
rotation information.
Unlike Register I, which is always positive and always increasing, Register Q will
contain signed numbers and is always decreasing in magnitude. The sign value of
Register Q at each iteration correlates to the direction of phase change that will be added
to the current approximation to express the angle of the resulting waveform. The actual
value of phase information added in each iteration is a function of the iteration number
rather than the values in Register I and Register Q. If Register Q contains a positive
value, this means that the resulting waveform has overshot its goal and needs to reduce
the value of phase. The next phase increment will be subtracted from the current
approximation in this case. A negative value for Register Q indicates the phase value is
too small and needs the next phase value to be added to it. This change in phase for each
iteration is expressed in Equation 49.
????? ? = ????? ? ? 1 ? sign Register Q ? tan?1( 12??1) (49)
The only relevant information of importance for obtaining the direct calculation
of phase in each is the sign value, or Most Significant Bit (MSB), of Register Q in each
iterative step. This bit can be stored within its own separate phase register during the
iterative process of calculating the magnitude. The final value of the phase register is
capable of expressing any value from 180? to +180?. A LUT can even be implemented,
if needed to translate the arctangent encoded value into a decimal format. Equation 49
73
can also substitute for the formula for translating between the phase register and decimal
phase value in a LUT. Table 41 shows an example of a CORDIC unit running for ten
iterations and obtaining ten phase bits. The complete model for the CORDIC Calculation
Unit is illustrated in Figure 44.
Table 41: CORDIC Calculation Unit Phase Bits Weight for First Ten Phase Bits
Iteration Generated Phase Bit Bit Weight
1 MSB 90.0000?
2 MSB1 45.0000?
3 MSB2 26.5651?
4 MSB3 14.0362?
5 MSB4 7.1250?
6 MSB5 3.5763?
7 MSB6 1.7899?
8 MSB7 0.8952?
9 MSB8 0.4476?
10 MSB9 0.2238?
74
Mag
nitu
de
DC1
Te
rm
DC2
Te
rm
CORD
IC
CON
TRO
LLER
Ph
ase
Register
I
Register
Q
1 1
>>N
>>N
Figure
4
4: Ill
ustra
tion of
C
irc
ular
C
ORDI
C C
alcu
lation Unit
75
This basic model suffers from two drawbacks. In this model of the CORDIC, each
iterative step must shift, a variable amount, the values in Register I and Register Q then
add them together. The first hindrance is that this model requires barrel shifters to be able
to implement this selective shift length for the shift and add process. An Nbit barrel
shifter would require N flipflops and N, Nto1 multiplexers to implement. This
represents a large amount of area overhead to implement for mixedsignal BIST systems
which are accumulating large values of DC1 and DC2, such as 32 bits and larger. To
resolve this issue, the model can be pipelined to break apart the barrel shifting operation
into N, 1 bit shift operations for each iteration. A simple counter can be used to keep
track of the number of shifts.
The second problem with the implementation of a CORDIC is speed of
calculation. The CORDIC model requires multiple clock cycles to complete the multiple
iterations required to obtain the result. The standard model only requires one clock cycle
per iteration, but by pipelining the shifting operation to remove the need for barrel
shifters, now multiple clock cycles are needed for each iterative step. This increases the
number of clock cycles required to obtain a valid result. However, once the CORDIC has
begun calculating a measurement of the magnitude and phase, the data is latched into the
circuit and no longer need to be held at the input. This can allow the ORA to capture the
measurement for the next frequency while the CORDIC circuit simultaneously extracts
magnitude and phase of the previous measurement. In addition, because the model has
been pipelined, the maximum allowable clock frequency has been increased allowing the
CORDIC to operate at a faster clock rate.
76
As with all CORDIC models, each iterative step introduces a moderate amount of
error into the measurement. This error is fixed, based on the number of iterations the
CORDIC takes to calculate the result and only skews the magnitude result. The error in
each step is given in Equation 229. However, because each of the desired tests of
linearity, frequency response, and noise measurement requires at least two measurements
to be directly compared to each other, this error factor cancels in each test.
4.1.2 Translation of Magnitude Value to Decibels
The final result of the CORDIC calculation unit returns the magnitude and phase
used in each test. However, these results are in an atypical format. Typically,
measurements of signal strength difference, ?P from the linearity test, magnitude
response, and SNR are all given in the logarithmic units of decibels, dB. The results
returned from the CORDIC calculation unit are in a nonlogarithmic, linear format for
amplitude. To simply evaluate the results of the test, the returned responses need to be in
a decibel format.
The conversion between linear and logarithmic can be implemented within a
single LUT. However, large values of magnitude will result in very large LUTs. There is
a logarithmic CORDIC algorithm, discussed in Chapter 2, designed specifically to
implement this conversion. However the area overhead required to construct a
logarithmic CORDIC outshadows its usefulness in smaller applications. To express
these units in decibels a modified linear CORDIC can be used in place of the logarithmic
CORDIC algorithm. The linear CORDIC consumes less resources than the logarithmic
CORDIC allowing it to be efficiently implemented in transformation approximations.
77
This linear CORDIC block, referred to as the Logarithmic Translation Unit in
Figure 41, in the test calculation circuit?s design will take a linear magnitude value and
reexpress this value in the form of Equation 410.
?????? = 20 ? log10(?????) (410)
This CORDIC procedure operates on a simpler shift and subtract principle than
the CORDIC Calculation Unit. This modified linear CORDIC operates on the
approximation that each binary power of two can be represented in decibel by Equation
411.
20 ? log10 2? = ? ? 6.0206?? (411)
By finding the highest order power of two, the logarithmic value can be
approximated to within 6.0206dB. However, a range of 6.0206dB represents a large
amount of error in the measurement. To scale the error down, a correction factor can be
added to the approximation. This is represented in Equation 412. This correction factor
will utilize the remaining bits below the largest one bit to further improve accuracy.
These lower bits can be represented by fractional addition to the current logarithmic
approximation. A small LookUp Table can be used to implement this addition by
observing the values on the next four bits below the highest one bit. The values that will
be entered into the LookUp Table are expressed in Equation 413.
????????????? = 20 ? log10 2? + ?????????? ?????? (412)
??? ????? ? = 20 ? log10(1 + ?16) (413)
78
To obtain this logarithmic value, the CORDIC will begin by loading the INPUT
value into one register as it did with the previous CORDIC, while the other register is
preloaded with the maximum possible logarithmic value expressible by the Nbit INPUT
value. The largest possible number expressed by a power of two as the INPUT register is
shown in Equation 414, where N represents the size in bits of the INPUT register. This
CORDIC?s approach is to shift through each bit of the INPUT register from the MSB
down to the LSB, until it locates the first bit with the value of one. For each shift
operation performed the CORDIC will subtract the value of approximately 6 dB from the
second register, which was preloaded with the maximum possible value. Once a bit with
the value of one is located, the next four bits in the INPUT register are passed through a
small 4bit LookUp Table. This LUT value is then added to the second register
containing the current approximation for the decibel value. The result is a very small
logarithmic approximation unit consisting of one subtractor unit, one adder unit, and a 4
bit LUT. The model for the Logarithmic Translation Unit is illustrated in Figure 45.
??????? ???????? ????? = ????(20 ? log10 2??1 ? 1) (414)
79
Maxi
mu
m
Val
ue
(Co
nstant
)
Lo
gari
thm
ic
Ap
pro
xim
atio
n
Register
Lo
gari
thm
ic O
utpu
t
Mag
nitu
de
Lo
gari
thm
ic
Tran
slatio
n Co
ntr
oll
er
Mag
nitu
de
Register
>>
1
Lo
ok
Up
Tabl
e
Figure
4
5: Ill
ustra
tion of
Loga
rithm
ic Tr
anslati
on
Unit
80
4.2 BuiltIn SelfTest Implementation Test Results
To experimentally verify the operation of this BIST approach using the onchip
calculator, the proposed model was synthesized and programmed onto a Xilinx Spartan 3
S1000 Field Programmable Gate Array (FPGA). Then each of the three required tests
was performed and their results measured. The following section highlights the findings
of these tests.
The first test of interest was the frequency response measurement. The results of
this measurement are depicted in Figure 46. The blue plot represents the measurement of
the offchip calculations, while the red plot represents the onchip calculation, and black
represents the measurements obtained by a spectrum analyzer. This test requires many
data points to be measured. By extracting values directly from the output of the CCU,
rather than the output of the logarithmic translation unit, a more accurate answer can be
obtained for this test to avoid any rounding that occurs in the division process and
conversion to logarithmic format.
The results obtained show that the difference between the calculation of the on
chip and offchip measurements differ by less than one tenth of a decibel in this example.
Both of these measurements differ by less than two tenths of a decibel from the actual
frequency response recorded by the spectrum analyzer. This shows that the CCU which is
generating the magnitude is properly producing magnitude measurements onchip. A
similar comparison between the calculated phase performed offchip, using the method
elaborated upon in Chapter 2, and the phase reported by the CCU can be performed.
81
Figure
4
6: P
lot
of Fre
que
nc
y R
esponse U
sing On
C
hip and O
ff
Chip C
alc
ulations
for
Mag
nit
ude

5

4
.
5

4

3
.
5

3

2
.
5

2

1
.
5

1

0
.
50
0.1
0.6
1.1
1.6
2.1
2.6
3.1
3.6
4.1
4.6
5.1
5.6
6.1
6.6
7.1
7.6
8.1
8.6
9.1
9.6
10.1
10.6
11.1
11.6
12.1
12.6
13.1
13.6
14.1
14.6
15.1
15.6
16.1
16.6
17.1
17.6
18.1
18.6
19.1
19.6
Manituge Response (dB)
Fr
e
que
nc
y
(
k
H
z
)
Fr
equ
ency
R
es
p
o
n
s
e
Mea
s
u
r
ed
t
h
r
o
u
g
h
O
f
f

C
h
i
p
a
n
d
O
n

C
h
i
p
Met
h
o
d
s
O
ff

c
h
ip
C
a
lc
u
la
t
io
n
On

c
h
ip
C
a
lc
u
la
t
io
n
Sp
e
c
t
r
u
m
A
n
a
ly
z
e
r
82
This second test result illustrates a comparison of the linearity ?P measurement
obtained by the proposed circuit in this chapter plotted against the same test results
calculated offchip using the ORA results. These results are shown in Figure 47. This
test utilizes the same color palette to express the plots taken as the frequency response
measurement. Represented in red is the result of the onchip calculation circuit,
represented in blue is the calculation performed offchip, and represented in black is the
correct measurement as recorded by an external spectrum analyzer. Both plots of onchip
and offchip calculation follow the same trend line and approximate the correct
measurement. At higher linearity measurements, the measured IM3 tones become too
weak to properly measure with small ADCs in the mixedsignal BIST model. This results
in deviation from the measurement obtained by the spectrum analyzer at high linearity
measurements.
83
05
101520253035404550
0
5
10
15
20
25
30
35
40
45
50
Spectrum Analyzer Obtained Measurements
B
I
S
T
O
bt
a
i
ne
d
M
e
a
s
ur
e
m
e
nt
s
L
i
n
e
a
r
i
t
y
R
e
s
u
l
t
s
For
O
n

chi
p
V
s
O
f
f

chi
p
A
n
a
l
y
s
i
s
O
ff

C
h
ip
C
a
lc
u
la
t
io
n
On

C
h
ip
C
a
lc
u
la
t
io
n
Sp
e
c
t
r
u
m
A
n
a
ly
z
e
r
Figure
4
7: P
lot
of L
inea
rity ?P R
esult
s for
On
C
hip and O
ff
Chip Te
st C
alcula
tions
84
There are two minor differences between these two plots. The first difference
occurs in the lower range of measurements from 20dB and below. The results in this
range represent a measurement and division by two numbers which are very close in
magnitude to each other. This hardware model operates on integer values and cannot
perform floating point calculations as the offchip calculation does; because of this, some
information about the signal difference is lost during the division.
Another potential source for error in this range is the translation process into the
logarithmic decibels. Because the logarithmic translation circuit?s input is an integer
number, there are decibel values which cannot be achieved due to rounding. The first
nonzero response from the logarithmic translation circuit occurs when the input has a
value of two, this equates to an output of 6dB, making values 15dB not expressible due
to the rounding. However, for larger inputs, the logarithmic translation circuit can display
the correct decibel approximation. The seven smallest input values to the Logarithmic
Translation Unit are shown in Table 42. This table illustrates how smaller inputs have
increasingly larger inexpressible range between steps when compared to larger inputs.
Table 42: Small Value Measurements on the Input of the Logarithmic Translation Unit
Input Value Output Value (dB)
1 0 dB
2 6 dB
3 10 dB
4 12 dB
5 14 dB
6 16 dB
7 17 dB
The second difference becomes more noticeable in the higher range, but occurs
throughout the plot. Because the output of the logarithmic translation circuit can only be
85
expressed as integer decibels, the maximum accuracy of the output can only be
guaranteed to be within 1dB of the intended measurement. As observed in the onchip
result, each of the outputs is within 1 dB of the offchip calculation.
The final test of interest represents a measurement of the Signal to Noise Ratio
(SNR) of the system. Using this CCU to calculate the magnitude of multiple noise
measurements and a simple accumulator and divider to average these noise
measurements, the SNR can be obtained. When the measurements obtained by an off
chip calculation using only the ORA results are compared to the measurements obtained
by the onchip calculator, the results appear close. Small deviations are present in the
measurements due to rounding and averaging.
86
Chapter Five
Summary and Conclusions
This thesis discussed a method of testing the performance of analog circuits in
mixedsignal integrated circuit using a BuiltIn SelfTest approach presented in [4][12].
This approach utilizes selective spectrum analysis to isolate and capture particular
frequency components of a measured analog waveform to be analyzed. To evaluate the
performance of an analog device the BuiltIn SelfTest approach implemented three tests:
linearity to evaluate the intermodulation distortion, frequency response to evaluate the
relative magnitude and phase shift within the operational range, and noise figure to
determine the signal degradation due to the analog circuit.
5.1 MixedSignal BuiltIn SelfTest Improvements
A number of improvements to the mixedsignal BuiltIn SelfTest design were
presented in this thesis. The first improvement to this design was the introduction of a
method to automatically generate the hardware description language model, given a set of
user definable parameters. These parameters can be used to match system requirements to
generate a specific hardware model for a specific implementation. This program allows a
developer the ability to selectively tradeoff performance for area overhead.
To generate a waveform, the test pattern generator utilizes a direct digital
synthesis approach. This requires a numerically controlled oscillator to generate the
87
waveform from a phase accumulator. This is typically performed with waveforms stored
in lookup tables. The improvement to the mixedsignal BIST encodes only one quarter
of a complete waveform, as opposed to the entire waveform, to generate the output. This
compresses the required area of the lookup table by seventyfive percent as opposed to
NCOs which encode the entire table, while adding only minor decoding hardware to
reconstruct the full waveform.
Most hardware description languages lack the trigonometric functions necessary
for expressing a sinusoidal waveform. This is a necessary component in the generation of
the NCO in the TPG. An additional feature of the automatic generation of the mixed
signal BIST is the ability to automatically generate the lookup tables that comprise the
NCOs to the size of the model. This program takes advantage of the trigonometric
functions built into the standard C programming language libraries and reexpresses the
output within a VHDL file format. This implements a customized sinusoidal lookup
table in VHDL without needing VHDL operations for trigonometric functions.
A further improvement to the Direct Digital Synthesis based Test Pattern
Generator to improve spurious noise was presented. This improvement involved the
replacing the traditional accumulators used in the DDS design with a modified Nicholas
accumulator. These new accumulators act to dither the accumulated phase used in
generating the output waveform. This can reduce the effect of quantized noise, spurious
tones, and image tones generated unintentionally by the DDSbased TPG in the mixed
signal BIST. This is performed by spreading the noise of the few strong spurious tones
into many small signal noise tones. The program treats this new accumulator as an
88
optional replacement to the model allowing the developer to decide if it should be
generated within the design.
Additional improvements to the mixedsignal BIST approach were made in the
selective spectrum analysis based output response analyzer. Because the ORA consists
only two pairs of multipliers and accumulators, there is little to be improved upon.
However, for this implementation of the mixedsignal BIST, a new multiplier was
introduced which improves in the speed of calculation. This multiplier was based on the
modified Booth multiplier architecture, which reduces the number of partial products in
half. This was further optimized for speed and area by structuring the partial product
addition stages using the Wallacetree reduction technique. Then a new approach for
reducing the sign extension bits of the partial products was implemented into the
multiplier design. Finally, this multiplier was pipelined to greatly improve the speed of
the calculation.
5.2 MixedSignal BuiltIn SelfTest Additions
The originally proposed mixedsignal BIST model is capable only of extracting
the inphase and outofphase components of a measured signal. These components are
necessary for evaluating onchip performance; however the format these components are
in is not conducive for calculating the onchip measurements. To convert these two
components into the magnitude and phase of the measurement, a new addition to the
mixedsignal BIST model was employed.
Utilizing the Coordinate Rotation Digital Computing algorithm, a new component
to the model was constructed which allowed the mixedsignal BIST to calculate the
89
components of magnitude and phase from the ORA output. This model utilized an
iterative successive approximation approach to obtain the accumulated magnitude of the
signal of interest. In the processes of obtaining the magnitude, the iterative rotational
aspect of this CORDIC method also obtains the phase. When combined with additional
circuitry, the output of this unit allows for the analog measurements and tests to be
evaluated onchip. Utilizing additional features of the CORDIC algorithm, a logarithmic
translation circuit was constructed to convert the linear amplitude measurement obtained
by the calculation CORDIC into a logarithmic decibel format. This simplifies the final
result and facilitates onchip measurement.
5.3 Areas for Future Research and Development
It is recommended that improvements be made to reduce the overall area of the
test calculation circuit. When compared to the area of the ORA, the current test
calculation circuit represents a significant increase in area. Further improvements should
be made to CORDIC Calculation Unit to increase the calculation speed. At present, the
CCU represents the longest register to register delay in the entire mixedsignal BIST
model. Improving this component in the design will increase the maximum operating
speed of the entire mixedsignal model.
After a reduced test calculation circuit has been finalized, this new entity should
be integrated into the automatic mixedsignal BIST generation program along with any
userconfigurable options associated with the entity. Additional improvements can be
made to the automated BIST generation program. Currently, the automated mixedsignal
BIST generation program generates a communication interface length specific to the
90
implementation of that particular model. This forces the designer using the generator to
develop a custom communication interface independently. An improvement to the BIST
generator would be to export information about the contents of the communication
interface to aid in the development of a communication interface.
91
Bibliography
[1] R. C. Jaeger, Introduction to Microelectronic Fabrication. Upper Saddle River:
Prentice Hall, 1998.
[2] C. H. Stapper, "LSI Yield Modeling and Process Monitoring," IBM J. Res. Develop.
vol. 20, no. 3, pp. 228234, 1976.
[3] C. E. Stroud, A Designer?s Guide to BuiltIn SelfTest. Boston: Springer, 2002.
[4] J. Qin, C. E. Stroud and F. F. Dai, ?FPGABased Analog Functional Measurements
for Adaptive Control in MixedSignal Systems,? IEEE Trans. on Industrial
Electronics, vol. 54, no. 4, pp. 18851897, 2007.
[5] J. Qin, C. E. Stroud and F. F. Dai, ?Phase Delay Measurement and Calibration in
BuiltIn Analog Functional Testing,? Proc. IEEE Southeastern Symp. on System
Theory, pp. 145149, 2007.
[6] F. Dai, C. Stroud, C. Yang and S. Qi, ?Automatic Linearity (IP3) Test with BuiltIn
Pattern Generator and Analyzer,? Proc. IEEE International Test Conf., pp. 271
280, 2004.
[7] F. F. Dai, C. E. Stroud, and D. Yang, ?Automatic Linearity and Frequency Response
Tests With BuiltIn Pattern Generator and Analyzer,? IEEE Trans. on Very Large
Scale Integration (VLSI) Systems, vol. 14, no. 6, pp. 561572, 2006.
[8] D. Yang, C. E. Stroud and F. F. Dai, ?BuiltIn SelfTest for Automatic Analog
Frequency Response Measurement?. Proc. IEEE International Symp. on Circuits
and Systems, pp. 22082211, 2005.
[9] J. Qin, C. E. Stroud, and F. F. Dai, ?Noise Figure Measurement Using MixedSignal
BIST,? Proc. IEEE International Symp. on Circuits and Systems, pp. 21802183,
2007.
[10] C. E. Stroud, D. Yang and F. F. Dai, ?Analog Frequency Response Measurement in
MixedSignal Systems,? Proc. IEEE International Symp. on Circuits and Systems,
pp. 57365739, 2006.
[11] J. Qin, C. E. Stroud and F. F. Dai, ?Test Time of Multiplier/Accumulator Based
Output Response Analyzer in BuiltIn Analog Functional Testing,? Proc. IEEE
Southeastern Symp. on System Theory, pp. 363367, 2009.
[12] J. Qin, C. E. Stroud, and F. F. Dai, ?Phase Delay in MACBased Analog Functional
Test in MixedSignal Systems,? Proc. IEEE North Atlantic Test Workshop, pp.
4450, 2006.
92
[13] S. Qi, Foster Dai, C. E. Stroud, and D. Yang, ?Analog Circuit Testing Using BuiltIn
DirectDigital Synthesis?, Proc. IEEE North Atlantic Test Workshop, pp. 190
195, 2004.
[14] G. J. Starr, J. Qin, B. F. Dutton, C. E. Stroud, F. F. Dai and V. P. Nelson,
?Automated Generation of BuiltIn SelfTest and Measurement Circuitry for
MixedSignal Circuits and Systems,? Proc. IEEE International Symp. on Defect
and Fault Tolerance in VLSI Systems, pp. 1119, 2009.
[15] C. E. Stroud, J. R. Morton and A. Islam, ?An Automated BIST Approach for Mixed
Signal Systems,? Proc. IEEE North Atlantic Test Workshop, pp. 202209, 2004.
[16] D. K. Pradhan and I. G. Harris, Practical Design Verification. New York:
Cambridge, 2009.
[17] J. Vankka and K. Halonen, Direct Digital Synthesizers: Theory, Design and
Applications. Boston: Kluwer, 2001.
[18] E. C. Chu, Inside the FFT Black Box: Serial and Parallel Fast Fourier Transform
Algorithms. Boca Raton: CRC Press, 2000.
[19] W. L. Briggs, DFT: an Owner's Manual for the Discrete Fourier Transform.
Philadelphia: SIAM, 1995.
[20] B. Razavi, RF Microelectronics, Upper Saddle River: Prentice Hall, 1998.
[21] J. C. Pedro and N. B. Carvalho, ?On the Use of Multitone Techniques for Assessing
RF Components? Intermodulation Distortion,? IEEE Trans. On Microwave
Theory & Techniques, vol. 47, no. 12, pp. 23932402, 1999.
[22] J. Mielke, ?FrequencyDomain Testing of ADCs,? IEEE Design & Test of
Computers, vol. 13, no. 1, pp. 6469, 1996.
[23] M. Soma, S. Huynh, J. Zhang, S. Kim, and G. Devarayanadurg, ?Hierarchical ATPG
for Analog Circuits and Systems,? IEEE Design & Test of Computers, vol. 18, no.
1, pp. 7281, 2001.
[24] S. D. Huynh, K. Seongwon, M. Soma, and Z. Jinyan, ?Testability Analysis and
MultiFrequency ATPG for Analog Circuits and Systems,? Proc. International
Conf. on ComputerAided Design, pp. 376383, 1998.
[25] P. Variyam and A. Chatterjee, ?Test Generation for Comprehensive Testing of
Linear Analog Circuits Using Transient Response Sampling,? Proc. IEEE VLSI
Test Symp., pp. 6065, 1994.
[26] M. Schetzen, The Volterra and Wiener Theories of Nonlinear Systems. New York:
Wiley, 1980.
[27] R. C. Jaeger, Microelectronic Circuit Design. Boston: McGrawHill, 2008.
[28] E. E. Swartzlander, Application Specific Processors. Boston: Kluwer, 1997.
[29] J. M. Muller, Elementary Functions: Algorithms and Implementation. Boston:
Birkh?user, 1997.
93
[30] J. Qin, Selective Spectrum Analysis (SSA) and Numerically Controlled Oscillator
(NCO) in MixedSignal BuiltIn SelfTest, Doctoral Dissertation, Auburn
University, 2010.