An Experimental Evaluation of the Delta Operator in Digital Control
by
Brandon L. Eidson
A thesis submitted to the Graduate Faculty of
Auburn University
in partial ful llment of the
requirements for the Degree of
Master of Science
Auburn, Alabama
August 9, 2010
Keywords: Digital Control, Delta Operator, Finite Word-Length
Copyright 2010 by Brandon L. Eidson
Approved by:
John Y. Hung, Chair, Professor of Electrical and Computer Engineering
R. Mark Nelms, Professor and Chair of Electrical and Computer Engineering
Stanley J. Reeves, Professor of Electrical and Computer Engineering
Abstract
Interest in digital control systems has been on the rise over recent decades with the ever
decreasing cost and increasing performance of microprocessors and the academic advance-
ments in control theory. Although there are many bene ts to digital control, there are many
challenges. This study explores one obstacle presented by  nite word-length microproces-
sors: the limited range of numbers that can be represented. The goal is to compare its e ects
using two di erent discrete operators|the shift operator and the delta operator.
The experiment is designed in order to accommodate a second challenge in digital con-
trols: most engineers and technicians are far more experienced with continuous controller
design. Therefore, this analysis?s control design takes place in continuous-time. Both shift
and delta-operator-based di erence equations are derived from the continuous transfer func-
tion. The ability of each competing model to perform under  nite word-length conditions is
evaluated through mathematical analysis, simulation, and experimentation. These demon-
strations are made using a PID controller to compensate a DC-DC buck converter. It is
concluded that the delta operator representation is less susceptible to the numerical limita-
tions and shows greater performance resemblance to the original continuous compensator.
ii
Acknowledgments
Soli Deo gloria.
iii
Table of Contents
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
1 Topic Introduction and Background . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Digital Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 The Delta Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 The Focus of this Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Overview of the Delta Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 De nition of Delta Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Higher-Order Representations . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.1 Second-Order, Causal Delta Operator . . . . . . . . . . . . . . . . . . 7
2.2.2 Third-Order, Causal Delta Operator . . . . . . . . . . . . . . . . . . 8
2.2.3 In General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Stability Region Parallels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Mathematical Demonstration of Coe cient Constraints on Discrete Models . . . 12
3.1 General Mathematical Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1.1 General Transfer Function Conversion to Shift Operator Representation 12
3.1.2 Shift Operator Representation to Delta Operator Representation . . 15
3.2 Discrete Representations of a PID Controller . . . . . . . . . . . . . . . . . . 16
3.2.1 Z-Transforming the PID . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.2 The Shift Operator Di erence Equation . . . . . . . . . . . . . . . . 17
3.2.3 The Delta Operator Di erence Equation . . . . . . . . . . . . . . . . 19
iv
4 Experiment Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 Hardware and System Con guration . . . . . . . . . . . . . . . . . . . . . . 24
4.1.1 The Plant: DC-DC Buck Converter . . . . . . . . . . . . . . . . . . . 24
4.1.2 The Microcontroller: 18F PICTM . . . . . . . . . . . . . . . . . . . . 30
4.2 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2.1 Practical Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2.2 Addition/Subtraction Subroutines . . . . . . . . . . . . . . . . . . . . 35
4.2.3 Duty-Cycle Calculation: Shift Operator . . . . . . . . . . . . . . . . . 37
4.2.4 Duty Cycle Calculation: Delta Operator . . . . . . . . . . . . . . . . 40
4.2.5 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5 System Modeling and Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1 Modeling of DC-DC Buck Converters . . . . . . . . . . . . . . . . . . . . . . 45
5.2 Modeling of Analog PID Controllers . . . . . . . . . . . . . . . . . . . . . . . 54
5.3 Modeling of Non-ideal Digital Controllers in Simulink . . . . . . . . . . . . . 55
5.3.1 Shift-Based Digital PID Controller in Simulink . . . . . . . . . . . . . 56
5.3.2 Delta-Based Digital PID Controller in Simulink . . . . . . . . . . . . 57
6 Simulation and Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1 Continuous PID Controller Designs . . . . . . . . . . . . . . . . . . . . . . . 59
6.2 Discrete PID Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.2.1 Shift Operator Performance . . . . . . . . . . . . . . . . . . . . . . . 64
6.2.2 Delta Operator Performance . . . . . . . . . . . . . . . . . . . . . . . 69
7 Conclusions and Potential Future Work . . . . . . . . . . . . . . . . . . . . . . . 76
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
v
List of Figures
1.1 Block diagram of generic, continuous control system . . . . . . . . . . . . . . 2
1.2 Block diagram of generic, digital control system . . . . . . . . . . . . . . . . 2
1.3 Some digital control system weaknesses . . . . . . . . . . . . . . . . . . . . . 2
2.1 Stability region of d=dt operator . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Stability region of shift operator . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Stability region of delta operator . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Continuous PID coe cients that will not result in truncation using shift op-
erator parameterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Continuous PID coe cients that will not result in truncation using delta op-
erator parameterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Comparison of possible continuous PID coe cients without truncation occur-
ring in the shift and delta operators di erence equations, View 1 . . . . . . . 23
3.4 Comparison of possible continuous PID coe cients without truncation occur-
ring in the shift and delta operators di erence equations, View 2 . . . . . . . 23
4.1 Schematic for digitally controlled buck converter . . . . . . . . . . . . . . . . 25
4.2 An ideal buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3 Equivalent ideal buck converter with switch closed . . . . . . . . . . . . . . . 26
4.4 Equivalent ideal buck converter with switch open . . . . . . . . . . . . . . . 27
4.5 A simple voltage divider schematic . . . . . . . . . . . . . . . . . . . . . . . 28
4.6 General overview of software algorithm . . . . . . . . . . . . . . . . . . . . . 34
4.7 Subtraction when both numbers are known to be positive . . . . . . . . . . . 36
4.8 Addition of two numbers that could be either positive or negative . . . . . . 37
vi
4.9 Subtraction of two numbers that could be either positive or negative . . . . . 38
4.10 Overview of duty cycle calculation based on the shift operator . . . . . . . . 39
4.11 Overview of duty cycle calculation based on the delta operator . . . . . . . . 41
4.12 The approximate timing diagram for the shift-operator-based controller algo-
rithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.13 The approximate timing diagram for the delta-operator-based controller algo-
rithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.14 The approximate timing diagram for the overall system . . . . . . . . . . . . 44
5.1 A typical buck converter with inductor and capacitor ESRs . . . . . . . . . . 46
5.2 Non-ideal buck converter with transistor switch closed . . . . . . . . . . . . . 47
5.3 Non-ideal buck converter with transistor switch open . . . . . . . . . . . . . 47
5.4 State diagram for a buck converter . . . . . . . . . . . . . . . . . . . . . . . 49
5.5 Open-loop buck converter Simulink model . . . . . . . . . . . . . . . . . . . 51
5.6 PWM generator Simulink model . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.7 Simulink simulation of open-loop response with Vref = 2:5V . . . . . . . . . 52
5.8 Pspice schematic of open-loop buck converter . . . . . . . . . . . . . . . . . 52
5.9 Pspice simulation result of open-loop response . . . . . . . . . . . . . . . . . 53
5.10 Experimental versus simulation open-loop response . . . . . . . . . . . . . . 54
5.11 Closed-loop buck converter with continuous-time PID controller . . . . . . . 55
5.12 Closed-loop buck converter with discrete-time PID controller . . . . . . . . . 56
5.13 Simulation model of the shift-operator-based PID di erence equation . . . . 57
5.14 Block diagram of the delta operator . . . . . . . . . . . . . . . . . . . . . . . 57
5.15 Simulation model of the delta-operator-based PID di erence equation . . . . 58
6.1 Initial transient; Continuous PID; KP=50, KI=140000, KD=0.0075 . . . . . 60
6.2 Initial transient; Continuous PID; KP=70, KI=60500, KD=0.0084 . . . . . . 60
6.3 Initial transient; Continuous PID; KP=40, KI=40300, KD=0.0064 . . . . . . 61
vii
6.4 Initial transient; Continuous PID; KP=6, KI=20160, KD=0.0005 . . . . . . 61
6.5 Initial transient; Continuous PID; KP=170, KI=5040, KD=0.0127 . . . . . . 62
6.6 Initial transient; Continuous PID; KP=75, KI=2500, KD=0.0124 . . . . . . 62
6.7 Initial transient; Continuous PID; KP=300, KI=1260, KD=0.04 . . . . . . . 63
6.8 Initial transient; Continuous PID; KP=100, KI=1260, KD=0.03 . . . . . . . 63
6.9 Initial transient; shift operator PID; KP=50, KI=140000, KD=0.0075 . . . . 65
6.10 Initial transient; shift operator PID; KP=70, KI=60500, KD=0.0084 . . . . 65
6.11 Initial transient; shift operator PID; KP=40, KI=40300, KD=0.0064 . . . . 66
6.12 Initial transient; shift operator PID; KP=6, KI=20160, KD=0.0005 . . . . . 66
6.13 Initial transient; shift operator PID; KP=170, KI=5040, KD=0.0127 . . . . 67
6.14 Initial transient; shift operator PID; KP=75, KI=2500, KD=0.0124 . . . . . 67
6.15 Initial transient; shift operator PID; KP=300, KI=1260, KD=0.04 . . . . . . 68
6.16 Initial transient; shift operator PID; KP=100, KI=1260, KD=0.03 . . . . . . 68
6.17 Initial transient; delta operator PID; KP=50, KI=140000, KD=0.0075 . . . 69
6.18 Initial transient; delta operator PID; KP=70, KI=60500, KD=0.0084 . . . . 70
6.19 Initial transient; delta operator PID; KP=40, KI=40300, KD=0.0064 . . . . 70
6.20 Initial transient; delta operator PID; KP=6, KI=20160, KD=0.0005 . . . . . 71
6.21 Initial transient; delta operator PID; KP=170, KI=5040, KD=0.0127 . . . . 71
6.22 Initial transient; delta operator PID; KP=75, KI=2500, KD=0.0124 . . . . . 72
6.23 Initial transient; delta operator PID; KP=300, KI=1260, KD=0.04 . . . . . 72
6.24 Initial transient; delta operator PID; KP=100, KI=1260, KD=0.03 . . . . . 73
6.25 Initial transient; Continuous vs. Delta; KP=50, KI=140000, KD=0.0075 . . 74
6.26 Initial transient; Continuous vs. Delta; KP=70, KI=60500, KD=0.0084 . . . 74
6.27 Initial transient; Continuous vs. Delta; KP=40, KI=40300, KD=0.0064 . . . 75
6.28 Initial transient; Continuous vs. Delta; KP=6, KI=20160, KD=0.0005 . . . 75
viii
List of Tables
5.1 Model parameters for experimental buck converter . . . . . . . . . . . . . . . 50
6.1 Gains and coe cients used in the simulations and experiments for Ts = 49:6  s 64
ix
Chapter 1
Topic Introduction and Background
1.1 Digital Control
Academia?s interest in digital control has been increasing proportionally to the increase
in digital technologies. The combination of ever faster and lower-cost processors secures a
place in future digital control approaches in control system applications. The implementation
of complex algorithms with a single processor rather than a multitude of integrated circuits
is also increasingly attractive. The ease of modi cation and superior imperviousness to aging
add additional credibility to the overall value of digital control systems. However, the world
that engineers desire to control is inherently analog and continuous, so transforming a system
from a continuous, closed-loop control system (Figure 1.1) to a discrete, closed-loop control
system (Figure 1.2) does not come without challenges.
The implementation of the digital control system shown in Figure 1.2 can be described
more speci cally for this thesis by Figure 1.3, which points out some of the main weaknesses
of digital systems. Time delays are caused by the analog-to-digital converter and the com-
putation of the new control signal. An n-bit processor?s resolution is limited to increments
of (x2 x1)=2n, where x1 and x2 are the maximum and minimum values of the range that is
desired to be represented. Also, the processor itself can only work with numbers from 0 to
2n 1. This last limitation is the main focus of this thesis.
The bene ts and trade-o s associated with digital control systems versus analog control
systems are well recorded and documented at the beginning of nearly every paper on the sub-
ject. There is extensive modern research attempting to improve digital control performance
through complex control algorithms [1] [2], advanced digital control theory approaches [3]
1
Figure 1.1: Block diagram of generic, continuous control system
Figure 1.2: Block diagram of generic, digital control system
Figure 1.3: Some digital control system weaknesses
2
[4], reducing e ects of numerical limitations [5], and overcoming analog-to-digital, digital-
to-analog, and computational delays [6].
This research is rightly placed. However, it is not simply overcoming the various math-
ematical and physical challenges that will be necessary for the progress in digital control to
be utilized. Experienced engineers and academics are far more adept at and comfortable
with traditional analog control theory. There are advancements being made, though, that
have potential to reduce performance and pedagogical di culties at the same time.
1.2 The Delta Operator
The incremental di erence operator (or delta operator) has been proposed as an alter-
native to the shift operator when representing discrete functions. A very notable work on
the delta operator (and delta transform) has been produced by Richard Middleton and Gra-
ham Goodwin [7]. Their work thoroughly introduces all the major areas of digital control
theory through the use of the delta operator, proposing that the study of both continuous
and discrete controls can be accomplished simultaneously since there is a narrow distinction
between the two when considering the delta operator for discrete parameterizations. This
thesis introduces some of these basic concepts of the delta operator in Chapter 2, but for a
thorough understanding, Middleton and Goodwin?s textbook should be referenced [7].
Others have explored the potential bene ts of the delta operator over the shift operator,
especially when considering the e ects of  nite word-length. Chen, Wu, Istepanian and Chu
have shown that the closed-loop stability margin of delta operator parameterizations are
better than the shift operator approach [8] [9]. Li and Gevers demonstrated that the delta
operator representations of state-variable models are less sensitive to coe cient errors in the
state-space matrices due to  nite word-length [10]. Before these, Middleton and Goodwin
argued for the delta operator?s ability to:
1. better represent controller coe cients,
3
2. reduce rounding error, and
3. facilitate more straightforward design by pole assignment [11].
The delta operator signi cantly closes the gap between continuous and discrete control
theory. In addition to potential performance improvement over the z-Transform, the con-
ceptual and mathematical similarities between the  -Domain and the s-Domain can make
understanding discrete controls far easier|especially for someone already familiar with ana-
log controls. Some examples of these connections are introduced later in this text, but the
main focus will be on the delta and shift operators? coe cient representation restrictions
presented by  nite word-length.
1.3 The Focus of this Thesis
The proposed performance bene t of the delta operator over the shift operator under
 nite word-length situations could have many advantages in industry. For instance, con-
sider that most of today?s control engineers and technicians are experienced with continuous
control design. Also, even though the use of  oating-point processors is on the rise, many
applications still prefer  xed-point implementations due to their reduced cost and power
consumption and increased speed and simplicity. There are similar bene ts associated with
reduced word-length. Combining these realities reveals a bene t in having delta-operator-
based control algorithms.
This is, of course, dependent on the improved e ectiveness of the delta operator?s per-
formance and continuous-like behavior in practice over the shift operator when transforming
from an analog to a digital controller representation. This thesis explores one facet of the
proposed bene ts: the numerical characteristics of the controller coe cients due to  nite
word-length. An investigation of the mathematical traits of a shift-operator-based (q-based)
di erence equation and a delta-operator-based ( -based) di erence equation, both having
4
been derived from the same s-Domain transfer function, is conducted. The results are sim-
ulated and tested using an 8-bit programmable interface controller (PICTM) to implement
a proportional, integral, derivative (PID) compensator to control a DC-DC buck converter.
Other digital control weaknesses are minimized and/or held constant so as to explore the
 nite word-length characteristics.
Chapter 2 provides an overview of the delta operator. Chapter 3 conducts the mathe-
matical analysis of the shift and delta operators? resultant di erence equations and derives
the corresponding PID di erence equations. Chapter 4 explains the hardware and software
utilized to implement an experiment of the results from Chapter 3. The basic concepts of
the representative plant, a buck converter, are introduced, as well as the appropriateness of
an 18F series PICTM as the microprocessor for this experiment. Chapter 4 concludes with
an explanation of the software algorithms. The system modeling and simulation designs are
discussed in Chapter 5, and the simulation and experimental results are recorded in Chapter
6. Chapter 7 presents the thesis conclusions and provides recommendations for future work.
5
Chapter 2
Overview of the Delta Operator
Because the equivalent continuous-time operator is d=dt, one might suspect that it
would not bear much resemblance to the discrete shift operator, q. This is exactly what has
been observed by academia and industry for decades. However, if a discrete-time operator
equivalent to a derivative is used, an increased correspondence would be expected. This
premise is the historic motivation behind the development of the delta operator.
2.1 De nition of Delta Operator
The incremental di erence operator (or delta operator) is typically de ned as:
 = q 1T
s
where Ts is the sampling period and q is the classic forward-shift operator, de ned as:
qxk = xk+1
making
 xk = xk+1 xkT
s
where xk is a state at the k-th sample. This expression demonstrates the correlation the delta
operator makes between discrete and continuous time. Notice that the delta operator acts
like an approximation of a derivative as Ts approaches 0 (the sampling rate, fs, approaches
1). So, at an in nite sampling rate,  operating on xk would be identical to d=dt operating
on xk!
6
Now, for most practical purposes, it is necessary to write the delta operator in a causal
form. The causal (backward) delta operator is de ned as:
  1 = 1 q
 1
Ts (2.1.1)
where q 1 is the causal (backward) shift operator:
q 1xk = xk 1
Therefore,
  1xk = xk xk 1T
s
(2.1.2)
2.2 Higher-Order Representations
In most applications, higher-order operators are necessary to implement a control sys-
tem.
2.2.1 Second-Order, Causal Delta Operator
The second-order operator is:
  2xk =   1(  1xk)
=   1(xk xk 1T
s
)
The second-order delta operator can be viewed as the di erence of di erences, or the ap-
proximation of a second-order derivative as Ts approaches 0, in the following form:
  2xk =
xk xk 1
Ts  
xk 1 xk 2
Ts
Ts (2.2.1)
7
For implementing in a real-time program, the following form can be derived from observing
equations (2.1.2) and (2.2.1):
  2xk =  
 1xk   1xk 1
Ts (2.2.2)
2.2.2 Third-Order, Causal Delta Operator
Applying a third delta operator will help reveal a pattern for the causal delta operator,
as shown by the following:
  3xk =   1(  2xk)
=   1
 xk xk 1
Ts  
xk 1 xk 2
Ts
Ts
!
The third-order derivative approximation for the delta operator is seen here:
  3xk =
 xk xk 1
Ts
 
 
 xk 1 xk 2
Ts
 
Ts  
 xk 1 xk 2
Ts
 
 
 xk 2 xk 3
Ts
 
Ts
Ts (2.2.3)
If equations (2.1.2), (2.2.2) and (2.2.3) are examined closely, more programmable-friendly
forms can be found, such as:
  3xk =
   1xk   1xk 1
Ts
 
 
   1xk 1   1xk 2
Ts
 
Ts (2.2.4)
or
  3xk =  
 2xk   2xk 1
Ts (2.2.5)
8
2.2.3 In General
From examining equations (2.1.2), (2.2.2), and (2.2.5), a general pattern is observed so
that the following de nition can be made:
  nxk =  
 (n 1)xk   (n 1)xk 1
Ts (2.2.6)
where n represents any integer. This result is conceptually consistent as the delta operator is
thought of as a derivative approximation. Higher-order derivatives simply represent changes
in changes (e.g., acceleration being the change in velocity, which is the change in position).
2.3 Stability Region Parallels
One additional illustration will serve to introduce the shared relationship and bene t
the delta operator provides in relation to continuous control systems. The stability regions
of their root locus plots will be examined. These facts are simply recorded; the reader can
investigate [7] for further explanation.
All the poles of the Laplace transform model of stable continuous-time systems lie
strictly in the left-half of the s-plane (Figure 2.1). The eigenvalues of a system matrix in
linear state variable form are found in the same region.
The shift operator?s stability region is signi cantly di erent, consisting of only the unit
circle (Figure 2.2).
When the stability region of the delta operator (Figure 2.3) is observed, an interesting
relationship with the continuous-time diagram is seen. The circle?s origin is shifted to the
point  1=Ts +j0. The radius of the stability region circle is also 1=Ts. As Ts approaches 0,
the stability region of  and d=dt become identical!
9
Figure 2.1: Stability region of d=dt operator
Figure 2.2: Stability region of shift operator
10
Figure 2.3: Stability region of delta operator
11
Chapter 3
Mathematical Demonstration of Coe cient Constraints on Discrete Models
In order to implement a digital controller in software, the transfer function must be
written as a causal di erence equation. The  rst section of this chapter  nds the general
di erence equations from a generic continuous-time transfer function. Although the solutions
are somewhat complex, one can clearly see the numeric bene ts of the delta operator.
In the second section, two di erence equations are obtained for a classic PID controller.
The observed numeric bene ts in general are realized in this speci c example.
3.1 General Mathematical Analysis
3.1.1 General Transfer Function Conversion to Shift Operator Representation
A transfer function, G(s), is de ned as the relation between the input and output of a
general system:
G(s) = Y(s)X(s)
and its general form is:
G(s) = aks
k +ak 1sk 1 +:::+a1s+a0
bjsj +bj 1sj 1 +:::+b1s+b0
In order to discretize the transfer function, most advanced controls engineers would use
the bilinear (or Tustin or Trapezoidal) approximation. In order to reduce the complexity of
the math, Euler?s backward di erence approximation is utilized:
s 1 z
 1
Ts
12
where Ts is the sampling period. Making the above substitution yields:
G(z) =
ak
Tks (1 z
 1)k + ak 1
Tk 1s (1 z
 1)k 1 +:::+ a1
Ts(1 z
 1) +a0
bj
Tjs (1 z
 1)j + bj 1
Tj 1s (1 z
 1)j 1 +:::+ b1
Ts(1 z
 1) +b0
and after  nding common denominators of the numerator and denominator the result can
be written as:
G(z) =
 Tj
s
Tks
 ak(1 z 1)k +ak 1Ts(1 z 1)k 1 +:::+a1Tk 1
s (1 z
 1) +a0Tk
s
bj(1 z 1)j +bj 1Ts(1 z 1)j 1 +:::+b1Tj 1s (1 z 1) +b0Tjs
Since this thesis?s experiment is controlling a buck converter, it will be helpful to de ne
the discrete transfer function as:
G(z) = D(z)E(z)
where d[n] and e[n] represent the duty cycle and the error signal at time nTs, respectively,
where n = 1;2;3:::. So, the di erence equation can be found by cross multiplying:
D(z)[bj(1 z 1)j +bj 1Ts(1 z 1)j 1 +:::+b1Tj 1s (1 z 1) +b0Tjs] =
E(z)
 Tj
s
Tks
 
[ak(1 z 1)k +ak 1Ts(1 z 1)k 1 +:::+a1Tk 1s (1 z 1) +a0Tks ]
and substituting in the equivalent time-domain components:
d[n][bj(1 q 1)j +bj 1Ts(1 q 1)j 1 +:::+b1Tj 1s (1 q 1) +b0Tjs] =
e[n]
 Tj
s
Tks
 
[ak(1 q 1)k +ak 1Ts(1 q 1)k 1 +:::+a1Tk 1s (1 q 1) +a0Tks ]
(3.1.1)
This can be written more concisely by utilizing the binomial theorem:
(x+y)k =
kX
i=0
 k
i
 
xk iyi
13
where  
k
i
 
= k!i!(k i)!
A general expression emerges such that
(x+y)k + (x+y)k 1 +:::(x+y) + 1 =
kX
m=0
 k mX
i=0
 k m
i
 
x(k m) iyi
 
(3.1.2)
By applying equation (3.1.2) to equation (3.1.1), the di erence equation becomes:
d[n]
jX
m=0
 
bj mTms
j mX
i=0
 j m
i
 
( q) i
 
=
e[n]
 Tj
s
Tks
 kX
m=0
 
ak mTms
k mX
i=0
 k m
i
 
( q) i
 (3.1.3)
The  nal, causal di erence equation for d[n] based on the shift operator can be written as:
d[n] =
 jX
m=0
bj mTms
  1"
 d[n]
jX
m=0
 
bj mTms
j mX
i=1
 j m
i
 
( q) i
 
+
e[n]
 Tj
s
Tks
 kX
m=0
 
ak mTms
k mX
i=0
 k m
i
 
( q) i
 # (3.1.4)
Although this result is complex, what is important to understand is not. Observe in
particular the scaling term Tjs=Tks . Unless k = j, every coe cient in the di erence equation
multiplied by every shifted version of e[n] will have a term scaled by some power of Ts. This
same possibility exists for many of the coe cients even if k = j. Because a sampling period
is typically in ranges of 10 5 to 10 6 seconds, the coe cients will vary over many orders of
magnitude.
There are important implications for this scaling characteristic in  nite word-length
mircocontrollers. Speci cally, the maximum value a microcontroller can represent is 2  1,
where  is the number of bits. For example, an 8-bit microcontroller can only represent
values up to 255. The max value due to this hardware-related constraint has the potential
14
to be orders of magnitude smaller than the values required if the sampling period is in a
range typical for digital control systems.
3.1.2 Shift Operator Representation to Delta Operator Representation
By rearranging equation (2.1.1), one obtains
q 1 = 1 Ts  1
and equation (3.1.1) can be rewritten as:
d[n][bj(Ts  1)j +bj 1Ts(Ts  1)j 1 +:::+b1Tj 1s (Ts  1) +b0Tjs] =
e[n]
 Tj
s
Tks
 
[ak(Ts  1)k +ak 1Ts(Ts  1)k 1 +:::+a1Tk 1s (Ts  1) +a0Tks ]
Therefore,
d[n]
jX
m=0
bmTj ms Tms   m = e[n]
 Tj
s
Tks
 kX
m=0
amTk ms Tms   m
Combining the Ts?s and moving them in front of the summations yields:
d[n]Tjs
jX
m=0
bm  m = e[n]
 Tj
s
Tks
 
Tks
kX
m=0
am  m
This result shows that the sampling periods can be canceled from the equations:
d[n]
jX
m=0
bm  m = e[n]
kX
m=0
am  m
If b0 6= 0, the  nal, causal di erence equation for d[n] based on the delta operator can be
written as:
d[n] = b 10
h
 d[n]
jX
m=1
bm  m +e[n]
kX
m=0
am  m
i
(3.1.5)
15
Because the sampling periods canceled, the scaling issue associated with the coe cients
of the shift-operator-based di erence equations is no longer as severe!
Each delta operator term, though, factors in dividing by the sampling period. So, even
though the coe cients of the delta-operator-based di erence equation are not a ected by
the sampling period in the same way as the shift operator di erence equation, the sampling
period cannot be ignored altogether.
Also, if b0 = 0, some change in the duty cycle will have to be solved for, rather than
the new duty cycle itself, and this will introduce the sampling period into the coe cients.
This will be seen with the PID controller?s di erence equation. However, by using the
delta operator approach, the sampling period will be easily absorbed into the design of the
coe cients as will be demonstrated later.
3.2 Discrete Representations of a PID Controller
To demonstrate the superior numerical aspects of the delta operator, an experiment is
conducted to compare shift operator and delta operator control of a buck converter. A PID
compensator is designed in its analog form, then mathematically represented by two di erent
di erence equations|one shift-operator-based and the other delta-operator-based. In this
section, the two competing di erence equations are derived.
3.2.1 Z-Transforming the PID
The PID controller is one of the most common controllers used in industry process
system applications. A standard academic practice is to use the PID or compare to the PID
when testing new control techniques or aspects; see examples in [12, 13, 14, 15]. The Laplace
Transform form of the classical PID compensator is de ned as:
D(s)
E(s) = KP +sKD +
KI
s (3.2.1)
16
As before, Euler?s backward di erence approximation is utilized to discretize the PID transfer
function:
s 1 z
 1
Ts
Therefore,
D(z)
E(z) = KP +
KD(1 z 1)
Ts +
KITs
1 z 1
This simpli es to
D(z)
E(z) =
KPTs(1 z 1) +KD(1 2z 1 +z 2) +KIT2s
Ts(1 z 1)
and
D(z)
E(z) =
(KDTs )z 2 + ( Kp 2KDTs )z 1 + (KP + KDTs +TSKI)
(1 z 1) (3.2.2)
3.2.2 The Shift Operator Di erence Equation
To  nd a di erence equation, cross multiply both sides of equation (3.2.2):
D(z)(1 z 1) = E(z)(KDT
s
)z 2 + ( Kp 2KDT
s
)z 1 + (KP + KDT
s
+TSKI)
Then replace z 1 with q 1 as follows:
dn(1 q 1) = en[(KDT
s
)q 2 + ( Kp 2KDT
s
)q 1 + (KP + KDT
s
+TSKI)]
A causal di erence equation is obtained to calculate the change in duty cycle. The resultant
equation for  d is:
 d = (KDT
s
)enq 2 + ( Kp 2KDT
s
)enq 1 + (KP + KDT
s
+TsKI)en (3.2.3)
17
which is equivalent to:
 d = (KDT
s
)en 2 + ( Kp 2KDT
s
)en 1 + (KP + KDT
s
+TsKI)en (3.2.4)
Finally, equation (3.2.4) will be written as:
 d =  2en 2 + 1en 1 + 0en (3.2.5)
where
 2 = (KDT
s
) (3.2.6)
 1 = ( Kp 2KDT
s
) (3.2.7)
 0 = (KP + KDT
s
+TsKI) (3.2.8)
Equations (3.2.5) through (3.2.8) are the ones that will be used for programming the shift
operator?s di erence equation algorithm in this experiment. After the continuous coe cients,
KP, KD, and KI, have been determined, the  coe cients will be calculated.
Notice, however, that all three of these coe cients are substantially larger than the
continuous coe cients because of the additions and, more importantly, the scaling by 1=Ts
on the KD term. For a  -bit microcontroller, if
KD
Ts > 2
  1
the coe cients cannot be properly represented without truncation (or over ow), much less
the results of the multiplications! Although truncation historically refers to removing LSBs,
this thesis will use it to refer to removing MSBs (e.g., in an 8-bit microcontroller, the
value 290 will have to be truncated to 255). The plot in Figure 3.1 illustrates the possible
18
Figure 3.1: Continuous PID coe cients that will not result in truncation using shift operator
parameterization
combinations of continuous PID gains that can be selected that will not result in the shift
operator?s di erence equation coe cients being truncated (or over owing).
3.2.3 The Delta Operator Di erence Equation
A di erent representation of the di erence equation presented by equation (3.2.3) can
be obtained by making the following substitutions:
q 1 = 1 Ts  1
19
and
q 2 = 1 2Ts  1 +T2s  2
The result is as follows:
 d = (KDT
s
)T2sen  2 + (Kp + 2KDT
s
 2KDT
s
)Tsen  1+
(KP 2KDT
s
+TsKI KP + KDT
s
+ KDT
s
)en
which simpli es to
 d = (KDTs)en  2 + (KpTs)en  1 + (KITs)en (3.2.9)
As concluded from Section 3.1.2, because there is no constant in the denominator of the
original continuous transfer function (i.e., b0 = 0 in (3.1.5)), the sampling period appeared
in the coe cients of the delta-operator-based di erence equation. However, since it is not
possible to divide by Ts in the microcontroller chosen for the experiment (explained in detail
later), the sampling period will need to be absorbed into the coe cients. If the de nition of
the delta operator is substituted into equation (3.2.9),
 d = (KDTs)
 en en 1
Ts
   en 1 en 2
Ts
 
Ts + (KpTs)
 en en 1
Ts
 + (K
ITs)en
This can be rewritten as
 d = D[(en en 1) (en 1 en 2)] +P[en en 1] +Ien (3.2.10)
20
where
D = KDT
s
(3.2.11)
P = KP (3.2.12)
I = TsKI (3.2.13)
Equations (3.2.10) through (3.2.13) are used in the delta-operator-based algorithm. In
this form, the \division" will occur at the same time as the coe cient multiplication. Also,
notice that now only one term contains KD=Ts. This way, if KD is designed so that it must
be truncated after being scaled by 1=Ts, only one coe cient will be thrown o , as opposed
to all three coe cients used in equation (3.2.4). The possible continuous PID coe cients
that can be used without truncation occurring on the delta-operator-based coe cients are
shown in Figure 3.2. These are compared with the shift operator?s limitations in Figures 3.3
and 3.4.
Care must be taken when designing KI because  xed-point processors do not handle
decimals. If division is required, it must be by powers of 2. This consideration is described
in detail in the hardware section of the experimental implementation chapter.
For now, it is important to note that the continuous PID compensator gains, KD,
KP, and KI, are designed so that conveniently-programmable and untruncated di erence
equation coe cients are much easier and less limited with the delta-operator-based di erence
equations.
21
Figure 3.2: Continuous PID coe cients that will not result in truncation using delta operator
parameterization
22
Figure 3.3: Comparison of possible continuous PID coe cients without truncation occurring
in the shift and delta operators di erence equations, View 1
Figure 3.4: Comparison of possible continuous PID coe cients without truncation occurring
in the shift and delta operators di erence equations, View 2
23
Chapter 4
Experiment Implementation
In order to test the results from the mathematical demonstration, an experiment is
designed and implemented to compare the performance of a shift-operator-based controller
with a delta-operator-based controller. Both are implemented based on a continuously-
designed PID controller. Most of the schematics and simulation diagrams (Chapter 5) include
the capabilities of performing step-changes in load. These are not performed in this thesis;
only the initial transients will be observed.
4.1 Hardware and System Con guration
A DC-DC buck converter is provided to serve as a plant process, and an 18F1220 PICTM
microcontroller is selected as the equipment to create the compensated, closed-loop system.
The buck converter and controller are con gured as shown in Figure 4.1. The performance
characteristics are described in the following subsections.
4.1.1 The Plant: DC-DC Buck Converter
DC-DC converters are electronic devices used to regulate one DC voltage to another.
Buck converters are DC-DC converters speci cally designed to step down an input voltage
and are common control problems. A helpful way to introduce these devices is to derive
their ideal gain and e ciency. A typical schematic of an ideal buck converter is illustrated
in Figure 4.2.
Although buck converters can operate in a discontinuous conduction mode, this thesis
analysis and experiment will be limited to operation in continuous conduction mode only
(i.e., the inductor current is assumed to always be > 0). Therefore, for this thesis?s purposes,
24
Figure 4.1: Schematic for digitally controlled buck converter
Figure 4.2: An ideal buck converter
25
Figure 4.3: Equivalent ideal buck converter with switch closed
the buck converter will be operating in only two states: switch closed (\ON") and switch
opened (\OFF"). The signal q is a pulse-width modulated (PWM) signal that varies the
power transistor between saturation mode (switch closed or \ON") and cuto mode (switch
open or \OFF"). The switching period of q is denoted by TSW, and the ratio of its \ON"
time verses its switching period is de ned as the duty cycle, D:
D = TONT
SW
(4.1.1)
Notice that 0 D 1.
When the power transistor is conducting, 0 t TON, the buck converter is modeled
by Figure 4.3. In this case, the transistor acts as a closed switch (a short circuit), and the
diode is blocking, acting as an open circuit. When the power transistor enters cuto mode,
TON <t TSW, it begins to act as an open circuit, and the diode begins to conduct. This
is represented by Figure 4.4.
To easily analyze the relationship between the input and output voltage, the equal-area
criterion is utilized with respect to the inductor voltage, vL [16]. Using Kirchho ?s Voltage
Law around the outer loop in Figure 4.3 reveals that while the transistor switch is conducting,
26
Figure 4.4: Equivalent ideal buck converter with switch open
vL = Vin Vout. Likewise, from Figure 4.4, during the remainder of the switching period
when the transistor switch is open, vL = Vout. Therefore,
TON(Vin Vout) + (TSW TON)( Vout) = 0
Multiplying through yields:
VinTON VoutTON VoutTSW +VoutTON = 0
which simpli es to:
Vout = TONT
SW
Vin
Recalling equation (4.1.1) reveals that the duty cycle acts as the voltage gain for the
buck converter; therefore:
Vout = DVin
27
Figure 4.5: A simple voltage divider schematic
Another reason for selecting a buck converter is based on typical performance speci -
cations. Regulating a source voltage to a lower voltage can be done using a simple linear
regulator, such as a voltage divider network. However, many electronic circuit applications
require performance characteristics that typical voltage dividers cannot provide. Under-
standing this additional bene t of buck converters will complete a basic introduction.
The circuit shown in Figure 4.5 represents a simple voltage divider circuit whose output
voltage is described by:
Vout = VinRR
1 +R
This equation shows that the output voltage is a function of both the input voltage and
the load resistance. Since a constant output voltage is usually the desired e ect, using a
voltage divider to regulate the output voltage is not an option in any circumstance where
the input voltage or load resistance may vary. However, a closed-loop control system can be
implemented with a buck converter to vary the duty cycle so that a desired output voltage
can be maintained despite variations in the source voltage or load resistance.
28
Note also a voltage divider?s e ciency:
 = PoutP
in
= I
2R
I2R1 +I2R
= RR
1 +R
In this study?s experiments, it is desired to regulate 5 V to 2.5 V. This case would require
setting R1 = R, making  = 50%!
A buck converter?s e ciency can be approximated by only considering the conduction
loses (loses while the power transistor is in saturation mode). First, the input power is
calculated as follows:
Pin = VinIavg
= VinT
SW
Z TSW
0
i(t)dx
= VinT
SW
Vin
R TON
= DV
2
in
R
And the output power is calculated as follows:
Pout = RI2RMS
= R 1T
SW
Z TSW
0
i2(t)dx
= R TonT
SW
 V
in
R
 2
= DV
2
in
R
29
Given the calculated input and output power results, the buck converter e ciency is
determined as follows:
 = PoutP
in
= 1
The e ciency is 100%! However, this calculation for the conduction losses does not factor in
losses in the transistor, inductor, etc. More signi cantly, this completely ignores switching
losses. Even though the buck converter?s e ciency will not really be 100%, the e ciency is
signi cantly improved over a voltage divider.
4.1.2 The Microcontroller: 18F PICTM
There are a few aspects of the 18F1220 PICTM microcontroller that make its selection
appropriate for this experiment. The 18F1220?s processor can run up to 40 MHz by enabling
the controller?s internal phase-locked-loop and adding an external 10 MHz crystal oscillator.
The controller also has a hardware multiplier, allowing for multiplications to be performed in
one instruction cycle. Together, these features increase computational speed and, therefore,
minimize the e ects of computational delay in the digital controller.
The hardware multiplication capability also increases the number of possible compen-
sator coe cients from which to select. The typical method of rotating bits to the left
only allows for multiplication by powers of two. With the 18F1220?s built-in multiplication
instruction, one can multiply by any integer between 0 and 255. As a reminder, the micro-
controller does not have a hardware divide, so any type of division has to be implemented
in software. This issue is addressed in Section 4.2.
Additionally, the 18F1220 PICTM has built-in a 10-bit analog-to-digital converter (ADC)
and a 10-bit pulse-width modulator (PWM), which are both necessary for a digitally-
controlled, closed-loop buck converter. Although these modules are 10-bit and the result
of the multiply function is 16-bit, calculations and number representations are held constant
at 8 bits to reduce algorithm complexity and to clearly demonstrate the e ects of  nite
word-lengths.
30
The ADC is used to feedback the analog output voltage and represent it as a value
between 0 to 255. The PWM is loaded with values between 0 and 255, indicating minimum
and maximum duty cycles, respectively.
There is a trade-o to note with respect to the range of values that one wants to
represent. As this range increases, the resolution of numbers that can be represented in the
microcontroller decreases since:
Vstep = Vmax Vmin2n 1
where Vstep is the smallest incremental change in voltage that can be represented, n is the
number of bits, and Vmax and Vmin are the largest and smallest voltages, respectively, that
one wants to represent. The larger the range, the larger the potential measurement error.
This can be compensated for by windowing circuits as described in [13], but this requires
extra circuity and increased algorithm complexity that will unnecessarily complicate the
experiment at hand. Therefore, the ADC?s positive voltage reference is set to the source
voltage (5 V) and the negative voltage reference to ground (0 V), and the buck converter
will regulate an input voltage of 5 V to 2.5 V. As a result, for this experiment the voltage
per step is:
Vstep = 5 V255 = 19:61 mV per step
And, since 2.5 needs to be represented by 127.5, and decimals cannot be represented, Vref =
127 = (01111111)2.
It is important to note this ADC resolution error; i.e., there is an inherent error of
Vstep=2, or 9.8 mV, in the reference voltage. Also, the error in the ADC feedback could be
as great as 19.61 mV, which is 7.84% of the reference voltage. There is also a resolution
problem that a ects the accuracy of the PWM output because the maximum resolution of
an 8-bit PWM module is 1/255 or 0.39%. The reference and ADC resolution errors are likely
31
to show up in the steady-state error of the system. The PWM resolution error will e ect
the overall performance (rise-time and settling-time). Since these errors will be the same
regardless of the operator used for parameterizing the PID controller?s di erence equation,
the experiment?s ability to compare the two approaches is not hindered.
The 18F1220?s ADC module has one additional feature that should be discussed. There
is a programmable acquisition time that allows for a set delay before beginning the ADC
conversion. This allows the user to maintain a constant sampling rate and have su cient
time to complete the necessary calculations in between samples since other operations can
be performed during the acquisition and ADC conversion times. This design feature is
illustrated more fully in Subsection 4.2.5.
For this experiment, the PWM?s switching frequency is set to 156.25 kHz. A PWM
switching frequency value that is a few times larger than the sampling frequency, yet low
enough to be measured by the available oscilloscope is desired. A variety of frequencies were
used ranging from 39.06 kHz to 312.50 kHz. The e ect of varying the switching frequency
was unnoticeable in the experimental results.
Although many \more powerful" microcontrollers could have been selected to perform
this experiment, the practical bene t of using this design approach on a $2.50 microcontroller
[17] would have been lost. Digital Signal Processors, etc., are signi cantly more expensive.
For speci cations on the 18F1220?s hardware modules, its datasheet should be consulted
[18].
4.2 Software
Most digital control systems are based on software-implemented algorithms. Although
the 18F series PICsTM can be programmed in C, the real-time operation of a DC-DC buck
converter requires a speed that can only be accomplished through programming in assembly
language. Therefore, the PICTM assembly language is used for the experiment algorithm.
32
The following subsections outline the speci c parts of the algorithm. A general overview of
the algorithm?s overall structure is provided by Figure 4.6.
After initializing the algorithm constants and variables, the input/output pins and the
ADC and PWM modules are set up. The code does not immediately begin attempting
to compensate or else the power supplies? transients would dominate the initial transient
measured by the oscilloscope. The program waits for a push-button input and enters the
main loop. The main code logic is described simply by waiting for the ADC to complete,
calculating the new duty cycle, updating the PWM, and updating the stored \past values"
for the next time through the loop. This process continues until power to the microcontroller
is removed.
4.2.1 Practical Issues
Many of the weaknesses of digital controls are present to varying degrees in the 18F1220
PICTM. The general computational scheme of the microcontroller is based on 8-bits. Al-
though the PWM and ADC can operate with up to 10-bits and the multiply result is 16-bits,
the experiment will be restricted to 8-bit processes. Once again, increasing the bits would
increase the algorithm complexity and, therefore, amplify the e ects of computational delay.
Additionally, it is easier to draw conclusions about the e ects of numerical restrictions if
the same number of bits are used for all number representations and calculations. Since the
numerical range of a microcontroller is from 0 to 2n 1, the range of numbers that can be
dealt with in this experiment is 0 to 255.
This microcontroller is  xed-point, meaning only integers can be represented. There
are techniques for addressing this issue. For instance, all numbers, n, could be represented
in the microcontroller as n scaled by some power of 10. So, if every number is represented
by 100-times its value, 1.83 would be represented as 183. But this approach would mean
that the largest number that could be represented would be 2.55! Using this method, the
range, in general, would be 0 to (2n 1)=10x, where x = 0;1;2;:::. This experiment will
33
Figure 4.6: General overview of software algorithm
34
not attempt to handle  oating-point numbers (i.e., x = 0). Numbers will be rounded to the
nearest integer.
Another weakness is the inability to divide. Because of this, the classical method of
rotating bits will be utilized. Because numbers will be represented by combinations of eight
10s and 00s, rotating the bits right x times, is the equivalent of dividing by 2x. Not only
does this signi cantly limit the number of coe cient options, but with every rotate right,
resolution in the result is lost since those bits are dropped completely. The inability to
represent decimals will be present in both the shift and delta operator representations of
the di erence equations, so the analysis goals will be una ected. It will turn out, though,
that only the delta operator will have coe cients that will require division, putting it at a
slight disadvantage for this study. However, even though the responses will be a ected, the
simulation and experimental conclusions will not be distorted.
Negative numbers also cannot be inherently represented. The microcontroller is capable
of 2?s-complement arithmetic, but this would limit subtractions to only 7 bits since the MSB
serves as the sign bit. In order to keep the range of numerical representation constant, each
8-bit term has an additional variable associated with its sign. This gives the experiment
the ability to represent numbers from  2n + 1 to 2n 1, or  255 to 255. Keeping up with
the sign increases algorithm complexity and calculation time, but it is necessary to clearly
investigate the delta and shift operators? sensitivity to  nite word-lengths.
4.2.2 Addition/Subtraction Subroutines
In order to implement signed addition and subtraction, a few subroutines must be coded.
The SimpleSubtraction subroutine is designed to subtract two numbers that are both known
to be positive; the result, however, could be positive or negative. The  owchart for this
subroutine is presented in Figure 4.7. Note that the nature of this algorithm will never
result in an over ow or under ow.
35
Figure 4.7: Subtraction when both numbers are known to be positive
36
Figure 4.8: Addition of two numbers that could be either positive or negative
The two signed subroutines, GeneralAddition and GeneralSubtraction, follow the  owcharts
of Figures 4.8 and 4.9. If a result?s magnitude ever causes an over ow (exceeds 255), then
the value is truncated to 255. The logic of GeneralAddition and GeneralSubtraction will
never result in an under ow.
4.2.3 Duty-Cycle Calculation: Shift Operator
The  owchart of the duty cycle calculation based on the shift operator?s PID controller,
equation (3.2.5), can be found in Figure 4.10.
The  owchart is quite self-explanatory: the new error value is calculated based on the
reference and the ADC result, the new duty cycle is calculated, the PWM is updated, and
37
Figure 4.9: Subtraction of two numbers that could be either positive or negative
38
Figure 4.10: Overview of duty cycle calculation based on the shift operator
39
the past values of the error are updated. Every addition and subtraction that takes place
is a result of a call of the GeneralAddition or GeneralSubtraction subroutine (Figures 4.8
and 4.9, respectively), except for the \new error" subtraction. The calculation to  nd the
current error value calls the SimpleSubtraction subroutine (Figure 4.7) because neither the
reference value nor the ADC result will ever be negative.
The remainder of the calculations use GeneralAddition or GeneralSubtraction because
the variables can be either positive or negative. The logic, over ow handling, etc. are not
shown in Figure 4.10 and are accounted for in the addition and subtraction subroutines.
4.2.4 Duty Cycle Calculation: Delta Operator
Equation (3.2.10) lays the foundation to implement the delta-operator-based duty cycle
calculation. The  owchart of this section of the algorithm can be found in Figure 4.11.
The main point here is the new error calculation is the only one that does not use
the GeneralAddition and GeneralSubtraction subroutines, since that is the only calculation
where all the values are known to be non-negative.
Other than the di erent equations for calculating the new duty cycle, there is only one
di erence in the delta operator algorithm as compared to the shift operator algorithm. For
the shift operator, all the past values are updated after the new duty cycle value is applied
to the PWM output. For the delta operator approach, some past values are updated at this
point and other values are updated immediately before the new duty cycle is calculated.
This design requirement is because the delta operator?s di erence equation is not only based
on previous values of the error, but on previous di erences in error values. These values
cannot be determined until the new error value is calculated.
In some cases, this dissimilarity may be signi cant, not so much because the past values
are updated at a di erent point or because it slightly increases algorithm complexity, but
because additional calculations must be performed to arrive at these past values. This fact
indicates that, in general, the delta operator?s di erence equation algorithm will take longer
40
Figure 4.11: Overview of duty cycle calculation based on the delta operator
41
to execute than the shift operator algorithm. Therefore a higher maximum sampling rate
can be achieved using the shift operator?s parameterization. This will be shown in more
detail in Subsection 4.2.5. However, the emphasis of this thesis is not the length of time it
takes to perform the calculations. All experiments will be performed at constant sampling
rates.
4.2.5 Timing Diagram
The two main timing in uences of a real-time digital control system are typically the
ADC conversion time and the time it takes to calculate the new control signal value. The
A/D conversion clock, TAD, is selected by the software programmer, but there is a minimum
conversion time. With the processor running at 40 MHz, a TAD of 1.6  s is required. An
analog to digital conversion requires 11 TAD cycles to complete. For this experiment, it will
take 17.6  s for a conversion to complete (i.e., Tconv = 17.6  s).
A 40 MHz processor makes one clock cycle equal to 25 ns. A PICTM requires four clock
cycles to execute one instruction cycle; therefore, this program will perform one instruction
every 100 ns. At most, the current implementation of the shift operator?s algorithm executes
about 145 instruction cycles to complete the full duty cycle update loop. This equates to
a minimum requirement of about 14.5  s. The current delta operator approach uses up
to about 217 instruction cycles, or 21.7  s. The detailed timing diagrams for these two
algorithms are found in Figures 4.12 and 4.13. The explanations of each diagrams? segment
are well documented in the  owcharts previously shown in Figures 4.10 and 4.11.
To provide su cient time for all necessary calculations to complete and to maintain a
constant sampling rate, a programmable acquisition time, Tacq, will be utilized as described
earlier. One available selection option for this value is 20 TAD, or 32  s. This value was
selected for the initial experiments, so the total sampling period, Ts, is:
Ts = Tacq +Tconv = 32  s + 17:6  s = 49:6  s
42
Figure 4.12: The approximate timing diagram for the shift-operator-based controller algo-
rithm
Figure 4.13: The approximate timing diagram for the delta-operator-based controller algo-
rithm
43
Figure 4.14: The approximate timing diagram for the overall system
Therefore, the sampling frequency, fs, is about 20.16 kHz. The overall timing diagram at
this sampling rate can be seen in Figure 4.14
44
Chapter 5
System Modeling and Simulation
Before conducting the experiments, design tools are used to design and simulate the
control system. MATLAB/Simulink were chosen for the simulation platform. Simulating
the system allows for quick veri cation and design of the control algorithms.
First, a model of the plant, the DC-DC buck converter, is developed that can be imple-
mented in Simulink. Then, models of the shift-based and delta-based digital PID controllers
are developed. Each controller model is implemented in Simulink.
5.1 Modeling of DC-DC Buck Converters
In order to perform designs and simulations with a DC-DC buck converter, it is necessary
to develop a mathematical model describing its characteristics. There are multiple ways to
approach model development. This thesis develops a set of state equations because of the
following:
1. State equations are developed based on common  rst-principle physics relationships.
2. Corresponding state diagrams are easily implemented in simulation software such as
Simulink and LabVIEW.
3. An option to account for non-linear characteristics is available.
4. Adjustments to model parameters are easily made for model updates and variation
testing.
To account for some of the non-ideal properties in buck converters, the state equations
are based on Figure 5.1.
45
Figure 5.1: A typical buck converter with inductor and capacitor ESRs
The equivalent series resistances (ESRs) of the inductor and capacitor are represented
by rL and rC, respectively. The transistor will operate in saturation mode when it is \ON"
and has a drain-source resistance, rT. When the transistor switch is \OFF", the diode will
conduct and be modeled by a DC voltage source, vD, in series with a resistance, rD.
The switching e ects cause unavoidable non-linearities in buck converters; nevertheless,
these e ects can be included in the state-space model. This modeling will be demonstrated
in the development of the equations. One output equation is written in addition to the
two state equations for both the \ON" and \OFF" states (or operating modes) of the buck
converter. The inductor current, iL, and the capacitor voltage, vC, will serve as the state
variables for modeling. The output current, iout, control signal, q, and the input voltage, vin,
are considered \inputs."
By examining either the \ON" state (Figure 5.2) or the \OFF" state (Figure 5.3) of the
non-ideal buck converter, the output voltage is:
vout = vC +iCrC
46
Figure 5.2: Non-ideal buck converter with transistor switch closed
Figure 5.3: Non-ideal buck converter with transistor switch open
47
Writing this expression in terms of the state variables and inputs yields:
vout = vC +rC(iL iout) (5.1.1)
To  nd the required state equations, the di erential equations that relate capacitors?
and inductors? currents and voltages are used. Beginning with the inductor current:
diL
dt =
_iL = 1
LvL
The inductor voltage, vL, needs to be replaced with a combination of state variables and
inputs. When the transistor switch is \ON", the change in inductor current is:
_iL = 1
L(vin vo iLrL iLrT)
and when the transistor switch is \OFF", the inductor current is:
_iL = 1
L( vD vout iLrL iLrD)
Because these are time-based signals, vin and iLrT are multiplied by q, and vD and iLrD are
multiplied by the inverse of q,  q. This accounts for the non-linearities. Remember that q = 1
when 0 t TON, and q = 0 when TON <t (TSW TON). This yields:
_iL = 1
L
  v
out iLrL +q(vin iLrT)  q(vD +iLrD)
 (5.1.2)
The change in the capacitor voltage is:
dvC
dt = _vC =
1
CiC
48
Figure 5.4: State diagram for a buck converter
For both the \ON" and \OFF" states, iC = iL iout; therefore, the second state equation is:
_vC = 1C(iL iout) (5.1.3)
A state diagram can be composed using equations (5.1.1), (5.1.2), and (5.1.3). The state
diagram model is built directly from Simulink?s default library as shown in Figure 5.4.
Table 5.1 contains the model parameters for the simulation.
The composite Simulink model of the buck converter is presented in Figure 5.5 where
the power stage is the state diagram in Figure 5.4 and the PWM generator is shown in
Figure 5.6. The PWM generator works by subtracting a sawtooth wave from the duty cycle.
As long as the result is greater than 0, the output will be \ON". Dnom is the nominal
49
Symbol Parameter Value Units
Vin Input Voltage 5 V
R Load Resistance 5  
L Series Inductor 150  H
rL ESR of Inductor 10 m 
C Output Capacitor 1000  F
rC ESR of Capacitor 30 m 
VD Forward Drop Across Diode 0.4 V
rD ESR of Diode when Conducting 450 m 
rT Drain-Source Resistance of Transistor 40 m 
Vref Reference Voltage 2.5 V
Table 5.1: Model parameters for experimental buck converter
duty cycle, Vref=Vin. The simulations and experiments are performed with Vref = 2:5V.
Therefore, Dnom = 0:5.
The experimental buck converter used for this experiment was used previously by Feng?s
and Guo?s theses [12] [15]. Values for L, rL, C, and rC were attained from these two theses.
Values for Vin, Vref, and R were selected to minimize external circuitry and additional code
which would be required to handle resolution and referencing issues. The value of rT was
obtained from the power transistor?s data sheet [19]. The value for the diode voltage, vD,
is a typical drop across a Schottky diode and is consistent with the instantaneous forward
current to instantaneous forward voltage curve provided on the part?s datasheet [20]. The
diode resistance, rD, was selected to give a more reasonable amount of damping to the
simulation. This e ect is shown in the open-loop responses. The initial transient response
of Simulink?s open-loop model is shown in Figure 5.7.
To increase con dence in the model results, the open-loop response was plotted using
the schematic editor in Pspice; this schematic is shown in Figure 5.8. The result of the
Pspice simulation is shown in Figure 5.9.
50
Figure 5.5: Open-loop buck converter Simulink model
Figure 5.6: PWM generator Simulink model
51
Figure 5.7: Simulink simulation of open-loop response with Vref = 2:5V
Figure 5.8: Pspice schematic of open-loop buck converter
52
Figure 5.9: Pspice simulation result of open-loop response
With the exception of some additional damping in the Pspice model, the dynamic
response of the Pspice model and the Simulink model favor each other well.
The actual open-loop response was measured and is compared to the Simulink simulation
in Figure 5.10. The Pspice simulation replicates the actual system response more accurately
than the Simulink simulation does. However, the Simulink simulation satisfactorily resembles
the actual system so that it can be used for designing the closed-loop system. The digital
modeling of the system is immensely easier to accomplish in MATLAB/Simulink rather than
Pspice. The additional damping that the actual system will experience will be factored into
the design of the closed-loop system in the simulation.
53
Figure 5.10: Experimental versus simulation open-loop response
5.2 Modeling of Analog PID Controllers
Modeling a closed control loop with an analog PID controller in a graphical simulation
program is common practice. Figure 5.11 illustrates the simulation used to design the con-
troller coe cients, KP, KI, and KD, for this experiment. These coe cients correspond to
the classic PID equation given previously in equation (3.2.1).
The output voltage, Vo, is fed back and subtracted from the reference voltage, Vref. The
resultant error signal is fed into the three compensator terms. The three terms add together
to produce the control signal, or the duty cycle, D. As discussed previously, a change in D
adjusts the buck converter output voltage. The duty cycle is adjusted until the error signal
equals zero (i.e., the output voltage equals the reference voltage).
This simulation is set up to test the initial transient as well as a step change in load.
Testing the initial transient is equivalent to a reference step change from 0V to whatever
54
Figure 5.11: Closed-loop buck converter with continuous-time PID controller
reference voltage is desired (2:5V in the case of this experiment). The step change in load
will not be demonstrated in this thesis.
The following section describes the models used to simulate the two digital compen-
sators.
5.3 Modeling of Non-ideal Digital Controllers in Simulink
The closed-loop system model using a digital compensator is illustrated in Figure 5.12.
Digital controller constraints are modeled in this simulation. The ADC Delay block models
the time delay due to the analog-to-digital converter (17.6  s). This value is then scaled
to its equivalent digital value between 0-255 and any decimal is dropped due to the Zero-
Order Hold, Scale, Saturate and Quantizer blocks. Vref experiences a similar scaling and
quantization.
The output of the digital compensator is the change in duty cycle,  dn, so it is combined
with the previous value of the duty cycle, dn 1. (Recall that z 1 is equivalent to q 1.) The
duty cycle is truncated from 0-255 before being applied to the PWM. (The  255 to 255
55
Figure 5.12: Closed-loop buck converter with discrete-time PID controller
saturation block was simply for debugging purposes.) The input of the PWM subsystem
must be a value between 0 and 1, so the duty cycle is scaled accordingly. The Calculation
Delay block is applied to model the delay in the microcontroller computations. This value
is set to 32  s to represent the entire programmable acquisition time discussed earlier.
5.3.1 Shift-Based Digital PID Controller in Simulink
The digital PID controller simulation model for the shift operator is presented in Figure
5.13. This Simulink model represents di erence equation (3.2.5) being calculated consistent
with the method used by the 8-bit microcontroller in the experiment. Each multiplication
is saturated between 255 and 255 (this restriction was described earlier), and quantized in
the case of any  oating-point numbers that might arise. Two terms are summed together,
saturated, and summed to the  nal term, followed by one last saturation.
56
Figure 5.13: Simulation model of the shift-operator-based PID di erence equation
Figure 5.14: Block diagram of the delta operator
5.3.2 Delta-Based Digital PID Controller in Simulink
The closed-loop control system for this model is the same as the one shown in Figure
5.12 except the digital compensator subsystem is based on the delta operator rather than
the shift operator.
A block diagram of a delta operator is provided by Figure 5.14. The delta operator
used in this experiment is based on the de nition of the causal (or backward) delta operator
given in equation (2.1.2).
The form of the delta-operator-based di erence equation was derived so as to \ab-
sorb" the sampling period, Ts, into the coe cients (equation (3.2.10)). Since this is the
57
Figure 5.15: Simulation model of the delta-operator-based PID di erence equation
programmed form, it must be considered when designing the simulation. The gain block
in Figure 5.14, 1=Ts, is not present in the di erence equation block diagram since it is al-
ready accounted for in the coe cient gain block. The  nal form is incorporated in the
delta-operator-based PID controller simulation model shown in Figure 5.15.
All the calculations are performed just as they are in the microcontroller?s software.
The same saturation and quantization e ects are applied that have been to all the digital
models thus far.
58
Chapter 6
Simulation and Experimental Results
6.1 Continuous PID Controller Designs
A variety of gains are selected for KP, KI, and KD, to illustrate a variety of responses.
No strict methodology, such a Ziegler-Nichols or Cohen-Coon, is used to tune the gains. A
handful of responses with an assortment of overshoots, oscillations, and rise-times are desired
to provide diverse scenarios to compare the performances of the two digital approaches. The
plots in Figures 6.1!6.8 record the simulation results of the initial transients of the model
shown in Figure 5.11 using the gains indicated in each  gure description.
6.2 Discrete PID Controllers
The speci c values of the continuous gain selections and their corresponding di erence
equation coe cients can be found in Table 6.1.
The shift and delta coe cients are found using equations (3.2.8) and (3.2.13) with
Ts = 49:6  s. Recall that if any of the coe cients for the two digital operators exceedsj255j,
it is truncated to either  255 or 255. Also, coe cient decimals are rounded o . If a gain is
greater than 0, but less than 1, it is approximated by its closest inverse power of 2, i.e., 2 n,
multiplied by an integer.
As expected, the truncations experienced by the shift operator coe cients are more
severe and numerous than the delta operator coe cients.
59
Figure 6.1: Initial transient; Continuous PID; KP=50, KI=140000, KD=0.0075
Figure 6.2: Initial transient; Continuous PID; KP=70, KI=60500, KD=0.0084
60
Figure 6.3: Initial transient; Continuous PID; KP=40, KI=40300, KD=0.0064
Figure 6.4: Initial transient; Continuous PID; KP=6, KI=20160, KD=0.0005
61
Figure 6.5: Initial transient; Continuous PID; KP=170, KI=5040, KD=0.0127
Figure 6.6: Initial transient; Continuous PID; KP=75, KI=2500, KD=0.0124
62
Figure 6.7: Initial transient; Continuous PID; KP=300, KI=1260, KD=0.04
Figure 6.8: Initial transient; Continuous PID; KP=100, KI=1260, KD=0.03
63
Set 1 Set 2 Set 3 Set 4 Set 5 Set 6 Set 7 Set 8
Continuous Gains
KP 50 70 40 6 170 75 300 100
KI 140000 60500 40300 20160 5040 2500 1260 1260
KD 0.0075 0.0084 0.0064 0.0005 0.0127 0.0124 0.04 0.03
Shift Coe cients
 0 208 242 171 17 426 325 1107 705
 1 -352 -409 -298 -26 -682 -575 -1913 -1310
 2 151 169 129 10 256 250 806 605
Delta Coe cients
P 50 70 40 6 170 75 300 100
I 7 3 2 1 0.25 0.124 0.0625 0.0625
D 151 169 129 10 256 250 806 605
Table 6.1: Gains and coe cients used in the simulations and experiments for Ts = 49:6  s
6.2.1 Shift Operator Performance
The shift-operator-based PID controller transient results are displayed in the following
plots (Figures 6.9!6.16 ). Each case is based on the the simulation model shown in Figure
5.12, using the compensator shown in Figure 5.13.
Every response based on the shift operator PID controller is marginally stable except
one (Figure 6.12)! This poor performance was expected due to the extensive truncation that
occurs on most coe cients and computations within the algorithm.
Notice the additional damping on the experimental results as compared to the simulation
results. This outcome is precisely what the open-loop comparisons in Section 5.1 suggested
would occur. The experiments also have excessive ripple characteristics. This  nding is best
attributed to the 0.5% error in the measurement equipment (see its reference manuel [21]),
the nonlinear e ects the buck converter will have on the measurement equipment, and the
quantization error in the ADC and internal voltage reference.
These shift operator PID controller responses are unacceptable for any plant process
application and bear no resemblance to the original analog PID controller simulations.
64
Figure 6.9: Initial transient; shift operator PID; KP=50, KI=140000, KD=0.0075
Figure 6.10: Initial transient; shift operator PID; KP=70, KI=60500, KD=0.0084
65
Figure 6.11: Initial transient; shift operator PID; KP=40, KI=40300, KD=0.0064
Figure 6.12: Initial transient; shift operator PID; KP=6, KI=20160, KD=0.0005
66
Figure 6.13: Initial transient; shift operator PID; KP=170, KI=5040, KD=0.0127
Figure 6.14: Initial transient; shift operator PID; KP=75, KI=2500, KD=0.0124
67
Figure 6.15: Initial transient; shift operator PID; KP=300, KI=1260, KD=0.04
Figure 6.16: Initial transient; shift operator PID; KP=100, KI=1260, KD=0.03
68
Figure 6.17: Initial transient; delta operator PID; KP=50, KI=140000, KD=0.0075
6.2.2 Delta Operator Performance
The delta operator digital PID controller simulations used the same overall control
model as the shift operator (Figure 5.12), except the compensator model is replaced by the
one in Figure 5.15. The initial transient simulation and experimental plots follow in Figures
6.17 ! 6.24.
The overall performance, especially the steady-state error and rise-time, and resem-
blance between the simulation and experiment degrade in the responses of Figures 6.21 -
6.24. Once again, this was predicted earlier during the discussion of approximating divid-
ing by powers of two with \rotate rights." The precision lost in these cases is signi cant,
especially considering the reference voltage is only 2.5 V.
The delta-operator-based PID controller demonstrates general superior performance
over the shift-operator-based PID controller. The delta operator responses, in general, are
69
Figure 6.18: Initial transient; delta operator PID; KP=70, KI=60500, KD=0.0084
Figure 6.19: Initial transient; delta operator PID; KP=40, KI=40300, KD=0.0064
70
Figure 6.20: Initial transient; delta operator PID; KP=6, KI=20160, KD=0.0005
Figure 6.21: Initial transient; delta operator PID; KP=170, KI=5040, KD=0.0127
71
Figure 6.22: Initial transient; delta operator PID; KP=75, KI=2500, KD=0.0124
Figure 6.23: Initial transient; delta operator PID; KP=300, KI=1260, KD=0.04
72
Figure 6.24: Initial transient; delta operator PID; KP=100, KI=1260, KD=0.03
more stable and have less oscillation than the shift operator responses. There is also a favor-
able resemblance between the simulation and experimental responses, with some additional
damping seen in the experimental system.
The advantage of the delta operator?s di erence equation is further supported if their
experimental responses are compared to the corresponding continuous-time PID simulation
responses (Figures 6.25 ! 6.28). The algorithms that incorporated a division will not be
displayed because their loss of accuracy decreases this parallel.
Most of these responses coincide well with each other, especially considering the known
damping increase when operating in the \real world." With superior performance, increased
correspondence between numerical simulations and experimental results, and prevailing re-
semblance to the continuous-time results, the delta operator proves to outperform the shift
operator in discrete PID controllers under  nite word-length conditions.
73
Figure 6.25: Initial transient; Continuous vs. Delta; KP=50, KI=140000, KD=0.0075
Figure 6.26: Initial transient; Continuous vs. Delta; KP=70, KI=60500, KD=0.0084
74
Figure 6.27: Initial transient; Continuous vs. Delta; KP=40, KI=40300, KD=0.0064
Figure 6.28: Initial transient; Continuous vs. Delta; KP=6, KI=20160, KD=0.0005
75
Chapter 7
Conclusions and Potential Future Work
The work in this thesis explored the e ects of  nite word-length on digital controllers
implemented using two di erent digital operators|the shift operator and the delta operator.
After a mathematical analysis was performed, simulations and experiments were conducted
using a common controls application: a PID-compensated buck converter.
The mathematical derivations, simulations, and experiments performed in this thesis
suggest the same conclusion: the delta operator approach to parameterizing continuous
controllers exhibits certain numerical and, therefore, performance advantages over the shift
operator under  nite word-length conditions. Though there are several challenges that fall
under the category of \numerical," this thesis focused primarily on truncation that occurs
due to the limited range of numbers that can be represented in microcontrollers. When
using the approaches employed by this thesis to derive the discrete di erence equations, the
delta-operator-based coe cients are scaled less than the shift-operator-based coe cients.
The additional scale experienced by the shift operator?s di erence equation makes it more
susceptible to clipping caused by  nite word-length, signifying a decrease in performance
with respect to the delta operator.
The discovery of the delta operator?s superior controller performance and correlation
to continuous controllers could have bene ts considering that most expertise and experience
in controller design lies in the continuous realm. The results of this thesis suggest that one
could reasonably design a digital controller using continuous techniques. A program could
easily be written that would be used to calculate discrete coe cients that would correspond
to the continuous-designed coe cients. According to this study, this approach would be far
76
more likely to be successful if the digital controller were derived and implemented using the
delta operator rather than the shift operator.
There is additional work that could be done to solidify these claims. Performing these
experiments at additional sampling rates could reveal whether or not there are exceptions
to the e ects of  nite word-length found in this thesis. Controllers other than a PID could
be used for the simulations and experiments to determine if there are instances where the
e ects of  nite word-length are enlarged or lessened between the delta and shift operators.
Part of the mathematical analysis suggests that the delta operator could have an even more
noticeable improvement over the shift operator if a controller is selected where the actual
control signal could be solved, rather than the change in control signal (Subsection 3.1.2).
Another analysis could be performed using an alternative method to obtain the discrete
representations of the continuous transfer function. One could use a di erent emulation
technique, or derive the delta-based model directly from the continuous rather than the
shift-based model.
Lastly, the increase in time that it takes to perform the delta-based PID calculation
(Subsection 4.2.5) could point to a potential bene t of the shift operator over the delta oper-
ator if the limiting factor was sampling rate rather than word-length. Additional experiments
would have to be arranged to con rm this hypothesis.
77
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