Selective Spectrum Analysis and Numerically Controlled Oscillator in Mixed-Signal Built-In Self-Test by Jie Qin A dissertation submitted to the Graduate Faculty of Auburn University in partial ful llment of the requirements for the Degree of Doctor of Philosophy Auburn, Alabama December 13, 2010 Keywords: Mixed-Signal, Built-In Self-Test (BIST), Analog Functional Testing, Selective Spectrum Analysis (SSA), COordinate Rotation DIgital Computer (CORDIC), Numerically Controlled Oscillator (NCO), Direct Digital Synthesis (DDS) Copyright 2010 by Jie Qin Approved by: Fa Foster Dai, Co-chair, Professor of Electrical and Computer Engineering Charles E. Stroud, Co-chair, Professor of Electrical and Computer Engineering Vishwani Agrawal, James J. Danaher Professor of Electrical and Computer Engineering Richard C. Jaeger, Professor Emeritus of Electrical and Computer Engineering Abstract Built-In Self-Test (BIST) o ers a system the ability to test itself. Though it introduces inevitable extra cost for the added hardware, it also makes it possible to monitor, measure and calibrate the system on the y as will shown. With BIST, the reliability of the overall system can be improved and the testing and maintenance cost be reduced. This dissertation discusses a proposed mixed-signal BIST architecture and the implementation of one of its key components | numerically controlled oscillator (NCO). The proposed BIST is composed of a NCO-based test pattern generator (TPG) and a selective spectrum analysis (SSA)- based output response analyzer (ORA). It utilizes the digital-to-analog converter (DAC) and analog-to-digital converter (ADC), which typically exist in a mixed-signal system, to interface the digital TPG and ORA with the analog device under test (DUT). Theoretically the SSA-based ORA is equivalent to fast Fourier transform (FFT), but it only utilizes two digital multiplier/accumulators (MACs) and thus requires much less area overhead than the latter. Because of its ability to perform spectrum estimation, the SSA-based ORA is able to conduct a suite of the analog functional measurements such as frequency response, 1dB compression point (P1dB), 3rd-order interception point (IP3), etc.. Basically the SSA down converts the DUT?s output at the frequency under analysis to DC by multiplication and lters out the non-DC spectrum by accumulation, but usually the non-DC spectrum cannot be removed completely and causes calculation errors. Though these errors can be reduced by increasing accumulation time, the convergence rate is so slow that it requires long test time to achieve a reasonable accuracy. Theoretical analysis proves that the non-DC calculation errors can be minimized in short test time by stopping the accumulation at the integer multiple periods (IMPs) of the frequency under analysis. However, due to the discrete nature of a digital signal, it is impossible to correctly identify ii every IMP when it occurs. Thus the concept of fake and good IMPs is introduced and the circuits to generate them are also discussed. According to their advantages and drawbacks, they are chosen for di erent analog measurements. Performance of the SSA-based ORA is analyzed in a systematical way and it is shown that the proposed IMP circuits can greatly improve the e ciency of the ORA in terms of test time, area overhead, and measurement accuracy. The NCO is one of the key components in the proposed BIST architecture and employed in both TPG and ORA. A typical NCO consists of a phase accumulator and look-up table (LUT) to convert the linear output of the accumulator to a sine or cosine wave. However, as the size of the digital-to-analog converter (DAC) increases the hardware overhead of the tra- ditional NCO increases exponentially. COordinate Rotation DIgital Computer (CORDIC) is an iterative algorithm which is able to calculate trigonometric functions via simple addi- tion, subtraction and bit shift operations. As a result, the CORDIC size increases linearly with the size of the DAC. However, the traditional CORDIC algorithm requires many it- erations to achieve a reasonable degree of accuracy which excludes its use as a practical means for high-speed and area-e cient frequency synthesizers when compared with other LUT ROM compression techniques. This dissertation proposes a partial dynamic rotating (PDR) CORDIC algorithm. The proposed algorithm minimizes the number of iterations it requires as well as the e ort required to implement each iteration such that the CORDIC can be pipelined for per-clock-cycle generation of sine/cosine waveforms. In addition, the PDR CORDIC has a greater spur-free dynamic range (SFDR) and signal-to-noise-and-distortion (SINAD) than the traditional table methods used for NCO implementations. iii Acknowledgments I would like to express my deepest gratitude and respect to my major advisors, Dr. Charles E. Stroud and Dr. Fa Foster Dai. During my Ph.D. study, whenever I met di culties in my study and research, they were always there to give me constructive advices, share with me their insight and wisdom, and help me move forward. Without their encouragement and support, I would not be able to make it so far. I would also like to specially thank my Ph.D. committee members, Dr. Vishwani Agrawal and Dr. Richard C. Jaeger, and the outside reader, Dr. Richard Chapman, for spending their time and energy to read my dissertation and give me valuable feedbacks. Thanks also go to all the graduate students I had worked with at Auburn University, Michael Alex Lusco, Joseph D. Cali, Bradley F. Dutton, Xueyang Geng, Georgie J. Starr, Justin Dailey, etc.. It is really fun to work with them. I am deeply grateful to my dear parents, Shukuan Qin and Yanping Ma. They made me who I am today. Without their moral and nancial support, I would not be able to make these achievements. I also want to thank my brother, Hao Qin. Thank you for taking care of the whole family while I am abroad in USA. I am also deeply grateful to my smart and beautiful wife, Xiaoting Wang. Thank you for your valuable suggestions and support at almost every aspect of my life, thank you for the delicious food you prepared, and thank you for making my life so delightful and fun. Thank you for everything! The views, opinions, and/or ndings contained in this article/presentation are those of the author/presenter and should not be interpreted as representing the o cial views or policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the Department of Defense. iv Approved for Public Release, Distribution Unlimited. v Table of Contents Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv List of Illustrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii 1 Introduction to Analog and Mixed-Signal Built-In Self-Test (BIST) . . . . . . . 1 1.1 Digital Testing vs. Analog Testing . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Analog Testing Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.1 Structural Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.2 Functional Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.3 Analog and Mixed-Signal Built-In Self-Test . . . . . . . . . . . . . . . 9 1.3 Organization of the Dissertation . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 Overview to Spectrum-Based Analog Testing . . . . . . . . . . . . . . . . . . . . 16 2.1 Nonlinear and Frequency Dependent Model for Analog DUT . . . . . . . . . 17 2.2 Spectrum-Based Speci cations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.1 Single-Tone Speci cations . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.2 Two-Tone Speci cation . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 Architecture of Selective Spectrum Analysis-Based BIST . . . . . . . . . . . 28 2.3.1 Structural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.2 Overview of Testing Procedure . . . . . . . . . . . . . . . . . . . . . 31 2.3.3 Necessity of Calibration . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.4 RF Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3 Selective Spectrum Analysis Based Output Response Analyzer . . . . . . . . . . 37 vi 3.1 Theoretical Background of SSA . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1.1 Basic Operation of SSA and Its Equivalency to FFT . . . . . . . . . 37 3.1.2 Frequency Resolution of SSA . . . . . . . . . . . . . . . . . . . . . . 39 3.1.3 Accuracy and Sensitivity of SSA . . . . . . . . . . . . . . . . . . . . . 44 3.2 Integer Multiple Points (IMPs) in SSA . . . . . . . . . . . . . . . . . . . . . 54 3.2.1 IMPs for Frequency Response Measurement . . . . . . . . . . . . . . 54 3.2.2 Linearity Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.2.3 Noise and Spur Measurement . . . . . . . . . . . . . . . . . . . . . . 59 3.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.3.1 Implementation of IMP Circuits . . . . . . . . . . . . . . . . . . . . . 61 3.3.2 Frequency Response Measurement in SSA-based ORA . . . . . . . . 64 3.3.3 IP3 Measurement in SSA-based ORA . . . . . . . . . . . . . . . . . . 67 3.3.4 Noise and Spur Measurement in SSA-based ORA . . . . . . . . . . . 74 3.3.5 Comparison between the SSA and FFT based ORAs . . . . . . . . . 74 4 CORDIC based Test Pattern Generator . . . . . . . . . . . . . . . . . . . . . . 77 4.1 Introduction to Direct Digital Synthesis (DDS) . . . . . . . . . . . . . . . . 77 4.1.1 General Architecture and Design Concerns of DDS . . . . . . . . . . 77 4.1.2 Bit-Width of Phase Word vs. DAC Resolution . . . . . . . . . . . . . 79 4.1.3 Look-Up Table (LUT)-based NCO . . . . . . . . . . . . . . . . . . . 80 4.2 Overview of CORDIC Algorithm . . . . . . . . . . . . . . . . . . . . . . . . 83 4.2.1 Generalized CORDIC Algorithm . . . . . . . . . . . . . . . . . . . . 83 4.2.2 CORDIC Algorithm in Circular Coordinate System . . . . . . . . . . 87 4.2.3 Various Techniques for Improving CORDIC . . . . . . . . . . . . . . 92 4.3 Some Other LUT Compression Techniques . . . . . . . . . . . . . . . . . . . 102 4.4 CORDIC with Partial Dynamic Rotation . . . . . . . . . . . . . . . . . . . . 103 4.4.1 Partial Dynamic Rotation . . . . . . . . . . . . . . . . . . . . . . . . 105 4.4.2 LUT for Range Reduction . . . . . . . . . . . . . . . . . . . . . . . . 107 vii 4.4.3 X and Y Merging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.4.4 Optimization on Z-path . . . . . . . . . . . . . . . . . . . . . . . . . 114 4.4.5 - Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 viii List of Illustrations 1.1 Simpli ed illustration of digital signals. . . . . . . . . . . . . . . . . . . . . . 2 1.2 Interested characteristics in analog signals. . . . . . . . . . . . . . . . . . . . 4 1.3 Parameter variation and its e ect on speci cation and measurement. . . . . 6 1.4 Work ow of analog structural testing. . . . . . . . . . . . . . . . . . . . . . 8 1.5 General model of an adaptive mixed-signal system with BIST technology. . . 14 2.1 Simpli ed system view of analog DUTs. . . . . . . . . . . . . . . . . . . . . 17 2.2 Illustration of frequency spectrum measurement with single-tone test. . . . . 20 2.3 Illustration of 1dB gain compression point. . . . . . . . . . . . . . . . . . . . 22 2.4 Single tone test for noise and spur measurement. . . . . . . . . . . . . . . . . 23 2.5 Intermodulation in analog DUTs with two-tone stimulus. . . . . . . . . . . . 25 2.6 Comparison of spectrum at fundamental and 3rd-order IM frequencies. . . . 27 2.7 General model of mixed-signal SSA-based BIST architecture. . . . . . . . . . 29 2.8 A detailed view of the quadrature NCO in ORA. . . . . . . . . . . . . . . . 30 2.9 Phase delay measurement in digital portion of BIST circuitry. . . . . . . . . 33 2.10 Phase delay introduced by DAC/ADC circuitry. . . . . . . . . . . . . . . . . 34 2.11 RF extension of the proposed SSA-based BIST. . . . . . . . . . . . . . . . . 36 3.1 Selective spectrum analysis-based output response analyzer. . . . . . . . . . 38 3.2 Estimation error caused by the spectrum analysis. . . . . . . . . . . . . . . . 40 3.3 Another view angle to spectrum analysis from time window. . . . . . . . . . 41 3.4 The spectrum of a rectangle window. . . . . . . . . . . . . . . . . . . . . . . 44 ix 3.5 Spectrum analysis for signals with wrong window setup. . . . . . . . . . . . 47 3.6 Illustration of weakening side lobe impact on main lobe. . . . . . . . . . . . 48 3.7 Illustration of accuracy degradation by sampling frequency o set. . . . . . . 49 3.8 Window e ect on two frequency components with similar strength. . . . . . 52 3.9 Desensitization in spectrum analysis. . . . . . . . . . . . . . . . . . . . . . . 53 3.10 DC1 and DC2 vs. test time in frequency response measurement. . . . . . . . 55 3.11 A(f) vs. test time at LSB frequencies in IP3 measurement. . . . . . . . . . . 58 3.12 Phase accumulation in NCO. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.13 FIMP detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.14 FIMPs vs. GIMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.15 GIMP detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.16 Free-run and HFIMP accumulation in frequency response measurement. . . . 65 3.17 Accuracy vs. frequency with respect to number of HFIMP in frequency re- sponse measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.18 Common FIMP distribution along time. . . . . . . . . . . . . . . . . . . . . 69 3.19 Common GIMP detector for IP3 measurement. . . . . . . . . . . . . . . . . 70 3.20 Comparison among di erent accumulations in IP3 measurement. . . . . . . . 72 3.21 Accuracy of P vs. frequency in IP3 measurement. . . . . . . . . . . . . . . 73 4.1 Diagram for a typical DDS system. . . . . . . . . . . . . . . . . . . . . . . . 78 4.2 Signal-to-quantization noise ratio vs. (N, M). . . . . . . . . . . . . . . . . . 81 4.3 Logic implementation of quadrature LUT-based NCO. . . . . . . . . . . . . 82 4.4 Illustration of vector rotation in di erent coordinate systems. . . . . . . . . . 84 4.5 Illustration for operations in generalized CORDIC. . . . . . . . . . . . . . . 85 4.6 Logic implementation of iteration stage in pipelined CORDIC. . . . . . . . . 88 4.7 The SNR of conventional CORDIC vs. N and n. . . . . . . . . . . . . . . . 90 x 4.8 A carry-save adder (CSA) performing a hybrid addition. . . . . . . . . . . . 93 4.9 Illustration of Z-path in DCORDIC. . . . . . . . . . . . . . . . . . . . . . . 96 4.10 Phase oscillation in the conventional CORDIC. . . . . . . . . . . . . . . . . 98 4.11 Comparison among di erent table methods. . . . . . . . . . . . . . . . . . . 103 4.12 Top-level architecture of the porposed PDR-CORDIC. . . . . . . . . . . . . 104 4.13 Implementation of a partial dynamic rotation (PDR) stage. . . . . . . . . . . 106 4.14 Phase convergence comparison between 2-stage static and PDR rotators. . . 107 4.15 Illustration of LUT construction for CORDIC. . . . . . . . . . . . . . . . . . 108 4.16 Separation of phase word for LUT and rotation. . . . . . . . . . . . . . . . . 110 4.17 A simpli ed view of signal ow between two CORDIC stages. . . . . . . . . 111 4.18 An example of delay-optimized 6-input CSA. . . . . . . . . . . . . . . . . . . 113 4.19 Basic idea of angle recoding for PDR stages. . . . . . . . . . . . . . . . . . . 117 4.20 An illustration of angle recoding algorithm for PDR stages. . . . . . . . . . . 118 4.21 Logic implementation and signal ow diagram of 1st-order - lter. . . . . 121 4.22 Noise shaping e ect of 1st-order - lter. . . . . . . . . . . . . . . . . . . . 122 4.23 A variant of 1st-order - lter. . . . . . . . . . . . . . . . . . . . . . . . . 123 4.24 Signal ow diagram of a 3rd-order MASH-structure - . . . . . . . . . . . . 124 4.25 Noise shaping e ect of di erent - lter. . . . . . . . . . . . . . . . . . . . 125 4.26 A modi cation of MASH stage with order and bit-width controls. . . . . . . 126 4.27 Noise performance of the CORDIC-based NCO in the 1st-round fabrication. 130 4.28 Noise performance of the CORDIC-based NCO in the 2nd-round fabrication. 131 4.29 Spectrum and remaining phase when the worst-case SFDR for NCOs. . . . . 132 4.30 Randomizing e ect of - when the second worst-case SFDR for NCOs. . . 133 4.31 Layout diagram and die photo of the rst fabrication. . . . . . . . . . . . . . 134 4.32 Layout diagram of the second fabrication. . . . . . . . . . . . . . . . . . . . 135 xi List of Tables 3.1 Critical parameters of BIST system for simulation. . . . . . . . . . . . . . . 60 3.2 Simulation variables for frequency response measurement. . . . . . . . . . . . 67 3.3 Simulation variables for IP3 measurement. . . . . . . . . . . . . . . . . . . . 71 3.4 Number of slices/LUTs vs. MAC con gurations. . . . . . . . . . . . . . . . . 75 3.5 Resource usage of 256-point FFT implementations on Virtex II FPGAs. . . . 76 4.1 Synthesis results of sin/cos LUTs on Xilinx Spartan-3 FPGAs. . . . . . . . . 83 4.2 Elementary function calculations by generalized CORDIC algorithm. . . . . 86 4.3 Synthesis results of conventional CORDICs on Xilinx Spartan-3 FPGA. . . . 91 4.4 Possible f ig for PDR stages for N = 12 and M = 14. . . . . . . . . . . . . 114 4.5 Illustration of table method for 2 PDR stages when N = 12 and M = 14. . . 115 4.6 The group mapping relationship for angle recoding of PDR stages. . . . . . . 119 4.7 Speci cations of most important system performance merits. . . . . . . . . . 127 4.8 Important system parameters and techniques adopted in di erent NCO im- plementations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.9 System performances of the proposed CORDIC and comparison with state- of-art designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 xii List of Abbreviations ADC Analog-to-Digital Converter ATPG Automatic Test Pattern Generation BIST Built-In Self-Test BPF BandPass Filter BTM Bipartite Table Method CDCORDIC Critical Damped COordinate Rotation Computer DIgital Computer (CORDIC) CFIMP Common Fake Integer Multiple Period CGIMP Common Good Integer Multiple Period CIMP Common Integer Multiple Period CLA Carry Lookup-Ahead CORDIC COordinate Rotation DIgital Computer CS Carry Save CSA Carry Save Adder DAC Digital-to-Analog Converter DC Direct Current DCORDIC Di erential CORDIC DDS Direct Digital Synthesizer xiii DFF D Flip-Flop DFT Design For Test DNL Di erential Non-Linearity DRS Dynamic Rotation Selection DSP Digital Signal Processing DUT Device Under Test FCW Frequency Control Word FF Flip-Flop FFT Fast Fourier Transform FIMP Fake Integer Multiple Period FPGA Field Programmable Gate Array GIMP Good Integer Multiple Period HFIMP Half Fake Integer Multiple period I/O Input/Output IC Integrated Circuit IDDQ Quiescent Supply Current IIP3 Input 3rd-order Intercept Point IM Inter-Modulation IMP Integer Multiple Period INL Integral Non-Linearity xiv IP3 3rd-order Intercept Point LNA Low Noise Ampli er LO Local Oscillator LPF LowPass Filter LSB Least Signi cant Bit LSB Lower SideBand LTI Linear and Time Invariant MAC Multiplier/ACcumulator MASH Multi-stAge noise SHaping MOSFET Metal-Oxide-Semiconductor Field-E ect Transistor MRSS Multi-Resolution Spectrum Sensing MSB Most Signi cant Bit MSD Most Signi cant Digit MTM Multipartite Table Method MUX Multiplexer NCO Numerically Controlled Oscillator NF Noise Figure OBIST Oscillation Built-In Self-Test OIP3 Output 3rd-order Intercept Point ORA Output Response Analyzer xv P1dB 1dB Gain Compression Point PAR Parallel Angle Recoding PCB Printed Circuit Board PDR Partial Dynamic Rotation PDR-CORDIC Partial Dynamic Rotation CORDIC PI Primary Input PLL Phase Locked Loop PO Primary Output PPM Plus-Plus-Minus PSD Power Spectrum Density PVT Process/Voltage/Temperature RF Radio Frequency ROM Read-Only Memory RPD Radio Frequency Power Detector RTL Register Transfer Level SD Signed Digit SFDR Spur Free Dynamic Range SFF Scan Flip-Flop SINAD SIgnal-to-Noise And Distortion SNR Signal-to-Noise Ratio xvi SOC System On Chip SOP System On Package SPI Serial Peripheral Interface SSA Selective Spectrum Analysis THD Total Harmonic Distortion THD+N Total Harmonic Distortion Plus Noise TPG Test Pattern Generator USB Upper SideBand VGA Variable Gain Ampli er VHDL Very-high-speed integrated circuit Hardware Description Language VMA Vector Merging Adder xvii Chapter 1 Introduction to Analog and Mixed-Signal Built-In Self-Test (BIST) With the semiconductor process technology moving into the sub-micron and nanometer regime, the density and speed of the devices are far higher than before. This triggers the trend of e orts to integrate analog, mixed-signal, digital, and digital signal processing (DSP) subsystems into a single package or chip [1][2]. These subsystems used to be packaged separately and connected together with traces on printed circuit boards (PCBs) . Because of the parasitic capacitance from the package and PCB wires, the interconnections between the subsystems form one of the performance bottlenecks and greatly limit the system speed. However, with system on package (SOP) or system on chip (SOC) technology, the subsystems are able to communicate with each other with much shorter bond wires or even with the traces on the same silicon substrate. Not only does this save on the package and assembly cost, but also greatly reduces the parasitic e ects from the interconnection networks and helps to accelerate the signal interactions across the boundaries between subsystems. However, this trend also raises a lot of challenges on how to test these systems. First, while the level of integration increases, the number of input/output (I/O) pins does not increase accordingly. In other words, more implementation details are hidden inside the package or chip and thus the observability of critical signals becomes poorer in modern in- tegrated circuits (ICs) than traditional ones [2]. Secondly, the operational frequency of the latest circuits is so high that these circuits are very sensitive to their operating environment. For example, more and more ICs are running at the gigahertz range. It is not rare nowa- days for an IC to operate at tens of gigahertz. At these high frequency ranges, any kind of parasitic capacitance or inductance introduced by the test equipment would cause consid- erable performance variations and thus a ect the measurement accuracy. Thirdly, because 1 '0' '1' Thr eshold Figure 1.1: Simpli ed illustration of digital signals. the measurements are so sensitive, expensive dedicated test equipment has to be used for measurement and strict testing procedure has to be followed to guarantee the accuracy. All these issues pose a very challenging situation for probing the test points in modern ICs with test equipment. 1.1 Digital Testing vs. Analog Testing Digital subsystems usually contain a lot more components than analog ones. For ex- ample, it is now common to have millions of transistors for digital circuits, whereas usually fewer than 100 transistors are included in analog circuits [2]. However, the fact is that the testing of digital circuits is much less di cult. As illustrated in Figure 1.1, digital signals live in a world of either ?0? or ?1?, where everything is clearly de ned and di erentiable. A correctly designed digital circuit is expected to perform identically to its simulated behavior. If not, it is most likely that the unexpected behavior is caused by the defects in the fabrica- tion process. Di erent fault models, such as stuck-at faults, bridging faults, etc., have been developed to model these defects and ease the test generation and test evaluation [2]. For example, the most widely used stuck-at-0 and stuck-at-1 faults are modeled by assigning a xed value (?0? or ?1?) to a single line in a digital circuit regardless of inputs [2]. This simple 2 fault model allows us to inject faults into the gate-level description of a digital circuit, to ap- ply di erent test vectors to the circuit in behavior simulation (a.k.a. fault simulation in this context), to evaluate the fault coverage of the applied vectors, and to choose the vector with best fault coverage for circuit testing. The introduction of automatic test pattern generation (ATPG) algorithms even eliminates the necessity of human involvement and automates the process of searching test vectors [2][3]. In order to overcome the issues of limited observability and controllability in devices under test (DUTs) , the concept of scan test has been developed and widely adopted in digital testing. By replacing regular D ip- ops (DFFs) with scan ip- ops (SFFs), the ip- ops (FFs) at the critical test points can be connected together to form a scan chain [4]. In the normal mode, every SFF works as a regular DFF. However, in the scan mode, a test vector could be shifted into the scan chain bit by bit. Once all the data is shifted in and the test vector is ready, the SFFs are switched to the normal mode. After a certain number of clock cycles, the SFFs will then be switched to the scan mode and the internal signals captured by the SFFs could be shifted out of the DUT bit by bit. The scan test employs just four I/Os, three primary inputs (PIs) and one primary output (PO) , and makes it possible to manipulate and monitor any number of critical nodes, where FFs reside, in a circuit. It is because of the well-developed fault models and matured behavior simulation that the test generation for a digital DUT can be developed independently regardless of functional behavior of the DUT. This methodology proves to be very e ective for testing digital circuits, therefore, the concepts of ATPG and design for test (DFT) have been incorporated into the standard digital IC design ow and widely supported by various CAD tools. The testing of analog ICs, however, has fallen far behind and is typically performed manually. There are several reasons responsible for the di culties encountered in the analog testing. First, the e ciency of the analog circuits comes from the complex nature of the analog signals on both time and amplitude. Unlike the digital domain where only pulse 3 t x(t) DC O f f se t Vpp Peroid I ni tia l Phas e digi tal code output volt age Nonline arity i n D AC Figure 1.2: Interested characteristics in analog signals. sequences, shown in Figure 1.1, are of interest, waveforms in other shapes, such as sinu- soidal and modulated waveforms, are also widely adopted in analog circuits. Because of the continuous nature, the details of the waveforms are also very important. Some of the signal characteristics which might be of interest in analog testing are exempli ed in Figure 1.2. They include the initial phase, DC o set, period, peak-to-peak voltages, instantaneous voltage, etc. It is the versatile way to carry information that makes the analog circuits very e cient in terms of area and speed. It is also the versatile way to carry information that makes analog testing challenging because it is very di cult to build an abstract model to consider all these ways of information carriage and the faults which might happen in the carriage. Secondly, the absolute tolerances of semiconductor device parameters can vary by 20%, sometimes even 30% [5]. The causes are many fold. It could be caused by the process vari- ation during the fabrication, the voltage variation on the power supply, or the temperature variation from the environment (a.k.a. process/voltage/temperature (PVT) variation). Fur- thermore, the trend of SOC and SOP considerably increases the complexity and diversity of the environment where circuits might reside, so the e ects such as substrate coupling, cross 4 talk, and other electric/electromagnetic e ects must be considered for accurate analog simu- lations [6]. However, this usually involves building very complex circuit models. In addition, as the number of devices in a circuit increases, the complexity and execution time of the circuit model increases so quickly that it makes this kind of simulation and analysis almost impossible to be completed in a reasonable time duration. The two obstacles mentioned above prevent the analog testing from being studied and analyzed in a fashion independent of DUTs as in digital testing. 1.2 Analog Testing Techniques Most of the existing analog testing methods fall into one of two categories, structural (defect-based) testing or functional (speci cation-based) testing. The functional testing is the standard approach to perform analog testing and o ers very good accuracy. But it usually requires expensive dedicated test equipment and increases the cost of testing by a considerable amount. The concept of structural testing was introduced to attempt to solve this problem. It aims at providing an alternate set of measurements with more relaxed requirements instead of directly measuring speci cations. For example, usually a high fre- quency waveform generator is needed to produce the necessary radio frequency (RF) stimulus to drive a RF DUT; also di erent RF test equipment, such as a spectrum analyzer and noise gure (NF) analyzer, have to be used for measuring just two of the DUT?s speci cations: gain and NF. However, the indirect measurement proposed in [7] only utilizes the bias control voltage of a RF power ampli er as the test stimulus, measures its bias current, and predicts speci cations of gain, NF , etc. based on the bias measurement. By doing so, the demand for dedicated RF test equipment could be eliminated. 1.2.1 Structural Testing The theoretical background for structural testing can be illustrated as in Figure 1.3 [7][8]. The parameters of circuit components tend to vary from chip to chip (for same design) and 5 Par amet er Spac e P Speci fication Spac e S Me asurement Spac e M Regression Equat ion operation region of a "GOO D" sys tem ideal val ue Figure 1.3: Parameter variation and its e ect on speci cation and measurement. from time to time (for the same chip) because of PVT variations. It is undoubted that the parameter variation will also cause the variation on both the circuit speci cations and the indirect measurements. So if a mapping function between measurement space M and speci cation space S (f : M7!S) could be found, the circuit speci cations can be calculated from the indirect measurement. According to [7][8], f can be derived from g and h with nonlinear statistical multivariate regression techniques, where (g : P 7!S) and (h : P 7!M) are the mapping relationships between the parameter space P and speci cation space S, and the parameter space P and measurement space M respectively. As far as g and h are concerned, they are usually found by using circuit simulations. If the one-to-one map relationship f does exist for a DUT, it is not mandatory to nd the exact f for the purpose of fault detection. In other words, the criteria to di erentiate faulty and fault-free could be developed based on indirect measurements instead of the speci cations. A work ow of analog fault detection based on fault simulation is summarized in Figure 1.4, where the faults could be catastrophic faults (a.k.a. hard faults) and parametric faults (a.k.a. soft faults). The catastrophic faults are used to model the manufacturing defects 6 which fail a DUT?s basic operation, such as open and short on signal traces. The paramet- ric faults happen when the parameters of circuit components vary too much to stay within the acceptable range. Theoretically, the candidates of test stimulus could be any arbitrary waveform. However, considering the di culty of arbitrary waveform generation, the prac- tical choices could be piecewise linear [9], mutli-tone sinusoids [10][11], digital pulse trains [12], etc.. In the fault simulation, a number of fault-free DUTs (with acceptable process variations injected) and a number of faulty DUTs (with faults injected) are fed into a circuit simulator and driven by one of multiple possible test stimuli. Then the simulated response (indirect measurements) of the fault-free and faulty DUTs are recorded and analyzed by an optimization process. From the analysis results, the parameters of the test stimulus or even its basic shape could be adjusted to make the two categories of responses easily di er- entiated from each other. Through such a feedback system, it is believed that an optimal test stimulus could be reached in the end and applied in the actual testing to drive the real DUT. However, because of the limited accuracy and creditability of the analog simulation, the real performance of the obtained test stimulus may be worse than predicted. Under such situation, it is useful to form another feedback to the optimization process to adjust test stimulus again. Though the work ow looks very reasonable and feasible, there are some potential issues that limit its practical value. This ow works ne for catastrophic faults. In most cases, when a catastrophic fault occurs, a circuit behaves so di erently from its ideal response that a faulty circuit can be easily identi ed. However, this becomes more di cult with parametric faults since a typical parametric variation in IC fabrication could be as large as 30%. Now the dilemma is how large a parameter variation should be considered as a parametric fault. If a small variation is de ned, there will be additional yield loss. On the other hand, the rate of test escape will be increased if a large variation is de ned. Therefore, there is lack of well-accepted fault models in analog testing [1]. 7 DUT Faults Simul ationSimul ation Possi ble T e st Stim ulus es Fault -Free Response Faulty Response Optim ization Proce ss Real DUT Testing Results Optim al Test Stim uli Variations Figure 1.4: Work ow of analog structural testing. The other issue of the ow lies in the simulation for analog circuits. First, as the transistors shrink its size, the non-ideal e ects in these tiny transistors are becoming more and more serious. Second, the complexity and diversity of the environment where analog circuits reside increases considerably, and thus it has more and more impact on circuit performance. These two factors increase demand for complex and accurate circuit models. But it is very di cult to consider all the e ects in simulations. Thus, the analog simulation can only provide limited accuracy and creditability. It is common that the measurements from real analog ICs are noticeably o from the simulated performance. However, both the signature extraction and selection of test stimulus in this work ow are based on the simulation, so this also raises doubts on creditability of the analog structural testing. Furthermore, a large number of Monte-Carlo simulations are usually required to study the distribution of the measurement space M and discover the fault-free space, where para- metric variations within acceptable range occur, and the faulty space, where parametric 8 faults happen. These simulations usually require considerable execution time and raise an- other issue of analog structural testing | e ciency. Because of these issues, structural testing is not widely used in industry although it has received considerable attention from researchers in literature [13][14][15][16][17]. 1.2.2 Functional Testing Functional testing is also known as speci cation-based testing and widely employed in industry. It directly measures the performance merits of DUTs, compares the measurement results against well-de ned speci cations, and identi es the faulty circuits if they fall outside of provided tolerance limits. Because the functional testing is done against speci cations, it usually guarantees very high test accuracy. However, this method is usually performed manually with expensive test equipment and sometimes strict testing procedures have to be followed to capture accurate measurement results. Furthermore, some pieces of the equip- ment are dedicated for very limited measurements and oftentimes di erent equipments have to be used to fully characterize one DUT. Therefore, the traditional methodology of manual functional testing is more and more costly and time consuming. For example, the RF IC test cost could be as high as 50% of the total cost, depending on the complexity of the func- tionality to be tested [10]. Therefore, it becomes attractive to automate the testing process with low-cost and built-in self-test (BIST) circuitry. It is also most e ective to consider testing in the product cycle as early as possible [2]. Although it is inevitable that the BIST circuity will bring some resource overhead to a system, with properly designed BIST, the cost of added test hardware will be more than compensated for by the bene ts in terms of reliability and the reduced testing and maintenance cost [18]. 1.2.3 Analog and Mixed-Signal Built-In Self-Test Though the BIST technology is well developed and adopted for digital circuits, BIST dedicated for analog circuits is still in its early stage. A few BIST techniques have been 9 proposed to perform the on-chip analog testing [1]. Most of the analog and mixed-signal BIST approaches fall into the following two categories: intrusive and non-intrusive. The intrusive BIST requires mandatory modi cations to DUTs while the non-intrusive BIST leaves the DUTs untouched. Intrusive BIST The intrusive BIST approaches need to modify the original topology of a DUT for the purpose of monitoring or mode control. The current-based RF BIST approach proposed in [6] inserts a current sensor in the DUT?s bias network, monitors the bias current, and analyzes the current signature to tell if catastrophic or parametric faults happen in the DUT. A similar approach was proposed in [19] and uses a built-in current sensor to measure IDDQ for defect detection. In addition to current, other signals in DUTs can also be measured to test devices. For example, by inserting a test ampli er and two RF peak detectors, [20] claims to be able to utilize input impedance and DC voltage measurement to extract gain, noise gure, input impedance, and input return loss of a low noise ampli er (LNA). However, it is believed that this approach has very little practical applicability due to the massive overheads and signi cant intrusion on the DUT [6]. Another well-known family of intrusive BIST is the oscillation BIST (OBIST). This approach was rst proposed in [21]. With OBIST, an analog DUT has two working modes | normal and test mode, and is able to switch between the modes through external controls. The DUT acts as usual in normal mode; however, during test mode, the DUT is recon gured to form an oscillator and its oscillation frequency exhibits a strong dependence on various parameters of the circuit components involved in the oscillator. In other words, the DUT?s circuit parameters can be estimated based on the oscillation frequency and thus used for fault detection. However, because there is no universal methodology to transform a DUT into an oscillator, the e ort of building OBIST with minimal modi cations is not trivial. 10 It is obvious that the intrusive BIST approaches require no on-chip test pattern gen- erator (TPG) and thus can be implemented with small hardware overhead. However, they modify the original topology of the DUT to perform indirect measurements of DC current, DC voltage, oscillation frequency, etc., which could be captured with much looser require- ments. Therefore, essentially the intrusive BIST approaches are on-chip implementations of structural testing, thus a number of fault simulations are required to extract the measure- ment space and build the relationship between the indirect measurements and the possible catastrophic or parametric faults. Furthermore, the mandatory modi cations to the original circuit structure may also cause undesired performance variations. Non-Intrusive BIST The non-intrusive BIST applies no modi cations to DUTs and usually incorporates a test pattern generator (TPG) and an output response analyzer (ORA) . The former produces the necessary test stimulus to drive a DUT and the latter analyzes the output of the DUT to tell whether the DUT is faulty or fault-free. An on-chip ramp generator was proposed in [22] for measuring the nonlinearity of analog- to-digital converters (ADCs). Linear ADCs are supposed to produce a linearly increasing digital output to represent a linearly increasing analog input. However, real ADCs always introduce errors in the process of conversion and causes nonlinearity. Integral nonlinearity (INL) and di erential nonlinearity (DNL) are two of the most important speci cations for ADCs and a linear stimulus are usually required for measuring them [23]. The on-chip ramp generator provides a BIST alternative for these measurements. However, the measurement accuracy is greatly limited by the linearity of the on-chip ramp generator [10]. While applying an impulse to a linear, time invariant (LTI) system, the system output is the system transfer function which fully characterizes the system?s dynamic behavior. Thus, impulse response based testing has been utilized in [24][25]. The on-chip impulse generation 11 was suggested in [26] to test analog DUTs. It greatly simpli es the circuit complexity for gen- erating test stimulus; however, it requires analog fault models and Monte-Carlo simulations to extract the signatures of faulty and fault-free DUTs. The mixed-signal BIST approach given in [17] provides a variety of test waveforms and utilizes di erent accumulation modes for fault detection of a wide range of analog circuits. Its TPG is able to produce test waveforms of saw-tooth, reverse saw-tooth, triangular wave, pseudo-random, DC, step, pulse, frequency sweep, and ramp. The ORA uses the nal sum in its accumulator as the DUT?s signature. By comparing the extracted signature with a prede ned range of values, the DUT?s pass/fail status can be determined. Because this approach is based on structural testing, it has the similar issues as fault models and fault simulation. In order to perform a suite of analog functionality tests, such as frequency response, linearity, harmonic spur, signal-to-noise ratio (SNR) and NF measurements in a BIST envi- ronment, the frequency spectrum of the DUT?s output response needs to be measured by an ORA. Reference [27] utilizes an fast Fourier transform (FFT) processor to perform on-chip spectrum analysis. However, given a digital input with N samples, an FFT processor re- quires around N log2(N) multipliers and adders [28]. Such a prohibitive hardware overhead and power consumption prevent it from being an e cient BIST unless the FFT is an inherent component of the system. In contrast, analog spectrum analysis techniques try to perform the spectrum analysis in the analog domain and could be implemented with much less hardware overhead. The switched-capacitor spectrum analyzer proposed in [29] employs a switched-capacitor sine wave generator as the TPG and its ORA consists of a bandpass lter (BPF) , a variable gain ampli er (VGA), and a ADC. Because of the limitations of the switched-capacitor TPG, this BIST approach works at low frequency and is only able to measure spectrum at the frequency of fundamental and harmonics. The multi-resolution spectrum sensing (MRSS) technique proposed in [30] suggests correlating RF signals to time-frequency windows with 12 analog circuits. Since the windows are produced by digital window generator, it o ers the exibility to control the type and duration of the windows and thus the ability of multi- resolution of bandwidth. It is also reported in [31] that the RF power detector (RPD) was employed to perform on-chip RF voltage measurement. Although these BIST approaches o ers very low area overhead, all of them su er from limited dynamic range and coarse frequency sweeping due to the nature of analog processing. A fully digital selective spectrum analysis (SSA) technique was proposed in [10][32]. This approach includes a direct digital synthesizer (DDS)-based TPG and multiplier/accumulator (MAC)-based ORA and is capable of accurate frequency response, nonlinearity, spur search, and SNR measurements. The ORA consists of two MACs where the DUT output is mul- tiplied with an in-phase reference at the frequency under analysis and accumulated in one MAC and a similar procedure occurs in the other MAC but with an out-of-phase reference. Thus, the in-phase and out-of-phase components of the output at this frequency can be ex- tracted and used for calculations of magnitude and phase. Because the signals are in digital form, it can achieve very ne frequency resolution and provide accurate results with wide dynamic range. Since the SSA only analyzes the spectrum of one frequency point at a time, it can be implemented with much simpler circuitry than FFT-based BIST. Other Bene ts of BIST The concept of the adaptive control has been known and studied for decades [33]. The technology is mainly used in industrial systems whose critical parameters vary over time or with environmental variations, such as temperature, external pressure, humidity, etc. Its basic theory is to include an adaptive controller in a time-varying or environmentally sensitive system which can monitor the performance of the system and adjust it accordingly such that the performance variation can be diminished to an acceptable or even negligible level. However, its applications were restricted by the intensive computation required for adaptive control algorithms. 13 System BIST Circui try Tunabl e Circui try input output Figure 1.5: General model of an adaptive mixed-signal system with BIST technology. The advance of BIST technology provides a system not only the capability to test itself, but also an e cient means for calibrating, compensating, and adjusting the analog circuitry adaptively [10][32]. It is more than appropriate to be applied in a mixed-signal system with supports for adaptive control. The general model of an adaptive mixed-signal system built with the proposed BIST technology is illustrated in Figure 1.5. First the BIST circuitry captures the system output, through which the critical parameters of the system performance are determined in real time. Then the built-in tunable circuitry, such as capacitor banks, resistor banks, etc., will be adjusted according to the measurement results, such that the system variations could be compensated correspondingly. For example, if the cut-o frequency of the system deviates from the expected value, another capacitor in the capacitor bank can be activated to stabilize the cut-o frequency. If the linearity of a system is degraded because of increased interference or signal strength, the bias current of an ampli er in the system can be adjusted accordingly in the tunable circuitry. However, the key factor which determines the performance of an adaptive system, illustrated in Figure 1.5, is to accurately measure the functional parameters of the system with the BIST circuitry. Recently more and more eld programmable gate arrays (FPGAs) are adopted in var- ious mixed-signal systems for their ability to be recon gured in the eld to implement a desired function according to the real-time demands. Furthermore, with FPGAs in the digi- tal portion of a mixed-signal system, the FPGA can be recon gured with the BIST circuitry only when needed for analog test and measurement; otherwise, the normal system function 14 would reside in the FPGA such that there is no area or performance penalty associated with the BIST circuitry. 1.3 Organization of the Dissertation In this dissertation, we will investigate and discuss the design and implementation of the proposed SSA-based mixed-signal BIST in detail. This proposed BIST architecture has the ability to drive an analog DUT with one-tone or two-tone stimulus and conduct spectrum analysis on the DUT?s output. Therefore, it is able to perform a suite of analog measurements, such as frequency response, nonlinearity, etc.. The dissertation is organized as follows. Chapter 2 brie y presents the spectrum-based analog speci cations and the basic architecture of the SSA-based BIST. In Chapter 3, the theoretical background of the SSA- based ORA and its equivalency to FFT is studied; then the proposed integer multiple period (IMP) accumulations for di erent analog measurements and the performance improvement in terms of test time and accuracy are investigated. In Chapter 4, one of the most important components, the numerically controlled oscillator (NCO), and the coordinate rotation digital computer (CORDIC) algorithm for its implementation is explored in depth. Finally, the dissertation is concluded with remarks in Chapter 5. 15 Chapter 2 Overview to Spectrum-Based Analog Testing While analyzing a system, it is common to assume the system as an LTI system be- cause a LTI system has some very attractive features. First, a LTI system can be fully characterized by its response while applying an impulse to its input. That is also why the impulse response is called the system transfer function. Second, the system response with any arbitrary input can be calculated from the convolution of the input to the system trans- fer function. However, this assumption does not always hold true for analog circuits. Both the metal-oxide-semiconductor eld-e ect transistors (MOSFETs) and bipolar transistors exhibit strong nonlinear behaviors with respect to their input voltage (gate-source voltage for MOSFETs and base-emitter voltage for bipolar transistors) in their active region. The former supplies a drain current which is the square function of its gate-source voltage, while the latter does a collector current which is the exponential function of its base-emitter volt- age. In order to simplify the complexity of the circuit analysis, the concept of small signal was introduced to neglect the transistor?s nonlinear e ects and approximate the transistor?s operation with linear models. However, in reality, the nonlinearity of transistors still exists and leads to some interesting and important phenomena happening in analog DUTs. Furthermore, the reactive components are everywhere in analog circuits. They could be on-chip capacitors, inductors, or even the parasitic capacitance coming from the integrated components such as transistors, resistors, metal traces, etc. All these components make ana- log DUTs behave di erently at di erent frequencies because their impedance heavily depends on the frequency. Though they do not demand power consumption, the charging/discharging cycles of these devices introduces frequency-dependent delays to analog DUTs. Therefore, 16 Analog DUT x(t) y(t) Figure 2.1: Simpli ed system view of analog DUTs. nonlinear and frequency dependent models should be used instead to accurately describe an analog DUT. 2.1 Nonlinear and Frequency Dependent Model for Analog DUT A simpli ed system view of an analog DUT is drawn in Figure 2.1. In order to char- acterize such a system, the relationship between the input x(t) and output y(t) needs to be identi ed. Generally speaking, the relationship can be described by using a model as y(t) = h[x(t (f));f]; (2.1) where is introduced to model the delay the system introduces, and h( ) de nes how the system acts in terms of its input. Because an analog DUT usually exhibits di erent system characteristics at di erent frequencies, the frequency f is introduced for both h( ) and to show their dependence on frequency. Theoretically, any function can be expressed equiva- lently with its Taylor?s series as y(t) = 1X i=0 h(i)(0;f) i! x i(t ): (2.2) By replacing h(i)(0;f)i! with i(f), the above equation can be rewritten as a polynomial ex- pression of y(t) = NX i=0 i(f)xi(t ); (2.3) to describe an analog DUT [10][34]. In other words, the two frequency dependent variables i and need to be measured to characterize an analog DUT. The polynomial coe cients, 17 i, carry some of the most interesting physical properties of the DUT. For example, DC o set and gain are given by 0 and 1 respectively; i(i > 1) are introduced to model the nonlinearity of the DUT. The other variable describes the delay caused by the DUT at di erent frequencies. For simplicity purpose, oftentimes N = 3 is su cient to accurately describe an analog DUT. Because both i and are frequency dependent, Equation (2.3) could be quite com- plicated if the input x(t) is a wide-band signal. Usually multi-tone sinusoidal signals are applied to analog DUTs for testing because these signals just concentrate their energy at several frequency points. By doing so, Equation (2.3) becomes much simpler such that the interested information could be extracted with much less e ort. A multi-tone stimulus could be expressed as x(t) = X j Bj cos(2 fjt+ j); (2.4) where Bj, fj, and j is the amplitude, frequency, and initial phase of the j-th tone. Substitut- ing x(t) in Equation (2.3) with Equation (2.4), the DUT?s output, y(t), can be approximately given as y(t) 0 + 1 X j Bj cos[2 fj(t ) + j] + 2 X j Bj cos[2 fj(t ) + j] !2 + 3 X j Bj cos[2 fj(t ) + j] !3 ; (2.5) if the 4th and higher order terms are neglected. Therefore, not only does the output, y(t), appear at the input fundamental frequencies, but also the inter-modulation (IM) frequencies introduced by the 2nd and 3rd order terms. For simplicity, Equation (2.5) can be expressed in its equivalent form y(t) = MX k=0 Ak cos(2 fkt+ k); (2.6) 18 where Ak and k are the magnitude and phase of the output at frequency fk, which could be any possible fundamental and IM frequencies. Therefore, the DUT?s output spectrum has to be analyzed to nd all the possible pairs of (Ak, k) at frequency fk to characterize a DUT. 2.2 Spectrum-Based Speci cations In analog functional testing, usually only 1-tone or 2-tone stimuli are used to evaluate a circuit?s speci cations to ease the e ort of test stimuli generation. By using these stimuli, it is possible to measure a number of speci cations, including frequency response, nonlinearity, harmonic spurs, SNR, NF, etc. 2.2.1 Single-Tone Speci cations When a single-tone signal x(t) = Bcos(2 ft + ) is applied, the system output y(t) could be calculated from Equation (2.5) as y(t) 0 + 1Bcos[2 f(t ) + ] + 2B2 cos2[2 f(t ) + ] + 3B3 cos3[2 f(t ) + ]: (2.7) Based on the above equation, the following information, including frequency response, P1dB point, noise and spurs, could be extracted. Frequency Response If the system input x(t) is a small signal, its amplitude B is a small quantity and thus B3 << B2 << B. Based on this conclusion, we nd out that the third and four terms in Equation (2.7) become negligible in comparison with the second term. Therefore, the system 19 Freque ncy Spect r um M agni tude Ampli tude Response Single - T one Signa l Freque ncy Sw eeping ove r Bandw idth Figure 2.2: Illustration of frequency spectrum measurement with single-tone test. output y(t) can be further approximated as y(t) 0 + 1Bcos[2 f(t (f)) + ]: (2.8) From Equation (2.8), it can be observed that only the fundamental frequency component from the second term presents itself besides the DC o set 0. So the output spectrum (A, ) at frequency f can be expressed as A(f)[dB] = 20 log10[ 1(f)] [dB] + 20 log10B [dB]; (2.9a) (f) = 2 f (f): (2.9b) Because B and are the amplitude and phase of the input signal respectively, B and can be estimated by monitoring the input spectrum at frequency f. Bring the estimated B and back in Equation (2.9), the DUT?s frequency response, including the magnitude 1(f) and phase response 2 f (f), at the frequency f can be calculated based on the output spectrum A(f) and (f). As shown in Figure 2.2, by sweeping the frequency f over the band of interest and also calculating the spectrum di erence between the DUT?s input and 20 output at each frequency, the magnitude response 1 and phase response 2 f over the interested bandwidth can be characterized. 1dB Gain Compression Point If the single-tone input x(t) = Bcos(2 ft+ ) is fairly large, it is not true that B3 << B2 <