COMPACT MODELING OF SIGE HBTS USING VERILOG-A
Except where reference is made to the work of others, the work described in this
thesis is my own or was done in collaboration with my advisory committee.
This thesis does not include proprietary or classified information.
Zhiming Feng
Certificate of Approval:
Bogdan M. Wilamowski
Professor
Electrical and Computer Engineering
Guofu Niu, Chair
Professor
Electrical and Computer Engineering
Lloyd Stephen Riggs
Professor
Electrical and Computer Engineering
Stephen L. McFarland
Dean
Graduate School
COMPACT MODELING OF SIGE HBTS USING VERILOG-A
Zhiming Feng
A Thesis
Submitted to
the Graduate Faculty of
Auburn University
in Partial Fulfillment of the
Requirements for the
Degree of
Master of Science
Auburn, Alabama
August 7, 2006
COMPACT MODELING OF SIGE HBTS USING VERILOG-A
Zhiming Feng
Permission is granted to Auburn University to make copies of this thesis at its discretion,
upon the request of individuals or institutions and at their expense.
The author reserves all publication rights.
Signature of Author
Date of Graduation
iii
VITA
Zhiming Feng, son of Baogui Feng and Wenzhen Bian, was born on 29 April, 1973,
in Daan, Jilin Province, P. R. China. He received his BS degree from Jilin University
in 1995, majoring in Electronics and Information Systems. In Spring 2003, he was ac-
cepted into the Electrical and Computer Engineering Department of Auburn University,
Auburn, Alabama, where he has been pursuing his Masters degree.
iv
THESIS ABSTRACT
COMPACT MODELING OF SIGE HBTS USING VERILOG-A
Zhiming Feng
Master of Science, August 7, 2006
(B.S., Jilin University, July, 1995)
123 Typed Pages
Directed by Guofu Niu
SiGe HBTs, integrated with CMOS, have demonstrated their usefulness in digital
and analog circuit designs for wired and wireless telecommunication applications over
the past decade. Of critical importance to successful circuit design is the availability of
accurate device compact models and a good understanding of internal device character-
istics, especially for analog RFIC designs.
A technique that is beginning to be applied in research on device physics and com-
pact modeling based on the Verilog-A hardware language is presented in this thesis. This
new Verilog-A based model can be easily modified and implemented into circuit simu-
lators such as Cadence and Agilent ADS without the need to interface with simulators.
Moreover, the internal currents, charges, and noise sources are accessible, which is not
the case when built-in models are used in circuit simulators. Using the Verilog-A based
VBIC model, three applications for SiGe HBT noise modeling and VBIC temperature
mapping models are presented.
v
First, a new inverse circuit simulation based low frequency noise extraction method
is proposed based on the Verilog-A based VBIC model. The low frequency noise of de-
vice biasing at high currents can be measured more accurately through this method.
Secondly, in order to better understand the di?erent phase noise upconversion mecha-
nisms involved in the base current 1/f noise and base current short noise in oscillator
designs, the internal I
BE
and the internal I
CE
were separated from the external I
BE
and
the external I
CE
using the Verilog-A based VBIC model. Clearly, the noise generat-
ing current, I
BE
, is only a small portion of the terminal I
B
. In the third application,
a group of improved temperature mapping models that can be used to model of DC
currents down to 43 K are presented. The new VBIC based model was implemented us-
ing Verilog-A, compiled into binary code, and dynamically linked to a circuit simulator
through its compact modeling interface. Excellent Gummel and output fitting across a
wide temperature range from 300 K down to 43 K were achieved on a 50 GHz SiGe
HBT device.
Finally, the intermodulation linearity simulation capability of the VBIC, HICUM
and Mextram models were evaluated using harmonic balance in a 200 GHz SiGe HBT
technology. The impact of avalanche and selfheating on IIP3 were examined and a weak
avalanche shown to have a significant impact on IIP3. These results provide valuable
new insights into the device physics underlying linearity behavior and the use of quan-
tified simulations for data comparison of linearity that will be useful for both designers
and modelers.
vi
ACKNOWLEDGMENTS
I would like to express my gratitude to my supervisor, Dr. Guofu Niu. Without
him, this thesis would not have been possible. His patience and encouragement have
carried me through di?cult times, and his insights and suggestions have helped to shape
my research skills. I would also like to thank the other members of my committee,
Dr. Bogdan Wilamowski, and Dr. Lloyd Stephen Riggs for the assistance they have
provided.
I would like to thank Ying Li, Chendong Zhu, and Laleh Najafizadeh for helping
with device measurement, and Jun Pan for useful discussions on Cadence simulation
tools. I thank all the students in our research group, Yan Cui, Jin Tang, Xiaoyun Wei,
Kejun Xia, Yun Shi, Hua Yang, and Muthubalan Varadharajaperumal for the vivid dis-
cussions we have had on various topics and the fun of being a member of this fantastic
group. I am forever indebted to my family for the support they have provided me through
my entire life, and in particular I must acknowledge my wife and best friend, Yan Cui,
without whose love, encouragement and editing assistance, I would not have finished
this thesis.
This research would not have been possible without the financial assistance of
the National Science Foundation under grants ECS-0119623 and ECS-0112923, NASA
grant NNL05AA37C, and the Georgia Electronic Design Center at Georgia Tech. I am
also grateful for the assistance of C. Moore, M. Watson, M. Beatty, L. Nadeau of NASA,
E. Kolawa of JPL, and the IBM SiGe development group, as well the many contributions
vii
of the SiGe ETDP team, including: M. Mojarradi, B. Blalock, W. Johnson, R. Garbos,
R. Berger, F. Dai, L. Peltz, A. Mantooth, P. McCluskey, M. Alles, R. Reed, A. Joseph,
C. Eckert and J.D. Cressler.
viii
Style manual or journal used IEEE Transactions on Nuclear Science (together
with the style known as ?aums?). Bibliography follows van Leunen?s A Handbook for
Scholars.
Computer software used The document preparation package T
E
X (specifically
L
A
T
E
X) together with the departmental style-file aums.sty. The plots were generated
using VossPlot
R?
and MATLAB
R?
.
ix
TABLE OF CONTENTS
LIST OF FIGURES xiii
LIST OF TABLES xvi
1INTRODUCTION AND OVERVIEW 1
1.1 Basic Principles of SiGe HBT ...................... 2
1.2 Thesis Contributions ........................... 7
2VERILOG-A LANGUAGE 10
2.1 Introduction of Verilog-A ......................... 11
2.2 Verilog-A basics .............................. 13
2.2.1 Example: Simple Diode ..................... 14
2.3 Summary ................................. 24
3 VBIC MODELING 25
3.1 Modeling of Transfer Current ....................... 28
3.2 Modeling of Internal EB and BC Diodes ................ 39
3.3 Modeling of Quasi-Saturation ...................... 40
3.4 The Parasitic PNP Transistor ....................... 41
3.5 Temperature Mapping ........................... 42
3.5.1 Resistance ............................ 42
3.5.2 Capacitance ............................ 43
3.5.3 Knee current I
KF
......................... 43
3.5.4 Ideality Factor N
F
........................ 44
3.5.5 Saturation Current I
S
....................... 44
4VERILOG-A IMPLEMENTATION 47
4.1 Basic code description .......................... 47
4.2 Implementation into Simulators ..................... 49
4.2.1 Implementation into Agilent ADS ................ 49
4.2.2 Implementation into Cadence .................. 49
4.3 Main debugging issues .......................... 50
4.3.1 Syntax Errors ........................... 50
4.3.2 Convergence Problems ...................... 51
4.3.3 Logarithm Error ......................... 54
x
4.3.4 Noise Modeling .......................... 55
4.4 Comparison with built-in model ..................... 56
4.4.1 DC Simulation .......................... 57
4.4.2 ac Simulation ........................... 58
4.4.3 Noise Simulation ......................... 60
4.4.4 Large Signal Simulation ..................... 61
4.5 Summary ................................. 61
5USING VERILOG-A FOR SIGE HBT NOISE MODELING 63
5.1 Inverse circuit simulation for 1/f Noise ................. 63
5.2 Noise generating current in oscillators .................. 67
5.3 Summary ................................. 70
6TEMPERATURE SCALABLE MODELING OF DC CURRENTS 71
6.1 Evaluation of Temperature Mapping Models in VBIC .......... 73
6.2 Improved Temperature Mapping Models ................. 75
6.2.1 Improved N
F
Temperature Mapping Model ........... 76
6.2.2 Improved I
S
Temperature Mapping Model ........... 78
6.2.3 Improved I
KF
Temperature Mapping Model ........... 82
6.2.4 Temperature Mapping Models for R
th
and avc2......... 83
6.3 Simulation Results ............................ 84
6.4 Summary ................................. 87
7MODELING OF INTERMODULATION LINEARITY IN A 200 GHZ SIGE HBT
TECHNOLOGY 88
7.1 Standard Breakdown HBT ........................ 90
7.2 High Breakdown HBT .......................... 92
7.3 Impact of Avalanche and Self-heating .................. 95
7.4 Summary ................................. 96
8CONCLUSIONS AND FUTURE WORK 98
8.1 Conclusions ................................ 98
8.2 Future Work ................................ 100
BIBLIOGRAPHY 101
AVERILOG-A CODE WITH KEY IMPROVED TEMPERATURE MAPPING MOD-
ELS 105
A.1 Improved N
F
and N
EI
Temperature Mapping Models .......... 105
A.2 Improved E
a,true
, I
S
and I
BEI
Temperature Mapping Models ...... 106
xi
A.3 Improved I
KF
Temperature Mapping Model ............... 107
xii
LIST OF FIGURES
1.1 Energy band diagram of a graded-base SiGe HBT as compared to an
identically constructed Si BJT. ...................... 3
1.2 Comparison of Gummel characteristics of a comparably constructed
SiGe HBT and Si BJT. .......................... 4
1.3 Measured comparison of unity gain cuto? frequency f
T
as a function of
collector current for a comparably constructed SiGe HBT and Si BJT. . 5
2.1 Equivalent circuit of junction diode. ................... 14
2.2 Simulated Diode I
d
?V
id
and I
d
?V
d
curves. .............. 22
2.3 (a) Simulated Diode q
d
, q
di?
, and q
j
vs V
id
. (b) Extracted Diode C ?V
curves. ................................... 23
3.1 VBIC equivalent network ......................... 27
3.2 Band diagram of an intrinsic bipolar transistor. (a) V
BEI
= 0, V
BCI
= 0;
(b) V
BEI
> 0, V
BCI
> 0........................... 29
3.3 Zero bias charge Q
B0
, EB depletion charge Q
JE
, and CB depletion
charge Q
JC
in the neutral base region. .................. 34
4.1 (a) Gummel curve comparison of Verilog-A based VBIC model and
Cadence built-in VBIC model. (b) Output curve comparison of Verilog-
A based VBIC model and Cadence built-in VBIC model. ........ 57
4.2 S-parameters vs V
BE
curves of Verilog-A based VBIC model and Ca-
dence built-in VBIC model. ........................ 58
4.3 S-parameters vs f curves of Verilog-A based VBIC model and Cadence
built-in VBIC model. ........................... 59
4.4 f
T
vs I
C
of Verilog-A based VBIC model and Cadence built-in VBIC
model. .................................. 59
xiii
4.5 Bias and frequency dependence of NF
min
and R
n
of Verilog-A based
VBIC model and Cadence built-in VBIC model. ............ 60
4.6 P
out
vs P
in
of Verilog-A based VBIC model and Cadence built-in VBIC
model. .................................. 61
5.1 Small signal equivalent circuit assumed in the conventional method. . . 64
5.2 Comparison of S
I
BE
spectra extracted to the proposed inverse circuit
simulation and the conventional measurement method. V
CB
=2V,I
BE
=2
?A. .................................... 66
5.3 A simplified large transistor model. ................... 68
5.4 Comparison of terminal I
B
and internal I
BE
for the 50 GHz HBT. The
internal V
BE
is shown on the right y-axis. ................ 69
6.1 Comparison of Gummel curves from Cadence simulation results and
measurement data at low temperatures. .................. 72
6.2 Comparison of extracted isothermal N
F
and N
F
temperature mapping
model in VBIC. .............................. 74
6.3 Comparison of I
S
temperature mapping model in VBIC and extracted
isothermal I
S
parameters. ......................... 76
6.4 Improved N
EI
and N
F
model with new equations. ........... 77
6.5 E
a,true
as a function of temperature fitted using Eq. (6.27). ........ 82
6.6 Improved I
S
fitting with new E
a,true
model. ............... 83
6.7 Improved I
KF
fitting with new temperature mapping model. ...... 84
6.8 (a) ImprovedI
C
-V
BE
fitting with new models, and (b) ImprovedI
B
-V
BE
fitting with new models. .......................... 85
6.9 Improved DC output fitting at (a) 175 K, and (b) 43 K, with new models. 86
7.1 Comparison of measured and VBIC simulated S
11
& S
12
vs frequency
at V
CE
= 1.0 V, I
C
= 12.8 mA. Standard Breakdown HBT. ....... 90
xiv
7.2 Comparison of measured and VBIC simulated S
21
& S
22
vs frequency
at V
CE
= 1.0 V, I
C
= 12.8 mA. Standard Breakdown HBT. ....... 91
7.3 Comparison of simulated and measured IIP3 at V
CE
= 1.0, 1.3, 1.6 and
1.9 V. Standard Breakdown HBT. ..................... 93
7.4 Comparison of simulated and measured IIP3 at V
CE
= 1.3, 1.9, 2.5 and
3.1 V. High Breakdown HBT. ....................... 94
7.5 Comparison of simulated and measured M-1 at V
BE
= 0.65 V. Standard
Breakdown HBT. ............................. 96
7.6 Comparison of IIP3 simulated using di?erent combinations of avalanche
and self-heating settings and measured IIP3 at V
CE
= 1.9 V. Standard
Breakdown HBT. ............................. 97
xv
LIST OF TABLES
A.1 Parameters used for improved N
F
and N
EI
temperature mapping mod-
els. .................................... 105
A.2 Parameters used for improved E
a,true
, I
S
and I
BEI
temperature mapping
models. .................................. 106
A.3 Parameters used for improved I
KF
temperature mapping model. .... 107
xvi
CHAPTER 1
INTRODUCTION AND OVERVIEW
SiGe HBTs (heterojunction bipolar transistors), integrated with CMOS, have demon-
strated their superior abilities in digital and analog circuit designs for wired and wireless
telecommunication applications in recent years. Tremendous advances in fabrication
technology have led to the extreme scaling down of devices with corresponding perfor-
mance improvements. A 350 GHz peakf
T
SiGe technology was announced in 2003 [1],
that has led to the highest speed yet among current technologies. The rapid development
of this technology has made the study of device characteristics and modeling a high pri-
ority due to the unpredictable new features that have appeared with this device scaling.
Of critical importance to successful circuit design is the ability to implement accurate
device compact models, along with a good understanding of internal device character-
istics, especially for analog RFIC design. This indicates the need for a detailed study
of device characteristics and compact modeling techniques. Another important aspect
is the ease of modifying existing device compact models to keep pace with the rapid
development of modern technology and deal with the new features that continuously
arise with device scaling. This requires an improvement in the language tools used to
write portable device compact models that can be used with circuit simulators such as
Cadence and Agilent ADS. Moreover, mankind?s exploration of the universe calls for
robust circuit designs that will function in the extreme temperature environments found
1
outside the Earth?s atmosphere. Accurate device modeling over a wide temperature
range has desperately needed.
This thesis investigates both device physics and compact modeling using a new
technique ? the Verilog-A based VBIC (Vertical Bipolar Inter-Company) model, which
makes a portable device compact model for device simulator that can be easily modified
and implemented into circuit simulators without the need to interface with the simula-
tors. Moreover, the internal currents, charges, and noise sources are accessible, which
is currently not the case for the built-in models used in circuit simulators. Based on
the Verilog-A based VBIC model, three applications for SiGe HBT noise modeling and
VBIC temperature mapping models are presented. This introductory chapter briefly
reviews the basic principles of SiGe HBT, and provides an overview of the thesis.
1.1 Basic Principles of SiGe HBT
This section gives a brief overview of the DC and ac performance abilities of SiGe
HBTs. Only the final results are included. Detailed derivations can be found in [2].
The fundamental di?erences between the SiGe HBT and Si BJT (bipolar transistor)
are emitter-base (EB) and collector-base (CB) Si-SiGe heterojunctions. The essential
operational di?erences between SiGe HBT and Si BJT can be illustrated by considering
the schematic energy band diagram shown in Fig. 1.1. For simplicity, assume a constant
doping in the emitter, base and collector regions. The Ge mole fraction is linearly graded
from 0% near the EB junction to some maximum value near the CB junction. This
graded Ge profile creates an accelerating electric field in the neutral base.
2
Figure 1.1: Energy band diagram of a graded-base SiGe HBT as compared to an identi-
cally constructed Si BJT.
Germanium has a bandgap of 0.66 eV, which is considerably smaller than Silicon?s
bandgap of 1.12 eV. Hence, SiGe?s bandgap is less than the bandgap of Si and there is
a roughly 7.5 meV band o?set per 1% Ge. Adding Ge in the base primarily a?ects the
DC performance of SiGe HBT through the collector current density J
C
, which is pro-
portional to the minority carrier (electron) density in the base region. The Ge-induced
bandgap o?set exponentially increases the intrinsic carrier density and hence increases
the minority carrier density in the base region, leading to an increase in J
C
. Meanwhile,
because the emitter region is the same for both SiGe HBT and Si BJT, the base current
density J
B
is roughly the same. The Gummel curves for a SiGe HBT and a Si BJT are
compared in Fig. 1.2. The SiGe HBT and Si BJT have been identically processed to
3
allow unambiguous comparison. The SiGe HBT clearly has a much higher J
C
than the
Si BJT, although it has a similar J
B
. Accordingly, the DC current gain ?, defined as
J
C
/J
B
, is much higher in the SiGe HBT than in the Si BJT.
Figure 1.2: Comparison of Gummel characteristics of a comparably constructed SiGe
HBT and Si BJT.
In most RF and microwave circuit applications, it is the transistor frequency re-
sponse that limit system performance. An important figure-of-merit in bipolar transistor
is the unity gain cuto? frequency f
T
, which is given by
f
T
=
bracketleftbigg
1
g
m
(C
eb
+C
cb
) +?
b
+?
c
+?
e
bracketrightbigg
?1
(1.1)
4
where g
m
is the transconductance, C
eb
and C
cb
are the EB and CB capacitances and
?
b
, ?
c
, ?
e
are the base, collector and emitter transit times, respectively. Of these three
transit times, ?
b
is the primary portion that limits the maximum f
T
of a conventional
bipolar transistor. The built-in electric field created by the graded Ge content across the
neutral base region accelerates the minority carriers across the base region, resulting in
a decrease in ?
b
, and hence higher f
T
for a SiGe HBT. Fig. 1.3 shows a comparison of
the f
T
performance for a SiGe HBT and a comparably constructed Si BJT. Note that f
T
is increased from 35 GHz to 50 GHz by introducing a graded Ge mole fraction in the
base.
Figure 1.3: Measured comparison of unity gain cuto? frequency f
T
as a function of
collector current for a comparably constructed SiGe HBT and Si BJT.
5
A more relevant figure-of-merit for practical RF and microwave applications is the
maximum oscillation frequency f
max
, since it depends on both the f
T
and the device
parasitics. f
max
is given by
f
max
=
radicalBigg
1
8?C
cb
?
f
T
r
b
(1.2)
where C
cb
is the total CB capacitance and r
b
is the total base resistance. f
T
/r
b
ratio
needs to be increased to improve f
max
. For a double contact base, r
b
is related to the
product of base doping N
B
and base width W
B
by,
r
b
=
1
12q?
p
X
E
L
E
1
N
B
W
B
(1.3)
where X
E
is the lateral emitter width, L
E
is the lateral emitter length, and ?
p
is the
majority hole mobility in the base. For a conventional Si BJT, there is a tradeo?between
? and r
b
due to the base doping. Increasing the level of doping in the base will decrease
the minority carrier density in the base, resulting in a decrease in J
C
and, hence, ?.
Meanwhile, to reduce r
b
, the base doping needs to be increased. With careful bandgap
engineering, however, r
b
can be reduced by decreasing N
B
without compromising ?,
since ? can be increased exponentially by adjusting the Ge-induced bandgap o?set.
Moreover, as discussed above, f
T
is increased by the graded Ge content in the base. As
a result, it is possible to increase f
T
, and reduce r
b
without sacrificing ? performance,
leading to an increase in the f
T
/r
b
ratio, and hence improve f
max
for a SiGe HBT.
6
1.2 Thesis Contributions
This thesis presents a new technique for use in investigating device physics and
compact modeling using Verilog-A hardware language. This new Verilog-A based
model can be easily modified and implemented into circuit simulators without the need
to interface with simulators. The internal currents, charges, and noise sources, which
are currently not available when existing built-in models are used in circuit simulators,
all become accessible using this technique.
The Verilog-A Language is introduced in Chapter 2. The essence of using Verilog-
A based compact modeling in place of low-level simulator code is explained in detail.
An example of Verilog-A based modeling is given to illustrate the use of the Verilog-A
language. Chapter 3 introduces the physics behind the VBIC model and the temperature
models in VBIC.
In Chapter 4, the VBIC model is realized in the new Verilog-A language, and im-
plemented into the circuit simulators Cadence and ADS. Several problems such as syn-
tax errors, convergence problems and numerical problems were encountered and their
solutionis are reported in this chapter. Noise models were added in the Verilog-A based
model to be consistent with the Cadence built-in model. The DC,ac, noise and large sig-
nal simulation comparisons between Verilog-A based VBIC modeling and the Cadence
built-in VBIC model revealed identical results.
Based on the new Verilog-A based VBIC model, two applications for SiGe HBTs
noise modeling are presented in Chapter 5. First, a new inverse circuit simulation based
7
low frequency noise extraction method is proposed based on the Verilog-A based VBIC
model. The low frequency noise of a device biasing at high current can be measured
more accurately through this method. Secondly, to better understand the di?erent phase
noise upconversion mechanisms of the base current 1/f noise and base current short
noise in oscillator design, the internal I
BE
and the internal I
CE
were separated from the
external I
BE
and the external I
CE
using the Verilog-A based VBIC model. Clearly, the
noise generating current, I
BE
, makes up only a small portion of the terminal I
B
.
A group of improved temperature mapping models for modeling of DC currents
down to 43 K are presented in Chapter 6. The new VBIC based model was imple-
mented using Verilog-A, compiled into binary code, and dynamically linked to a circuit
simulator (ADS) through its compact modeling interface. Excellent Gummel and output
fitting across a wide temperature range from 300 K down to 43 K were achieved for a
50 GHz SiGe HBT device.
Intermodulation linearity that relates to the selectivity of an RF receiver is another
important figure-of-merit for SiGe HBTs. In Chapter 7, the intermodulation linearity
simulation capability of the VBIC, HICUM and Mextram models is evaluated using
harmonic balance in a 200 GHz SiGe HBT device and the impact of avalanche and
self-heating on IIP3 are discussed. A weak avalanche was shown to have a significant
impact on IIP3 and the results provide new insights into the device physics underlying
the linearity behavior and quantified simulation data for comparisons of linearity that
will be useful for both designers and modelers.
Chapter 8 presents the major conclusions of this work.
8
Appendix A presents the code for the new Verilog-A based VBIC model, along
with a group of improved temperature mapping models for modeling DC currents down
to 43 K.
9
CHAPTER 2
VERILOG-A LANGUAGE
In most circuit simulators, compact models such as the built-in model are embed-
ded in the simulators and serve as the basic simulation function components. Mean-
while, the interfaces in the compact model define its connections with the simulators
and the analysis engine. As a consequence, an in-depth understanding of simulator ar-
chitecture and analysis engine is a basic requirement for model developers due to the
complexity involved, which extends far beyond the model descriptions. Moreover, any
changes in the models will require lengthy, recompilation and re-linking to the SPICE
program, which in turn increases the model implementation process period and reduces
the number of choices for end users. In addition, these kind of models are not portable
for use in di?erent simulators as a result of their own di?erently compiled model inter-
faces.
C (Spice3) programming has been the standard language for most compact models
used in circuit simulators since 1985 because of its flexibility and ease of compilation
for the simulators. However, writing the model source code is still a lengthy task. For
example, the BSIM4 model requires over 20k lines and could take an experienced engi-
neer months to write and debug.
10
2.1 Introduction of Verilog-A
Verilog-A (one of the subsets of Verilog-AMS), is derivated from IEEE 1364-1995
Verilog HDL and is an IEEE standard analog hardware description language that uses
modules to describe the structure and behavior of analog systems and their components
for multi-domain simulations (electrical, thermal, and mechanical). With the release
of the Verilog-AMS Language Reference Manual (LRM) version 2.2 by Accellera on
February 14, 2005 [3], many new features were added, making it possible to easily de-
velop new compact models for semiconductor devices such as transistors and diodes in
a standard language. Today, Verilog-A is widely accepted as a more powerful, portable,
suitable, and flexible language for compact model description.
Specialized features are provided by Verilog-A to create and use modules that en-
capsulate high-level behavioral descriptions of systems and components [3]:
? Verilog-A modules are compatible with Verilog-AMS HDL.
? Analog behavioral modeling descriptions are contained in a separate analog block.
? Branches can be named for easy selection and access.
? Parameters can be specified with valid range limits.
? Systems can be modeled by using expressions consisting of operators, variables,
and signals, including:
? a full set of operators including trigonometric functions, integrals, and deriva-
tives;
11
? a set of waveform filters to modify the waveform results for faster and more
accurate simulations, such as transition, slew, Laplace, and Z-domain;
? a set of events to control when a certain code is simulated;
? selection of the simulation time step for simulation control; and
? support for accessing SPICE primitives from within the language.
The major reason for choosing Verilog-A as a standard language for the compact
model is to avoid the need for complex interfaces in the circuit simulators [4]. With
the development of the modern semiconductor manufacturing processes, the period re-
quired for new device releases is becoming shorter and shorter, and the geometries of
the devices themselves are becoming smaller and smaller. The new equations written in
C for the new physical e?ects need to be installed into the circuit simulators in a very
short time. However, the simulator interface, which includes various functions such
as topology checking, parameter reading, Jacobian matrix and current vectors loading,
and value initializing, presents a significant barrier for model developers [4] [5]. Nor-
mally, an in-depth understanding of interfaces is more di?cult than the description of
the compact model, resulting in a slowdown when adopting a new model process. Since
Verilog-A is a simulator-independent standard language, the model developers no longer
need to deal with these specific details.
Moreover, Verilog-A is a higher-level language than the C programming language.
For example, the symbolic partial derivations of the charges and currents in compact
models can be automatically computed by Verilog-A simulators. Traditionally, partial
12
derivatives of the equations in a compact model for the Newton-Raphson algorithm need
to be written in the C programming language in circuit simulators.
From a device research standpoint, an important benefit of Verilog-A based com-
pact modeling is that users can access the internal currents, charges, and noise parame-
ters which cannot be modified in the built-in models traditionally used in circuit simu-
lators such as Spectre and ADS. This makes it possible for individuals or small research
groups to develop and modify a compact model according to their specific research
objectives. Three important applications based on a Verilog-A VBIC model will be
introduced in chapters 5 and 6.
2.2 Verilog-A basics
As an e?cient language for writing compact models, Verilog-A is both simple
and easy to learn. As mentioned previously, Verilog-A uses modules to describe the
structure and behavior of analog systems and their components. Here, the module can
be described mathematically by its terminals and external parameters. Both electrical
and non-electrical system descriptions can be used with Verilog-A. The concepts of
nodes, branches, and terminals are provided to support the conservative and signal-flow
descriptions. In addition, Kirchho??s Potential and Flow Laws (KPL and KFL) are
obeyed in the analog behavior solutions, and defined by the quantities associated with
the analog behaviors.
13
2.2.1 Example: Simple Diode
Diode Model Equations
The example of a simple junction diode will provide a better understanding of the
utility of Verilog-A. Fig. 2.1 shows the equivalent circuit of a junction diode used in this
example. Here, only a brief discussion regarding the usage of Verilog-A is given. For
more detailed description, please refer to [3] [5] and [6].
int
a
c
G
min
i
d
q
d
V
id
R
S
Figure 2.1: Equivalent circuit of junction diode.
A single linear resistor R
S
represents both the external contact resistance and any
voltage drop in the neutral n and p regions. The voltage drop in the neutral regions is
significant under a high level injection condition. G
min
is the minimum conductance,
which is a constant selected for numerical reasons. The dc characteristic of the device
14
is modeled by a nonlinear current source i
d
with the ideal diode equation
i
d
= i
s
exp
parenleftbigg
V
id
nV
T
? 1
parenrightbigg
(2.1)
where i
s
is the saturation current, V
T
= kT is the thermal voltage, n is the emission
coe?cient, and V
id
is the intrinsic voltage between nodes int and c.
The charge storage element q
d
in Fig. 2.1 models both the di?usion charge storage
by injected minority carriers and the charge stored in the depletion region. The total
charge q
d
is given by
q
d
= q
di?
+q
j
(2.2)
q
di?
is the di?usion charge, which depends on the transit time parameter tt,
q
di?
= i
d
tt (2.3)
with a di?usion capacitance c
di?
(V ),
c
di?
(V ) =
dq
di?
dV
=
1
nV
T
i
d
tt. (2.4)
q
j
is the stored charge in the depletion region,
q
j
=
integraldisplay
V
id
0
c
j
(V )dV (2.5)
15
where c
j
(V ) is the junction capacitance. Substituting (2.3) and (2.5) into (2.2), we have
q
d
= i
d
tt+
integraldisplay
V
id
0
c
j
(V )dV (2.6)
Assuming an abrupt junction, c
j
(V ) is:
c
j
(V ) =
c
j0
radicalBig
1 ?
V
id
?
(2.7)
where c
j0
is zero voltage junction capacitance, and ? is the built-in potential. However,
(2.7) has numerical problems at V
id
? ?, and c
j
(V ) is not continuous at V
id
= ?.To
solve this discontinuity problem, a factor f
c
is introduced: 0 <f
c
< 1. If V
id
<f
c
?,
(2.7) is used. IfV
id
? f
c
?, c
j
(V ) begins at the capacitance determined by the theoretical
curve c
j
(f
c
?), and with a slope determined by the slope of the tangent to the theoretical
curve at the break point V
id
= f
c
?,
c
j
(V )
vextendsingle
vextendsingle
V
id
?f
c
?
=
c
j0
(1?f
c
)
3
2
bracketleftbigg
1 ?
3
2
f
c
+
V
2?
bracketrightbigg
(2.8)
Therefore, taking integration of (2.7) and (2.8), the total charge q
d
is as follows. If
V
id
<f
c
?,
q
d
= i
d
tt+ 2c
j0
?
?
?
1 ?
radicalBigg
1 ?
V
id
?
?
?
(2.9)
16
If V
id
? f
c
?,
q
d
= i
d
tt+ 2c
j0
?
bracketleftBig
1 ?
radicalbig
1 ?f
c
bracketrightBig
+
c
j0
(1?f
c
)
3
2
(V
id
?f
c
?)
parenleftbigg
1 ?
5
4
f
c
+
V
id
4?
parenrightbigg
(2.10)
Verilog-A code
The Verilog-A code for the above simple diode model is as follows.
?include "disciplines.vams"
?include "constants.vams"
?define GMIN 1.0e-12
module diodefinal (a, c);
inout a, c;
electrical a,c,int;
branch (a,int) v_rs;
branch (int,c) v_id;
parameter real is=10f from (0.0:inf);
parameter real n=1.0 from (0.0:inf);
parameter real rs=1 from [0.0:inf);
parameter real fc=0.9 from (0.0:1.0);
parameter real tt=1e-12 from [0.0:inf);
parameter real cjo=1e-15 from [0.0:inf);
17
parameter real phi=0.7 exclude 0.0;
parameter real kf=0.0 from [0.0:inf);
parameter real af=1.0 from (0.0:inf);
parameter real imax=1.0 from[0.0:inf);
parameter real imelt=imax from[0.0:inf);
real Grs, expi, vmax, id, qd;
analog begin
Grs = rs >1.0e-6 ? 1/rs : 1.0e6;
expi = limexp(V(v_id)/(n*$vt));
vmax = n*$vt*ln(imax/is+1);
if (V(v_id) < vmax) begin
id = is*(expi-1);
end else begin
id = imax+(V(v_id)-vmax)*(imax+is)/(n*$vt);
end
if (V(v_id)<fc*phi) begin
qd = tt*id+2*cjo*phi*(1-sqrt(1-V(v_id)/phi));
end else begin
qd = tt*id+2*cjo*phi*(1-sqrt(1-fc))+
cjo*(V(v_id)-fc*phi)*(1-1.25*fc+V(v_id)/(4*phi))/pow((1-fc), 1.5);
end
18
I(v_rs) <+ V(v_rs)*Grs;
I(v_id) <+ id+?GMIN*V(v_id);
I(v_id) <+ ddt(qd);
I(v_rs) <+ white_noise(4*?P_K*$temperature*Grs);
I(v_rs) <+ white_noise(2*?P_K*id)+flicker_noise(kf*pow(abs(id),af),1);
if (I(<a>) > imelt)
$strobe( "Warning: diode is melting!" );
end
endmodule
disciplines is used for definitions of related physical signal types, variables, and
absolute tolerance, which can be defined by users. This file can be loaded into model de-
scriptions by the command ?include. Basic physical quantities such as units, expected
quantity size, and access name are described in disciplines. constants.vams is
used to define the mathematical and physical constants necessary for the descriptions
involved in device modeling.
?define is used for text macro substitution, which allows meaningful names to be
used to present commonly used pieces of text. It can be used both inside and outside
module definitions.
As a basic building block, a Verilog-A module describes the individual compo-
nents, and can be instantiated into a netlist of circuit simulators. The module name
diode is followed by the ports (a, c), which are used for component connection. The
port direction is declared by inout, which indicates the signal flow. For the compact
19
model, the port type electrical is defined by the disciplines file, where the signal
associated with the ports is declared in terms of its variable voltage and variable current.
branch is a new statement and represents an explicit term in model descriptions. A
branch is a path between two nets. Two branches, v_rs and v_id, are declared in this
example. The branch declaration statement can be directly used for current and voltage
descriptions and to simplify model descriptions.
parameter is used for parameter declaration and should follow the port statement.
The default value should be given and can be re-specified when the module is instanti-
ated. real defines the type of parameters, although this is optional. Sometimes range
limits are used to specify that the parameters fall within a particular range and may
be used to avoid non-theoretical values or mathematical calculation errors. Here, the
parentheses () exclude the endpoints while the brackets [] include the endpoints, and
exclude indicates that it must not include the endpoints. If the specified value is out
of range when the module is instantiated, the simulator will automatically generate an
error message.
The realstatement, which represents a real physical connection between structural
entities, declares id to be a real variable. It should not store its value. For an analog
process, the real net is associated with a continuous time kernel and is always initialized
to zero. It can only be connected to a compatible interconnect and other real expressions.
The expression rs>1.0e-6 ? 1.0/rs : 1.0e6 is used for conditional opera-
tion. If rs>1.0e-6 evaluates as false, then 1.0e6 is used as the result of the conditional
expression; if rs>1.0e-6 evaluates as true, 1.0/rs is used as the result.
20
The analog block is used to describe the behavior of the module. Delimited by
the keywords begin and end, statements which are used to describe the relationship of
signals in an analog block can be grouped together and executed sequentially in a given
order. Only one analog block can be used in each module.
Analog conditional statements such as if-else are used to determine whether a
statement should be executed or not. The terms GMIN and imax are used to aid conver-
gence and prevent numerical overflow during iterations in simulation. The term imelt
is used as a limit warning for the junction current.
The branch contribution operator <+ is used in statement to describe analog behav-
ior. It can only be used in an analog block. A branch contribution statement is separated
by a branch contribution operator into two parts, a left side and a right side. In gen-
eral, the right side can be any expression which evaluates to or can be promoted to a
real value. The left side specifies the source branch signal where the right side is to be
assigned.
The symbol $ serves as a system function or system task indicator. It is often used
in environment parameter functions. For example, the simulation temperature is defined
as $temperature, which does not take any input arguments and returns the circuit?s
ambient temperature in Kelvin units, and the thermal voltage is represented by $vt.
The operators + - * / and functions sqrt, pow, ln, exp, and abs are available in
Verilog-A. In general, the operator limexp is used instead of exp to obtain better conver-
gence in a semiconductor compact model. The charge time-derivation operator function
ddt is used for capacitive current. The noise sources are described by white_noise
21
and flicker_noise, which generate white noise and pink noise, respectively. The
term ?P_Q is included in the constants.vams file. The <> is used to delimit the port
name. The I(<a>) used here presents the accessing current that passes through module
port a. The $strobe term is used to display simulation data or print a newline character
when the simulator has converged on a solution for all nodes. The endmodule keyword
is used when the module definition is complete.
Simulation Results
A voltage V
d
is applied between nodes a and c. The simulated Diode I
d
?V
id
and
I
d
?V
d
curves are shown in 2.2.
0 0.2 0.4 0.6 0.8 1
10
?10
10
?5
10
0
V
id
, V
d
    (V)
I
d
    (mA)
I
d
 vs V
id
I
d
 vs V
d
V
d
 = R
S
 ? I
d
 + V
id
 
R
S
 = 1 ?
Figure 2.2: Simulated Diode I
d
?V
id
and I
d
?V
d
curves.
22
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0
0.2
0.4
0.6
0.8
x 10
?14
V
id
    (V)
Charges    (C)
total q
d
 = q
diff
 + q
j
 
q
diff
 
q
j
 
f
c
 = 0.9 
? = 0.7 V 
(a)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0
0.2
0.4
0.6
0.8
x 10
?14
V
id
    (V)
Capacitances    (F)
total C
diff
 + C
j
 
C
j
 
C
diff
 
f
c
 = 0.9 
? = 0.7 V 
C
j0
 
(b)
Figure 2.3: (a) Simulated Diode q
d
, q
di?
, and q
j
vs V
id
. (b) Extracted Diode C ? V
curves.
23
q
d
, q
di?
, and q
j
vs intrinsic voltage V
id
are shown in Fig. 2.3 (a). The extracted C
V
curves are shown in Fig. 2.3 (b). Note that both c
j
and q
j
are continuous at V
id
= ?.
2.3 Summary
This chapter introduced the Verilog-A Language. The use of a Verilog-A based
compact modeling in place of low-level simulator code was explained in detail. Fi-
nally, an example of Verilog-A based modeling was given to demonstrate the use of the
Verilog-A programming language.
24
CHAPTER 3
VBIC MODELING
The SPICE Gummel-Poon (SGP) model has been the IC industry standard for mod-
eling bipolar junction transistors (BJT) for almost thirty years. However, the Gummel-
Poon model is unable to model collector resistance modulation (quasi-saturation) and
parasitic substrate transistor action, and is not adequate to model modern HBT (het-
erojunction bipolar transistor) devices due to the high speed and accurate simulation
requirements for the modern telecommunication industries, especially for RF design.
An improved VBIC (Vertical Bipolar Inter-Company model) was introduced by IC
and CAD industry representatives in 1995 and is widely used. VBIC is based on the
SPICE Gummel-Poon model, with a modified version of the Kull-Nagel quasi-saturation
model. The main improvements in VBIC compared to SGP [7] include:
? a modified form is used in Early e?ect (g
o
) modeling to better describe the output
conductance of the bipolar transistor,
? an improved quasi-saturation modeling process is implemented to avoid a nega-
tive value for the output conductance,
? parasitic substrate PNP transistor modeling,
? parasitic fixed (oxide) capacitance modeling,
? avalanche multiplication modeling,
25
? improved temperature dependence modeling,
? decoupling of base and collector currents,
? electrothermal (self heating) modeling,
? C
?
continuous (smooth) modeling,
? improved HBT modeling.
VBIC is used particularly for 4-terminal vertical NPN transistors. For 5-terminal
vertical PNP transistors in smartpower technologies, VBIC can be treated as a subcircuit.
However, the geometry scaling cannot be taken into account in VBIC because of the
plethora of BJT structure and layout considerations.
Fig. 3.1 shows an equivalent network for VBIC, which includes an intrinsic NPN
transistor (the same equivalent circuit used in the standard Gummel-Poon model), a
parasitic PNP transistor, and parasitic resistances and capacitances. The external local
thermal network is used only with the electrothermal version of the model. It is com-
posed of a thermal resistance R
th
, a thermal capacitance C
th
, and a thermal source (heat
generation) I
th
which can model the thermal properties of a BJT transistor by connecting
to the local heating and power dissipation in the device. The excess phase for forward
transport current I
tzf
is also considered in another separate external subcircuit.
In this thesis, only a brief discussion on VBIC modeling is provided. For a more
detailed model description, please refer to [7] and [8].
26
Figure 3.1: VBIC equivalent network
27
3.1 Modeling of Transfer Current
The band diagram of an intrinsic bipolar transistor is shown in Fig. 3.2. Nodes bi,
ei, and ci are the internal nodes shown in Fig. 3.1. V
BEI
is the intrinsic BE forward
bias voltage between nodes bi and ei. V
BCI
is the intrinsic BC forward bias voltage
between nodes bi and ci. At zero bias, i.e., V
BEI
= 0 and V
BCI
= 0, the neutral base
region starts at 0, and ends at W
p
. The quasi-Fermi level of the electrons E
fn
is flat,
and equal to the quasi-Fermi level of the holes E
fp
, as shown in Fig. 3.2 (a). When a
forward bias V
BEI
is applied to the internal device, the EB junction depletion width is
shortened. The left edge of the quasineutral base region moves from 0 to x1, as shown
in Fig. 3.2 (b). Similarly, the right edge of the quasineutral base region moves from W
p
to x2 when a forward bias V
BCI
is applied to the CB junction. x2 ?x1 gives the width
of the quasineutral base region.
As the recombination is negligible in a narrow base, the electron current density in
the base region can be written as,
J
n
= n?
n
dE
fn
dx
(3.1)
where n is the electron concentration, and ?
n
is the electron minority carrier mobility.
The hole quasi-Fermi level E
fp
can be assumed to be constant, since
dE
fp
dx
=
J
p
p?
p
? 0 (3.2)
28
bi
ei ci
E
B
C
0 W
p
E
C
E
V
E
Fn
E
Fp
(a)
V
BEI
 = 0
V
BCI
 = 0
E
Fn
bi
ei ci
E
B
C
x1 x2
E
C
E
V
E
Fn
E
Fp
(b)
E
Fn
E
Fn
V
BEI
 > 0
V
BCI
 > 0
qV
BEI qV
BCI
Figure 3.2: Band diagram of an intrinsic bipolar transistor. (a) V
BEI
= 0, V
BCI
= 0; (b)
V
BEI
> 0, V
BCI
> 0.
29
where p is the majority hole concentration in the base, which is very large. ?
p
is the hole
majority carrier mobility, and J
p
is the hole current density in the base region. The np
product is
E
fn
?E
fp
= kT ln
parenleftbigg
np
n
2
i
parenrightbigg
(3.3)
where k is Boltzmann?s constant, T is temperature in degrees Kelvin, and n
i
is the
e?ective intrinsic concentration. From (3.1), (3.2) and (3.3), J
n
can be rewritten as
J
n
= n?
n
d(E
fn
?E
fn
)
dx
(3.4)
= qD
n
n
2
i
p
d
dx
parenleftbigg
np
n
2
i
parenrightbigg
(3.5)
where q is the magnitude of the electronic charge and the electron di?usivity D
n
is
related to the electron mobility ?
n
through the Einstein relations, D
n
= ?
n
kT/q.
Electrons, injected from the emitter into the base, reach the collector and become
the collector current. Moving qD
n
n
2
i
p
in (3.5) to the left-hand side gives
J
n
p(x)
qD
n
n
2
i
dx = d
parenleftbigg
np
n
2
i
parenrightbigg
(3.6)
Integrating on both sides gives
J
n
integraldisplay
x2
x1
p(x)
qD
n
n
2
i
dx =
np
n
2
i
vextendsingle
vextendsingle
vextendsingle
vextendsingle
x2
?
np
n
2
i
vextendsingle
vextendsingle
vextendsingle
vextendsingle
x1
(3.7)
30
The boundary conditions for EB and CB junctions are
np
n
2
i
vextendsingle
vextendsingle
vextendsingle
vextendsingle
x1
= exp
parenleftbigg
V
BEI
V
T
parenrightbigg
(3.8)
np
n
2
i
vextendsingle
vextendsingle
vextendsingle
vextendsingle
x2
= exp
parenleftbigg
V
BCI
V
T
parenrightbigg
(3.9)
where V
T
= kT/q is the thermal voltage. Applying these boundary conditions gives
J
n
integraldisplay
x2
x1
p(x)
qD
n
n
2
i
dx = ?
bracketleftbigg
exp
parenleftbigg
V
BEI
V
T
parenrightbigg
? exp
parenleftbigg
V
BCI
V
T
parenrightbiggbracketrightbigg
(3.10)
Note that the negative value for J
n
indicates that the electrons are flowing towards the
collector. Let
Q
B
= q
integraldisplay
x2
x1
p(x)dx (3.11)
which represents the total majority charge per unit area in the base. Assuming D
n
and
n
2
i
are position independent, (3.10) can then be rewritten as
J
n
= ?
q
2
D
n
n
2
i
Q
B
bracketleftbigg
exp
parenleftbigg
V
BEI
V
T
parenrightbigg
? exp
parenleftbigg
V
BCI
V
T
parenrightbiggbracketrightbigg
(3.12)
Defining Q
B0
as the Q
B
at zero applied voltage, i.e., V
BEI
= 0, V
BCI
= 0,
Q
B0
= q
integraldisplay
W
p
0
N
B
(x)dx (3.13)
31
The Q
B
/Q
B0
ratio is denoted as q
b
, which represents the normalized base charge. Then
(3.12) can be rewritten as
J
n
=
J
S
q
b
bracketleftbigg
exp
parenleftbigg
V
BEI
V
T
parenrightbigg
? exp
parenleftbigg
V
BCI
V
T
parenrightbiggbracketrightbigg
(3.14)
J
S
=
q
2
D
n
n
2
i
Q
B0
(3.15)
where J
S
is the saturation current density.
The simple theory discussed above shows that the forward collector current is ex-
ponentially related to the inverse thermal voltage. Empirically, however, a non-ideality
factor N
F
must be introduced to numerically describe the nonideal e?ect induced by
the spatial coordinate dependence of mobility, doping concentration, di?usion constant,
and carrier lifetimes. Similarly, a non-ideality factor N
R
is used for the reverse collector
current. Therefore the final collector current is
I
C
= A
E
|J
n
| =
I
tf
?I
tr
q
b
(3.16)
I
tf
= I
S
bracketleftbigg
exp
parenleftbigg
V
BEI
N
F
V
T
parenrightbigg
? 1
bracketrightbigg
(3.17)
I
tr
= I
S
bracketleftbigg
exp
parenleftbigg
V
BCI
N
R
V
T
parenrightbigg
? 1
bracketrightbigg
(3.18)
I
S
= A
E
J
S
(3.19)
where I
tf
and I
tr
are the forward and reverse transport currents. A
E
is the emitter area,
and I
S
represents the saturation current.
32
Moving on to examine the normalized base charge q
b
, p(x) in the base has three
components: the base doping N
B
(x),n
be
(x) due to EBapplied voltage V
BEI
, and n
bc
(x)
due to CB applied voltage V
BCI
,
p(x) = N
B
(x) +n
be
(x) +n
bc
(x) (3.20)
Therefore, Q
B
changes with applied voltages V
BEI
and V
BCI
in several ways:
1. x1 changes withV
BEI
, causing extra depletion charge ofQ
JE
as shown in Fig. 3.3,
corresponding to the reverse Early E?ect.
Q
JE
=
integraldisplay
0
x1
qN
B
(x)dx (3.21)
2. x2 changes withV
BCI
, causing extra depletion charge ofQ
JC
as shown in Fig. 3.3,
corresponding to the forward Early E?ect.
Q
JC
=
integraldisplay
x2
W
p
qN
B
(x)dx (3.22)
3. n
be
(x) changes with V
BEI
, corresponding to the di?usion charge Q
ne
.
Q
ne
=
integraldisplay
x2
x1
qn
be
(x)dx
vextendsingle
vextendsingle
vextendsingle
vextendsingle
V
BEI
>0,V
BCI
=0
(3.23)
33
N
B
(x)
xx2
x1 0
W
p
Q
B0
Q
JC
Q
JE
V
BEI
0 0
V
BCI
>0 >0
Figure 3.3: Zero bias charge Q
B0
, EB depletion charge Q
JE
, and CB depletion charge
Q
JC
in the neutral base region.
4. n
bc
(x) changes with V
BCI
, corresponding to the di?usion charge Q
nc
.
Q
nc
=
integraldisplay
x2
x1
qn
bc
(x)dx
vextendsingle
vextendsingle
vextendsingle
vextendsingle
V
BEI
=0,V
BCI
>0
(3.24)
The total base charge Q
B
is the sum of Q
B0
, Q
JE
, Q
JC
, Q
ne
, and Q
nc
:
Q
B
=
integraldisplay
x2
x1
(N
B
(x) +n
be
(x) +n
bc
(x))dx (3.25)
= Q
N
B
+Q
ne
+Q
nc
(3.26)
Q
N
B
=
integraldisplay
x2
x1
N
B
(x)dx (3.27)
34
Q
N
B
=
integraldisplay
0
x1
N
B
(x)dx+
integraldisplay
W
p
0
N
B
(x)dx+
integraldisplay
x2
W
p
N
B
(x)dx, (3.28)
= Q
JE
+Q
B0
+Q
JC
. (3.29)
Therefore q
b
can be written as
q
b
?
=
Q
NB
Q
B0
+
Q
ne
Q
B0
+
Q
nc
Q
B0
(3.30)
= q
1
+
Q
ne
Q
B0
+
Q
nc
Q
B0
(3.31)
and
q
1
?
=
Q
NB
Q
B0
(3.32)
?
= 1 +
Q
JE
Q
B0
+
Q
JC
Q
B0
(3.33)
q
1
is a function of bias, and represents the normalized base charge under the low level
injection conditions, where
Q
ne
Q
B0
lessmuch 1 and
Q
nc
Q
B0
lessmuch 1, and hence q
b
? q
1
.
In practice, it is not possible to directly determine Q
JE
and Q
JC
. Instead the EB
and CB depletion capacitances are given as
C
je
(V ) =
dQ
JE
dV
BEI
(3.34)
C
jc
(V ) =
dQ
JC
dV
BCI
(3.35)
35
Therefore, (3.33) can be rewritten as
q
1
= 1 +
1
Q
B0
integraldisplay
V
BEI
0
C
je
(V )dV +
1
Q
B0
integraldisplay
V
BCI
0
C
jc
(V )dV (3.36)
Let C
JE
= C
je
(0), and C
JC
= C
jc
(0). Define the reverse Early voltage V
ER
and the
forward Early voltage V
EF
as
V
ER
?
=
Q
B0
C
JE
(3.37)
V
EF
?
=
Q
B0
C
JC
(3.38)
Therefore, (3.36) can be rewritten as,
q
1
= 1 +q
je
+q
jc
(3.39)
q
je
=
1
V
ER
1
C
JE
integraldisplay
V
BEI
0
C
je
(V )dV (3.40)
q
jc
=
1
V
EF
1
C
JC
integraldisplay
V
BCI
0
C
jc
(V )dV (3.41)
However, in VBIC modeling, V
ER
and V
EF
are treated as completely independent pa-
rameters for flexibility in fitting data. Moreover, V
ER
C
JE
does not necessarily equal
V
EF
C
JC
in real device model parameters.
At high injection, the di?usion charges Q
ne
and Q
nc
are important. Assuming the
transit time? associated with each di?usion charge remains the same as for low injection
36
Q
ne
=
I
tf
?
f
q
b
(3.42)
Q
nc
=
I
tr
?
r
q
b
(3.43)
where ?
f
and ?
r
are the forward and reverse transit time, respectively. Now (3.31) can
be rewritten as
q
b
= q
1
+
I
tf
?
f
q
b
Q
B0
+
I
tr
?
r
q
b
Q
B0
(3.44)
= q
1
+
q
2
q
b
(3.45)
and
q
2
?
=
I
tf
?
f
Q
B0
+
I
tr
?
r
Q
B0
(3.46)
Further assuming ?
f
and ?
r
are independent of bias, the forward Knee current I
KF
and
reverse Knee current I
KR
can be defined as,
I
KF
=
Q
B0
?
f
(3.47)
I
KR
=
Q
B0
?
r
(3.48)
37
Then (3.46) is rewritten as
q
2
?
=
I
tf
I
KF
+
I
tr
I
KR
(3.49)
Solving (3.45) gives q
b
in terms of q
1
and q
2
,so
q
b
=
1
2
bracketleftbigg
q
1
+
radicalBig
q
2
1
+ 4q
2
bracketrightbigg
(3.50)
In summary, the equations for transfer current are:
I
C
= A
E
|J
n
| =
I
tf
?I
tr
q
b
(3.51)
I
tf
= I
S
bracketleftbigg
exp
parenleftbigg
V
BEI
N
F
V
T
parenrightbigg
? 1
bracketrightbigg
(3.52)
I
tr
= I
S
bracketleftbigg
exp
parenleftbigg
V
BCI
N
R
V
T
parenrightbigg
? 1
bracketrightbigg
(3.53)
q
b
?
=
1
2
bracketleftbigg
q
1
+
radicalBig
q
2
1
+ 4q
2
bracketrightbigg
(3.54)
q
1
= 1 +q
je
+q
jc
(3.55)
q
je
=
1
V
ER
1
C
JE
integraldisplay
V
BEI
0
C
je
(V )dV (3.56)
q
jc
=
1
V
EF
1
C
JC
integraldisplay
V
BCI
0
C
jc
(V )dV (3.57)
q
2
?
=
I
tf
I
KF
+
I
tr
I
KR
(3.58)
38
3.2 Modeling of Internal EBand BC Diodes
The internalEBdiode is more complicated in the VBIC model than that in Gummel-
Poon model because of the need to introduce additional emission coe?cients. The ideal
base current and nonideal current are included in the internal EB diode by
I
bt
= I
BE
+I
BEX
(3.59)
= I
BEI
bracketleftbigg
exp
parenleftbigg
V
BEI
N
EI
V
T
parenrightbigg
? 1
bracketrightbigg
+I
BEN
bracketleftbigg
exp
parenleftbigg
V
BEX
N
EN
V
T
parenrightbigg
? 1
bracketrightbigg
(3.60)
The ratio between I
BE
and I
BEX
is defined by parameter W
BE
.
The current in the internal BC diode can be written as
I
bc
= I
BCI
bracketleftbigg
exp
parenleftbigg
V
BCI
N
CI
V
T
parenrightbigg
? 1
bracketrightbigg
+I
BCN
bracketleftbigg
exp
parenleftbigg
V
BCX
N
CN
V
T
parenrightbigg
? 1
bracketrightbigg
(3.61)
A weak avalanche current source I
gc
, modeled by the formula of Klosterman and
de Graa?, is also included in the BC diode,
I
gc
= (I
cc
?I
bc
)A
VC1
(P
C
?V
BCI
)exp
bracketleftbig
?A
VC2
(P
C
?V
BCI
)
M
C
?1
bracketrightbig
(3.62)
The excess phase is modeled in the external subcircuit of Fig. 3.1 for both ac and
transient analyses. If the capacitance of Q
cxf
and the inductance of F
lxf
are assumed
to be C and L, respectively, the voltage V
xf2
across the 1 ? resistance caused by the
39
controlled current source I
tf
can be written as
V
xf2
=
1
1 +j?RC ??
2
LC
(3.63)
where L = T
D
/3, C = T
D
, and T
D
= 1/?
0
. The current I
xf2
flows through R and
produces a voltage, which can be used to describe the delay in the voltage response of
the transfer current.
3.3 Modeling of Quasi-Saturation
The voltage drop across the collector resistance, which includes the resistance
formed by the undepleted portion of the epilayer, the subcollector and the collector
contact, decreases the potential di?erences across the CB space charge layer, resulting
in an increase in the base width and, hence, the base transit time and may even cause the
BC diode to be internally forward biased. This phenomena is called the quasi-saturation
e?ect. Using a modified version of the Kull model, the quasi-saturation e?ects are in-
cluded in the modeling of the intrinsic collector (epi) region to avoid producing a nega-
tive value for g
o
at high V
BE
. If the velocity saturation is ignored, the current in the epi
layer is written as
I
epi0
=
V
rci
+V
T
bracketleftBig
K
bci
?K
bcx
? ln
parenleftBig
K
bci
+1
K
bcx
+1
parenrightBigbracketrightBig
R
CI
(3.64)
40
where
K
bci
=
bracketleftbigg
1 +? exp
parenleftbigg
V
BCI
V
T
parenrightbiggbracketrightbigg
1/2
(3.65)
K
bcx
=
bracketleftbigg
1 +? exp
parenleftbigg
V
BCX
V
T
parenrightbiggbracketrightbigg
1/2
(3.66)
Moreover, an alternative velocity saturation model is introduced,
? = ?
0
/[1 + (?
0
??
e
/v
sat
)
2
]
1/2
(3.67)
Meanwhile, converting V
rci
into I
epi0
R
CI
, the current across R
CI
becomes
I
rci
=
?
?
?
?
?
?
?
?
?
I
epi0
?
?
1 +
I
epi0
R
CI
V
O
parenleftbigg
1+
0.5(V
2
rci
+0.01)
1/2
V
O
H
RCF
parenrightbigg
?
?
2
?
?
?
?
?
?
?
?
?
1/2
(3.68)
where H
RCF
is a dimensionless fitting parameter that allows one to partially replace V
O
by V
RCI
.
3.4 The Parasitic PNP Transistor
For the npn bipolar device with a p-type substrate, the parasitic vertical pnp transis-
tor formed by the BC and CS junctions can be modeled by a simplified Gummel-Poon
41
equivalent circuit. The forward current can be written as
I
tfp
= I
SP
bracketleftbigg
W
SP
exp
parenleftbigg
V
BEP
N
FP
V
T
parenrightbigg
+ (1?W
SP
)exp
parenleftbigg
V
BCI
N
FP
V
T
parenrightbigg
? 1
bracketrightbigg
(3.69)
The normalized base charge of the parasitic transistor only comprises high-level injec-
tion e?ects, as the Early e?ect can be neglected, so
q
bp
= 1 +
q
2p
q
bp
(3.70)
q
2p
=
I
tfp
I
KP
(3.71)
The parasitic base currents are then modeled similar to the internal EB base current.
3.5 Temperature Mapping
The temperature e?ects of saturation currents, current gains, serious resistances,
and depletion capacitances in BJT are all modeled in the VBIC model.
3.5.1 Resistance
The temperature dependence of the series resistances is modeled as:
R
X
(T) = R
X
(T
nom
)
parenleftbigg
T
T
nom
parenrightbigg
X
RX
(3.72)
Here, X
RX
is di?erent for the emitter, base, collector and substrate resistances.
42
3.5.2 Capacitance
The temperature dependence of zero-bias depletion capacitances is modeled as:
C
X
(T) =
parenleftbigg
P
X
(T)
P
X
(T
nom
)
parenrightbigg
M
X
(3.73)
where M
X
denotes the grading exponent of the corresponding junction. The built-in
voltage P
X
is modeled by a temperature-dependent function derived from
P
X
= V
T
parenleftbigg
n
n0
p
p0
n
2
ie
parenrightbigg
(3.74)
3.5.3 Knee current I
KF
The Knee current I
KF
was originally used as the onset of the high injection e?ect
in the base, but in the VBIC model it is used as an empirical parameter. The temperature
dependence of the Knee current I
KF
is modeled as:
I
KF
(T) = I
KF
(T
nom
)
parenleftbigg
T
T
nom
parenrightbigg
X
IKF
(3.75)
where X
IKF
is the temperature coe?cient for I
KF
.
43
3.5.4 Ideality Factor N
F
N
F
is the ideality factor for the collector current I
C
. The temperature dependence
of N
F
is modeled as:
N
F
(T) = N
F
(T
nom
)
parenleftbig
1 +T
nf
d
T
parenrightbig
(3.76)
where T
nf
is the temperature coe?cient for N
F
. d
T
= T ?T
nom
.
3.5.5 Saturation Current I
S
From (3.15) and (3.19), assuming that freezeout does not occur,Q
B0
is independent
of temperature and the saturation current I
S
is
I
S
(T) = A
E
q
2
D
n
(T)n
2
i
(T)
Q
B0
(3.77)
At the reference temperature T
nom
,
I
S
(T
nom
) = A
E
q
2
D
n
(T
nom
)n
2
i
(T
nom
)
Q
B0
(3.78)
which becomes
I
S
(T) = I
S
(T
nom
)
D
n
(T)
D
n
(T
nom
)
n
2
i
(T)
n
2
i
(T
nom
)
(3.79)
= I
S
(T
nom
)
T
T
nom
?
n
(T)
?
n
(T
nom
)
n
2
i
(T)
n
2
i
(T
nom
)
(3.80)
44
Since n
2
i
is proportional to T
?
exp
parenleftBig
?
E
g
(T)
kT
parenrightBig
, and ?
n
is proportional to T
?m
, (3.80) can
be rewritten as
I
S
(T) = I
S
(T
nom
)
parenleftbigg
T
T
nom
parenrightbigg
?+1?m
exp
parenleftbigg
?
E
g
(T)
kT
+
E
g
(T
nom
)
kT
nom
parenrightbigg
(3.81)
= I
S
(T
nom
)
parenleftbigg
T
T
nom
parenrightbigg
X
TI
exp
parenleftbigg
?
E
g
(T)
kT
+
E
g
(T
nom
)
kT
nom
parenrightbigg
(3.82)
where E
g
is the bandgap energy, andX
TI
= ? + 1 ?m. Assuming linear T dependence
of E
g
(T),
E
g
(T) = E
g
(0) ??T (3.83)
Thus,
?
E
g
(T)
kT
+
E
g
(T
nom
)
kT
nom
= ?
1
kT
parenleftbigg
E
g
(0) ??T ? (E
g
(0) ??T
nom
)
T
T
nom
parenrightbigg
(3.84)
= ?
1
kT
E
g
(0)
parenleftbigg
1 ?
T
T
nom
parenrightbigg
(3.85)
Substituting (3.85) in (3.82) gives
I
S
(T) = I
S
(T
nom
)
parenleftbigg
T
T
nom
parenrightbigg
X
TI
exp
bracketleftbigg
?
1
kT
E
a
parenleftbigg
1 ?
T
T
nom
parenrightbiggbracketrightbigg
(3.86)
E
a
= E
g
(0) (3.87)
45
The general temperature dependence of saturation currents is therefore modeled in VBIC
as:
I
X
(T) = I
X
(T
nom
)
parenleftbigg
T
T
nom
parenrightbigg
X
X
/N
X
exp
bracketleftbigg
?
E
X
N
X
V
T
parenleftbigg
1 ?
T
T
nom
parenrightbiggbracketrightbigg
(3.88)
The temperature variation of the current gain is directly determined by the temperature
dependences of the saturation currents. The thermal network in Fig. 3.1 can be used to
calculate the excess temperature due to the power dissipated in the device.
46
CHAPTER 4
VERILOG-A IMPLEMENTATION
The Verilog-A language and VBIC model have been introduced in Chapter 2 and
Chapter 3. In this chapter, the VBIC model is reframed in Verilog-A language, and im-
plemented into two circuit simulators, Cadence and ADS. The major problems such as
syntax errors, convergence problems and numerical problems, are solved. The DC, ac,
noise and large signal simulation comparisons between Verilog-A based VBIC modeling
and the Cadence built-in VBIC model show identical results.
4.1 Basic code description
The Verilog-A code, based on VBIC version 1.2, used in this thesis can be down-
loaded from several open source websites [9] [10] [11] and was automatically generated
from special code. The four terminal mode was chosen to ensure consistency with the
IBM design kit used in this work.
The Verilog-A based VBIC code includes the basic node definitions, branch defi-
nitions, parameter definitions, temperature mappings, electrical branch constituent rela-
tions, and branch contributions for the VBIC model. The thermal network and excess
phase network are also included.
The major improvements introduced in the version 1.2 Verilog-A based VBIC code
compared to previous versions include:
47
? base-emitter breakdown model added
? bug in built-in potential fixed
? smooth depletion capacitance model re-parameterized
? separate temperature dependencies added for all resistances and I
SP
? temperature dependence added for I
KF
? reach-through voltage for C
bc
limiting added
? ability to separately control saturation currentI
S
in reverse operation (GaAs/AlGaAs
HBTs)
? only one thermal node is used, and tl was dropped (this was deemed unnecessary
as it was never used in implementations)
? reference directions of current sources in thermal end excess-phase networks were
changed, to be from node to ground (for Verilog-A compatibility)
? transport current explicitly separated into forward and reverse components, for
convenience and compatibility of code between constant and excess-phase ver-
sions
? N
KF
parameterization of forward beta rollo? added
? ability to switch to SGP base charge formulation added (Q
BM
)
48
4.2 Implementation into Simulators
4.2.1 Implementation into Agilent ADS
In Agilent ADS, a directory called veriloga was created for the current project,
and the Verilog-A module was placed in that directory [12]. The Verilog-A module
can be instantiated as a symbol using the ?User Compiled Models?, which is a function
provided in ADS. The Verilog-A compiler in ADS, developed by Tiburon Design Au-
tomation, then automatically compiles all Verilog-A files in the ADS Project veriloga
directory into simulator. This compiler-based solution results in a simulation time for
the Verilog-A based models that is comparable to that of the built-in models.
4.2.2 Implementation into Cadence
The same Verilog-A VBIC model code used in ADS can also be implemented into
Cadence. In Cadence, a Verilog-A module can be created using the Verilog-A editor
without modifying the interface between the internal compact model and the simula-
tor [13]. The newly created Verilog-A module can then be instantiated into the simula-
tor, and added into the new schematic window as a symbolic view instance. Here, the
Verilog-A based VBIC model code was implemented into Cadence in the same way.
The discussions in the following sections in this chapter are all based on the Verilog-
A based VBIC code implemented in Cadence.
49
4.3 Main debugging issues
Since the Verilog-A based VBIC code downloaded from open websites is automat-
ically generated from special code, it could not be directly used in Cadence and ADS
due to syntax errors. Moreover, the convergence problems induced by numerical issues
had to be considered in common Verilog-A based model coding. The main debugging
procedures involved were as follows.
4.3.1 Syntax Errors
Cadence does not support the symbol $limexp, which is defined in the Verilog-A
VBIC code in order to achieve better convergence. Consequently, all the syntax errors
due to $limexp had to be corrected to limexp. For instance, the Verilog-A equation for
the forward transit time tff is defined as:
tff=TF*(1.0+QTF*q1)*(1.0+XTF*$limexp(V(bci)*IVTF/1.44)
*(slTF+mIf*mIf)*sgIf);
For this project, it had to be modified to:
tff=TF*(1.0+QTF*q1)*(1.0+XTF*limexp(V(bci)*IVTF/1.44)
*(slTF+mIf*mIf)*sgIf);
The module name vbic in Verilog-A VBIC code also conflicts with the primitive
definition in Cadence, causing a name duplication in the primitive VBIC. It was there-
fore corrected to vbicfinal.
50
4.3.2 Convergence Problems
Once the syntax errors had been dealt with, the Verilog-A based model was imple-
mented into Cadence. However, the DC and ac simulations su?ered from convergence
problems, especially for the large signal simulations. Since the high level Verilog-A
description had to be automatically converted to low level simulator code, junction lim-
iting and linearization of exponentials must be explicitly handled to aid convergence and
prevent numerical overflow [14].
The simulator global parameters gmin, imax, and imelt set the limitation of the
diode-like branch current level. The main purpose of explicitly adding these global
parameters was to help with convergence. They also solved the ambiguity problem
induced by the linearization scheme in the limexp function [14]. The gmin related
current in the Verilog-A code was therefore added in each diode-like branch as follows:
Ibe = Ibe + gmin * V(bei);
Ibex = Ibex + gmin * V(bex);
Ibep = Ibep + gmin * V(bep);
Ibc = Ibc + gmin * V(bci);
Ibcp = Ibcp + gmin * V(bcp);
where gmin= 1.0e-12. imax is the branch current threshold. If imax is exceeded during
iterations, the linear model is used instead of the exponential model until the current
drops below imax, or until convergence is achieved. Theimelt serves as a limit warning
for the junction current [15]. Using the forward transport current I
tf
as an example, the
51
programming flow is as follows [16]. Defining V
max
= N
F
V
T
ln
parenleftBig
imax
I
S
+ 1
parenrightBig
,ifV
BEI
<
V
max
,
I
tf
= I
S
bracketleftbigg
exp
parenleftbigg
V
BEI
N
F
V
T
parenrightbigg
? 1
bracketrightbigg
(4.1)
which is the normal exponential model. If V
BEI
? V
max
,
I
tf
= imax+
V
BEI
?V
max
N
F
V
T
(imax+I
S
) (4.2)
which becomes the linear model of V
BEI
. All other currents are limited in the same
way. An example of I
tf
in Verilog-A is as follows. First, an analog function expf
that includes a switch to the exponential model and the linear model controlled by the
threshold current imax is defined for a junction current. This analog function is suitable
for all the junction currents.
analog function real expf;
input v,fac1,fac2;
real v,fac1,fac2;
real vmax, expL;
begin
if (fac2>0) begin
vmax= fac1*ln(1.0+imax/fac2);
end else begin
52
vmax = 0.0;
end
expL = limexp(v/fac1);
if (v<vmax) begin
expf = expL;
end else begin
expf = imax+(v-vmax)*(imax+fac2)/fac1;
end
end
endfunction
Finally, the Ifi is written as,
fac = NFatT*Vtv;
expfi = expf(V(bei),fac, ISatT);
Ifi = ISatT*(limexp(expfi)-1);
The imelt, used for a current limit warning in a single branch like be, is described
as,
if (I(be) > imelt)
$strobe( "Warning: branch be is melting!" );
The Warning message ?Warning: branch be is melting!? will be displayed in the
output log file. If it is used for port current, like b, it is described as,
53
if (I(<b>) > imelt)
$strobe( "Warning: device port b is melting!" );
4.3.3 Logarithm Error
Once the convergence problems had been solved, the Verilog-A based model ran
relatively smoothly and fast. However, the Verilog-A based model DC and ac simu-
lation results failed to produce the same results as the Cadence built-in VBIC model.
Carefully debugging the code revealed that it was the definition of log that was causing
the deviations. In Verilog-A, log stands for log
10
, not log
e
as needed here. Therefore,
ln must be used instead of log.
In the original Verilog-A VBIC code, the function definitions of psiio, psiin, and
psibi are related to the temperature mapping model of all the capacitances. They are
defined using log, as shown in the following,
psiio = 2.0*(Vtv/rT)*log(exp(0.5*P*rT/Vtv)-exp(-0.5*P*rT/Vtv));
psiin = psiio*rT-3.0*Vtv*log(rT)-Ea*(rT-1.0);
psibi = psiin+2.0*Vtv*log(0.5*(1.0+sqrt(1.0+4.0*exp(-psiin/Vtv))));
If log is not corrected to be ln, this will cause the inaccurate temperature mapping
models observed for the capacitances. Even at room temperature, problems will occur
in the high bias due to the self-heating e?ect. The corrected code becomes,
psiio = 2.0*(Vtv/rT)*ln(exp(0.5*P*rT/Vtv)-exp(-0.5*P*rT/Vtv));
psiin = psiio*rT-3.0*Vtv*ln(rT)-Ea*(rT-1.0);
54
psibi = psiin+2.0*Vtv*ln(0.5*(1.0+sqrt(1.0+4.0*exp(-psiin/Vtv))));
Another error introduced by the log definition is related to the epi layer current
I
rci
. The original code is,
Iohm=(V(rci)+Vtv*(Kbci-Kbcx-log(rKp1)))/RCIatT;
derf=IVO*RCIatT*Iohm/(1.0+0.5*IVO*IHRCF*sqrt(V(rci)*V(rci)+0.01));
Irci=Iohm/sqrt(1+derf*derf);
If not corrected, this causes an the error in I
rci
. The corrected code becomes,
Iohm=(V(rci)+Vtv*(Kbci-Kbcx-ln(rKp1)))/RCIatT;
derf=IVO*RCIatT*Iohm/(1.0+0.5*IVO*IHRCF*sqrt(V(rci)*V(rci)+0.01));
Irci=Iohm/sqrt(1+derf*derf);
4.3.4 Noise Modeling
At present, the Verilog-A model does not include noise modeling. For RF simu-
lation purposes, it is necessary to add in a noise modeling component in the Verilog-A
based VBIC model in order to be consistent with the Cadence built-in model. The noise
models were added as follows.
I(cei) <+ white_noise(2*?QQ*abs(Itzf));
I(bei) <+ white_noise(2*?QQ*abs(Ibe))
+flicker_noise(KFN*pow(abs(Ibe,AFN),BFN);
I(bex) <+ white_noise(2*?QQ*abs(Ibex))
55
+flicker_noise(KFN*pow(abs(Ibex),AFN),BFN);
I(rcx) <+ white_noise(4*?KB*Tdev*(1/RCX));
I(rci) <+ white_noise(4*?KB*Tdev*(1/RCI));
I(rbx) <+ white_noise(4*?KB*Tdev*(1/RBX));
I(rbi) <+ white_noise(4*?KB*Tdev*(1/RBI));
I(re) <+ white_noise(4*?KB*Tdev*(1/RE));
I(rs) <+ white_noise(4*?KB*Tdev*(1/RS));
I(cep) <+ white_noise(2*?QQ*abs(Iccp));
I(bep) <+ white_noise(2*?QQ*abs(Ibep))
+flicker_noise(KFN*pow(abs(Ibep),AFN),BFN);
I(rbp) <+ white_noise(4*?KB*Tdev*(1/RBP));
4.4 Comparison with built-in model
Finally, the complete Verilog-A based VBIC model was successfully implemented
into Cadence. The DC, ac, noise, and large signal simulation results for a 50 GHz tech-
nology device were compared between the Verilog-A based VBIC model and Cadence
built-in VBIC model. The emitter area used was 0.5?2.5 ?m
2
. The results of the com-
parison show that the new Verilog-A based VBIC model is identical to the Cadence
built-in VBIC model.
56
4.4.1 DC Simulation
Fig. 4.1 (a) shows a Gummel curve comparison of the Verilog-A based VBIC
model and Cadence built-in VBIC model. Perfect agreement is achieved. A compar-
ison of the output curves of the Verilog-A based VBIC model and the Cadence built-in
VBIC model is shown in Fig. 4.1 (b). The Verilog-A based VBIC model clearly agrees
with the Cadence built-in VBIC model very well.
0.5 0.6 0.7 0.8 0.9 1
10
?12
10
?10
10
?8
10
?6
10
?4
10
?2
V
BE
    (V)
I
B
 & I
C
    (A)
Cadence built?in VBIC
Verilog?A VBIC
V
CB
 = 0 V
(a)
0 1 2 3 4 5
?1
0
1
2
3
4
5
6
x 10
?3
V
CE
    (V)
I
C
    (A)
Cadence built?in VBIC
Verilog?A VBIC
I
B
 = 5 ?A 
I
B
 = 15 ?A 
I
B
 = 25 ?A 
I
B
 = 35 ?A 
I
B
 = 45 ?A 
(b)
Figure 4.1: (a) Gummel curve comparison of Verilog-A based VBIC model and Ca-
dence built-in VBIC model. (b) Output curve comparison of Verilog-A based VBIC
model and Cadence built-in VBIC model.
57
4.4.2 ac Simulation
Fig. 4.2 and 4.3 show the comparisons of the bias and frequency dependence of S-
parameters for the Verilog-A based VBIC model and the Cadence built-in VBIC model.
All of the S-parameters of the Verilog-A based VBIC model are identical to the Cadence
built-in VBIC model. Since the S-parameters of the Verilog-A based VBIC model are
identical to the Cadence built-in VBIC model, the cuto? frequency f
T
is the same for
the two models, as shown in Fig. 4.4.
0.7 0.8 0.9 1
?4
?3
?2
?1
0
0.7 0.8 0.9 1
?35
?30
?25
?20
Cadence built?in VBIC
Verilog?A  VBIC
0.7 0.8 0.9 1
?20
?10
0
10
20
30
0.7 0.8 0.9 1
?8
?6
?4
?2
0
S
11
(dB)
V
BE
 (V)
S
12
(dB)
V
BE
 (V)
S
21
(dB)
V
BE
 (V)
S
22
(dB)
V
BE
 (V)
A
E
 = 0.5 ? 2.5 ?m
2
 
Freq = 2 GHz 
Figure 4.2: S-parameters vs V
BE
curves of Verilog-A based VBIC model and Cadence
built-in VBIC model.
58
2 4 6 8 10
?3
?2.5
?2
?1.5
Cadence built?in VBIC
Verilog?A  VBIC
2 4 6 8 10
?30
?28
?26
?24
?22
?20
2 4 6 8 10
10
15
20
25
2 4 6 8 10
?10
?8
?6
?4
?2
0
S
11
(dB)
Frequency (GHz)
S
12
(dB)
Frequency (GHz)
S
21
(dB)
Frequency (GHz)
S
22
(dB)
Frequency (GHz)
V
CB
 = 0 V  V
BE
 = 0.85 V 
A
E
 = 0.5 ? 0.25 ?m
2
 
Figure 4.3: S-parameters vs f curves of Verilog-A based VBIC model and Cadence
built-in VBIC model.
10
?6
10
?5
10
?4
10
?3
10
?2
0
5
10
15
20
25
30
35
40
45
50
I
C
  (A)
f
T
  (GHz)
Cadence built?in VBIC
Verilog?A VBIC
A
E
 = 0.5 ? 2.5 ?m
2
 
V
CB
 = 0 V 
Figure 4.4: f
T
vsI
C
of Verilog-A based VBIC model and Cadence built-in VBIC model.
59
4.4.3 Noise Simulation
The Verilog-A based VBIC model generates identical minimum noise figure NF
min
and noise resistanceR
n
results to the Cadence built-in VBIC mode, as shown in Fig. 4.5.
10
?2
10
0
0
2
4
6
8
Cadence built?in VBIC
Verilog?A  VBIC
0 2 4 6 8 10
0
0.5
1
1.5
2
10
?2
10
0
0
100
200
300
400
500
0 2 4 6 8 10
10
11
12
13
NF
min
(dB)
I
C
 (mA)
NF
min
(dB)
Frequency (GHz)
R
n
 (
?
)
I
C
 (mA)
R
n
 (
?
)
Frequency (GHz)
A
E
 = 0.5 ? 2.5 ?m
2
 
V
CB
 = 0 V    Freq = 2 GHz
A
E
 = 0.5 ? 2.5 ?m
2
 
V
CB
 = 0 V    V
BE
 = 0.85 V
A
E
 = 0.5 ? 2.5 ?m
2
 
V
CB
 = 0 V    Freq = 2 GHz
A
E
 = 0.5 ? 2.5 ?m
2
 
V
CB
 = 0 V    V
BE
 = 0.85 V
Figure 4.5: Bias and frequency dependence of NF
min
and R
n
of Verilog-A based VBIC
model and Cadence built-in VBIC model.
60
4.4.4 Large Signal Simulation
P
out
vs P
in
of Verilog-A based VBIC model and Cadence built-in VBIC model are
compared in Fig. 4.6. The results show that the Verilog-A based VBIC model produces
identical large signal simulation results to the Cadence built-in VBIC mode.
?40 ?30 ?20 ?10 0
?20
?10
0
10
20
Input Power    (dBm)
Output Power  (dBm)
Cadence built?in VBIC
Verilog?A VBIC
Figure 4.6: P
out
vs P
in
of Verilog-A based VBIC model and Cadence built-in VBIC
model.
4.5 Summary
The VBIC model was converted into the Verilog-A language, and implemented
into circuit simulators Cadence and ADS. The main problems that arose, including syn-
tax errors, convergence problems and numerical problems, were solved. Noise models
61
were then added to the Verilog-A based model to be consistent with the Cadence built-in
model. Comparisons of the DC, ac, noise and large signal simulation comparisons be-
tween the Verilog-A based VBIC model and the Cadence built-in VBIC model revealed
identical results.
62
CHAPTER 5
USING VERILOG-A FOR SIGE HBT NOISE MODELING
As discussed in Chap 2, the main reason for using Verilog-A based modeling is its
convenience, as it can be easily modified without the need to interface with the circuit
simulator. In addition, the internal currents, capacitors, and noise sources are accessible,
which is not the case for built-in models. This makes it possible for device and modeling
researchers to investigate the device physics and modeling in detail and more e?ciently.
In this chapter, two Verilog-A based VBIC model applications for SiGe HBT noise
modeling are presented.
5.1 Inverse circuit simulation for 1/f Noise
Transistor low-frequency noise is an important issue in both the baseband and RF
circuits of a wireless transceiver due to its conversion to phase noise. In a bipolar tran-
sistor, the major low-frequency noise source lies in the base current. Experimentally, it
has been established that this base current noise source is located between the internal
base and emitter nodes in an equivalent circuit. This base current low-frequency noise,
denoted as i
bn
, is often measured indirectly from the collector voltage noise by applying
to the transistor base a source impedance that is much greater than the input impedance,
as shown in Fig 5.1. The measured collector voltage noise is converted to collector cur-
rent noise using S
I
C
= S
V
C
/R
2
C,eff
which is then converted to the base current noise
using S
I
B
= S
I
C
/?
2
ac
, with ?
ac
being the low-frequency small signal ac current gain. ?
ac
63
is often determined from the device?s Gummel characteristics, measured under a biasing
condition close to that used in the noise measurement. The base current noise can also
be measured ?directly? from the base using a high precision current amplifier with an
input impedance much lower than the transistor input impedance. Each method has its
advantages and disadvantages in practice, as discussed in [17]. In general, the indirect
method is easier to implement, and is widely used. The indirect method was applied
for this research project [18]. Similar limitations and assumptions exist in the ?direct?
measurement method.
Figure 5.1: Small signal equivalent circuit assumed in the conventional method.
The widely used conventional measurement method is based on a simplified equiv-
alent circuit derived under isothermal conditions. However, in modern SiGe HBTs,
self-heating can be significant, in part due to their high operating current density. To en-
able high current density operation, the collector doping is increased with device vertical
64
scaling, which then increases the collector-base junction field and thus creates problems
with avalanche multiplication. Errors are therefore expected in the low-frequency noise
measured using conventional method in high speed SiGe HBTs.
Here, a new method was developed to extract the base current low-frequency noise
that takes into account the higher order physical e?ects that are significant in modern
SiGe HBTs, such as avalanche multiplication and self-heating. Instead of basing the
extraction on a simplified small signal equivalent circuit, the same circuit as that used in
noise measurement was simulated. The circuit simulator used in this work was Cadence
SpectreRF. For a given internal base current noise excitation, the collector voltage noise
was simulated, and the noise transfer function, or the noise gain G
noise
, obtained from
the ratio of the simulated collector voltage noise and internal base current noise exci-
tation. The internal base current noise was then extracted from the measured collector
voltage noise using S
I
B
= S
V
C
/G
noise
. This extraction method is referred to as inverse
circuit simulation based low-frequency noise extraction, as the input base current noise
is essentially simulated from the measured output voltage noise.
The Verilog-A based VBIC model is the best way to implement this new inverse cir-
cuit simulation method due to its easy access to the internal base and collector currents,
the key point of this method. The VBIC model also takes into account self-heating and
avalanche multiplication e?ects. As a result, the impact of self-heating and avalanche
multiplication on low-frequency noise extraction are automatically included. Further-
more, other non-ideal e?ects such as the Early e?ect, terminal parasitic resistances, and
high injection e?ects are also accounted for.
65
When a unity magnitude small signal noise current is placed between the inter-
nal base and emitter nodes, the resulting collector voltage noise gives the noise gain.
The measured collector voltage noise is then divided by the simulated noise gain for all
frequencies to obtain the internal base current noise spectrum, i.e. S
I
BE
= S
V
C
/G
noise
.
Fig 5.2 compares the S
I
BE
spectra extracted using the conventional method and the pro-
posed inverse circuit simulation method. V
CB
= 2V,I
BE
= 10 ?A, terminal base current
I
B
is 8.1 ?A,. The S
I
BE
extracted from inverse circuit simulation is almost 10 times
higher than that from the conventional method.
Figure 5.2: Comparison of S
I
BE
spectra extracted to the proposed inverse circuit simu-
lation and the conventional measurement method. V
CB
=2V,I
BE
=2 ?A.
In the research reported here, an inverse circuit simulation based method was de-
veloped for the extraction of base current noise spectra in advanced SiGe HBTs. A
66
key di?erence from the conventional method is that the noise gain is obtained much
more accurately by taking into account higher order e?ects such as avalanche multipli-
cation and self-heating. The utility of the method was demonstrated by examining the
collector-base voltage and base transport current dependence of 1/f noise. The pro-
posed method can be applied to the extraction of the correlation between base current
noise and collector current noise using a double channel dynamic signal analyzer.
5.2 Noise generating current in oscillators
Oscillator phase noise is an important concern for RF semiconductor technology.
Physically speaking, oscillator phase noise results from transistor 1/f noise, base re-
sistance thermal noise, the base and collector current shot noise, as well as any other
thermal noise sources in the passive components (e.g. inductors).
Besides 1/f noise, there is always thermal noise due to base resistance and the
base and collector current shot noise associated with the DC currents. To identify the
phase noise limitations of today?s technologies, it is helpful to separate the phase noise
contributions from various physical noise sources. The bottle neck of phase noise can
then be identified and improved [19] [20].
In a small signal noise measurement, the transistor is biased at a fixedI
B
orI
C
. The
small signal base current 1/f noise and base current shot noise are simple functions of
the base terminal current I
B
, and the collector current shot noise is simple function of
terminal current I
C
. In an oscillator, the situation is complicated as:
67
1. The terminal base current I
B
has a large capacitive component, which does not
contribute to either 1/f noise or shot noise. Instead, the internal base to emitter
junction current, I
BE
, is responsible for noise generation. This is illustrated in
Fig. 5.3 using a simplified large signal transistor model. Similarly, the terminal
I
C
is di?erent from the noise generating collector to emitter transport currentI
CE
.
2. The internal I
BE
and I
CE
responsible for base and collector current noise genera-
tion is periodically oscillating.
Figure 5.3: A simplified large transistor model.
Therefore, to understand the phase noise upconversion process, it is first necessary
to separate the internal I
BE
from the external I
B
, and the internal I
CE
from the external
I
C
. The internal I
BE
and the internal I
CE
can be accessed by the Verilog-A based VBIC
model to better understand the di?erent upconversion mechanisms of the base current
1/f noise and base current short noise.
68
Fig. 5.4 shows the waveforms of the terminal I
B
, the noise generating internal I
BE
,
and internal base-emitter voltage V
BE
for an oscillator designed with the 50 GHz peak
f
T
SiGe HBT. The di?erence between I
B
and I
BE
is obvious even where the device
peak f
T
is much higher than the oscillation frequency (5.5 GHz). Due to the nature
of oscillations, the base emitter junction is turned on and o? periodically, as shown on
the right y-axis of Fig. 5.4 . A significant portion of the terminal base current is due
to capacitive charging and discharging of the strongly nonlinear junction capacitances.
The noise generating current, I
BE
, is only a small portion of the terminal I
B
.
Figure 5.4: Comparison of terminal I
B
and internal I
BE
for the 50 GHz HBT. The
internal V
BE
is shown on the right y-axis.
69
5.3 Summary
Using the Verilog-A base VBIC model, a new inverse circuit simulation based
method for extraction of base current noise spectra in advanced SiGe HBTs was pro-
posed. The utility of the method was demonstrated by examining the collector-base
voltage and base transport current dependence of 1/f noise. To better understand the
di?erent upconversion mechanisms of the base current 1/f noise and base current short
noise, the internal I
BE
from the external I
B
, and the internal I
CE
from the external I
C
were successfully separated by the Verilog-A based VBIC model.
70
CHAPTER 6
TEMPERATURE SCALABLE MODELING OF DC CURRENTS
SiGe HBTs have demonstrated their ability to operate over a wide temperature
range that is of particular interest for designers of extreme environment electronics,
from -230
?
Cto300
?
C, along with excellent tolerance to high doses of radiation [2].
This, together with its integration with CMOS, makes SiGe BiCMOS technology very
attractive for implementing electronics for aviation and space exploration [21].
Of critical importance to successful circuit design is the availability of accurate
device models. At present, designers of electronics for extreme environment electron-
ics have to use the same device models used by general purpose electronics designers,
which are only suitable between -55
?
Cto120
?
C. Fig. 6.1 compares the measured and
simulated Gummel curves at 43 K and 85 K for an IBM SiGe HBT with 50 GHz peak
f
T
. The general purpose model parameters from IBM?s design kit were used to gener-
ate the curves in the figure, which are intended for applications from -55
?
Cto120
?
C.
Clearly, the VBIC model, as is, does not work well at these low temperatures.
A temporary solution is to use VBIC as an isothermal model. The temperature
dependences of device parameters are turned o?, and device parameters are extracted to
fit measured data at a single temperature. This can be repeated for several temperature
points across the temperature range of interest. Clearly, this approach does not allow
for self-heating. More importantly, this approach cannot be used to design circuits that
require continuous description of device performance over temperature [2], such as the
71
0.8 0.9 1 1.1 1.2
10
?14
10
?12
10
?10
10
?8
10
?6
10
?4
10
?2
V
BE
    (V)
I
B
  &  I
C
   (A)
T = 43 K
T = 85 K
Solid lines: Measured Data  
Dash lines: Simulated Data  
V
CB
 = 0 V 
A
E
 = 0.5 ? 2.5 ?m
2
 
Figure 6.1: Comparison of Gummel curves from Cadence simulation results and mea-
surement data at low temperatures.
bandgap reference circuit, a fundamental circuit block critical to the reliable operation of
numerous analog, digital, and mixed-signal circuits over a wide range of temperatures.
The VBIC model is chosen for these simulations as it is used in the design kit for this
technology.
Here, the temperature dependence of key VBIC model parameters for DC current
modeling from 300 K to 43 K was examined. The temperature mapping models were
then evaluated. A group of improved temperature mapping models for DC currents were
presented and implemented using Verilog-A, with an emphasis on lower temperature
operation down to 43 K. Excellent fitting was obtained using a single set of model
72
parameters. These results are useful for the design of circuits that need to operate from
300 K down to 43 K [22].
6.1 Evaluation of Temperature Mapping Models in VBIC
The isothermal model parameters were first extracted using gradient search and
quasi-Newton search optimization based on least-squares error functions. Device physics
was considered during extraction to obtain physically meaningful parameters.
In VBIC, as outlined in Chapter 3, the collector current is described by
I
C
=
I
tf
?I
tr
q
b
(6.1)
I
tf
= I
S
bracketleftbigg
exp
parenleftbigg
V
BEI
N
F
V
T
parenrightbigg
? 1
bracketrightbigg
(6.2)
I
tr
= I
S
bracketleftbigg
exp
parenleftbigg
V
BCI
N
R
V
T
parenrightbigg
? 1
bracketrightbigg
(6.3)
I
S
and N
F
are temperature dependent. The T dependence of I
S
is described by
I
S
(T) = I
s,nom
r
X
is
N
F,nom
T
e
?
Ea(1?r
T
)
N
F,nom
V
T
(6.4)
where the subscript nom indicates nominal temperature, r
T
= T/T
nom
, X
is
is the temper-
ature exponent of I
S
, and E
a
= E
g
(0) is activation energy for I
S
. The T dependence of
N
F
in VBIC is given by
N
F
(T) = N
F,nom
(1+T
nf
d
T
) (6.5)
73
where T
nf
is temperature coe?cient of N
F
, and d
T
= T ?T
nom
.
As shown in Eq. (6.5), N
F
in VBIC is linearly dependent on temperature. The
extracted isothermal N
F
parameter, however, indicates a stronger dependence on tem-
perature, as shown in Fig. 6.2. A similar temperature dependence is also observed for
the extracted N
EI
parameter, the counterpart of N
F
for base current that is described in
VBIC.
0 50 100 150 200 250 300
1
1.1
1.2
1.3
1.4
1.5
Temperature (K)
Forward Ideality Factor N
F
Extracted N
F
N
F
 Model in VBIC
V
CB
 = 0 V 
A
E
 = 0.5 ? 2.5 ?m
2
 
Figure 6.2: Comparison of extracted isothermal N
F
and N
F
temperature mapping
model in VBIC.
Fig. 6.3 shows the extracted isothermal I
S
vs temperature, together with fitting
results using Eq. (6.4). The fitting is good at high temperature, but becomes worse at
low temperatures. Attempts were made to calibrate temperature related parameter E
a
74
and X
is
to obtain a better fitting, but it was not possible to fit the data for 43 K and 110
K simultaneously.
Other parameters related to DC current modeling were also extracted for all the
temperatures, and their temperature mapping models were evaluated, including terminal
resistances, quasi-saturation parameters, forward knee current I
KF
, ideal B-E saturation
current I
BEI
, and so forth. In general, the temperature mapping models of many of
the parameters in VBIC were not su?cient to cover the wide temperature range from
300 K to 43 K. Improved equations are therefore clearly necessary. For the following
parameters, the temperature mapping models in VBIC were found to be su?cient:
1. terminal resistances: intrinsic base resistance R
bi
, extrinsic base resistance R
bx
,
extrinsic collector resistance R
cx
, and emitter resistance R
e
.
2. quasi-saturation parameters: intrinsic collector resistance R
ci
, epi drift saturation
voltage V
o
, epi doping parameter G
amm
, and high current RC factor H
rcf
.
The temperature mapping models of the key parameters that need to be improved for
modeling over a wide temperature range are discussed below.
6.2 Improved Temperature Mapping Models
The primary reason for the limited applicable temperature range of current mod-
els is thought to be that the model equations were derived using simplified physics or
assumptions that do not cover the wide temperature range of interest for this work. Im-
proved temperature mapping models for key parameters of importance to DC currents
75
0 50 100 150 200 250 300
10
?100
10
?50
10
0
Temperature (K)
Saturation Current    I
S
 (A)
Extracted I
S
I
S
 model in VBIC
V
CB
 = 0 V 
A
E
 = 0.5 ? 2.5 ?m
2
 
Figure 6.3: Comparison of I
S
temperature mapping model in VBIC and extracted
isothermal I
S
parameters.
were therefore constructed. The corresponding Verilog-A code for each section can be
found in Appendix A.
6.2.1 Improved N
F
Temperature Mapping Model
As shown in Fig. 6.2, the ideality factor N
F
increases exponentially with decreas-
ing temperature as a result of carrier transport mechanism across the E-B heterojunc-
tion [23]. To better describe the temperature dependence of N
F
, two extra terms, A
nf
and X
nf
, can be introduced based on the N
F
temperature mapping model in VBIC. The
76
modified equation is
N
F
(T) = N
F,nom
(1+T
nf
d
T
+A
nf
(r
X
nf
T
? 1)). (6.6)
Similarly, N
EI
also increases exponentially with decreasing temperature due to
additional base current induced by extra recombination [23]. This can be modeled using
the same temperature mapping equation, but with di?erent N
F,nom
, T
nf
, A
nf
, and X
nf
values. Fig. 6.4 shows the improved N
EI
and N
F
modeling results using Eq. (6.6).
0 50 100 150 200 250 300
1
1.1
1.2
1.3
1.4
1.5
Extracted N
EI
New N
EI
 Model
Extracted N
F
New N
F
 Model
Ideality Factor N
EI
 and N
F
V
CB
 = 0 V 
Temperature (K)
N
EI
 
N
F
 
A
E
 = 0.5 ? 2.5 ?m
2
 
Figure 6.4: Improved N
EI
and N
F
model with new equations.
77
6.2.2 Improved I
S
Temperature Mapping Model
The most significant parameter responsible for T dependence of I
S
is E
a
, which is
essentially the bandgap energy at 0 K, and thus a constant. However, a close examination
of the derivation of I
S
shows that this is only true when the bandgap is assumed to be
a linear function of temperature. This assumption becomes less valid, however, over a
wide temperature range. A new derivation of I
S
taking into account the nonlinear T
dependence of the bandgap leads to a new I
S
equation of similar form to (6.4), but with
a temperature dependent activation energy, which we denote asE
a,true
[24]. The detailed
derivation of E
a,true
is shown as follows. Physically, as derived in (3.82) in Chapter 3,
I
S
can be rewritten as
I
S
(T) = I
S
(T
nom
)
parenleftbigg
T
T
nom
parenrightbigg
X
IS
exp
bracketleftbigg
?
E
g
(T)
KT
+
E
g
(T
nom
)
KT
nom
bracketrightbigg
(6.7)
Empirically,
E
g
(T) = E
g
(0) ?
?T
2
T +?
(6.8)
where ? and ? are temperature related parameters. E
g
can be introduced into the expo-
nential term of I
S
. Let
A = ?
E
g
(T)
KT
+
E
g
(T
nom
)
KT
nom
(6.9)
= ?
1
KT
bracketleftbigg
E
g
(T) ?E
g
(T
nom
)
T
T
nom
bracketrightbigg
(6.10)
78
E
g
(T
nom
) is obtained by substituting T by T
nom
in (6.8),
E
g
(T
nom
) = E
g
(0) ?
?T
2
nom
T
nom
+?
(6.11)
Substituting (6.8) and (6.11) in (6.13) gives
A = ?
1
KT
bracketleftbigg
E
g
(0) ?
?T
2
T +?
?E
g
(0)
T
T
nom
+
?T
2
nom
T
nom
+?
T
T
nom
bracketrightbigg
(6.12)
= ?
1
KT
bracketleftbigg
E
g
(0)
parenleftbigg
1 ?
T
T
nom
parenrightbigg
+
?T
2
nom
T
nom
+?
T
T
nom
?
?T
2
T +?
bracketrightbigg
(6.13)
Let
B =
?T
2
nom
T
nom
+?
T
T
nom
?
?T
2
T +?
(6.14)
=
?T
2
T
nom
+??TT
nom
??T
2
T
nom
???T
2
(T +?)(T
nom
+?)
(6.15)
=
??TT
nom
???T
2
(T +?)(T
nom
+?)
(6.16)
=
??TT
nom
parenleftBig
1 ?
T
T
nom
parenrightBig
(T +?)(T
nom
+?)
(6.17)
=
??
T
T
nom
T
2
nom
(T +?)(T
nom
+?)
parenleftbigg
1 ?
T
T
nom
parenrightbigg
(6.18)
Substituting (6.18) into (6.13) produces
A = ?
1
KT
bracketleftBigg
E
g
(0)
parenleftbigg
1 ?
T
T
nom
parenrightbigg
+
??
T
T
nom
T
2
nom
(T +?)(T
nom
+?)
parenleftbigg
1 ?
T
T
nom
parenrightbigg
bracketrightBigg
(6.19)
79
A = ?
1
KT
parenleftbigg
1 ?
T
T
nom
parenrightbigg
bracketleftBigg
E
g
(0) +
??
T
T
nom
(T
nom
)
2
(T +?)(T
nom
+?)
bracketrightBigg
(6.20)
= ?
1
KT
(1 ?r
T
)
bracketleftbigg
E
g
(0) +
??r
T
(T
nom
)
2
(T +?)(T
nom
+?)
bracketrightbigg
(6.21)
Substituting (6.21) into (6.7), I
S
becomes
I
S
(T) = I
S
(T
nom
)
parenleftbigg
T
T
nom
parenrightbigg
X
IS
exp
braceleftbigg
?
1
KT
(1 ?r
T
)
bracketleftbigg
E
g
(0) +
??r
T
(T
nom
)
2
(T +?)(T
nom
+?)
bracketrightbiggbracerightbigg
(6.22)
Comparing (6.22) to (3.86) in Chapter 3, the new E
a
is
E
a
(T) = E
g
(0) +
??r
T
(T
nom
)
2
(T +?)(T
nom
+?)
(6.23)
Mapping E
a
from T
nom
to T gives
E
a
(T
nom
) = E
g
(0) +
??(T
nom
)
2
(T
nom
+?)
2
(6.24)
hence,
E
g
(0) = E
a
(T
nom
) ?
??(T
nom
)
2
(T
nom
+?)
2
(6.25)
80
Finally, E
a,true
is
E
a,true
(T) = E
a
(T
nom
) +
??r
T
(T
nom
)
2
(T +?)(T
nom
+?)
?
??(T
nom
)
2
(T
nom
+?)
2
(6.26)
= E
a,nom
+
??
2
T
2
nom
(r
T
? 1)
(? +T
nom
)
2
(? +T)
(6.27)
where E
a,nom
= E
a
(T
nom
). Then I
S
is changed to
I
S
(T) = I
s,nom
r
X
is
N
F,nom
T
e
?
Ea,true(1?r
T
)
N
F,nom
V
T
(6.28)
In addition, to alleviate the convergence problem at low temperatures, the temperature
dependent parameter N
F
is used to replace N
Fnom
in the I
S
equation. The new I
S
equation is
I
S
(T) = I
s,nom
r
X
is
N
F
T
e
?
Ea,true(1?r
T
)
N
F
V
T
(6.29)
E
a,true
can be extracted as the E
a
required to fit the I
S
at each temperature in the
original I
S
model. Fig. 6.5 compares the extracted and modeled E
a,true
. A good fitting
has been obtained.
With the new I
S
model, good I
S
modeling is achieved, as shown in Fig. 6.6, from
300Kdownto43K.ThenewI
S
model is also expected to work at temperatures from
300 K to at least 400 K, the same range for which the conventional I
S
model works.
The same equation is also applied to describe the saturation current for I
B
, I
BEI
.
81
0 50 100 150 200 250 300
1
1.02
1.04
1.06
1.08
1.1
1.12
1.14
1.16
1.18
1.2
Temperature   (K)
E
a,true
  (V)
Extracted E
a,true
E
a,true
 with Model
Figure 6.5: E
a,true
as a function of temperature fitted using Eq. (6.27).
6.2.3 Improved I
KF
Temperature Mapping Model
The knee current I
KF
, which was originally used to physically describe high injec-
tion in the base of a BJT, has now become an empirical parameter for SiGe HBT due
to highly doped base. However, the I
KF
extraction results show that the I
KF
tempera-
ture mapping model in VBIC is no longer adequate for SiGe HBTs. A new temperature
mapping model for I
KF
is proposed
I
KF
(T) = I
KF,nom
(1?T
ikf
d
T
+A
ikf
(r
X
ikf
T
? 1)) (6.30)
Using Eq. 6.30, excellent fitting of I
KF
is achieved, as shown in Fig. 6.7.
82
0 50 100 150 200 250 300
10
?100
10
?80
10
?60
10
?40
10
?20
10
0
Extracted I
S
New I
S
 model with E
a,true
Saturation Current    I
S
 (A)
V
CB
 = 0 V 
Temperature (K)
A
E
 = 0.5 ? 2.5 ?m
2
 
Figure 6.6: Improved I
S
fitting with new E
a,true
model.
6.2.4 Temperature Mapping Models for R
th
and avc2
The temperature dependence of thermal resistance R
th
, which describes the ex-
cess temperature due to dissipated power, is not included in VBIC. The extracted R
th
decreases with decreasing temperature. The temperature dependence ofR
th
can be mod-
eled similarly to the way other regular resistances are modeled [25] [26].
The avalanche model parameter avc2 is a linear function of T in VBIC. A more
complicated temperature model for better output curve fitting is therefore necessary. It
has also been observed that the weak avalanche model itself in VBIC has limitations at
43 K, even when used as an isothermal model. Avalanche current data cannot be fitted
by simply changing the temperature related avalanche parameters at 43 K.
83
0 50 100 150 200 250 300
0
1
2
3
4
x 10
?3
Temperature   (K)
I
KF
   (A)
Extracted I
KF
New I
KF
 Model
V
CB
 = 0 V 
A
E
 = 0.5 ? 2.5 ?m
2
 
Figure 6.7: Improved I
KF
fitting with new temperature mapping model.
6.3 Simulation Results
The VBIC based new model was implemented using Verilog-A, a hardware de-
scription language, compiled into binary code, and dynamically linked to a circuit simu-
lator (ADS) through its compact modeling interface. Fig. 6.8 shows the collector current
and base current modeling results. Good fitting down to 43 K was obtained. Fig. 6.9 (a)
and (b) show the output curve modeling results at 175 K and 43 K, respectively. Good
data-model fitting was obtained at both temperatures. Note that a single set of model
parameters was used to achieve fitting at all temperatures.
84
0.4 0.5 0.6 0.7 0.8 0.9 1 1.1
10
?10
10
?8
10
?6
10
?4
10
?2
10
0
V
BE
   (V)
I
C
   (A)
Solid lines: Measured Data
Dash lines: Model         
V
CB
 = 0 V 
300 K 
223 K 175 K 110 K 
43 K 
A
E
 = 0.5 ? 2.5 ?m
2
 
(a)
0.5 0.6 0.7 0.8 0.9 1 1.1
10
?10
10
?8
10
?6
10
?4
10
?2
V
BE
     (V)
I
B
    (A)
Solid lines: Measured Data
Dash lines: Model         
V
CB
 = 0 V 
300 K 223 K 175 K 
110 K 43 K 
A
E
 = 0.5 ? 2.5 ?m
2
 
(b)
Figure 6.8: (a) Improved I
C
-V
BE
fitting with new models, and (b) Improved I
B
-V
BE
fitting with new models.
85
0 1 2 3 4
0
0.5
1
1.5
2
2.5
x 10
?3
I
C
   (A)
T = 175 K 
Solid lines: Measured Data
Dash lines: Model         
V
CE
   (V)
A
E
 = 0.5 ? 2.5 ?m
2
 
I
B
 = 20 ?A 
14 ?A 
8.1 ?A 
4.35 ?A 
1.35 ?A 
0.1 ?A 
(a)
0 0.5 1 1.5 2 2.5 3 3.5
0
0.2
0.4
0.6
0.8
1
x 10
?3
I
C
   (A)
Solid lines: Measured Data
Dash lines: Model         
A
E
 = 0.5 ? 2.5 ?m
2
 
V
CE
   (V)
T = 43 K 
I
B
 = 8.93 ?A  
6.1 ?A 
3.38 ?A 
1.68 ?A 
0.452 ?A 
(b)
Figure 6.9: Improved DC output fitting at (a) 175 K, and (b) 43 K, with new models.
86
6.4 Summary
This chapter reported the experimental examination of the temperature dependence
of key VBIC model parameters for DC current modeling from 300 K to 43 K, and
evaluated their temperature mapping models. New model equations were presented and
implemented using Verilog-A. An excellent fitting was obtained using a single set of
model parameters.
87
CHAPTER 7
MODELING OF INTERMODULATION LINEARITY IN A 200 GHZ SIGE HBT
TECHNOLOGY
Intermodulation linearity is an important figure-of-merit for RF devices, as it re-
lates to the selectivity of a RF receiver and the spectral purity of a RF transmitter. Vari-
ous theories, simulations, and experimental investigation of linearity have been reported
for Si, SiGe and III-V bipolar transistors [27] [28] [29] [30] [31] [32]. Accurate sim-
ulation and modeling of linearity is challenging, as it requires accurate descriptions
of the higher order derivatives of all the nonlinear current and charge relationships in
the device. From a circuit design standpoint, it is desirable to understand how linear-
ity changes as a function of biasing current and voltage, as well as device breakdown
voltage, as both biasing point and breakdown voltage are design variables. Another im-
portant issue practically is how accurate the compact models are in simulating linearity.
Model validation is typically done using DC I-V data and small signal s-parameters,
rather than linearity data because of the complexity involved and the time consuming
nature of linearity measurements.
The purpose of this work was to evaluate the linearity simulation capability of
the VBIC, HICUM and Mextram models in a 200 GHz SiGe HBT technology using
harmonic balance. The results provide valuable new insights into the device physics
underlying linearity behavior, guidelines to optimal biasing, device selection (e.g. high
breakdown versus low breakdown versions), as well as quantified simulations for data
88
comparison of linearity that will be useful for designers and modelers. The input 3rd
order intercept point, IIP3, is used here as a figure-of-merit for intermodulation linearity.
IIP3 was measured on the I
C
-V
CE
plane for devices of various size and breakdown
voltage [34].
Initially, the models used in this work were examined by comparing the simulated
and measured I-V and small signal s-parameters. For the standard breakdown HBT,
VBIC, Mextram and HICUM models were used from the design kit developed for the
same HBT used in this work. All three of the models produced reasonable fittings
for the I-V curves at low current levels. Fig. 7.1 and Fig. 7.2 show comparisons of
the measured and VBIC simulated S-parameters vs frequency at V
CE
= 1.0 V, I
C
=
12.8 mA. Clearly, VBIC can model standard breakdown HBT well at low current. The
Mextram and HICUM models also produced reasonable fitting of S-parameters at low
current. The main di?erence is the high current behavior for the models. A detailed
comparison of the high current I-V and S-parameters as a function of bias shows that
for all the models, accuracy degrades at higher I
C
(even below peak f
T
). Only the
VBIC model is available for the high breakdown HBT. ADS, as opposed to Cadence
SpectreRF, was used for this part of the research, because of its accuracy and e?ciency
for IP3 simulation. The Cadence design kit was accessed through the ADS dynamic link
in the Cadence tools.
89
0 10 20 30 40
?1
?0.5
0
0.5
data
VBIC in ADS
0 10 20 30 40
?0.8
?0.6
?0.4
?0.2
0
0 10 20 30 40
0
0.02
0.04
0.06
0.08
0.1
0 10 20 30 40
0
0.01
0.02
0.03
0.04
0.05
?
(S
11
) 
Freq    (GHz)
?
(S
11
) 
Freq    (GHz)
?
(S
12
) 
Freq    (GHz)
?
(S
12
) 
Freq    (GHz)
8HP 0.12 ? 18 ?m
2
, SBV
V
CE
 = 1.0 V, I
C
 = 12.8 mA
Figure 7.1: Comparison of measured and VBIC simulated S
11
& S
12
vs frequency at
V
CE
= 1.0 V, I
C
= 12.8 mA. Standard Breakdown HBT.
7.1 Standard Breakdown HBT
Fig. 7.3 (a)-(d) compare the simulated and measured IIP3 as a function of I
C
for
the standard breakdown HBT. Initially, the V
CE
= 1.0 V case was examined. All three
of the models performed well at I
C
< 5 mA. For I
C
>5mAandI
C
< 20 mA, all
of the models were o? by approximately 2 dB. At V
CE
= 1.0 and 1.3V, only HICUM
was able to model the high current IP3 rollo? and rise behavior (near 30 mA), because
of its improved high current region modeling. However, in terms of the IIP3 value
90
0 10 20 30 40
?15
?10
?5
0
5
data
VBIC in ADS
0 10 20 30 40
2
4
6
8
10
12
0 10 20 30 40
?0.2
0
0.2
0.4
0.6
0.8
0 10 20 30 40
?0.6
?0.5
?0.4
?0.3
?0.2
?0.1
?
(S
21
) 
Freq    (GHz)
?
(S
21
) 
Freq    (GHz)
?
(S
22
) 
Freq    (GHz)
?
(S
22
) 
Freq    (GHz)
8HP 0.12 ? 18 ?m
2
, SBV
V
CE
 = 1.0 V, I
C
 = 12.8 mA
Figure 7.2: Comparison of measured and VBIC simulated S
21
& S
22
vs frequency at
V
CE
= 1.0 V, I
C
= 12.8 mA. Standard Breakdown HBT.
discrepancy, the VBIC model was the most accurate below 25 mA. Model comparisons
at V
CE
= 1.3 V were similar to those at V
CE
= 1.0 V. At V
CE
= 1.6 and 1.9 V, HICUM
and Mextram show no clear advantages over VBIC.
91
7.2 High Breakdown HBT
Moving on to a comparison of the simulated and measured IIP3 for the high break-
down HBT, Fig. 7.4 (a)-(d) compares simulated and measured IIP3 as a function of I
C
for V
CE
= 1.3, 1.9, 2.5 and
92
?20
?10
0
IIP3    (dBm)
?20
?10
0
IIP3    (dBm)
data
VBIC
MEXTRAM
HICUM
?20
?10
0
IIP3    (dBm)
0 10 20 30 40 50
?20
?10
0
10
I
C
    (mA)
IIP3    (dBm)
V
CE
 = 1.0 V
V
CE
 = 1.3 V
V
CE
 = 1.6 V
V
CE
 = 1.9 V
8HP 0.12 ? 18 ?m
2
 
SBV Device 
Freq = 5 GHz 
(a) 
(b) 
(c) 
(d) 
Figure 7.3: Comparison of simulated and measured IIP3 at V
CE
= 1.0, 1.3, 1.6 and 1.9
V. Standard Breakdown HBT.
93
?40
?20
0
20
IIP3    (dBm)
data
VBIC in ADS
?20
?10
0
10
IIP3    (dBm)
?20
?10
0
10
IIP3    (dBm)
0 2 4 6 8 10
?20
?10
0
I
C
    (mA)
IIP3    (dBm)
V
CE
 = 1.3 V
V
CE
 = 1.9 V
V
CE
 = 2.5 V
V
CE
 = 3.1 V
8HP 0.12 ? 18 ?m
2
 
HBV Device 
Freq = 5 GHz 
(a) 
(b) 
(c) 
(d) 
Figure 7.4: Comparison of simulated and measured IIP3 at V
CE
= 1.3, 1.9, 2.5 and 3.1
V. High Breakdown HBT.
94
3.1 V, using VBIC, the only model available. The simulation agrees well with the mea-
surement at lower I
C
and lower V
CE
and captures the overall variation of IIP3 with I
C
and V
CE
. Quantitative agreement, however, is not satisfactory at higher I
C
or higher
V
CE
.
7.3 Impact of Avalanche and Self-heating
The Volterra series based analysis reported in [29] showed that cancellation of CB
capacitance nonlinearity and avalanche nonlinearity can result either in improvement of
IIP3, or they can enhance each other to further degrade IIP3. In this simulation, it is pos-
sible to turn on and o? the avalanche function, as well as self-heating, to examine their
impact on IIP3. Initially, the avalanche model was examined by comparing the simu-
lated and measured multiplication factor M-1, as shown in Fig. 7.5. Good multiplication
factor M-1 fitting was obtained. Fig. 7.6 compares the IIP3 simulated with various op-
tions for the standard breakdown HBT, at V
CE
=1.9V. The M-1 value in simulation (and
measurement) is 0.002 at 5 mA and V
CE
= 1.9V, which is weak. Below 25 mA, the IIP3
simulated with avalanche is considerably higher, both with and without self-heating.
Above 25 mA, the IIP3 simulated without avalanche is higher. In the existing compact
models, M-1 is only a function of the internal VCB. Therefore, only the I
C
dependence
of M-1 due to the ICRC voltage drop is included, while the I
C
dependence of avalanche
due to charge modulation in the CB junction is not accounted for. This results in an
overestimation of M-1 at higher I
C
in simulation. Including the decrease of M-1 with
increasing I
C
brings the high I
C
region IIP3 closer to the experimental results in the
95
high I
C
region. Given that a weak avalanche can have a large impact on IIP3, accurate
measurement and modeling of the I
C
dependence of avalanche are clearly necessary.
Self-heating exhibited only a weak e?ect on IIP3.
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
10
?8
10
?6
10
?4
10
?2
10
0
V
CB
    (V)
Multiplication Factor M?1
data
simulation
8HP 0.12 ?18 ?m
2
, SBV 
V
BE
 = 0.65 V 
Figure 7.5: Comparison of simulated and measured M-1 at V
BE
= 0.65 V. Standard
Breakdown HBT.
7.4 Summary
This chapter presented the results of VBIC, HICUM, and Mextram simulation of
intermodulation linearity in a 200 GHz standard breakdown SiGe HBT device and com-
pared the I
C
and V
CE
dependences of IIP3. At relatively low values of I
C
and V
CE
,
96
0 10 20 30 40 50 60
?16
?14
?12
?10
?8
?6
?4
?2
0
data
VBIC with AV on, SH on
VBIC with AV on, SH off
VBIC with AV off, SH on
VBIC with AV off, SH off
IIP3  (dBm) 8HP 0.12 ? 18 ?m
2
, SBV 
Freq = 5 GHz, V
CE
 = 1.9 V
I
C
  (mA)
Figure 7.6: Comparison of IIP3 simulated using di?erent combinations of avalanche
and self-heating settings and measured IIP3 at V
CE
= 1.9 V. Standard Breakdown HBT.
VBIC, HICUM, and Mextram all yielded reasonably accurate IIP3. However, at rela-
tively higherI
C
(still well below peakf
T
for standard breakdown HBT) andV
CE
, signif-
icant deviations between simulation and measurement occurred. In some cases, HICUM
better captured the trend of IIP3 variation with I
C
in the high current region. The e?ect
of avalanche on IIP3 was shown to be significant, while the e?ect of self-heating on IIP3
was weak.
97
CHAPTER 8
CONCLUSIONS AND FUTURE WORK
8.1 Conclusions
This research study investigated device physics and compact modeling using a new
technique ? the Verilog-A based VBIC model, which makes a portable device compact
model for the simulator and can be easily modified and implemented into SPICE sim-
ulators without the need to construct new interfaces. The internal currents, charges,
and noise sources used in SPICE simulators, which are not available in built-in models,
became readily accessible using this technique.
Chapter 2 introduced the Verilog-A Language. The principles involved in using
Verilog-A based compact modeling instead of low-level simulator code were discussed.
An example of Verilog-A based diode modeling was given to provide a better under-
standing of the Verilog-A language. The device physics behind the VBIC model and the
temperature models in VBIC were introduced in Chapter 3. The VBIC model was con-
verted to the Verilog-A language, and implemented into the SPICE simulators Cadence
and ADS in Chapter 4. The major problems that arose, such as syntax errors, conver-
gence problems and numerical problems, were addressed and solved. Noise models
were added to the Verilog-A based model to be consistent with the Cadence built-in
model. The DC, ac, noise and large signal simulation comparisons showed identical
results for the Verilog-A based VBIC modeling and the Cadence built-in VBIC model.
98
Based on the new Verilog-A based VBIC model, two applications for SiGe HBTs
noise modeling were presented in Chapter 5. First, a new inverse circuit simulation
based low frequency noise extraction method was prosed based on the Verilog-A based
VBIC model. The low frequency noise of device biasing at high current can be mea-
sured more accurately through this method. Second, to better understand the di?erent
phase noise upconversion mechanisms of the base current 1/f noise and base current
short noise in oscillator design, the internal I
BE
and the internal I
CE
were separated
from the external I
BE
and the external I
CE
using Verilog-A based VBIC model. The
results showed that the noise generating current I
BE
made up only a small portion of the
terminal I
B
.
A group of improved temperature mapping models for modeling DC currents down
to 43 K were presented in Chapter 6. The new VBIC based new model was implemented
using Verilog-A, compiled into binary code, and dynamically linked to a circuit simula-
tor (ADS) through its compact modeling interface. The detailed coding of the Verilog-A
based VBIC model with a group of improved temperature mapping models was docu-
mented in Appendix A. Excellent Gummel and output fitting across a wide temperature
range from 300 K down to 43 K were achieved for a 50 GHz SiGe HBT device.
The intermodulation linearity simulation capability of the VBIC, HICUM and Mex-
tram models were evaluated using harmonic balance in a 200 GHz SiGe HBT device in
Chapter 7. The impact of avalanche and selfheating on IIP3 were examined. The results
showed that a weak avalanche has a significant impact on IIP3. The results provided
99
valuable new insights into the device physics underlying linearity behavior and quanti-
fied simulations for data comparisons of linearity that will be useful for designers and
modelers.
8.2 Future Work
The Verilog-A based modeling is a very powerful new method that provides useful
insights into device characteristics to improve compact modeling. Topics for future
investigation include:
1. SiGe HBT noise modeling can be investigated using the Verilog-A based VBIC
model. The internal noise sources can be analyzed and the correlation between
the internal noise sources can be addressed by the Verilog-A based model. This is
potentially very useful, especially for accurate high bias and high frequency noise
modeling of the SiGe HBTs desired for RFIC circuit designs.
2. Verilog-A based modeling methods can also be similarly applied to the BSIM
model for MOSFET devices.
100
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104
APPENDIX A
VERILOG-A CODE WITH KEY IMPROVED TEMPERATURE MAPPING MODELS
A.1 Improved N
F
and N
EI
Temperature Mapping Models
According to (6.6) in Chapter 6, the improved temperature model for N
F
and N
EI
in Verilog-A based model is as follows.
NFatT = NF*(1.0+dT*Tnf+Anf*(pow(rT, Xnf)-1));
NEIatT = NEI*(1.0+dT*Tnei+Anei*(pow(rT, Xnei)-1));
Table A.1 lists the value of the parameters in the improved models.
Parameter Value Parameter Value
NF 1.00072 NEI 1.0001
Tnf -0.00018 Tnei -0.00005
Anf 0.0012 Anei 0.0012
Xnf -2.94 Xnei -2.89
Table A.1: Parameters used for improved N
F
and N
EI
temperature mapping models.
105
A.2 Improved E
a,true
, I
S
and I
BEI
Temperature Mapping Models
According to (6.27) and (6.29) in Chapter 6, the improved temperature model for
E
a,true
and I
S
in Verilog-A based model is as follows.
EAatT = EA+EAalpha*pow(EAbeta,2)*pow(Tini,2)*(rT-1)
/(pow((EAbeta+Tini),2)*(EAbeta+Tdev));
EAIEatT = EAIE+EAIEalpha*pow(EAIEbeta,2)*pow(Tini,2)*(rT-1)
/(pow((EAIEbeta+Tini),2)*(EAIEbeta+Tdev));
ISatT = IS*pow((pow(rT,XIS)*
limexp(-EAatT*(1.0-rT)/Vtv)),(1.0/NFatT));
IBEIatT = IBEI*pow((pow(rT,XII)*
limexp(-EAIEatT*(1.0-rT)/Vtv)),(1.0/NEIatT));
Table A.2 lists the value of the parameters in the improved models.
Parameter Value Parameter Value
IS 1.62694e-18 IBEI 1.09629e-20
XIS 1.78 XII 1.78
EA 1.13 EAIE 1.145
EAalpha 2 EAIEalpha 2.7
EAbeta 1.326 EAIEbeta 1.21
Table A.2: Parameters used for improved E
a,true
, I
S
and I
BEI
temperature mapping
models.
106
A.3 Improved I
KF
Temperature Mapping Model
According to (6.30) in Chapter 6, the improved temperature model for I
KF
in
Verilog-A based model is as follows.
IKFatT = IKF*(1.0-dT*Tikf+Aikf*(pow(rT, Xikf)-1));
Table A.3 lists the value of the parameters in the improved models.
Parameter Value
IKF 0.00382
Tikf 0.00141
Aikf 2.64
Xikf 0.355
Table A.3: Parameters used for improved I
KF
temperature mapping model.
107