Multi-objective Direct Quasi-Sliding Mode Control of a Two Phase Buck
Converter
by
Christopher Wilson
A dissertation submitted to the Graduate Faculty of
Auburn University
in partial fulfillment of the
requirements for the Degree of
Doctor of Philosophy
Auburn, Alabama
August 4, 2012
Keywords: multiphase buck converter, sliding mode control, variable structure systems,
nonlinear control systems, MIMO
Copyright 2012 by Christopher Wilson
Approved by
Robert N. Dean, Co-Chair, Associate Professor of Electrical and Computer Engineering
John Y. Hung, Co-Chair, Professor of Electrical and Computer Engineering
George T. Flowers, Professor of Mechanical Engineering
Abstract
Multiphase converters are the state of the art for high efficiency point-of-load conversion
for modern processors and FPGAs with wide operating load conditions. However, there
are a variety of control issues that must be addressed, such as dynamically adjusting the
number of active phases, robustness to disturbances, and phase current regulation. To
achieve the highest efficiency conversion, the phase currents should not necessarily be split
evenly between phases. Unfortunately, most of the literature concerning multiphase buck
converters implements equal current sharing between phases.
Sliding mode controllers are known for their robustness and insensitivity to disturbances
and plant parameter variations. Sliding mode control is particularly suited for power elec-
tronics due to the inherent switching between two system structures. The control effort of
the sliding mode controller depends solely on which side of the surface the system state
currently resides. This effort can be implemented in two ways: direct and indirect.
This work designs, simulates, and implements a direct sliding mode controller for a two-
phase buck converter. The technical approach extends a single-phase sliding mode controller
to control a two-phase buck converter. Since there are two phases, two switching surfaces
are necessary. Thus, suitable surfaces must be developed to address the challenges of phase
delay in addition to the overall goal of output voltage regulation. This work is tested in
simulation with good results and is implemented with some modifications on a hardware test
platform consisting of a TI TMS320F28335 microcontroller and two buck converter phases.
The proposed controller can be extended to support regulating to desired phase?s currents
and dynamically change the numbers of active phases based on load conditions. This work
confirms that the sliding mode controller is a suitable controller design for multiphase buck
ii
converters and is the basis for future work improving current sharing, implementing phase
shedding, and expanding the maximum number of active phases.
iii
Acknowledgments
Put text of the acknowledgments here.
iv
Table of Contents
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Prior Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Buck Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Control Issues for Multiphase Buck Converters . . . . . . . . . . . . . 3
1.1.3 Sliding Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Buck Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Architecture improvements . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.2 Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.3 Control Improvements . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Sliding Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Sliding Mode Control of a Single-phase Buck Converter . . . . . . . . . . . . . . 19
4 Sliding Mode Control of a Multiphase Buck Converter . . . . . . . . . . . . . . 22
4.1 Model of a Multiphase Buck Converter . . . . . . . . . . . . . . . . . . . . . 22
4.2 SMC of a Two-Phase SR Buck Converter . . . . . . . . . . . . . . . . . . . . 23
4.2.1 Output Voltage Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . 24
v
4.2.2 Control Input Balance . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2.3 Inductor Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . 26
4.2.4 Load Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2.5 Complete Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1 Implementation Hardware and Test Setup . . . . . . . . . . . . . . . . . . . 34
6.2 Experimental Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7 Validations through Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.1 Voltage Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2 Phase Current Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.3 Experimental Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
A Source Code for Two Phase Controller: . . . . . . . . . . . . . . . . . . . . . . . 62
B Source Code for Single Phase Controller: . . . . . . . . . . . . . . . . . . . . . . 114
vi
List of Figures
3.1 Single-phase buck converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 Two-phase buck converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 Simulated voltage response for load increase. . . . . . . . . . . . . . . . . . . . . 30
5.2 Simulated current response for load increase. . . . . . . . . . . . . . . . . . . . . 31
5.3 Simulated voltage response for load decrease. . . . . . . . . . . . . . . . . . . . 32
5.4 Simulated current response for load decrease. . . . . . . . . . . . . . . . . . . . 33
6.1 Single-phase buck test board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2 Controller Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3 Carrier board for testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4 Load board used for testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1 Output voltage response for load increase. . . . . . . . . . . . . . . . . . . . . . 43
7.2 Output voltage response for load decrease. . . . . . . . . . . . . . . . . . . . . . 43
7.3 Output voltage response for load decrease. . . . . . . . . . . . . . . . . . . . . . 44
7.4 Phase current response for load increase. . . . . . . . . . . . . . . . . . . . . . . 45
7.5 Total phase current response for load increase. . . . . . . . . . . . . . . . . . . . 45
vii
7.6 Output current response for load increase. . . . . . . . . . . . . . . . . . . . . . 46
7.7 Output current response for load decrease. . . . . . . . . . . . . . . . . . . . . . 47
7.8 Phase current response for load decrease. . . . . . . . . . . . . . . . . . . . . . . 47
7.9 Total phase current response for load decrease. . . . . . . . . . . . . . . . . . . 48
viii
List of Tables
5.1 Parameter values used in the simulations. . . . . . . . . . . . . . . . . . . . . . 29
6.1 Parameter values for the hardware test setup. . . . . . . . . . . . . . . . . . . . 34
6.2 Parameter values used in the hardware controller. . . . . . . . . . . . . . . . . . 41
ix
Chapter 1
Introduction
Multiphase buck converters are utilized for high efficiency over wide operating loads [1].
Additionally, the multiphase buck converter can possess a smaller output voltage ripple than
single-phase buck converters. Both of these advantages are accomplished by interleaving the
active phases with a suitable phase delay, properly sharing current between active phases,
and dynamically adjusting the number of active phases (phase shedding). The goal of this
work is to extend an existing sliding mode (SM) controller for a single-phase buck converter to
includeproperphaseshiftingforatwo-phasebuckconverterwhilemaintainingandimproving
transient responses and steady-state voltage ripple.
1.1 Prior Work
This section will present some relevant motivations and background material for multi-
phase buck converters and sliding mode controllers. It is broken up into three subsections.
The first section will present motivations for using a multiphase buck converter and the
typical point-of-load application requirements the multiphase buck converter is designed to
solve. The second section will present some control issues associated with a multiphase buck
converter. The third section will present some background material on sliding mode control
theory.
1.1.1 Buck Converters
With the rapid ascension of the internet and cloud computing, large data centers have
been built to satisfy the ever increasing demands for information and processing [2]. Due
to the increased power density afforded by modern processors, the power density of data
1
centers has also been steadily increasing. Correspondingly, the energy required to power and
cool data centers has been growing as well [3]. In many cases, the cost of energy for one
year exceeds the price of the servers themselves. This high energy usage can be reduced by
using more efficient power supplies and topologies, which will also have the added benefit of
reducing cooling requirements [4].
While there are various power distribution architectures and converters, one of the most
challenging converters from an efficiency standpoint is the point-of-load (POL) converter.
This converter takes in an intermediate DC voltage, typically 12V, from upstream supplies
and converts it to a high-current, low voltage suitable for modern processors [5]. From
an energy efficiency standpoint, this converter is very challenging due to the high current
outputs required by modern processors. In many cases, the output of the POL is 1V at
100A. Since power is proportional to current squared (P ? I2), small parasitic resistances
in the converter can cause dramatic power losses at higher currents.
In addition, the microprocessors that the POL powers have very stringent voltage tol-
erances. In the case of the Intel Core i7 processor, the processor requires 1.5% tolerance, or
at 1V, 15mV at 65A [6]. Some FPGA vendors use similar tolerances. The Altera Stratix V
requires 3% steady-state tolerance at 0.85V and 130A [7]. These tight tolerances and wide
load range lead to a multiphase buck converter typically being used for POL applications
[8].
For some customers, the end-to-end energy efficiency of the power distribution system
is the primary concern. This is driven by the continually increasing cost of energy. In
some cases, the yearly cost of energy is more that the cost of the computer system. Since
the efficiency of the converters is load dependent and peaks at a certain load conditions,
multiphase buck converters are a good fit for energy efficiency. Subsequent phases can be
turned on as the load increases to keep the currently operating phases at their peak operating
efficiencies. As the load decreases, phase shedding can occur, turning off phases to maintain
a high overall efficiency.
2
1.1.2 Control Issues for Multiphase Buck Converters
In order to achieve the maximum efficiency across a wide range of loads, the controller
must regulate the output voltage while ensuring optimal distribution of the load currents.
As Costabeber investigated, efficiency of the overall converter is dependent on the load and
the number of operating phases [1]. Thus, the controller must be able to enable and disable
phases depending on the load conditions.
However, in addition to adjusting the number of phases, the controller must regulate the
current in the phases. Typically multiphase buck converter controllers simply enforce equal
current distribution between the phases [9]. This has the advantage of reducing per-phase
currents and therefore the corresponding I2R losses. However, as Vilchis et al. point out,
maximum efficiency operating conditions are highly load dependent and can be optimized
by adjusting the currents in each phase independently [10].
The controller should also be robust to widely-varying load, line, and component con-
ditions. As the Intel Core i7 specification states, the idle current for the processor is 2 A
and full load is up to 65 A [6]. Many computers schedulers are scheduling the processor
for maximum throughput and then idling to improve battery life in mobile applications [11].
Thus, these wide current transients will become standard to improve mobile battery life. Ad-
ditionally, the controller should also be immune to line voltage changes. As servers continue
to be consolidated into multi-processor systems, the end POL converter will be connected to
other POL converters and the upstream power supply, either an ac-dc converter or another
dc-dc converter [4]. Since each processor?s power draw influences the equivalent impedance
the POL presents to the upstream supply, the input voltage on each POL converter will
vary due to processor transients. Thus, regardless of what the other processors are doing,
each POL should maintain output voltage regulation. The controller should also be robust
against component parameter variations due to aging [12]. The POL should output the same
3
voltage regardless of component age until component failures occur. Multiphase buck con-
verters are also capable of tolerating phase failures should the switches fail open. Therefore,
the controller should be able to adjust and continue operating.
1.1.3 Sliding Mode Control
SM controllers are a family of nonlinear controllers that are particularly suited for
variable structure systems, such as switching power converters. SM controllers are designed
to switch between multiple system structures. The resulting closed loop dynamics are often
geometrically described in state-space as trajectories along a sliding ?surface? [13].
There has been significant work in designing SM controllers for power switching sys-
tems. There are two methods to implement sliding mode in power converters: direct and
indirect [14, 15]. Direct control utilizes the sliding surface?s sign to directly feed the switches.
Indirect control, however, utilizes the sliding surface to vary the duty cycle in a traditional
pulse-width modulation (PWM) scheme. Li and Ye utilize SM controllers for a single phase
buck converter [16]. Kordkheili and Mehrasa develop a SM controller for a three-phase ac-dc
boost converter [17]. Biel et al design two SM controllers, one for a boost converter and one
for a buck converter [18]. The boost converter is then connected to the buck converter. A
sinusoidal reference to the buck converter generates the desired AC signal.
There has been some work to implement a SM controller for multiphase buck converters.
Lee et al. utilizes a cascaded approach where the control effort of one phase is added to the
surface of the next phase and integrated to obtain the second phase?s control effort [19].
However, they only consider fixed numbers of active phases for the converter. Additionally,
there are a variety of scenarios where a designer might not want to have similar phase-shifted
responses, such as in the cascaded approach. For the mutliphase buck converter to maintain
the highest efficiency over a wide load range, it may be better to run most of the phases at
a peak efficiency operating point and only one or two phases at lower efficiency operating
points, instead of running all at identical operating points at an overall lower efficiency [1].
4
This also has the advantage of shutting down unused phases, eliminating their corresponding
switching and conduction losses.
Therefore, a similar but unique surface for each phase of a multiphase buck converter is
desired. A similar surface is desired such that all phases will respond to any load transients.
However, the surface should be unique so that the steady state voltage ripple is reduced and
each of the phase currents is controlled to attain optimal converter efficiency. In the devel-
opment of these surfaces, it is beneficial to examine the single-phase buck converter model
and corresponding SMC, examine the multiphase buck converter model, and expand the
single-phase SMC with the necessary additional terms to control the multiphase converter.
1.2 Contributions
This work develops a design methodology for sliding mode control of a two phase buck
converter. In contrast to prior works in the area, the new method enables design of different
control strategies for each of the two phases. The design methodology enables the applica-
tion of the two-phase converter to other control objectives, beyond mere voltage regulation.
For example, the added objective of efficiency control can be addressed. To demonstrate the
efficacy of the contribution, a design to meet the objectives of voltage regulation and proper
time delay between phases is presented. The author also shows how the controller is imple-
mented on a Texas Instruments (TI) C2000x family processor. The design methodology also
forms a basis for extensions to additional phases.
1.3 Organization
Up until now, only highlights of the engineering problems, control issues, and start-of-
the-art solutions have been presented. In the remaining chapters, the author gives in-depth
descriptions about buck converters, sliding mode control theory, application of sliding mode
control theory to buck converters, extension of the single-phase sliding mode controller to
5
two-phase, and implementation of the two phase sliding mode controller. Specifically, Chap-
ter 2 presents an in-depth review of the literature on single and multiphase buck converters
and sliding mode control theory. Chapter 3 presents the highlights of the single phase con-
verter and its sliding mode controller which forms the basis of the multiphase controller
presented in Chapter 4. Readers who are familiar with the general field may wish to skip to
Chapter 4 where the new design methodology is detailed. Simulation results of the proposed
controller are presented in Chapter 5. Experimental evaluations are presented in Chapter 6
and 7. Contributions are summarized in Chapter 8, with an eye to future directions.
6
Chapter 2
Background
2.1 Buck Converters
Buck converters are conceptually fairly simple power converters. However, given their
applicability to step-down voltage and allow for high currents, much work is still being per-
formed on them to improve their efficiency and transient responses through various additions
and techniques. These techniques can generally be thought of as improvements to the buck
architecture, the converter model, and the control system.
2.1.1 Architecture improvements
The architectural improvements to the buck converter mainly focus on various designs
which should espouse improved efficiency, controller performance, or volume reductions.
Some work has been done on the system level which involves separating a monolithic
centralized controller and putting controllers on each phase [20]. Huang et al. then link
the individual per-phase controllers with an overall controller which manages phase syncing
and multiple phase transient responses. Huang et al. claim that the controller bandwidth is
improved due to reduced phase delay from the phase output voltage to the controller.
Other works take the traditional multiphase concept and tweak it slightly to enable
better transient responses. Wen et al. propose using an auxiliary supply to provide sup-
plemental current support during load transients, essentially creating a second phase with
a small inductor and high switching frequency which is driven from the gate supply volt-
age [21]. Similarly, Du et al. investigate using two buck converters with different switching
frequencies [22]. The slow phase is designed to support most of the load and is optimized
7
for steady-state performance. The fast phase is designed to support load transients and
therefore possesses a smaller inductance and faster switching speeds.
Other authors tend to augment a multiphase buck converter with additional converter
types to improve efficiency or density. Mahdavikhah et al. focus specifically on increasing
the power density of the converter and add an additional capacitive divider stage before
the two-phase interleaved buck converter to achieve the increased power density [23]. The
capacitive divider allows a lower input voltage which allows for an increased duty cycle of
the buck converter. Panguloori et al. provide an interesting approach by using an isolated
full bridge current doubling rectifier in parallel with the standard buck converter [24]. The
buck converter operates to supply load transients and improve the transient voltage response
while the full bridge current doubler tries to meet the new load current demands. Upon the
current doubler matching the load current demand, the buck converter turns back off. This
approach is similar to the one provided by Du and Wen.
Still other works propose adding additional components and changing the overall ar-
chitecture of the individual buck converters. Abe et al. develop a cascaded buck converter
where all but the last cascaded converter introduces a capacitor between the high-side switch
and the inductor node [25]. Additionally, the next phase is fed from the node between the
high-side switch of the previous phase and the added capacitor. The goal of this technique
is to reduce the effective voltage across any switch to at most 2/3 Vin. However, one disad-
vantage of this technique is that now the full converter input current passes through the first
phase?s high-side switch. Additionally, if that switch fails open, the entire converter fails.
Thus, such a technique succeeds in its initial goal, but is only as reliable as the first phase?s
high-side switch.
Similarly, Lee et al. suggest a new architecture for two-phase buck converters keeping the
same number of active switches but introducing an additional series capacitor into one of the
phases [26]. This reduces the voltage stress on one of the switches to 1/2 Vin. Additionally,
the switching voltage on the switching MOSFETs is reduced, thereby reducing the switching
8
losses. The author?s full loss calculations show greatly improved efficiencies in the new design;
however, the authors neglect to include the additional losses in the added capacitor in these
calculations. Regardless, the measured efficiency numbers do show improvement at light
load conditions.
Garcia et al. utilize work done for zero-voltage switching (ZVS) for buck converters to
utilize current balance between the multiple phases [27]. Their technique, however, requires
ripple currents that are higher than twice the average current in each phase?s inductor,
increasing RMS losses. To overcome those shortcomings, additional output capacitance is
required. Additionally, Garcia utilizes the negative current flowing in the inductor to develop
ZVS in the high side switch. The negative current also requires extra energy from the other
phases, reducing the overall converter?s efficiency.
Rahimi et al propose adding an additional 3 diodes, 2 capacitors, and an inductor on
the inductor node of a synchronous buck converter [28]. This allows the main switches to
experience a resonant condition and allows for zero current turn-on and zero voltage turn-off
of the main and synchronous switches.
Hwu and Chen develop a modified buck converter utilizing a differential mode trans-
former in between the phase inductors and the switches [29]. The advantage of their approach
is that current sharing between inductors is automatically enforced by the transformers. In-
terestingly, the authors do not discuss the desired phase delays between phases to reduce
the output voltage ripple.
Jang et al examine the issue of small-duty cycles on multiphase converter efficiencies
and develop an architecture utilizing two additional MOSFETs and capacitors to provided
reduced switching voltages and to increase the effective duty cycle [30].
Xu et al look at the same issue and propose a tapped coupled inductor approach where
the number of turns in the inductor are determined by the desired transient response [31].
They shown higher efficiency numbers due to the addition of a capacitor which provides
reduced switching voltages across the main switching MOSFETs.
9
Indeed, many authors analyze the coupled inductors approach to improving buck con-
verter performance, size, and efficiency. Xu et al provide evidence that for some situations,
coupled inductors provide better energy efficiency with similar transient responses [32]. Na-
garaja et al work to further refine the design techniques for utilizing coupled inductors in
multiphase buck converters [33]. Wu et al develop averaged models for the coupled inductor
design and illustrate the design ideas in a prototype converter [34]. Wibowo et al also analyze
coupled inductor buck converters and show a roughly 10% reduction in voltage transients
due to load changes over non-coupled inductors [35].
Garinto and later his collaborator, Taufik, discuss the advantages of multi-interleaved
buck converters which can reduce the output filter requirements and the overall volume,
but increases the number of inductors [36, 37, 38] per phase. Additionally, since multiple
inductors are now carrying the full output current load, the I2R losses are increased as well.
Taufik et al eventually reduce the number of necessary inductors but still require n+2, where
n is the number of phases [39].
2.1.2 Modeling
Various improvements have been made in the literature concerning the modeling of the
buck converter and the various converter improvements.
Qiu et al utilize harmonic balance to generate nonlinear models of single and multiphase
buck converters which show the sidebands generated by the square-wave pulsing, which are
not shown in linear models [40]. Kondrath and Kazimierczuk develop an analytical model
for wide-frequency and high-frequency small-signal models for the buck converter [41]. Their
work shows that at low frequencies, the converter appears as a second order system. However,
for high frequencies, the inductor and parasitic inductance of the capacitor dominate, making
the system appear like a first order inductor. Similarly, Qiu introduces multifrequency small-
signal models for multiphase buck converters to show control-loop bandwidth limitations [42].
10
Eirea and Sanders develop a method for estimating the phase current unbalance be-
tween the various phases [43]. Their method depends on similar high-side switch resistances
between phases and makes use of the input voltage drop when the phases turn on. With
unbalanced phases, the input voltage droops further with the higher current phase than
with the lower current phase. This droop imbalance then allows estimation of the imbalance
between phase currents.
Bouhalli et al discuss magnetic coupling issues to buck converters and present a model
used for their analysis of various coupling configurations [44]. Their work shows that some
configurations of inductor coupling are better suited to higher phase counts.
Shao et al look at the use of identifying return current paths to determine optimal
thermal placement of inductors and capacitors [45]. Their work reduces the generation of
electromagnetic interference at high frequencies by reducing the parasitic inductance of the
high current loops.
2.1.3 Control Improvements
In addition to the architecture additions and new modeling techniques, buck converters
are also experiencing an increase in the number of proposed controller architectures. Such
controllers can be categorized based on controllers which adjust phase currents and phase
shedding, adaptive voltage positioning, hysteretic controllers, and hybrid controllers.
There are a variety of control approaches to performing phase shedding and phase
current balance. Costabeber et al. look at time-optimal phase shedding for multiphase buck
converters which only utilizes a feed-forward approach for control [1]. Unfortunately, the
system only looks at time-optimality for changing the phase currents. The output voltage
during the phase shedding transients isn?t considered. Additionally, Costabeber examines
the efficiency of the overall converter based on load and the number of active phases. Pascual
et al look at improving light load efficiency by shedding phases and propose a controller to
11
adjust a linear controller to enable the phase-shedding based on load [46]. The controller is
verified in simulations.
In addition to phase sheddding, phase current balance is an often stated goal of multi-
phase controllers in order to improve efficiency by reducing per-phase currents and improve
reliability by not loading one particular phase with more losses over time. Retegui look at
the multiphase buck converter as a high-power current source and provide control with min-
imized current ripple by anticipating the average crossings of the phase currents [9]. Chiu
et al develop a modified high-gain peak current controller to combat phase current oscilla-
tions that are present in typical high gain peak current control schemes for multiphase buck
converters [47].
Other control approaches ignore phase shedding and focus solely on adaptive voltage
positioning (AVP) for modern computer processors with both nonlinear [48] and linear [49]
controllers. Another use for adaptive voltage control includes envelope modulation for RF
amplifiers [50].
Other authors propose using analog hysteretic controllers which can posses AVP and
modular design [51], nonlinear and constant frequency [52], and predictive [53] control.
Vilchis et al. propose non-uniform current sharing between phases as well as a method
of load dependant operating modes as a method to increase efficiency in battery powered
applications [54, 10].
Some interesting work has also been done merging linear and nonlinear controllers for
various modes of operation. Boscaino et al. utilize a primary linear controller during steady-
state operations with a nonlinear controller to modify those parameters during transient
events [55]. Barroado et al follow a similar approach, but utilize only the nonlinear controller
outside of certain threshold levels of the output voltage [56]. Du et al., however, propose
using linear control loops, but keep competing loops from saturating during various loop
competitions [57].
12
Interestingly, Zaman et al seek to control the thermal issues for multiphase current mode
buck converters and present a peak-current digital controller to reduce peak temperatures
in the switching MOSFETs [58].
2.2 Sliding Mode Control
Since being developed by Russian scientists and engineers in the 1950?s an 1960?s, sliding
mode control has been steadily developed for various applications.
Several authors have looked at discrete sliding mode control. Orosco and Vazquez
presentthenecessaryreachingandexistenceconditionsfordiscreteslidingmodecontrollers[59].
Janardhanan et al present a method of discrete output feedback for quasi-sliding mode con-
trol with numerical simulations for uncertain systems [60]. Bandal and Vernekar develop
a discrete-time sliding mode controller utilizing multirate output feedback for a magnetic
levitation system [61]. They also develop a new formulation on discrete-time sliding mode
control which guarantees a discrete system response similar to a continuous time sliding
mode controller. Matas et al present a discrete sliding mode controller with output tracking
for a boost converter [62].
Hybrid control techniques have also been developed which utilize linear and nonlinear
controllers together, or utilize structures similar to linear controllers. Li et al develop a
hybrid PD-sliding mode controller which uses the PD controller for transient performance
and the sliding mode controller for steady-state disturbance rejection [63]. Tan et al develop
a fixed-frequency PWM-based quasi-sliding mode controller which exhibits similar structure
to a PD linear controller with additional terms for input and output voltage [64]. Fur-
ther, they develop an error voltage based sliding mode controller with a form very similar
to a PID [65] and then further refine the idea and offer general design considerations for
such a controller [66]. Li and Ye also develop a sliding mode controller based on the PID
approach [16].
13
However, Sira-Ramirez shows equivalence between sliding regimes of variable-structure
feedback control and PWM responses in nonlinear dynamical systems [67]. Thus the hybrid
techniques for nonlinear plants, such as dc-dc converters, actually just utilize two different
sliding surfaces: one explicit and one implicit. Similarly, Iqbal et al propose a combined slid-
ing mode controller utilizing both first order sliding modes and dynamic sliding modes [68].
Ackermann and Utkin develop an explicit form for the discontinuity plane for the SM con-
trollers and then show a two controller approach, where static controllers force the system
into sliding mode and dynamic controllers enforce the desired dynamic properties [69].
One issue often seen with sliding mode controllers is the requirement for infinite switch-
ing speed to slide across the sliding surface [13]. However, since real circuits cannot switch
infinitely fast, a phenomenon known as chattering occurs. Therefore to minimize the chat-
tering effect, Mohanty uses a sliding mode controller with a boundary layer when controlling
an induction motor drive [70]. The boundary layer provides a hysteresis zone around the
sliding mode where the controller will not switch.
Adjusting the hysteresis zone, or boundary layer width, is also a method for controlling
the frequency of the converters, as discussed by Cardoso et al [71]. Nguyen and Lee propose
using an adaptive hysteresis band to control the switching speed to adjust for variations
in components [72]. They then discuss some practical methods for implementing indirect
sliding mode control utilizing fixed-frequency PWM methods [73].
However, many other authors utilize adaptive sliding modes to dynamically adjust the
sliding surfaces. Fei presents an adaptive sliding mode tracking controller based on a PI
switching surface using an integral sliding term and an adaptive sliding mode controller [74].
Yu et al develop a new sliding mode controller design, termed adaptive seeking sliding mode
control, to adaptively estimate and compensate the chattering effect due to continuous and
slowly varying disturbances [75]. Comanescu and Xu present two robust sliding mode model
reference adaptive system observers for speed estimation in a sensorless vector controlled
induction machine drive [76]. Wai uses an adaptive sliding mode controller to control the
14
position of an induction servomotor drive [77]. The interesting thing about Wai?s approach
is that the surface proposed has no reaching phase; the entire trajectory is in sliding motion
within disturbance bounds. Additionally, Wai proposes an adaptive approach which relaxes
the requirements on the disturbance bounds to stay in the sliding mode.
In addition to adaptive work, sliding mode control has been used as the basis for fuzzy
and neural-based controllers. Kung and Lai utilize sliding mode control techniques to design
fuzzy control rules [78]. Next, region-wise linear fuzzy controller is designed based on the
fuzzy sliding mode controller which is then tuned to find the optimal linear fuzzy parameters
with a genetic algorithm. Betin et al use sliding mode theory to define optimal scaling values
for a fuzzy logic controller [79]. Zhang et al utilize a second order time-varying system to
model higher order time-invariant systems and propose a fuzzy sliding mode control scheme
for the reduced order time-variant system [80]. Perry et al create a fuzzy sliding mode-like
controller for buck converters which ensures zero steady-state error [15]. Raviraj and Sen
compare PI, SM, and fuzzy controllers and outline the mismatch between characteristics
which lead to varying performance between the controllers [81].
In addition to the fuzzy sliding mode controllers, sliding mode has also been applied to
neural networks. Xiaojiang et al utilize a neural sliding mode controller to perform trajectory
tracking for multi-link robots with uncertainty in model parameters and disturbances [82].
Interestingly, Topalov et al use a sliding mode controller to perform online training of a
neural network controller without requiring a priori knowledge of plant dynamics [83].
With multi-input sliding mode controllers, it becomes necessary to define multiple sur-
faces. This is due to each system input requiring a control output, and consequently, the
defined surface upon which to switch. Qian et al develop an hierarchical SM controller where
two sliding surfaces define the system controller [84]. First, the system is designed to slide
along one surface and then slides along the second. Yu et al demonstrate a cascaded sliding
mode controller applied to a nonlinear bicycle robot [85]. The system is divided into two
15
different subsystems and each sub-sliding surface is designed. The ultimate control system
slides along each sub-sliding surface controlling the robot effectively in simulation.
Sliding mode control also has an extensive history with power converters. Mahdavi
et al analyze small and large signal disturbances around the operating points for DC-DC
converters controlled by sliding mode controllers [86]. Then they utilize state space averaging
and a neural network to implement a sliding mode controller on a Cuk converter [87]. Fossas
et al use SMC to control the output voltage of a Cuk converter and transform the constant
sliding mode surface into a time-varying surface once sliding mode is obtained [88].
In addition to the Cuk converter, SMC has been applied to the boost converters. Giral
et al look at the use of SMC for boost converters for voltage doubling and quadrupling [89].
Lopez et al utilize sliding mode control based on the equivalent control method to parallel
multiple boost converters and implement current sharing between the various phases[90].
Shtessel et al study the nonminimum phase tracking control for boost and buck-boost power
converters under SMC [91].
Single phase buck converters have also been a popular topic for investigation of sliding
mode techniques. Ahmed et al focus on the robustness of the sliding mode controller for a
buck converter for three areas of operation: start up, line/load variation, and component
variation. Their work shows the SMC has good immunity to component variations [92]
and load and line disturbances [14]. Vazquez et al propose a technique for voltage-only
SMC for buck converters [93]. Sira-Ramierz relates SMC of a buck converter to classical ?
modulators and ??? modulators [94]. Alarcon et al design and implement a CMOS ASIC
which implements versatile sliding mode control laws for DC-DC converters [95]. Fossas
and Ras discuss a second-order sliding mode controller which greatly reduces the chattering
effect in a buck converter [96].
Extension of the single phase buck converter to the multiphase converter has also been a
topic of particular interest. Mazumder et al propose a SMC for parallel buck converters using
integral-variable structure and multiple sliding surface control and examine the existence
16
criteria and stability of the sliding manifolds for the paralleled converters [97]. Mazumder
and Kamisetty provide an analog implementation of a sliding mode controller for multiphase
buck converters [98]. Their experimental results show good performance for the multiphase
converter at step changes but show no ability to implement phase shedding. Additionally,
they utilize the indirect method of control via a PWM. Utkin designs a SMC which dictates
the number of phases necessary for the desired amplitude of chattering in a multiphase
buck converter [99]. Unfortunately, his approach does not provide for dynamically variable
numbers of phases or non-balanced current between phases. Biel et al utilize Lee and Utkin?s
approach in [19] and adjust Lee?s sliding parameter K to achieve voltage control and minimize
chattering [100].
Shtessel et al study the system of modular power converters and how multiple systems
which share the same input bus can effect each other if the controller is not specifically
designed to account for these changes [101]. They present a SMC for each of the end-stage
modules to include the effect of voltage input droop due to increased current demands from
other paralleled stages. Lopez et al create a sliding surface which can successfully interleave
phases and share current equally [102]. However, their approach requires measuring the
currents for use in the surfaces. Additionally, it does not allow independent control of phase
currents.
In addition to controllers, sliding mode can also be used for observers. Lienhardt et al use
sliding mode observers to determine the capacitor voltages in stacked multicell converters
[103]. Zhou et al discuss sliding mode observer-based sliding mode control for nonlinear
systems with distributed delays [104].
2.3 Summary
However, in all the literature searched, there has not been a digital sliding mode con-
troller which has been specifically designed to support various independent current levels
17
which will enable optimization of the efficiency of the multiphase buck converter across vari-
ous load conditions. Mazumder and Kamisetty provide a SMC for mulitphase converters, but
it does not support load shedding or phase-current setting [98]. Vilchis et al utilize various
non-uniform buck converter phases to support high efficiencies at various load conditions,
but never actually experimentally implement the work [54, 10]. Thus, the goal of this work,
a discrete sliding mode controller which can serve as the foundation for independent phase
current setting and supports phase shedding, has not been addressed in prior works.
18
Chapter 3
Sliding Mode Control of a Single-phase Buck Converter
The single-phase controller is based on the controller by Tan et al [66]. To help define the
notation used later in the paper, the key elements of Tan?s work are repeated here. Familiar
readers should skip to Section 4.1. A single-phase buck converter is shown in Fig. 3.1. The
buck converter consists of an output capacitor, C, an inductor, L1, and two switches: the
main switch, SW1, and a synchronous rectifier, SR1. Unlike the traditional buck converter,
the synchronous buck converter replaces the diodes with controlled synchronous rectifier
(SR) switches and is able to achieve a higher efficiency [105].
SR1
SW1
+?V
gs2
+?V
gs1
+?V
i
L1
+ ?vL1
iL1
C
?
+
vC
ic
RLo
ad
?
+
Vo
io
vs1
Figure 3.1: Single-phase buck converter.
The states of this converter are defined as:
x1 = Vref ?Vo (3.1)
x2 = ?x1 = ?dVodt
= ? 1C
parenleftbiggintegraldisplay parenleftbiggV
iu1 ?Vo
L1
parenrightbigg
dt? VoR
Load
parenrightbigg
(3.2)
19
where u1 is the control input and has the values of [0,1]. This is a voltage formulation of
the states, where the integral term in x2 represents the inductor current.
The single-phase buck converter controller is derived from [65], and will be summarized
here. Augmenting the two states given by Eqns (3.1) and (3.2) with:
x3 =
integraldisplay
x1dt (3.3)
The sliding mode surface can be considered as:
S = ??x
= ?1x1 + ?2x2 + ?3x3 (3.4)
The control input is formulated to be:
u1 =
?
???
???
0 for S < 0
1 for S > 0
(3.5)
The existence of the sliding mode can be determined by examining the stability of the
surface. State trajectories will move to the switching surface if they satisfy the so called
?reaching condition? given by:
S ? ?S < 0 (3.6)
20
For the case S > 0:
?S < 0 (3.7)
?S =
parenleftbigg?
1
?2 ?
1
CRLoad
parenrightbigg
x2 + VrefCL
1
+
parenleftbigg?
3
?2 ?
1
CL1
parenrightbigg
x1 ? ViCL
1
< 0 (3.8)
Similarly, for S < 0:
?S > 0 (3.9)
?S =
parenleftbigg?
1
?2 ?
1
CRLoad
parenrightbigg
x2 + VrefCL
1
+
parenleftbigg?
3
?2 ?
1
CL
parenrightbigg
x1 > 0 (3.10)
For the sliding mode to exist, the coefficients, ?, must satisfy:
0 <
parenleftbigg?
1
?2 ?
1
CRLoad
parenrightbigg
x2 + VrefCL
1
+
parenleftbigg?
3
?2 ?
1
CL1
parenrightbigg
x1 < ViCL
1
(3.11)
Now that the single-phase case has been presented, the model of the multiphase buck
converter will be presented.
21
Chapter 4
Sliding Mode Control of a Multiphase Buck Converter
In order to present the proposed multiphase sliding mode controller, the model of the two
phase buck converter will be derived. Next, the proposed two phase sliding mode controller
will be developed. Chapter 5 will present the simulation results of the proposed controller.
Chapter 6 will present the hardware test bench. Chapter 7 will present the experimental
results of the controller.
4.1 Model of a Multiphase Buck Converter
A multiphase buck converter consists of parallel buck converters sharing a single output
capacitor. An example two-phase synchronous buck converter is shown in Fig. 4.1. The
converter has two control inputs, u1 and u2, which are represented by switch pairs (Vgs1,Vgs2)
and (Vgs3,Vgs4), respectively. When u1 is on, Vgs1 is high and Vgs2 is off.
SR1
SW1
+?V
gs2
+?V
gs1+
?Vi L1
+ ?vL1
iL1
C
?
+
vC
ic
RLo
ad
?
+
Vo
io
vs1
SW2 SR2
L2
+
?
vL2
iL2
+?
Vgs4
+?
Vgs3
vs2
Figure 4.1: Two-phase buck converter.
22
The state variables for the multiphase converter are defined slightly differently than the
single-phase case:
x1 = Vref ?Vo (4.1)
x2 = ?x1 = ?dVodt
= ? 1C
parenleftbiggintegraldisplay V
iu1 ?Vo
L1 dt +
integraldisplay V
iu2 ?Vo
L2 dt?
Vo
RLoad
parenrightbigg
(4.2)
x3 =
integraldisplay
x1dt (4.3)
where u1 and u2 are the control inputs for phase 1 and 2, respectively, and have values of
[0,1]. Notice the addition of the second integral term in Eqn (4.2) to account for the second
phase.
Similarly, extension of the two-phase case to higher phase counts is easily seen by in-
cluding additional integral terms for each phase. For example, a n phase converter will have
the same x1 state, with x2 being defined as:
x2 = ? 1C
parenleftbiggintegraldisplay V
iu1 ?Vo
L1 dt +
integraldisplay V
iu2 ?Vo
L2 dt + ...
+
integraldisplay V
iun?1 ?Vo
Ln?1 dt +
integraldisplay V
iun ?Vo
Ln dt?
Vo
RLoad
parenrightbigg
(4.4)
Now that the model of a two-phase SR buck converter has been developed, the two-phase
SM controller will be developed.
4.2 SMC of a Two-Phase SR Buck Converter
Extension of the single-phase SMC to the multiphase case poses some additional chal-
lenges in exchange for some increased performance opportunities. The additional input
source u2 adds an extra degree of freedom that must be accounted for in an additional
switching surface. However, this extra input can allow improved transient response and
reduce output voltage ripple. The goal of this controller design is to take the single-phase
23
controller and adapt it as necessary for multiple phases. The equivalent multiphase sliding
surfaces will begin expansion as:
S1 = ?1x1 + ?2x2 + ?3x3 (4.5)
S2 = ?1x1 + ?2x2 + ?3x3 (4.6)
where S1,S2 are the sliding surfaces for phase 1 and 2, respectively. The ? gains are devel-
oped according to the design rules in [66]. The design process will be described below and
motivations for adding additional terms to Eqns (4.5) and (4.6) will be given.
4.2.1 Output Voltage Ripple
In order to maintain minimum voltage ripple, the phase delay of phase 2 should be
180? [106]. However, there is currently nothing in Eqns (4.14) and (4.15) to enforce this.
Therefore, an additional term is added to each surface to inject a resettable ramp in the
sliding surface:
S1 = ?1x1 + ?2x2 + ?3x3 + ?4x4 (4.7)
S2 = ?1x1 + ?2x2 + ?3x3 + ?4x5 (4.8)
where
x4 =
?
???
???
integraltext 1 dt for u
1 = 0
0 for u1 = 1
(4.9)
x5 =
?
???
???
integraltext 1 dt for u
2 = 0
0 for u2 = 1
(4.10)
24
The ramps x4 and x5 are reset when S1 > 0 and S2 > 0, respectively. When S1 < 0, then x4
will start incrementing until S1 becomes greater than 0. Similarly, x5 will start incrementing
when S2 < 0 and will reset when S2 becomes greater than 0. Unlike indirect SMC methods
[107, 108], this ramp is not for frequency control. Instead, it is designed to ensure proper
phase delay between the phases to minimize steady state voltage ripple.
The gain term, ?4 is a positive value shared between the phases which serves to adjust
the impact of the ramp, relative to the voltage dynamics. Since the ramp is reset whenever
the input for that phase goes high, the other phase will possess a higher value for the sliding
surface during the next switching interval. This enables alternation between the phases as
desired. The value for ?4 should be chosen such that ?4x4 and ?4x5 are slightly smaller
than the steady-state dynamics right before the corresponding input turns on and resets the
integrators. Too large of an ?4 results in oscillations and poor voltage regulation. Too low
of an ?4 results in phase current oscillations between the phases and increased ripple.
4.2.2 Control Input Balance
Since the only time both inputs should be on is during a large voltage transient, each
surface also includes a term to subtract the input of the other surface. This ensures both
phases do not turn on at the same time under steady-state operating conditions. Addition-
ally, this serves as the initial impulse to enable the previously discussed ramps to perform
proper phase delay control. If this term is neglected, then both inputs can switch on at the
same time during steady-state operation, resulting in a larger ripple than the single-phase
case. However, both phases can still turn on during voltage transient effects as the surfaces
in (4.5) and (4.6) will dominate the effect on the input term. Phrased another way, during
initial transient effects:
?1x1 + ?2x2 + ?3x3 >> sign(un) (4.11)
25
The newly modified surfaces are given by:
S1 = ?1x1 + ?2x2 + ?3x3 + ?4x4 ?sign(u2) (4.12)
S2 = ?1x1 + ?2x2 + ?3x3 + ?4x5 ?sign(u1) (4.13)
4.2.3 Inductor Current Monitoring
Since only the voltage dynamics are monitored in the original single-phase surface, there
are no additional constraints on the phase currents. In buck converters with synchronous
rectification (SR), such as the case in Fig 4.1, care must be taken to ensure the inductor
current does not become negative. In converters without SR, the SR switches (SR1 and
SR2) are replaced with diodes, which will prevent negative inductor current.
One possible response of the SR multiphase converter in (4.5) and (4.6) is for one phase
to dramatically increase its current to positive infinity while the other phase performs the
opposite response and decreases its current to negative infinity. So long as the net difference
in phase currents keeps the voltage dynamics requirements, this is allowable. However, of
course, no practical designer will desire this action as the unchecked current will cause the
plant to fail. Thus, an additional term is added to each surface and is designed to constrain
the phase currents from becoming negative:
S1 = ?1x1 + ?2x2 + ?3x3 + ?4x4 ?sign(u2)
+ ?Neg (1?sign(iL2)) (4.14)
S2 = ?1x1 + ?2x2 + ?3x3 + ?4x5 ?sign(u1)
+ ?Neg1 (1?sign(iL1)) (4.15)
Consequently, ?Neg and ?Neg1 are very large negative gains used to ensure that phase turns
off when the opposite phase?s current becomes negative. Thus, the other phase is forced
to maintain the desired voltage dynamics and increase its current. If too small of an ?Neg
26
value is selected, then the phase currents may oscillate around zero, resulting in drastically
decreased efficiency of the controller.
4.2.4 Load Current Sharing
One observed effect of the controller equations given in (4.7) and (4.8) is an alternation
of the load current between the phases. For example, one phase will provide nearly the
full output load current while the other phase hovers above zero. This is due to one phase
staying on longer than another phase during transient events.
In order to facilitate current sharing, an additional term is added to each surface. This
term is normally on while ?Si is positive. However, when ?Si is negative, this term becomes
smaller. The effect of this term adjusts current sharing during transients. The terms x6 and
x7 with their corresponding gains ?6,?7 are introduced to S1 and S2, respectively. These
terms form a positive offset to the surface when ?S is positive, and a decreasing resettable
ramp when the ?S is negative.
S1 = ?1x1 + ?2x2 + ?3x3 + ?4x4 ?sign(u2)
+ ?Neg (1?sign(iL2))+ ?6x6 (4.16)
S2 = ?1x1 + ?2x2 + ?3x3 + ?4x5 ?sign(u1)
+ ?Neg1 (1?sign(iL1))+ ?7x7 (4.17)
27
where
x6 =
?
???
???
?D1 ?integraltext 1 dt for sign
parenleftBig ?
S1
parenrightBig
< 0
?D1 for sign
parenleftBig ?
S1
parenrightBig
> 0
(4.18)
x7 =
?
???
???
?D2 ?integraltext 1 dt for sign
parenleftBig ?
S2
parenrightBig
< 0
?D2 for sign
parenleftBig ?
S2
parenrightBig
> 0
(4.19)
The gain terms ?6 and ?7 should also be chosen such that ?6x6 and ?7x7 are small compared
to the steady-state dynamics. Typical values chosen for this application are:
?6 = 12?
D1
(4.20)
?7 = 12?
D2
(4.21)
where ?D1 and ?D2 are the desired phase offsets. Too low or high of ?6 or ?7 results in
unbalanced load sharing.
4.2.5 Complete Controller
The complete sliding surfaces are given in (4.16) and (4.17). The controller outputs are
given by:
ui =
??
??
???
0 for Si < 0
1 for Si > 0
(4.22)
Since the SM controller for the two-phase buck converter has been developed, a com-
parison is made to the single-phase converter to ensure similar or improved voltage dynamic
performance while improving the transient response and decreasing steady-state voltage rip-
ple.
28
Chapter 5
Simulation Results
Simulationswereperformedforasingle-phaseandtwo-phasebuckconverters. Hysteresis
modulation was performed as described by [66] to maintain a constant switching frequency
of 250kHz. The parameters used in the simulation can be found in Table ??. For both the
simulations, the same ?1, ?2, and ?3 were used to maintain the same error voltage dynamics.
The values from Table 5.1 come from a prototype converter which will be utilized for future
experimental validation.
Parameter Value
C 121.1?F
L1 1?H
L2 1?H
Vi 12V
Vref 1V
RLoad 0.1?
?1 10
?2 968.8
?3 582,892
?4 0.002
?6 1.25x10?3
?7 2.5x10?3
?Neg -1x106
?Neg1 -1x106
?D1 400
?D2 200
Table 5.1: Parameter values used in the simulations.
A 100% load increase was performed from 0.1 ? to 0.05 ?, or 10 A to 20 A. The voltage
response is shown in Fig. 5.1. The current response is shown in Fig. 5.2. In the two-phase
buck converter current response figures, phase A represents the first phase and phase B
29
represents the second phase. For the single-phase buck, the output voltage drops 65 mV
and recovers in 60 ?s. For the two-phase buck, the voltage drops 45 mV and settles in the
60 ?s. However, the two-phase buck is within the steady-state output voltage ripple of the
single-phase buck in only 50 ?s. Interestingly for the two-phase buck during the transient
effect, the phase shift varies slightly until the error dynamics have started to settle. At which
point the phase shift resumes its correct 180? shift.
?20 0 20 40 60 80 100
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1
1.01
1.02
Voltage Response for 100% step increase: 10A to 20A
Time (us)
Output Voltage (V)
 
 
1 phase
2 phase
Student Version of MATLAB
Figure 5.1: Single (dashed) and two-phase (solid) converter output voltage under 100% load
step (10A ? 20A).
A 50% load decrease was performed from 0.05 ? to 0.1 ?, or 20 S to 10 S. The voltage
response is shown in Fig. 5.3. The current response is shown in Fig 5.4. For the single-phase
buck, the output voltage rises 270 mV and settles in 80 ?s. For the two-phase buck, the
output voltage rises to 212 mV and settles in 50 ?s.
30
?20 0 20 40 60 80 100
2
4
6
8
10
12
14
16
18
20
22
Current Response for 100% step increase: 10A to 20A
Time (us)
Phase Current (A)
 
 
1 phase
2 phase ? A
2 phase ? B
Student Version of MATLAB
Figure 5.2: Single (dashed) and two-phase (dash-dot, solid) converter phase current under
100% load step (10A ? 20A).
31
?20 0 20 40 60 80 100
0.85
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
Voltage Response for 50% step decrease: 20A to 10A
Time (us)
Output Voltage (V)
 
 
1 phase
2 phase
Student Version of MATLAB
Figure 5.3: Single (dashed) and two-phase (solid) converter output voltage under 50% load
drop (20S ? 10S).
32
?20 0 20 40 60 80 100
0
5
10
15
20
25
Current Response for 50% step decrease: 20A to 10A
Time (us)
Phase Current (A)
 
 
1 phase
2 phase ? A
2 phase ? B
Student Version of MATLAB
Figure 5.4: Single (dashed) and two-phase (dash-dot, solid) converter phase current under
50% load drop (20S ? 10S).
33
Chapter 6
Experimental Setup
The simulated controller is now implemented on hardware. This chapter is broken into
two sections. Section one will discuss the hardware used and the test setup. Section two will
describe the experimental algorithm as implemented in the controller.
6.1 Implementation Hardware and Test Setup
An example phase is shown in Figure 6.1. Each phase utilizes an EPC 2015 eGaN
MOSFET for the primary switch, which is driven by the TI LM5113 eGaN MOSFET
driver. Phase currents are sensed by the CQ-2065e high speed current sensor, which has
a typical bandwidth from DC to 1MHz and a range of ?50 A. Each phase also utilizes a
MBRB4030T4GOSCT-ND 30 V 40 A Schottky diode for inductor commutation currents.
The current version of the buck converter is designed to be modular for testability. Thus,
each phase is on its own separate board which plugs into a master carrier board. The con-
nector is a 2 row, 50-pin header connector. Three signals are brought back to the controller?s
analog to digital converter (ADC): the switching node voltage, labeled as vs1 in Fig 4.1, the
output voltage, and the output of the current sensor. The inductance and capacitance for
each phase is given in Table 6.1.
Parameter Nominal Value
C1 121.1?F
C2 121.1?F
L1 100?H
L2 100?H
Vi 12V
Table 6.1: Parameter values for the hardware test setup.
34
Figure 6.1: Single-phase buck test board.
The controller chip is a TI TMS320F28335 C2000x series processor on a TI ControlCard,
shown on the red PCB in Fig. 6.2. This particular chip supports up to 150MHz clock rate
with a 8-stage pipeline. It also possesses a 12MHz pipelined ADC broken into two groups
of 8. Each group has its own sample and hold circuit which feeds a shared ADC stage.
The chip also possess 6 PWM channels capable of duty cycles with high resolution up to
180 picoseconds (ps). Most importantly, the chip supports a 32-bit x 32-bit multiply and
accumulate into a 64-bit result register. This allows high numerical precision and a wide
range of supported values.
The carrier board, shown in Fig. 6.3, is responsible for connecting up to five buck
converter phases and sending signals between the control card and the phases. It is also
responsible for combining the output of the individual stages and sending it to the load.
The carrier also has 121.1?F of capacitance to filter the output currents before sending to
the load. The board also contains the 5V TTL-level FTDI compatible serial port and the
JTAG programmer port. In addition, there are status LEDs and various input buttons to
allow user input without a computer. The board also sports three power inputs across the
top. The left-most connection is the digital 5V supply. The center connection is the buck
converter?s Vin. The right most connection is the auxiliary 5V gate-driver supply for the
buck converters.
35
Figure 6.2: TMS320F28335 microcontroller on the ControlCard.
The load for the tests is shown in Fig 6.4. It is comprised of a heavy-copper weight
PCB containing surface mount resistors of various values and two voltage inputs. One
voltage input is the output voltage of the carrier boards. The other input is a gate voltage
for switching MOSFETs. The configuration for the test is two groups of 4 resistors each of
1?, 0.5?, 0.2?, and 0.1?. One group is on the west side of the board and the other group is
on the east side of the board. The resistors are connected to the output voltage of the carrier
board and to the drains of MOSFET transistors. Each transistor has its source connected
to ground and its gate connected to a jumper. This allows each resistor to be enabled or
disabled based on the position of the jumper, either 5V or ground, respectively. The load
board?s minimum output resistance is 6.9 m? or, in terms of admittance, 144 siemens.
For load increase tests, the trigger was connected to the gate of the transistor and the
jumper was moved from ground to 5V. For load decrease tests, the trigger was also connected
36
Figure 6.3: Carrier board for testing.
Figure 6.4: Load board used for testing.
to the gate and a pull-up resistor was added between 5V and the gate. The jumper was then
connected between the gate and ground, turning off the transistor and disabling the resistor.
37
The original simulated system has too fast of a time-constant for the direct mode con-
troller to compute the sliding surfaces and maintain decent regulation of the converter at
an input voltage of twelve volts. Thus, the decision was made to utilize a larger inductor
to slow down the time constant. This problem could be rectified using a faster processor
or implementing the logic in a fast FPGA where many calculations could be performed
simultaneously.
6.2 Experimental Algorithm
The experimental algorithm is slightly changed from the simulated algorithm due to
a few key issues. The controller does not perform as quickly on floating point operations
as it does on integer operations. Since the MATLAB/Simulink simulation utilizes floating
point at its core, the algorithm should be adapted slightly to utilize 32-bit integer math.
Additionally, the MATLAB/Simulink simulation performs multiple convergence loops for
each simulation time-step, essentially performing all computations simultaneously. Since
the microcontroller can only perform calculations consecutively, the sign(un) terms where
n = 1,2 are particularly problematic. This is problematic because the calculation of S1
requires foreknowledge of S2 and the calculation of S2 requires foreknowledge of S1.
Additionally, the integration term is allowed to saturate so as not to overflow its in-
teger bounds and to reduce the integrator wind-up effect. Also, the synchronous rectifier
is not utilized in this test. Therefore, the phase current term in the simulated system,
?Neg (1?sign(iLn)),n = 1,2 cannot be negative and consequently the term will always be
0 and can be ignored. The control equations implemented on the TMS320F28335 are given
below:
38
S = ?1x1 + ?2z?1x1 + ?3z?1x2 (6.1)
S1 = S + ?4Ramp1 + ?6x6 + ?C2z?1c2 (6.2)
S2 = S + ?4Ramp2 + ?7x7 + ?C1z?1c1 (6.3)
where x1 is the error voltage in ADC sample values given by:
x1 = (Vref ?VADC) (6.4)
and x2 is a saturating integrator:
x2 = maxx
2min
parenleftbigg
minx
2max
parenleftbiggsummationdisplay x
1
k1
parenrightbiggparenrightbigg
(6.5)
and the ramps are defined as resettable ramps:
Ramp1 =
?
???
???
0 for S1 > ?
Ramp1 +1 for S1 < ?
(6.6)
Ramp2 =
?
???
???
0 for S2 > ?
Ramp2 +1 for S2 < ?
(6.7)
39
x6 and x7 are resettable decreasing ramps:
x6 =
?
???
???
?D1 for (S1 ?z?1S1) > 0
maxx2max (x6 ?1) for (S1 ?z?1S1) ? 0
(6.8)
x7 =
?
???
???
?D2 for (S2 ?z?1S2) > 0
maxx2max (x7 ?1) for (S2 ?z?1S2) ? 0
(6.9)
c1 and c2 are defined as the output of the controller:
c1 =
?
???
???
1 for S1 > ?
0 for S1 < ??
(6.10)
c2 =
?
???
???
1 for S2 > ?
0 for S2 < ??
(6.11)
The coefficients for the hardware algorithm can be found in Table 6.2.
40
Single Phase Values Two Phase Values
Parameter Value
Vref 1160 ADC Counts
Vref 0.85 V
?1 10 10
?2 -2 -2
?3 1 1
?4 - 10
?6 - 1
?7 - 2
? 80 80
neg? -80 -80
?C1 - -200
?C2 - -200
?D1 - 10
?D2 - 5
x2max 0x4000
x2min 0x4000
Table 6.2: Parameter values used in the hardware controller.
41
Chapter 7
Validations through Experiments
The controller implemented in the previous chapter is tested under multiple conditions.
Two tests are performed: load increase and load decrease. This chapter is split into three
sections. The first section will examine the voltage responses to the load variations. The
second section will examine the phase current responses to the same load variations. Finally,
the third section will develop some analysis on the outcomes of the data presented in the
two previous sections.
7.1 Voltage Responses
The load step is performed from 4 S to 9 S, where S=??1. Fig. 7.1 shows the voltage
response with a 5 S step increase applied at t = 0. The two phase controller shows less droop
and overshoot and recovers slightly faster than the single phase.
The next test performed on the system was a load decrease from 9 S to 4 S. As noted
above, the response is very consistent between the single phase and two phase controllers.
Fig 7.2 shows the voltage response for a load decrease from 9S to 4S. The single phase voltage
response peaks at 1.5 V and then drops to 0.46 V. The two phase voltage response peaks
at 1.25 V and then drops to 0.625 V before recovering in 0.7 ms. Fig 7.3 shows the single
phase settling time as 1.2 ms.
42
?2 ?1 0 1 2 3 4 5 6 7
x 10?4
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
1.05 Single and 2?phase Voltage Responses to 4S => 9S load change.
Time (s)
Voltage (V)
 
 
1?Phase
2?Phase
Figure 7.1: Output voltage response of the single and two-phase converter response with
125% load increase (4S ? 9S) at t = 0.
?2 ?1 0 1 2 3 4 5 6 7
x 10?4
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8 Single and 2?phase Voltage Responses to 9S => 4S load change.
Time (s)
Voltage (V)
 
 
1?Phase
2?Phase
Figure 7.2: Output voltage response of the single and two-phase converter response with
44% load decrease (9S ? 4S) at t=0.
43
?4 ?2 0 2 4 6 8 10 12 14
x 10?4
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4 Single and 2?phase Voltage Responses to 9S => 4S load change.
Time (s)
Voltage (V)
 
 
1?Phase
2?Phase
Figure 7.3: Output voltage response of the single and two-phase converter response with
44% load decrease (9S ? 4S) at t=0.
7.2 Phase Current Responses
This section will examine the individual phase current responses and the overall con-
verter current response to the two load changes. The first load change examined is the load
increase from 4 S to 9 S. Fig. 7.4 shows the individual phase currents during the load step
at t = 0. Notice at t = 0, all phases turn on and increase the inductor currents at a rate of
(Vin ? Vo)/L. Since both phases in the two phase system turn on, the system experiences
twice the rise rate as in the single phase case. Fig. 7.5 shows the total phase currents for each
system. For the two phase system, the sum of both phases at each time instant is plotted.
Fig. 7.6 shows the output current response for the same 5 S load step. The output
capacitor provides the instantaneous current shortly after the load step. The phases recover
after the initial surge of current provided by the capacitor as shown by the output current
droop around 25 ?s. Since both phases in the two phase system turn on during the load step,
44
?2 ?1 0 1 2 3 4 5 6 7 8
x 10?4
?5
0
5
10
15 Phase Currents for 4S=>9S load change
Time(s)
Current (A)
 
 
1?Phase
2?Phase(a)
2?Phase(b)
Figure 7.4: Phase current responses of the single and two-phase converter response with
125% load increase (4S ? 9S) at t=0.
?2 ?1 0 1 2 3 4 5 6 7 8
x 10?4
?5
0
5
10
15 Total Phase Currents for 4S=>9S load change
Time(s)
Current (A)
 
 
1?Phase
2?Phase (tot)
Figure 7.5: Total phase current responses of the single and two-phase converter response
with 125% load increase (4S ? 9S) at t=0.
45
the two phase system recovers closer to the steady-state output current of 7.25 A, giving it
a smaller droop and overshoot compared to the single phase system.
?2 ?1 0 1 2 3 4 5 6 7
x 10?4
2
3
4
5
6
7
8
9
10 Single and 2?phase Output Current Responses to 4S => 9S load change.
Time (s)
Current (A)
 
 
1?Phase
2?Phase
Figure 7.6: Output current response of the single and two-phase converter response with
125% load increase (4S ? 9S) at t=0.
The next test performed on the system was a load decrease from 9 S to 4 S. Fig 7.7 shows
the output current response of the converters. At t = 0, the output current drops due to the
load change from 9 S to 4 S. Since the inductor currents cannot change instantaneously, the
output capacitor absorbs the excess current, which results in the voltage peak as shown in
Fig. 7.2.
Fig. 7.8 shows the current responses for each phase of the converters. The two phase
system can respond faster due to the two inductors both decreasing the current. Fig. 7.9
shows the total phase currents for each converter. Notice both converters produce roughly
the same currents indicating that both converters are responding in a similar fashion. This
fulfills one of the desired design goals for the two phase controller.
46
?2 ?1 0 1 2 3 4 5 6 7
x 10?4
1
2
3
4
5
6
7
8 Single and 2?phase Output Current Responses to 4S => 9S load change.
Time (s)
Current (A)
 
 
1?Phase
2?Phase
Figure 7.7: Output current response of the single and two-phase converter response with
44% load decrease (9S ? 4S) at t=0.
?2 ?1 0 1 2 3 4 5 6 7 8
x 10?4
?5
0
5
10
15 Phase Currents for 9S=>4S load change
Time(s)
Current (A)
 
 
1?Phase
2?Phase(a)
2?Phase(b)
Figure 7.8: Phase current responses of the single and two-phase converter response with 44%
load decrease (9S ? 4S) at t=0.
47
?2 ?1 0 1 2 3 4 5 6 7 8
x 10?4
?5
0
5
10
15 Phase Currents for 9S=>4S load change
Time(s)
Current (A)
 
 
1?Phase
2?Phase (tot)
Figure 7.9: Total phase current responses of the single and two-phase converter response
with 44% load decrease (9S ? 4S) at t=0.
7.3 Experimental Analysis
As can be seen from the prior two sections, the transient response of the converter in
the two phase converter is improved over the single phase converter. As shown in Figs.
7.5 and 7.9, the total output currents of the converter are very similar. Unfortunately,
the experimental implementation of the converter does not keep the two phases in perfect
phase synchronization. Even though the phase synchronization is not ideal, the steady-state
voltage behavior, as shown in Fig 7.1 after t=2x10?4, is improved.
48
Chapter 8
Conclusions
This work designs, simulates, and implements a direct sliding mode controller for a two-
phase buck converter. The technical approach extends the the single-phase controller that
Tan et al. [66] developed to the multiphase case. Since there are two phases, two switching
surfaces are necessary. Four new terms are introduced in each switching surface equation for
synchronous rectifying buck converters. These terms address the challenges of phase delay,
current balance, and inductor current monitoring. This work is tested in simulation with
good results.
Next, theworkisimplementedonahardwaretestplatformconsistingofaTITMS320F28335
microcontroller and two buck converter phases. The proposed simulated algorithm is then
modified for implementation on the microcontroller. Two load varying tests are performed
and the proposed multiphase converter shows improved transient response relative to the
single-phase converter. The proposed controller can be extended to support regulating to
desired phase currents and dynamically changing the number of active phases based on load
conditions.
This work confirms the sliding mode controller is a suitable controller design for multi-
phase buck converters. The proposed controller shows robustness to load disturbances and
shows improved responses over the single-phase sliding mode controller. More importantly,
it also forms the basis for future work improving current sharing, implementing phase shed-
ding, and expanding the maximum number of active phases which will improve converter
efficiency.
49
8.1 Future Work
This work can be extended in a number of ways. First, phase shedding or adding based
on load conditions can be incorporated into the surfaces. This would allow more flexibility
in the delivery of the load current by adding or removing additional phases, improving the
efficiency of the overall converter by reducing the per-phase currents. However, this also
requires monitoring the currents in each phase. Something that is not currently required by
the controller as proposed in hardware and incurs additional cost and computation.
Second, current regulation per phase based on the load condition can also be incor-
porated to enable each phase to operate at or near its peak efficiency. Current regulation
complements phase shedding so that the converter can maintain peak efficiency regardless
of load conditions.
Finally, the work can be extended to support higher number of phases while maintaining
the desired voltage responses and distributing current between the phases efficiently. This
allows the converter to support wider operation ranges and higher maximum load currents
for the same basic phase design.
50
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Appendices
61
Appendix A
Source Code for Two Phase Controller:
main.c
1 //###########################################################################
2 //
3 // FILE: main.c
4 //
5 // TITLE: For use with Buck Carrier board v1 and buck daughter boards v3+.
6 //
7 // ASSUMPTIONS:
8 //
9 // 1) Phase 1 Gate connected to GPIO0
10 // 2) Phase 2 Gate connected to GPIO2
11 // 3) Vout connected to ADC A0, A1, A2, A3
12 // 4) Current sensor connected to B0, B2
13 //
14 // DESCRIPTION:
15 // Communicates with the computer via serial port 9600 baud , 8 data ,
16 // 1 stop , no parity .
17 //
18 // As is , the program configures SCI?A for 9600 baud with
19 // SYSCLKOUT = 150MHz and LSPCLK = 37.5 MHz
20 //###########################################################################
21 #include ?SerialHandler .h?
22 #include ?ADCHandler.h?
23 #include ?PWMHandler.h?
24 #include ?TimerHandler .h?
25 #include ?I2CHandler .h?
26 #include ?Globals .h?
27 #include ?controller .h?
28 #include ?DSP28x Project .h? // Device Headerfile and Examples Include File
29
30
31 Uint16 PhaseStatus ;
32 Uint16 PhaseCount ;
33 union LEDS LEDStatus;
34 union LEDS LEDStatus2;
35
36 union MAINFLAGS MainFlags ;
37 union BUTTONS ButtonStatus ;
38
39 int32 a1 ,a2 ,a3 ,a4 ,a5 , S, S1old , S2old ,S1 ,S2 ,dS1 ,dS2 , xint ;
40 int32 u1 , u1old1 , u1old2 ;
41 const int32 alpha1 = 10;//100;//?2;
62
42 const int32 alpha2 = ?2;//4;
43 const int32 alpha3 = 1;//?2;
44 const int32 alpha4 = 10;//10;
45 const int32 alpha5 = 10;//10;//?1;
46 const int32 alpha6 = 1;//1;//?1;
47 const int32 alpha7 = 2;//2;//?1;
48 const int32 alphaC0 = ?200;//?10;
49 const int32 alphaC1 = ?200;//?10;
50 const int16 Vref = 1160;
51 const int32 kappa = 80;
52 const int32 negkappa = ?80;
53 const int32 taud1 = 10;
54 const int32 taud2 = 5;
55
56 int32 adcbuffer [32];
57
58 #pragma DATA SECTION(DMABuf1,?DMARAML4?) ;
59 volatile Uint16 DMABuf1[40];
60
61 volatile Uint16 ?DMADest;
62 volatile Uint16 ?DMASource;
63
64 void main(void)
65 {
66 Uint16 i , i2ccounter , idx ;
67 int32 ramp1 ,ramp2;
68 int32 adcV1 ,adcV2 , adcI1 , adcI2 ;
69 int32 x6 ,x7;
70 int32? adcP;
71 Uint32 c0 , c1 ;
72
73 char ?msg;
74
75 EALLOW;
76
77 MainFlags . all = 0;
78
79 // Step 1. Initialize System Control :
80 // PLL, WatchDog, enable Peripheral Clocks
81 // This example function is found in the DSP2833x SysCtrl .c file .
82 InitSysCtrl () ;
83
84 // For this example , only init the pins for the SCI?A port .
85 // This function is found in the DSP2833x Sci .c file .
86 InitSciaGpio () ;
87
88 // Specific clock setting for this example :
89 EALLOW;
90 SysCtrlRegs .HISPCP. all = ADCMODCLK; // HSPCLK = SYSCLKOUT/ADCMODCLK
91 //ADC clock now = 25MHz.
92
93 // Step 3. Clear all interrupts and initialize PIE vector table :
94 // Disable CPU interrupts
95 DINT;
63
96
97 // Initialize PIE control registers to their default state .
98 // The default state is all PIE interrupts disabled and flags
99 // are cleared .
100 // This function is found in the DSP2833x PieCtrl .c file .
101 InitPieCtrl () ;
102
103 // Disable CPU interrupts and clear all CPU interrupt flags :
104 IER = 0x0000 ;
105 IFR = 0x0000 ;
106
107 // Initialize the PIE vector table with pointers to the shell Interrupt
108 // Service Routines (ISR) .
109 // This will populate the entire table , even if the interrupt
110 // is not used in this example . This is useful for debug purposes .
111 // The shell ISR routines are found in DSP2833x DefaultIsr .c.
112 // This function is found in DSP2833x PieVect .c.
113 InitPieVectTable () ;
114
115 EALLOW;
116 SysCtrlRegs .PCLKCR0. bit .TBCLKSYNC = 0;
117
118 InitPwmModule() ;
119
120 EALLOW;
121 SysCtrlRegs .PCLKCR0. bit .TBCLKSYNC = 1;
122
123 InitADCModule() ;
124
125 EINT; // Enable Global interrupt INTM
126 ERTM; // Enable Global realtime interrupt DBGM
127
128
129 // Step 5. User specific code :
130 PhaseStatus = 0;
131 PhaseCount = 0;
132 for ( i=0; i<BUF SIZE; i++)
133 {
134 SampleTable [ i ] = 0;
135 }
136
137
138
139 scia fifo init async () ; // Initialize the SCI FIFO
140 scia echoback init () ; // Initalize SCI for echoback
141
142 // Kill all PWMs initially .
143 EALLOW;
144 EPwm1Regs.TZFRC. bit .OST = 1; // Kill PWM1
145 EPwm2Regs.TZFRC. bit .OST = 1; // Kill PWM2
146 EPwm3Regs.TZFRC. bit .OST = 1; // Kill PWM3
147 EPwm4Regs.TZFRC. bit .OST = 1; // Kill PWM3
148 EPwm5Regs.TZFRC. bit .OST = 1; // Kill PWM3
149
64
150
151 msg = ?\r\nWelcome to PowerControl ! \r\nHopefully this controller will
work!\ r\n\0?;
152 scia msg (msg) ;
153
154 //Configure GPIOs
155 GpioCtrlRegs .GPAPUD. bit .GPIO0 = 0; // Enable pull?up on GPIO0
156 GpioCtrlRegs .GPAPUD. bit .GPIO1 = 0; // Enable pull?up on GPIO1
157 GpioCtrlRegs .GPAPUD. bit .GPIO2 = 0; // Enable pull?up on GPIO2
158 GpioCtrlRegs .GPAPUD. bit .GPIO3 = 0; // Enable pull?up on GPIO3
159 GpioCtrlRegs .GPAPUD. bit .GPIO4 = 0;
160 GpioCtrlRegs .GPAPUD. bit .GPIO6 = 0;
161
162 GpioCtrlRegs .GPADIR. bit .GPIO0 = 1; // Set as output
163 GpioCtrlRegs .GPADIR. bit .GPIO1 = 1; // Set as output
164 GpioCtrlRegs .GPADIR. bit .GPIO2 = 1; // Set as output
165 GpioCtrlRegs .GPADIR. bit .GPIO3 = 1; // Set as output
166 GpioCtrlRegs .GPADIR. bit .GPIO4 = 1; // Set as output
167 GpioCtrlRegs .GPADIR. bit .GPIO6 = 1; // Set as output
168
169
170 GpioDataRegs .GPACLEAR. all = 0x0F;
171
172 GpioCtrlRegs .GPAMUX1. bit .GPIO0 = 0; // Configure GPIO0 as GPIO //EPWM1A
173 GpioCtrlRegs .GPAMUX1. bit .GPIO1 = 0; // Configure GPIO1 as GPIO //EPWM1B
174 GpioCtrlRegs .GPAMUX1. bit .GPIO2 = 0; // Configure GPIO2 as GPIO //EPWM1A
175 GpioCtrlRegs .GPAMUX1. bit .GPIO3 = 0; // Configure GPIO3 as GPIO //EPWM1B
176 GpioCtrlRegs .GPAMUX1. bit .GPIO4 = 0;
177 GpioCtrlRegs .GPAMUX1. bit .GPIO6 = 0;
178
179 // Start SEQ1
180 AdcRegs.ADCTRL2. all = 0x2000 ;
181
182 idx = 9;
183 xint = 0;
184 S1old = 0;
185 S2old = 0;
186 dS1 = 0;
187 dS2 = 0;
188 u1old1 = 0;
189 u1old2 = 0;
190 S1 = 0;
191 S2 = 0;
192 ramp1 = 0;
193 ramp2 = 100;
194 adcV1 = 0;
195 adcV2 = 0;
196 adcI1 = 0;
197 adcI2 = 0;
198 x6 = 0;
199 x7 = 0;
200 c0 = 0;
201 c1 = 0;
202 while(1) // Infinite Loop
65
203 {
204 if (idx++ > 7)
205 idx = 0;
206 adcP = &adcbuffer [4? idx ];
207 adcV1 = AdcMirror .ADCRESULT0;
208 adcI1 = AdcMirror .ADCRESULT1;
209 adcV2 = AdcMirror .ADCRESULT2;
210 adcI2 = AdcMirror .ADCRESULT3;
211 //ADC freerunning . Latest sample will be in ADCMirror.ADCRESULTn (Use
mirror for fastest response times)
212 u1 = Vref ? (adcV1 + adcV2) /2;
213 ?(adcP++) = adcV1;
214 ?(adcP++) = adcI1 ;
215 ?(adcP++) = adcV2;
216 ?(adcP++) = adcI2 ;
217
218 a2 = alpha2?u1old1 ;
219 a3 = alpha3?xint ;
220 xint = xint + (u1 >> 4) ;
221 if ( xint > 0x00004000){
222 xint = 0x00004000 ;
223 }
224 if ( xint < ?0x00004000){
225 xint = ?0x00004000 ;
226 }
227 a1 = alpha1?u1;
228
229 S = a1+a2+a3 ;//+a4+a5;
230 S1 = S + alpha4?ramp1 + alpha6?x6 + alphaC1?c1 ;
231 u1old1 = u1;
232 if (S1 > kappa){
233 GpioDataRegs .GPASET. all = 0x05 ;//0x05 ; //Phase 2 for monitoring
234 EPwm1Regs.TBCTR = 0;
235 c0 = 1;
236 ramp1 = 0;
237 }
238 if (S1 < negkappa){
239 GpioDataRegs .GPACLEAR. all = 0x05 ; //Phase 2 for monitoring .
240 c0 = 0;
241 }
242 S2 = S + alpha5?ramp2 + alpha7?x7 + alphaC0?c0 ;
243 if (S2 > kappa){
244 GpioDataRegs .GPASET. all = 0x50 ; //Phase 4 for monitoring
245 EPwm1Regs.TBCTR = 0;
246 c1 = 1;
247 ramp2 = 0;
248 }
249 if (S2 < negkappa){
250 GpioDataRegs .GPACLEAR. all = 0x50 ; //Phase 4 for monitoring .
251 c1 = 0;
252 }
253 dS1 = S1 ? S1old ;
254 dS2 = S2 ? S2old ;
255 if (dS1 <= 0)
66
256 x6 ?= 1;
257 else
258 x6 = taud1 ;
259 if (dS2 <= 0)
260 x7 ?= 1;
261 else
262 x7 = taud2 ;
263 ramp1++;// = EPwm1Regs.TBCTR;
264 ramp2++;// = EPwm2Regs.TBCTR;
265 if ( x6 < ?0x04000000){
266 x6 = ?0x04000000 ;
267 }
268 if ( x7 < ?0x04000000){
269 x7 = ?0x04000000 ;
270 }
271 S1old = S1;
272 S2old = S2;
273 }
274
275 }
276
277 //===========================================================================
278 // End of main.c
279 //===========================================================================
67
controller.h
1 #ifndef CONTROLLER H
2 #define CONTROLLER H
3
4 ///SetupController () : Designed to set appropriate outputs back to GPIO for SMC
to toggle at will .
5 void SetupController () ;
6
7 ///TurnOffController () : Returns control of GPIO pins back to PWM.
8 void TurnOffController () ;
9
10 ///TurnOnPhase1() : Turns off Phase1 Low side FET then turns on phase 1 high
set FET.
11 void TurnOnPhase1() ;
12
13 ///TurnOffPhase1() : Turns off phase1 high side FET then turns on phase 1
low side fet ;
14 void TurnOffPhase1() ;
15
16 #endif /?CONTROLLER H ?/
68
Globals.h
1 #ifndef GLOBALS H
2 #define GLOBALS H
3
4 #include ?DSP28x Project .h? // Device Headerfile and Examples Include File
5
6 //extern Uint16 LoopCount;
7 //extern Uint16 ErrorCount ;
8 //extern Uint16 ConversionCount ;
9 //extern Uint16 XmitFlag ;
10 //extern Uint16 I2CTXFlag;
11 //extern Uint16 I2CRXFlag;
12 extern Uint16 PhaseStatus ;
13 extern Uint16 PhaseCount ;
14 //extern Uint16 LEDStatus;
15
16 struct MAINFLAGBITS{ // bits description
17 Uint16 XmitFlag :1; // 0 Transmit ADC information back
18 Uint16 I2CTXFlag :1; // 1 Transmit Something over I2C
19 Uint16 I2CRXFlag :1; // 2 Receive something over I2C
20 Uint16 Timer0Flag :1; // 3 Do a low priority background task on timer0
21 Uint16 ControllerFlag :1; // 4 Controller flag , set/cleared by serial
comm
22 Uint16 OldControllerFlag :1; // 5 Old controller flag , used to do edge
adjustments .
23 Uint16 rsv6 :1; // 6 Reserved
24 Uint16 rsv7 :1; // 7 Reserved
25 Uint16 rsv8 :1; // 8 Reserved
26 Uint16 rsv9 :1; // 9 Reserved
27 Uint16 rsv10 :1; // 10 Reserved
28 Uint16 rsv11 :1; // 11 Reserved
29 Uint16 rsv12 :1; // 12 Reserved
30 Uint16 rsv13 :1; // 13 Reserved
31 Uint16 rsv14 :1; // 14 Reserved
32 Uint16 rsv15 :1; // 15 Reserved
33 };
34
35 union MAINFLAGS{
36 Uint16 all ;
37 struct MAINFLAGBITS bit ;
38 };
39
40 extern union MAINFLAGS MainFlags ;
41
42
43 struct BUTTONBITS{ // bits description
44 Uint16 PB1:1; // 0 Transmit ADC information back
45 Uint16 PB2:1; // 1 Transmit Something over I2C
46 Uint16 PB3:1; // 2 Receive something over I2C
47 Uint16 PB4:1; // 3 Do a low priority background task on timer0
48 Uint16 SW1 1:1; // 4 Reserved
49 Uint16 SW1 2:1; // 5 Reserved
50 Uint16 SW1 3:1; // 6 Reserved
69
51 Uint16 SW1 4:1; // 7 Reserved
52 Uint16 rsv8 :1; // 8 Reserved
53 Uint16 rsv9 :1; // 9 Reserved
54 Uint16 rsv10 :1; // 10 Reserved
55 Uint16 rsv11 :1; // 11 Reserved
56 Uint16 rsv12 :1; // 12 Reserved
57 Uint16 rsv13 :1; // 13 Reserved
58 Uint16 rsv14 :1; // 14 Reserved
59 Uint16 rsv15 :1; // 15 Reserved
60 };
61 struct BUTTONNIBBLE{ // bits description
62 Uint16 PB:4; // 0 Transmit ADC information back
63 Uint16 SW1:4; // 4 Reserved
64 Uint16 rsv8 :1; // 8 Reserved
65 Uint16 rsv9 :1; // 9 Reserved
66 Uint16 rsv10 :1; // 10 Reserved
67 Uint16 rsv11 :1; // 11 Reserved
68 Uint16 rsv12 :1; // 12 Reserved
69 Uint16 rsv13 :1; // 13 Reserved
70 Uint16 rsv14 :1; // 14 Reserved
71 Uint16 rsv15 :1; // 15 Reserved
72 };
73 union BUTTONS{
74 Uint16 all ;
75 struct BUTTONBITS bit ;
76 struct BUTTONNIBBLE nib ;
77 };
78
79 extern union BUTTONS ButtonStatus ;
80
81 struct LEDBITS{ // bits description
82 Uint16 LED0:2; // 0 Transmit ADC information back
83 Uint16 LED1:2; // 4 Reserved
84 Uint16 LED2:2; // 8 Reserved
85 Uint16 LED3:2; // 9 Reserved
86 Uint16 LED4:2; // 10 Reserved
87 Uint16 LED5:2; // 11 Reserved
88 Uint16 LED6:2; // 12 Reserved
89 Uint16 LED7:2; // 13 Reserved
90 };
91 union LEDS{
92 Uint16 all ;
93 struct LEDBITS bit ;
94 };
95
96 extern union LEDS LEDStatus;
97 extern union LEDS LEDStatus2;
98
99 #endif /?GLOBALS H ?/
70
ADCHandler.h
1 #ifndef ADCHANDLERH
2 #define ADCHANDLERH
3
4 #include ?DSP28x Project .h? // Device Headerfile and Examples Include File
5
6 //??????????????????????? ADC start parameters
????????????????????????????????
7 #if (CPU FRQ 150MHZ) // Default ? 150 MHz SYSCLKOUT
8 #define ADCMODCLK 0x3 // HSPCLK = SYSCLKOUT/2?ADCMODCLK2 = 150/(2?3) =
25.0 MHz
9 #endif
10 #if (CPU FRQ 100MHZ)
11 #define ADCMODCLK 0x2 // HSPCLK = SYSCLKOUT/2?ADCMODCLK2 = 100/(2?2) =
25.0 MHz
12 #endif
13 #define ADC CKPS 0x1 // ADC module clock = HSPCLK/2?ADC CKPS = 25.0MHz
/(1?2) = 12.5MHz
14 //#define ADC SHCLK 0xf // S/H width in ADC module periods
= 16 ADC clocks
15 #define ADC SHCLK 0x3 // S/H width in ADC module periods ( val+1)
= 4 ADC clocks
16 #define AVG 1000 // Average sample limit
17 #define ZOFFSET 0x00 // Average Zero offset
18 #define BUF SIZE 1024 // Sample buffer size
19 //??????????????????????? End ADC start parameters
????????????????????????????
20
21 void InitADCModule() ;
22
23 interrupt void adc isr (void) ;
24
25
26 //ADC Variables
27 extern Uint16 SampleTable [BUF SIZE ];
28
29 #endif /?ADCHANDLER H ?/
71
ADCHandler.c
1 #include ?ADCHandler.h?
2 #include ?controller .h?
3 #include ?DSP28x Project .h? // Device Headerfile and Examples Include File
4
5
6
7 //ADC Variables
8 Uint16 SampleTable [BUF SIZE ];
9 //const int16 alpha1 = 10;
10 //const int16 alpha2 = 726;
11 //const int16 alpha3 = 1;
12 //const int16 kappa = 45;
13 //const int16 Vref = 1160;
14
15 interrupt void adc isr (void)
16 {
17
18 // static Uint16 idx = 16;
19 // static int32 S = 0;
20 // static int16 adcVold = 0;
21 // int16 adcV;
22 // int16 x1 , x2 ;
23 // idx++;
24 // adcV = AdcRegs.ADCRESULT0 >>4;
25 //
26 // x1 = Vref ? adcV;
27 // x2 = adcV ? adcVold ;
28 // S = alpha1?x1 + alpha2?x2+alpha3?adcVold ;
29 //// if (S > kappa){
30 // if (( idx & 1)==0){
31 // TurnOnPhase1() ;
32 // }
33 //// if (S < kappa){
34 // else{
35 // TurnOffPhase1() ;
36 // }
37 //// SampleTable [ idx+4] = AdcRegs.ADCRESULT1 >>4;
38 //// SampleTable [ idx++] = adcV;
39 // adcVold = adcV;
40 //// if ( idx > 19){
41 //// idx = 16;
42 //// SampleTable [0] = (SampleTable [16] + SampleTable [17] + SampleTable
[18] + SampleTable [19]) >> 2;
43 //// SampleTable [1] = (SampleTable [20] + SampleTable [21] + SampleTable
[22] + SampleTable [23]) >> 2;
44 //// }
45 //// Voltage2 [0] = AdcRegs.ADCRESULT1; //>>4;
46 //
47 // // If 40 conversions have been logged , start over
48 //// if (ConversionCount == 0x1FD) //two seconds
49 //// {
50 //// ConversionCount = 0;
72
51 //// XmitFlag = 1;
52 //// }
53 //// else ConversionCount++;
54 //
55 // Reinitialize for next ADC sequence
56 AdcRegs.ADCTRL2. bit .RST SEQ1 = 1; // Reset SEQ1
57 AdcRegs.ADCST. bit .INT SEQ1 CLR = 1; // Clear INT SEQ1 bit
58 PieCtrlRegs .PIEACK. all = PIEACK GROUP1; // Acknowledge interrupt to PIE
59
60 return;
61 }
62
63
64 void InitADCModule(){
65 InitAdc () ;
66
67 // Specific ADC setup for this example :
68 // AdcRegs.ADCTRL1. bit .ACQ PS = ADC SHCLK;
69 AdcRegs.ADCTRL1. bit .ACQ PS = 0; // One clock sample&hold
70 AdcRegs.ADCTRL1. bit .CPS = 0; // Disable an additional prescaler .
71 AdcRegs.ADCTRL3. bit .ADCCLKPS = 0;//ADC CKPS;// trying for 12.5 MHz sample
rate .
72 AdcRegs.ADCTRL3. bit .SMODE SEL = 1; // Simultaneous sampling mode
73 AdcRegs.ADCTRL1. bit .SEQ CASC = 1; // 1 Cascaded mode
74 AdcRegs.ADCTRL1. bit .CONTRUN = 1; // Setup continuous run
75
76 AdcRegs.ADCMAXCONV. all = 0x0001 ; // Setup all conv ?s on SEQ1,
only 1 conversion (CONV00)
77 AdcRegs.ADCCHSELSEQ1. bit .CONV00 = 0x0; // Sample Phase 1 Vout/IOut
store in ADCRESULT0, ADCRESULT1
78 AdcRegs.ADCCHSELSEQ1. bit .CONV01 = 0x4; // Sample Phase 2 Vout/IOut
store in ADCRESULT2, ADCRESULT3
79
80 // AdcRegs.ADCTRL2. bit .EPWM SOCA SEQ1 = 1; // Enable SOCA from ePWM to
start SEQ1
81 // AdcRegs.ADCTRL2. bit .INT ENA SEQ1 = 1; // Enable SEQ1 interrupt (
every EOS)
82
83
84 }
73
SerialHandler.h
1 #ifndef SERIALHANDLER H
2 #define SERIALHANDLER H
3
4 #include ?DSP28x Project .h? // Device Headerfile and Examples Include File
5
6 #define TXBUFFSIZE 128
7 //Union and structure definitions
8 struct SCIISRBITS{ // bits description
9 Uint16 TXFlag:1; // 0 TX Interrupt Occured
10 Uint16 RXFlag:1; // 1 RX Interrupt Occured
11 Uint16 unassigned :14;
12 };
13
14 union SCI ISR FLAGS{
15 Uint16 all ;
16 struct SCIISRBITS bit ;
17 };
18
19 struct SCIFLAGBITS{ // bits description
20 Uint16 UpdateDuty :1; // 0 Update Duty Cycle Flag
21 Uint16 UpdateHRDuty:1; // 1 Update HR Duty cycle flag
22 Uint16 UpdateDBRising :1; // 2 Update Deadband rising flag
23 Uint16 UpdateDBFalling :1; // 3 Update deadband falling flag
24 Uint16 UpdatePeriod :1; // 4 Update Period
25 Uint16 KillPWM:1; // 5 Kill PWM
26 Uint16 UpdatePhase2 :1; // 6 Update Phase 2
27 Uint16 UpdatePhase3 :1; // 7 Update Phase 3
28 Uint16 UpdatePhase4 :1; // 8 Update Phase 4
29 Uint16 UpdatePhase5 :1; // 9 Update Phase 5
30 Uint16 SendEverything :1; // 10 Send Complete Status
31 Uint16 UpdateController :1; // 11 Turn on/off the controller
32 Uint16 unassigned :4;
33 };
34
35 union SCIFLAGS{
36 Uint16 all ;
37 struct SCIFLAGBITS bit ;
38 };
39
40
41 //Global Scope variables
42 extern union SCI ISR FLAGS SciIsrFlags ;
43 extern union SCIFLAGS SciFlags ;
44
45 extern Uint16 ReceivedChar ;
46 //extern Uint16 XmitFlag ;
47
48 //Async TXBuffer FIFO;
49 extern Uint16 TXBuffer [TXBUFFSIZE];
50 extern Uint16? TXBufferFIFOFront;
51 extern Uint16? TXBufferFIFOEnd;
52 extern Uint16? TXBufferEnd;
74
53
54 interrupt void scirxa isr (void) ;
55 interrupt void scitxa isr (void) ;
56
57 void scia echoback init (void) ;
58 void scia fifo init (void) ;
59 void scia xmit (int a) ;
60 void scia msg (char ?msg) ;
61 void scia xmit num(Uint16 val ) ;
62
63 void scia fifo init async (void) ;
64 void scia xmit async (int a) ;
65 void scia msg async (char ?msg) ;
66 void scia xmit num async(Uint16 val ) ;
67
68
69
70 #endif /?SERIALHANDLER H ?/
75
SerialHandler.c
1 #include ?SerialHandler .h?
2 #include ?PWMHandler.h?
3 #include ?Globals .h?
4 #include ?DSP28x Project .h? // Device Headerfile and Examples Include File
5
6 union SCI ISR FLAGS SciIsrFlags ;
7 union SCIFLAGS SciFlags ;
8
9 Uint16 ReceivedChar ;
10
11 Uint16 TXBuffer [TXBUFFSIZE];
12 Uint16? TXBufferFIFOFront;
13 Uint16? TXBufferFIFOEnd;
14 Uint16? TXBufferEnd;
15
16 interrupt void scirxa isr (void){
17 // char? msg;
18 static Uint16 value ;
19 // static Uint16 phaseValue = 0;
20 EALLOW;
21 ReceivedChar = SciaRegs .SCIRXBUF. all ;
22 switch(ReceivedChar){
23 case ?x ? :
24 EPwm1Regs.TZFRC. bit .OST = 1; // Kill PWM1
25 EPwm2Regs.TZFRC. bit .OST = 1; // Kill PWM2
26 EPwm3Regs.TZFRC. bit .OST = 1; // Kill PWM3
27 EPwm4Regs.TZFRC. bit .OST = 1; // Kill PWM4
28 EPwm5Regs.TZFRC. bit .OST = 1; // Kill PWM5
29 EPwm6Regs.TZFRC. bit .OST = 1; // Kill PWM6
30 SciFlags . bit .KillPWM = 1;
31 break;
32 case ? i ? :
33 value = EPwm1Regs.CMPA. half .CMPA + 1;
34 SciFlags . bit .UpdateDuty = 1;
35 break;
36 case ?k ? :
37 value = EPwm1Regs.CMPA. half .CMPA ? 1;
38 SciFlags . bit .UpdateDuty = 1;
39 break;
40 case ? . ? :
41 value = EPwm1Regs.CMPA. half .CMPAHR + 0x100 ;
42 SciFlags . bit .UpdateHRDuty = 1;
43 break;
44 case ? , ? :
45 value = EPwm1Regs.CMPA. half .CMPAHR ? 0x100 ;
46 SciFlags . bit .UpdateHRDuty = 1;
47 break;
48 case ?o ? :
49 value = EPwm1Regs.DBRED + 1;
50 SciFlags . bit . UpdateDBRising = 1;
51 break;
52 case ? l ? :
76
53 value = EPwm1Regs.DBRED ? 1;
54 SciFlags . bit . UpdateDBRising = 1;
55 break;
56 case ?p ? :
57 value = EPwm1Regs.DBFED + 1;
58 SciFlags . bit . UpdateDBFalling = 1;
59 break;
60 case ? ; ? :
61 value = EPwm1Regs.DBFED ? 1;
62 SciFlags . bit . UpdateDBFalling = 1;
63 break;
64 case ?u ? :
65 value = EPwm1Regs.TBPRD + 1;
66 SciFlags . bit . UpdatePeriod = 1;
67 break;
68 case ? j ? :
69 value = EPwm1Regs.TBPRD ? 1;
70 SciFlags . bit . UpdatePeriod = 1;
71 break;
72 case ?y ? :
73 value = EPwm2Regs.TBPHS. half .TBPHS + 1;
74 SciFlags . bit . UpdatePhase2 = 1;
75 break;
76 case ?h ? :
77 value = EPwm2Regs.TBPHS. half .TBPHS ? 1;
78 SciFlags . bit . UpdatePhase2 = 1;
79 break;
80 case ?t ? :
81 value = EPwm3Regs.TBPHS. half .TBPHS + 1;
82 SciFlags . bit . UpdatePhase3 = 1;
83 break;
84 case ?g ? :
85 value = EPwm3Regs.TBPHS. half .TBPHS ? 1;
86 SciFlags . bit . UpdatePhase3 = 1;
87 break;
88 case ?r ? :
89 value = EPwm4Regs.TBPHS. half .TBPHS + 1;
90 SciFlags . bit . UpdatePhase4 = 1;
91 break;
92 case ? f ? :
93 value = EPwm4Regs.TBPHS. half .TBPHS ? 1;
94 SciFlags . bit . UpdatePhase4 = 1;
95 break;
96 case ?e ? :
97 value = EPwm5Regs.TBPHS. half .TBPHS + 1;
98 SciFlags . bit . UpdatePhase5 = 1;
99 break;
100 case ?d ? :
101 value = EPwm5Regs.TBPHS. half .TBPHS ? 1;
102 SciFlags . bit . UpdatePhase5 = 1;
103 break;
104 case ?1 ? :
105 EPwm1Regs.TZCLR. all = 5;
106 PhaseCount += 1;
77
107 break;
108 case ?2 ? :
109 EPwm2Regs.TZCLR. all = 5;
110 PhaseCount += 1;
111 break;
112 case ?3 ? :
113 EPwm3Regs.TZCLR. all = 5;
114 PhaseCount += 1;
115 break;
116 case ?4 ? :
117 EPwm4Regs.TZCLR. all = 5;
118 PhaseCount += 1;
119 break;
120 case ?5 ? : //Phase 5
121 EPwm5Regs.TZCLR. all = 5;
122 PhaseCount += 1;
123 break;
124 case ?a ? : //ADC
125 MainFlags . bit . XmitFlag = 1;
126 break;
127 case ?s ? : //status
128 SciFlags . bit . SendEverything = 1;
129 break;
130 case ?n ? :
131 if(??PwmPointer < PwmPeriods)
132 PwmPointer = PwmPeriods + 13;
133 value = ?PwmPointer;
134 SciFlags . bit . UpdatePeriod = 1;
135 break;
136 case ?m? :
137 if(++PwmPointer > PwmPeriods+13)
138 PwmPointer = PwmPeriods;
139 value = ?PwmPointer;
140 SciFlags . bit . UpdatePeriod = 1;
141 break;
142 case ?c ? :
143 MainFlags . bit .I2CTXFlag = 1;
144 break;
145 case ?v ? :
146 MainFlags . bit .I2CRXFlag = 1;
147 break;
148 case ?Z? :
149 SciFlags . bit . UpdateController = 1;
150 break;
151 // default :
152 // scia xmit async (ReceivedChar) ;
153 // break ;
154 }
155 scia xmit async (ReceivedChar) ;
156 if ( SciFlags . bit .KillPWM == 1){
157 // scia xmit async ( ?x ?) ;
158 PhaseCount = 0;
159 SciFlags . bit .KillPWM = 0;
160 }
78
161 if ( SciFlags . bit .UpdateDuty == 1){
162 EPwm1Regs.CMPA. half .CMPA = value ;
163 EPwm2Regs.CMPA. half .CMPA = value ;
164 EPwm3Regs.CMPA. half .CMPA = value ;
165 EPwm4Regs.CMPA. half .CMPA = value ;
166 EPwm5Regs.CMPA. half .CMPA = value ;
167 // EPwm2Regs.TBPHS. half .TBPHS = (value>>1);
168 scia xmit num async(value) ;
169 SciFlags . bit .UpdateDuty = 0;
170 }
171 if ( SciFlags . bit .UpdateHRDuty == 1){
172 EPwm1Regs.CMPA. half .CMPAHR = value ;
173 EPwm2Regs.CMPA. half .CMPAHR = value ;
174 EPwm3Regs.CMPA. half .CMPAHR = value ;
175 EPwm4Regs.CMPA. half .CMPAHR = value ;
176 EPwm5Regs.CMPA. half .CMPAHR = value ;
177 scia xmit num async(value) ;
178 SciFlags . bit .UpdateHRDuty = 0;
179 }
180 if ( SciFlags . bit . UpdateDBRising == 1){
181 EPwm1Regs.DBRED = value ;
182 EPwm2Regs.DBRED = value ;
183 EPwm3Regs.DBRED = value ;
184 EPwm4Regs.DBRED = value ;
185 EPwm5Regs.DBRED = value ;
186 // scia xmit async ( ?o ?) ;
187 // scia xmit async ( ? l ?) ;
188 scia xmit num async(value) ;
189 SciFlags . bit . UpdateDBRising = 0;
190 }
191 if ( SciFlags . bit . UpdateDBFalling == 1){
192 EPwm1Regs.DBFED = value ;
193 EPwm2Regs.DBFED = value ;
194 EPwm3Regs.DBFED = value ;
195 EPwm4Regs.DBFED = value ;
196 EPwm5Regs.DBFED = value ;
197 // scia xmit async ( ?p ?) ;
198 // scia xmit async ( ?; ?) ;
199 scia xmit num async(value) ;
200 SciFlags . bit . UpdateDBFalling = 0;
201 }
202 if ( SciFlags . bit . UpdatePeriod == 1){
203 EPwm1Regs.TBPRD = value ;
204 EPwm2Regs.TBPRD = value ;
205 EPwm3Regs.TBPRD = value ;
206 EPwm4Regs.TBPRD = value ;
207 EPwm5Regs.TBPRD = value ;
208 scia xmit num async(value) ;
209 //FIXME: Need to autmatically update periods if the phases are active .
210 // phaseValue = (?PhaseStatus) & 0x1F) ;
211 // value = 0;
212 //
213 // EPwm1Regs.TBPHS. half .TBPHS = 0;
214 // if (PhaseCount > 1){
79
215 // value = (EPwm1Regs.TBPRD / PhaseCount) ;
216 // if (phaseValue & 0x02)
217 // EPwm2Regs.TBPHS. half .TBPHS = value ;
218 // else
219 // EPwm2Regs.TBPHS. half .TBPHS = 0;
220 // if (phaseValue & 0x04)
221 // EPwm3Regs.TBPHS. half .TBPHS = value ;
222 // else
223 // EPwm3Regs.TBPHS. half .TBPHS = 0;
224 // if (phaseValue & 0x08)
225 // EPwm4Regs.TBPHS. half .TBPHS = value ;
226 // else
227 // EPwm4Regs.TBPHS. half .TBPHS = 0;
228 // if (phaseValue & 0x10)
229 // EPwm5Regs.TBPHS. half .TBPHS = value ;
230 // else
231 // EPwm5Regs.TBPHS. half .TBPHS = 0;
232 // }
233
234 SciFlags . bit . UpdatePeriod = 0;
235 }
236 if ( SciFlags . bit . UpdatePhase2 == 1){
237 EPwm2Regs.TBPHS. half .TBPHS = value ;
238 // scia xmit async ( ?y ?) ;
239 // scia xmit async ( ?h ?) ;
240 scia xmit num async(value) ;
241 SciFlags . bit . UpdatePhase2 = 0;
242 }
243 if ( SciFlags . bit . UpdatePhase3 == 1){
244 EPwm3Regs.TBPHS. half .TBPHS = value ;
245 // scia xmit async ( ? t ?) ;
246 // scia xmit async ( ?g ?) ;
247 scia xmit num async(value) ;
248 SciFlags . bit . UpdatePhase3 = 0;
249 }
250 if ( SciFlags . bit . UpdatePhase4 == 1){
251 EPwm4Regs.TBPHS. half .TBPHS = value ;
252 // scia xmit async ( ?r ?) ;
253 // scia xmit async ( ? f ?) ;
254 scia xmit num async(value) ;
255 SciFlags . bit . UpdatePhase4 = 0;
256 }
257 if ( SciFlags . bit . UpdatePhase5 == 1){
258 EPwm5Regs.TBPHS. half .TBPHS = value ;
259 // scia xmit async ( ?e ?) ;
260 // scia xmit async ( ?d ?) ;
261 scia xmit num async(value) ;
262 SciFlags . bit . UpdatePhase5 = 0;
263 }
264 if ( SciFlags . bit . SendEverything == 1){
265 scia xmit num async(EPwm1Regs.TBPRD) ;
266 scia xmit num async(EPwm1Regs.CMPA. half .CMPA) ;
267 scia xmit num async(EPwm1Regs.DBRED) ;
268 scia xmit num async(EPwm1Regs.DBFED) ;
80
269 scia xmit num async(EPwm1Regs.TZFRC. all ) ;
270 scia xmit num async(EPwm2Regs.TZFRC. all ) ;
271 scia xmit num async(EPwm2Regs.TBPHS. half .TBPHS) ;
272 scia xmit num async(EPwm3Regs.TZFRC. all ) ;
273 scia xmit num async(EPwm3Regs.TBPHS. half .TBPHS) ;
274 scia xmit num async(EPwm4Regs.TZFRC. all ) ;
275 scia xmit num async(EPwm4Regs.TBPHS. half .TBPHS) ;
276 scia xmit num async(EPwm5Regs.TZFRC. all ) ;
277 scia xmit num async(EPwm5Regs.TBPHS. half .TBPHS) ;
278 SciFlags . bit . SendEverything = 0;
279 }
280 if ( SciFlags . bit . UpdateController == 1){
281 if (MainFlags . bit . ControllerFlag == 1){
282 //Controller on, turn it off .
283 MainFlags . bit . ControllerFlag = 0;
284 }
285 else{
286 //Controller off , turn it on.
287 MainFlags . bit . ControllerFlag = 1;
288 }
289 }
290 // msg = ?\r\n?;
291 // scia msg async(msg) ;
292 SciIsrFlags . bit .RXFlag = 1;
293 SciaRegs .SCIFFRX. bit .RXFFINTCLR = 1; // Reset interrupt .
294 PieCtrlRegs .PIEACK. all = PIEACK GROUP9; // Acknowledge interrupt to PIE
295 }
296
297
298
299 // Test 1,SCIA DLB, 8?bit word , baud rate 0x000F , default , 1 STOP bit , no
parity
300 void scia echoback init ()
301 {
302 // Note: Clocks were turned on to the SCIA peripheral
303 // in the InitSysCtrl () function
304 SciFlags . all = 0x00 ;
305
306 SciaRegs .SCICCR. all =0x0007 ; // 1 stop bit , No loopback
307 // No parity ,8 char bits ,
308 // async mode, idle?line protocol
309 SciaRegs .SCICTL1. all =0x0003 ; // enable TX, RX, internal SCICLK,
310 // Disable RX ERR, SLEEP, TXWAKE
311 SciaRegs .SCICTL2. all =0x0003 ;
312 SciaRegs .SCICTL2. bit .TXINTENA =1;
313 // SciaRegs .SCICTL2. bit .RXBKINTENA =1;
314 SciaRegs .SCIFFRX. bit .RXFFIENA = 1;
315
316 #if (CPU FRQ 150MHZ)
317 SciaRegs .SCIHBAUD =0x0001 ; // 9600 baud @LSPCLK = 37.5MHz.
318 SciaRegs .SCILBAUD =0x00E7;
319 #endif
320 #if (CPU FRQ 100MHZ)
321 SciaRegs .SCIHBAUD =0x0001 ; // 9600 baud @LSPCLK = 20MHz.
81
322 SciaRegs .SCILBAUD =0x0044 ;
323 #endif
324 SciaRegs .SCICTL1. all =0x0023 ; // Relinquish SCI from Reset
325 }
326
327 // Transmit a character from the SCI
328 void scia xmit (int a)
329 {
330 while (SciaRegs .SCIFFTX. bit .TXFFST != 0) {}
331 SciaRegs .SCITXBUF=a;
332
333 }
334
335 void scia msg (char ? msg)
336 {
337 int i ;
338 i = 0;
339 while(msg[ i ] != ?\0 ?)
340 {
341 scia xmit (msg[ i ]) ;
342 i++;
343 }
344 }
345
346 // Initalize the SCI FIFO
347 void scia fifo init ()
348 {
349 SciaRegs .SCIFFTX. all=0xE040;
350 // SciaRegs .SCIFFRX. all=0x204f ;
351 SciaRegs .SCIFFRX. all=0x2061 ; //1 byte fifo generates interrupt
352 // SciaRegs .SCIFFRX. all=0x2071 ;
353 SciaRegs .SCIFFCT. all=0x0;
354
355 }
356
357 void scia xmit num(Uint16 val ){
358 int nibble = val & 0x000F;
359 int ascii [4];
360 int counter = 0;
361 for(counter = 0; counter < 4; counter++){
362 if ( nibble > 9)
363 ascii [3?counter ] = nibble+55;
364 else
365 ascii [3?counter ] = nibble+48;
366 val = val >> 4;
367 nibble = val &0x000F;
368 }
369 scia xmit ( ascii [0]) ;
370 scia xmit ( ascii [1]) ;
371 scia xmit ( ascii [2]) ;
372 scia xmit ( ascii [3]) ;
373 }
374
375
82
376 interrupt void scitxa isr (void){
377 Uint16 i ;
378 //Interrupt occured , meaning TX FIFO empty
379 //Check if TXBuffer is empty. If so , disable interrupts and finish out .
380 if (TXBufferFIFOFront == TXBufferFIFOEnd){
381 SciaRegs .SCIFFTX. bit .TXFFIENA = 0; //disable interrupts
382 }
383 else{ //Data in TXBuffer
384 for( i = 0; i < 15; i++)
385 {
386 SciaRegs .SCITXBUF=?TXBufferFIFOFront;
387 TXBufferFIFOFront++;
388 if (TXBufferFIFOFront > TXBufferEnd)
389 TXBufferFIFOFront = TXBuffer ;
390 if (TXBufferFIFOFront == TXBufferFIFOEnd)
391 break;
392 }
393 }
394 SciIsrFlags . bit .TXFlag = 1;
395 SciaRegs .SCIFFTX. bit .TXFFINTCLR = 1; // Reset interrupt .
396 PieCtrlRegs .PIEACK. all = PIEACK GROUP9; // Acknowledge interrupt to PIE
397 }
398
399
400 // Initalize the SCI FIFO
401 void scia fifo init async ()
402 {
403 SciaRegs .SCIFFTX. all=0xE040; //Empty TX generates interrupt , but don ? t
enable the interrupt yet .
404 SciaRegs .SCIFFRX. all=0x2061 ; //1 byte fifo generates interrupt
405 SciaRegs .SCIFFCT. all=0x0;
406 TXBufferFIFOFront = TXBuffer ;
407 TXBufferFIFOEnd = TXBuffer ;
408 TXBufferEnd = TXBuffer + (TXBUFFSIZE?1)?sizeof (Uint16) ; // the ?1 is there
because TXBuffer counts .
409 }
410
411 // Transmit a character from the SCI
412 void scia xmit async (int a)
413 {
414 //while (SciaRegs .SCIFFTX. bit .TXFFST != 0) {}
415 ?TXBufferFIFOEnd++ = a; //Store a in TXBufferFIFOEnd and then increment
TXBufferFIFOEnd
416 // TXBufferFIFOEnd++;
417 if (TXBufferFIFOEnd > TXBufferEnd)
418 TXBufferFIFOEnd = TXBuffer ;
419 // SciaRegs .SCITXBUF=a;
420 SciaRegs .SCIFFTX. bit .TXFFIENA = 1;
421 }
422
423 void scia msg async (char ? msg)
424 {
425 int i ;
426 i = 0;
83
427 while(msg[ i ] != ?\0 ?)
428 {
429 scia xmit async (msg[ i ]) ;
430 i++;
431 }
432 }
433
434
435
436 void scia xmit num async(Uint16 val ){
437 int nibble = val & 0x000F;
438 int ascii [4];
439 int counter = 0;
440 for(counter = 0; counter < 4; counter++){
441 if ( nibble > 9)
442 ascii [3?counter ] = nibble+55;
443 else
444 ascii [3?counter ] = nibble+48;
445 val = val >> 4;
446 nibble = val &0x000F;
447 }
448 scia xmit async ( ascii [0]) ;
449 scia xmit async ( ascii [1]) ;
450 scia xmit async ( ascii [2]) ;
451 scia xmit async ( ascii [3]) ;
452 }
84
TimerHandler.h
1 #ifndef TIMERHANDLER H
2 #define TIMERHANDLER H
3
4 #include ?Globals .h?
5 #include ?DSP28x Project .h? // Device Headerfile and Examples Include File
6
7
8 void InitTimerModule(void) ;
9 void Timer0Callback(void) ;
10
11 interrupt void timer0 isr () ;
12
13 #endif /?TIMERHANDLER H ?/
85
TimerHandler.c
1 #include ?TimerHandler .h?
2 #include ?I2CHandler .h?
3 #include ?Globals .h?
4
5 Uint16 timerCounter ;
6
7 void InitTimerModule (){
8 CpuTimer0Regs.TCR. bit .TSS = 1; //Stop timer .
9 CpuTimer0Regs.TCR. bit .TIF = 1; //Clear any triggered interrupts .
10 CpuTimer0Regs.TPR. all = 0x0000 ;
11 CpuTimer0Regs.TPRH. all = 0x0000 ;
12 // CpuTimer0Regs.PRD. half .MSW = 0x0907 ; //Setup timer for 1 second at 150MHz.
13 // CpuTimer0Regs.PRD. half .LSW = 0xF00F;
14 // CpuTimer0Regs.PRD. half .MSW = 0x0241 ; //Setup timer for 0.25 second at 150
MHz.
15 // CpuTimer0Regs.PRD. half .LSW = 0xFC03;
16 CpuTimer0Regs.PRD. half .MSW = 0x002D; //Setup timer for 20ms second at 150MHz
.
17 CpuTimer0Regs.PRD. half .LSW = 0xFE02;
18 CpuTimer0Regs.TCR. all = 0xC020; //Start the timer back and reload the period
into the timer .
19 //Enable the interrupt .
20 //Timers count down from the period value .
21
22 timerCounter = 0;
23 }
24
25 interrupt void timer0 isr (){
26
27 // if (timerCounter == 0)
28 // {
29 // EPwm2Regs.CMPA. half .CMPA = (EPwm2Regs.CMPA. half .CMPA>>1);
30 // timerCounter++;
31 // }
32 // else
33 // {
34 // EPwm2Regs.CMPA. half .CMPA = (EPwm2Regs.CMPA. half .CMPA<<1);
35 // timerCounter = 0;
36 // }
37 MainFlags . bit . Timer0Flag = 1;
38 CpuTimer0Regs.TCR. bit .TIF = 1; //Clear timer interrupt .
39 PieCtrlRegs .PIEACK. all = PIEACK GROUP1; // Acknowledge interrupt to PIE
40 }
41
42 void Timer0Callback (){
43 // static Uint16 counter = 0;
44 Uint16 tmp = 0;
45 LEDStatus. all = 0;
46 LEDStatus2. all = 0;
47 ButtonStatus . all = PollButtons () ;
48 if (ButtonStatus . nib .PB < 0xF){
49 EPwm1Regs.TZFRC. bit .OST = 1; // Kill PWM1
86
50 EPwm2Regs.TZFRC. bit .OST = 1; // Kill PWM2
51 EPwm3Regs.TZFRC. bit .OST = 1; // Kill PWM3
52 EPwm4Regs.TZFRC. bit .OST = 1; // Kill PWM4
53 EPwm5Regs.TZFRC. bit .OST = 1; // Kill PWM5
54 EPwm6Regs.TZFRC. bit .OST = 1; // Kill PWM6
55 }
56 if (ButtonStatus . bit .PB1 == 0)
57 LEDStatus2. bit .LED0 = LCD ON;
58 if (ButtonStatus . bit .PB2 == 0)
59 LEDStatus2. bit .LED1 = LCD ON;
60 if (ButtonStatus . bit .PB3 == 0)
61 LEDStatus2. bit .LED2 = LCD ON;
62 if (ButtonStatus . bit .PB4 == 0)
63 LEDStatus2. bit .LED3 = LCD ON;
64 if (ButtonStatus . bit .SW1 1 == 0)
65 LEDStatus2. bit .LED4 = LCD ON;
66 if (ButtonStatus . bit .SW1 2 == 0)
67 LEDStatus2. bit .LED5 = LCD ON;
68 if (ButtonStatus . bit .SW1 3 == 0)
69 LEDStatus2. bit .LED6 = LCD ON;
70 if (ButtonStatus . bit .SW1 4 == 0)
71 LEDStatus2. bit .LED7 = LCD ON;
72 SetPCA3Status(LEDStatus2. all ) ;
73 PhaseStatus = PollPhases () ;
74 if (( PhaseStatus & 0x0001) == 0){ //Phase 1 Board plugged in .
75 if (EPwm1Regs.TZFLG. bit .OST == 1){ //channel off
76 LEDStatus. bit .LED0 = LCD BLINK1;
77 }
78 else{
79 LEDStatus. bit .LED0 = LCD ON;
80 tmp += 1;
81 }
82 }
83
84 if (( PhaseStatus & 0x0002) == 0){ // Phase 2 Board plugged in .
85 if (EPwm2Regs.TZFLG. bit .OST == 1){ //channel off
86 LEDStatus. bit .LED1 = LCD BLINK1;
87 }
88 else{
89 LEDStatus. bit .LED1 = LCD ON;
90 tmp += 1;
91 }
92 }
93
94 if (( PhaseStatus & 0x0004) == 0){ // Phase 3 Board plugged in .
95 if (EPwm3Regs.TZFLG. bit .OST == 1){ //channel off
96 LEDStatus. bit .LED2 = LCD BLINK1;
97 }
98 else{
99 LEDStatus. bit .LED2 = LCD ON;
100 tmp += 1;
101 }
102 }
103
87
104 if (( PhaseStatus & 0x0008) == 0){ // Phase 4 Board plugged in .
105 if (EPwm4Regs.TZFLG. bit .OST == 1){ //channel off
106 LEDStatus. bit .LED3 = LCD BLINK1;
107 }
108 else{
109 LEDStatus. bit .LED3 = LCD ON;
110 tmp += 1;
111 }
112 }
113
114 if (( PhaseStatus & 0x0010) == 0){ // Phase 5 Board plugged in .
115 if (EPwm5Regs.TZFLG. bit .OST == 1){ //channel off
116 LEDStatus. bit .LED4 = LCD BLINK1;
117 }
118 else{
119 LEDStatus. bit .LED4 = LCD ON;
120 tmp += 1;
121 }
122 }
123 PhaseCount = tmp;
124 // if (counter == 0){
125 // tmp2 = LCD BLINK2
126 // LEDStatus += tmp2 <<10;
127 // counter++;
128 // }
129 // else{
130 // tmp2 = LCD OFF
131 // LEDStatus += tmp2 <<10;
132 // counter = 0;
133 // }
134 // tmp += 0xAFA0;
135 SetPCA1Status(LEDStatus. all ) ;
136
137
138 }
88
PWMHandler.h
1 #ifndef PWMHANDLERH
2 #define PWMHANDLERH
3
4 #include ?DSP28x Project .h? // Device Headerfile and Examples Include File
5
6 //??????????????????????? PWM Parameters
??????????????????????????????????????
7
8 //Deadband definitions
9 #define EPWMMAXDB 0x03FF
10 #define EPWMMINDB 0x0001
11
12 #define DB UP 1
13 #define DBDOWN 0
14
15 //??????????????????????? End PWM Parameters
??????????????????????????????????
16
17 //EPWM Variables
18 //extern Uint32 EPwm1TimerIntCount;
19 //extern Uint32 EPwm2TimerIntCount;
20 //extern Uint32 EPwm3TimerIntCount;
21 //extern Uint16 EPwm1 DB Direction;
22 //extern Uint16 EPwm2 DB Direction;
23 //extern Uint16 EPwm3 DB Direction;
24
25 extern Uint16 PwmPeriods [14];
26 extern Uint16 ?PwmPointer;
27
28 void InitPwmModule() ;
29
30 //Pwm init functions
31 void EPwm1Init(void) ;
32 void EPwm2Init(void) ;
33 void EPwm3Init(void) ;
34 void EPwm4Init(void) ;
35 void EPwm5Init(void) ;
36 void EPwm6Init(void) ;
37
38
39 interrupt void epwm1 isr(void) ;
40 interrupt void epwm2 isr(void) ;
41 interrupt void epwm3 isr(void) ;
42
43 #endif /?PWMHANDLERH ?/
89
PWMHandler.c
1 #include ?PWMHandler.h?
2
3 //EPWM Variables
4 //Uint32 EPwm1TimerIntCount;
5 //Uint32 EPwm2TimerIntCount;
6 //Uint32 EPwm3TimerIntCount;
7 //Uint16 EPwm1 DB Direction;
8 //Uint16 EPwm2 DB Direction;
9 //Uint16 EPwm3 DB Direction;
10
11 Uint16 PwmPeriods [14];
12 Uint16 ?PwmPointer;
13
14
15 //
16 //interrupt void epwm1 isr(void)
17 //{
18 //// if (EPwm1 DB Direction == DB UP)
19 //// {
20 //// if (EPwm1Regs.DBFED < EPWM1MAXDB)
21 //// {
22 //// EPwm1Regs.DBFED++;
23 //// EPwm1Regs.DBRED++;
24 //// }
25 //// else
26 //// {
27 //// EPwm1 DB Direction = DBDOWN;
28 //// EPwm1Regs.DBFED??;
29 //// EPwm1Regs.DBRED??;
30 //// }
31 //// }
32 //// else
33 //// {
34 //// if (EPwm1Regs.DBFED == EPWM1 MIN DB)
35 //// {
36 //// EPwm1 DB Direction = DB UP;
37 //// EPwm1Regs.DBFED++;
38 //// EPwm1Regs.DBRED++;
39 //// }
40 //// else
41 //// {
42 //// EPwm1Regs.DBFED??;
43 //// EPwm1Regs.DBRED??;
44 //// }
45 //// }
46 // EPwm1TimerIntCount++;
47 //
48 // // Clear INT flag for this timer
49 // EPwm1Regs.ETCLR. bit .INT = 1;
50 //
51 // // Acknowledge this interrupt to receive more interrupts from group 3
52 // PieCtrlRegs .PIEACK. all = PIEACK GROUP3;
90
53 //
54 //}
55 //
56 //interrupt void epwm2 isr(void)
57 //{
58 //
59 //// if (EPwm2 DB Direction == DB UP)
60 //// {
61 //// if (EPwm2Regs.DBFED < EPWM2MAXDB)
62 //// {
63 //// EPwm2Regs.DBFED++;
64 //// EPwm2Regs.DBRED++;
65 //// }
66 //// else
67 //// {
68 //// EPwm2 DB Direction = DBDOWN;
69 //// EPwm2Regs.DBFED??;
70 //// EPwm2Regs.DBRED??;
71 //// }
72 //// }
73 //// else
74 //// {
75 //// if (EPwm2Regs.DBFED == EPWM2 MIN DB)
76 //// {
77 //// EPwm2 DB Direction = DB UP;
78 //// EPwm2Regs.DBFED++;
79 //// EPwm2Regs.DBRED++;
80 //// }
81 //// else
82 //// {
83 //// EPwm2Regs.DBFED??;
84 //// EPwm2Regs.DBRED??;
85 //// }
86 //// }
87 //
88 // EPwm2TimerIntCount++;
89 //
90 // // Clear INT flag for this timer
91 // EPwm2Regs.ETCLR. bit .INT = 1;
92 //
93 // // Acknowledge this interrupt to receive more interrupts from group 3
94 // PieCtrlRegs .PIEACK. all = PIEACK GROUP3;
95 //
96 //}
97 //
98 //interrupt void epwm3 isr(void)
99 //{
100 // if (EPwm3 DB Direction == DB UP)
101 // {
102 // if (EPwm3Regs.DBFED < EPWM3MAXDB)
103 // {
104 // EPwm3Regs.DBFED++;
105 // EPwm3Regs.DBRED++;
106 // }
91
107 // else
108 // {
109 // EPwm3 DB Direction = DBDOWN;
110 // EPwm3Regs.DBFED??;
111 // EPwm3Regs.DBRED??;
112 // }
113 // }
114 // else
115 // {
116 // if (EPwm3Regs.DBFED == EPWM3 MIN DB)
117 // {
118 // EPwm3 DB Direction = DB UP;
119 // EPwm3Regs.DBFED++;
120 // EPwm3Regs.DBRED++;
121 // }
122 // else
123 // {
124 // EPwm3Regs.DBFED??;
125 // EPwm3Regs.DBRED??;
126 // }
127 // }
128 //
129 //
130 // EPwm3TimerIntCount++;
131 //
132 // // Clear INT flag for this timer
133 // EPwm3Regs.ETCLR. bit .INT = 1;
134 //
135 // // Acknowledge this interrupt to receive more interrupts from group 3
136 // PieCtrlRegs .PIEACK. all = PIEACK GROUP3;
137 //
138 //}
139
140 void InitPwmModule(){
141
142 InitEPwm1Gpio() ;
143 InitEPwm2Gpio() ;
144 InitEPwm3Gpio() ;
145
146 PwmPointer = PwmPeriods;
147 PwmPeriods [0] = 0x358 ; //175kHz
148 PwmPeriods [1] = 0x2ED; //200kHz
149 PwmPeriods [2] = 0x29A; //225kHz
150 PwmPeriods [3] = 0x257 ; //250
151 PwmPeriods [4] = 0x220 ; //275
152 PwmPeriods [5] = 0x1F3; //300
153 PwmPeriods [6] = 0x1CC; //325
154 PwmPeriods [7] = 0x1AB; //350
155 PwmPeriods [8] = 0x18F; //375
156 PwmPeriods [9] = 0x176 ; //400
157 PwmPeriods[10] = 0x160 ; //425
158 PwmPeriods[11] = 0x14C; //450
159 PwmPeriods[12] = 0x13B; //475
160 PwmPeriods[13] = 0x12B; //500
92
161
162 EPwm1Init() ;
163 EPwm2Init() ;
164 EPwm3Init() ;
165 EPwm4Init() ;
166 EPwm5Init() ;
167 EPwm6Init() ;
168 }
169
170 void EPwm1Init()
171 {
172
173 EPwm1Regs.TBPRD = 374; // Set timer period
174 EPwm1Regs.TBPHS. half .TBPHS = 0x0000 ; // Phase is 0
175 EPwm1Regs.TBCTR = 0x0000 ; // Clear counter
176
177 // Setup TBCLK
178 EPwm1Regs.TBCTL. bit .CTRMODE = TB COUNT UP; // Count up
179 EPwm1Regs.TBCTL. bit .PHSEN = TB DISABLE; // Disable phase loading
180 // EPwm1Regs.TBCTL. bit .HSPCLKDIV = TB DIV4; // Clock ratio to
SYSCLKOUT
181 // EPwm1Regs.TBCTL. bit .CLKDIV = TB DIV4;
182 EPwm1Regs.TBCTL. bit .HSPCLKDIV = TB DIV1; // Clock ratio to SYSCLKOUT
183 EPwm1Regs.TBCTL. bit .CLKDIV = TB DIV1;
184 EPwm1Regs.TBCTL. bit .SYNCOSEL = TB CTR ZERO;
185
186 EPwm1Regs.CMPCTL. bit .SHDWAMODE = CCSHADOW; // Load registers every ZERO
187 EPwm1Regs.CMPCTL. bit .SHDWBMODE = CCSHADOW;
188 EPwm1Regs.CMPCTL. bit .LOADAMODE = CC CTR ZERO;
189 EPwm1Regs.CMPCTL. bit .LOADBMODE = CC CTR ZERO;
190
191 EALLOW;
192 EPwm1Regs.HRCNFG. all = 0x0;
193 EPwm1Regs.HRCNFG. bit .EDGMODE = HR FEP; //Falling Edge Position
194 EPwm1Regs.HRCNFG. bit .CTLMODE = HRCMP; //CMPAHR controls value .
195 EPwm1Regs.HRCNFG. bit .HRLOAD = HR CTR ZERO; //Shadow load on CTR=0
196 // Setup compare
197 EPwm1Regs.CMPA. half .CMPA = 45;
198 EPwm1Regs.CMPA. half .CMPAHR = 0x0000 ;
199 // EPwm1Regs.CMPB = 3000;
200
201 // Set actions
202 EPwm1Regs.AQCTLA. bit .ZRO = AQ SET;
203 EPwm1Regs.AQCTLA. bit .CAU = AQ CLEAR; // Set PWM1A on Zero
204 // EPwm1Regs.AQCTLA. bit .CAD = AQ CLEAR;
205
206 EPwm1Regs.AQCTLB. bit .ZRO = AQ SET;
207 EPwm1Regs.AQCTLB. bit .CAU = AQ CLEAR; // Set PWM1A on Zero
208 // EPwm1Regs.AQCTLB. bit .CAD = AQ SET;
209
210 // Active Low PWMs ? Setup Deadband
211 EPwm1Regs.DBCTL. bit .OUTMODE = DB FULL ENABLE;
212 //EPwm1Regs.DBCTL. bit .POLSEL = DB ACTV LO;
213 EPwm1Regs.DBCTL. bit .POLSEL = DB ACTV HIC;
93
214 EPwm1Regs.DBCTL. bit .IN MODE = DBA ALL;
215 EPwm1Regs.DBRED = EPWMMINDB;
216 EPwm1Regs.DBFED = EPWMMINDB;
217
218 // Setup Trip?Zone for ePWM1:
219 EALLOW;
220 EPwm1Regs.TZSEL. bit .OSHT1 = TZ ENABLE; //TZ1 is a one?shot killer
221 EPwm1Regs.TZCTL. bit .TZA = TZ FORCE LO;
222 EPwm1Regs.TZCTL. bit .TZB = TZ FORCE LO;
223 EPwm1Regs.TZEINT. bit .OST = TZ ENABLE;
224 // EDIS;
225
226 EPwm1Regs.ETSEL. bit .INTEN = 0; // disable INT
227 }
228
229 void EPwm2Init()
230 {
231
232 EPwm2Regs.TBPRD = 374; // Set timer period
233 EPwm2Regs.TBPHS. half .TBPHS = 0x0000 ; // Phase is 0
234 EPwm2Regs.TBCTR = 0x0000 ; // Clear counter
235
236 // Setup TBCLK
237 EPwm2Regs.TBCTL. bit .CTRMODE = TB COUNT UP; // Count up
238 EPwm2Regs.TBCTL. bit .PHSEN = TB DISABLE; // Disable phase loading
239 // EPwm2Regs.TBCTL. bit .HSPCLKDIV = TB DIV4; // Clock ratio to
SYSCLKOUT
240 // EPwm2Regs.TBCTL. bit .CLKDIV = TB DIV4;
241 EPwm2Regs.TBCTL. bit .HSPCLKDIV = TB DIV1; // Clock ratio to SYSCLKOUT
242 EPwm2Regs.TBCTL. bit .CLKDIV = TB DIV1;
243 EPwm2Regs.TBCTL. bit .SYNCOSEL = TB CTR ZERO;
244
245 EPwm2Regs.CMPCTL. bit .SHDWAMODE = CCSHADOW; // Load registers every ZERO
246 EPwm2Regs.CMPCTL. bit .SHDWBMODE = CCSHADOW;
247 EPwm2Regs.CMPCTL. bit .LOADAMODE = CC CTR ZERO;
248 EPwm2Regs.CMPCTL. bit .LOADBMODE = CC CTR ZERO;
249
250 EALLOW;
251 EPwm2Regs.HRCNFG. all = 0x0;
252 EPwm2Regs.HRCNFG. bit .EDGMODE = HR FEP; //Falling Edge Position
253 EPwm2Regs.HRCNFG. bit .CTLMODE = HRCMP; //CMPAHR controls value .
254 EPwm2Regs.HRCNFG. bit .HRLOAD = HR CTR ZERO; //Shadow load on CTR=0
255 // Setup compare
256 EPwm2Regs.CMPA. half .CMPA = 45;
257 EPwm2Regs.CMPA. half .CMPAHR = 0x0000 ;
258 // EPwm2Regs.CMPB = 3000;
259
260 // Set actions
261 EPwm2Regs.AQCTLA. bit .ZRO = AQ SET;
262 EPwm2Regs.AQCTLA. bit .CAU = AQ CLEAR; // Set PWM1A on Zero
263 // EPwm2Regs.AQCTLA. bit .CAD = AQ CLEAR;
264
265 EPwm2Regs.AQCTLB. bit .ZRO = AQ SET;
266 EPwm2Regs.AQCTLB. bit .CAU = AQ CLEAR; // Set PWM1A on Zero
94
267 // EPwm2Regs.AQCTLB. bit .CAD = AQ SET;
268
269 // Active Low PWMs ? Setup Deadband
270 EPwm2Regs.DBCTL. bit .OUTMODE = DB FULL ENABLE;
271 //EPwm2Regs.DBCTL. bit .POLSEL = DB ACTV LO;
272 EPwm2Regs.DBCTL. bit .POLSEL = DB ACTV HIC;
273 EPwm2Regs.DBCTL. bit .IN MODE = DBA ALL;
274 EPwm2Regs.DBRED = EPWMMINDB;
275 EPwm2Regs.DBFED = EPWMMINDB;
276
277 // Setup Trip?Zone for ePWM1:
278 EALLOW;
279 EPwm2Regs.TZSEL. bit .OSHT1 = TZ ENABLE; //TZ1 is a one?shot killer
280 EPwm2Regs.TZCTL. bit .TZA = TZ FORCE LO;
281 EPwm2Regs.TZCTL. bit .TZB = TZ FORCE LO;
282 EPwm2Regs.TZEINT. bit .OST = TZ ENABLE;
283 // EDIS;
284
285 EPwm2Regs.ETSEL. bit .INTEN = 0; // disable INT
286 }
287
288 void EPwm3Init()
289 {
290
291 EPwm3Regs.TBPRD = 374; // Set timer period
292 EPwm3Regs.TBPHS. half .TBPHS = 0x0000 ; // Phase is 0
293 EPwm3Regs.TBCTR = 0x0000 ; // Clear counter
294
295 // Setup TBCLK
296 EPwm3Regs.TBCTL. bit .CTRMODE = TB COUNT UP; // Count up
297 EPwm3Regs.TBCTL. bit .PHSEN = TB DISABLE; // Disable phase loading
298 // EPwm3Regs.TBCTL. bit .HSPCLKDIV = TB DIV4; // Clock ratio to
SYSCLKOUT
299 // EPwm3Regs.TBCTL. bit .CLKDIV = TB DIV4;
300 EPwm3Regs.TBCTL. bit .HSPCLKDIV = TB DIV1; // Clock ratio to SYSCLKOUT
301 EPwm3Regs.TBCTL. bit .CLKDIV = TB DIV1;
302 EPwm3Regs.TBCTL. bit .SYNCOSEL = TB CTR ZERO;
303
304 EPwm3Regs.CMPCTL. bit .SHDWAMODE = CCSHADOW; // Load registers every ZERO
305 EPwm3Regs.CMPCTL. bit .SHDWBMODE = CCSHADOW;
306 EPwm3Regs.CMPCTL. bit .LOADAMODE = CC CTR ZERO;
307 EPwm3Regs.CMPCTL. bit .LOADBMODE = CC CTR ZERO;
308
309 EALLOW;
310 EPwm3Regs.HRCNFG. all = 0x0;
311 EPwm3Regs.HRCNFG. bit .EDGMODE = HR FEP; //Falling Edge Position
312 EPwm3Regs.HRCNFG. bit .CTLMODE = HRCMP; //CMPAHR controls value .
313 EPwm3Regs.HRCNFG. bit .HRLOAD = HR CTR ZERO; //Shadow load on CTR=0
314 // Setup compare
315 EPwm3Regs.CMPA. half .CMPA = 45;
316 EPwm3Regs.CMPA. half .CMPAHR = 0x0000 ;
317 // EPwm3Regs.CMPB = 3000;
318
319 // Set actions
95
320 EPwm3Regs.AQCTLA. bit .ZRO = AQ SET;
321 EPwm3Regs.AQCTLA. bit .CAU = AQ CLEAR; // Set PWM1A on Zero
322 // EPwm3Regs.AQCTLA. bit .CAD = AQ CLEAR;
323
324 EPwm3Regs.AQCTLB. bit .ZRO = AQ SET;
325 EPwm3Regs.AQCTLB. bit .CAU = AQ CLEAR; // Set PWM1A on Zero
326 // EPwm3Regs.AQCTLB. bit .CAD = AQ SET;
327
328 // Active Low PWMs ? Setup Deadband
329 EPwm3Regs.DBCTL. bit .OUTMODE = DB FULL ENABLE;
330 //EPwm3Regs.DBCTL. bit .POLSEL = DB ACTV LO;
331 EPwm3Regs.DBCTL. bit .POLSEL = DB ACTV HIC;
332 EPwm3Regs.DBCTL. bit .IN MODE = DBA ALL;
333 EPwm3Regs.DBRED = EPWMMINDB;
334 EPwm3Regs.DBFED = EPWMMINDB;
335
336 // Setup Trip?Zone for ePWM1:
337 EALLOW;
338 EPwm3Regs.TZSEL. bit .OSHT1 = TZ ENABLE; //TZ1 is a one?shot killer
339 EPwm3Regs.TZCTL. bit .TZA = TZ FORCE LO;
340 EPwm3Regs.TZCTL. bit .TZB = TZ FORCE LO;
341 EPwm3Regs.TZEINT. bit .OST = TZ ENABLE;
342 // EDIS;
343
344 EPwm3Regs.ETSEL. bit .INTEN = 0; // disable INT
345 }
346
347 void EPwm4Init()
348 {
349
350 EPwm4Regs.TBPRD = 374; // Set timer period
351 EPwm4Regs.TBPHS. half .TBPHS = 0x0000 ; // Phase is 0
352 EPwm4Regs.TBCTR = 0x0000 ; // Clear counter
353
354 // Setup TBCLK
355 EPwm4Regs.TBCTL. bit .CTRMODE = TB COUNT UP; // Count up
356 EPwm4Regs.TBCTL. bit .PHSEN = TB DISABLE; // Disable phase loading
357 // EPwm4Regs.TBCTL. bit .HSPCLKDIV = TB DIV4; // Clock ratio to
SYSCLKOUT
358 // EPwm4Regs.TBCTL. bit .CLKDIV = TB DIV4;
359 EPwm4Regs.TBCTL. bit .HSPCLKDIV = TB DIV1; // Clock ratio to SYSCLKOUT
360 EPwm4Regs.TBCTL. bit .CLKDIV = TB DIV1;
361 EPwm4Regs.TBCTL. bit .SYNCOSEL = TB CTR ZERO;
362
363 EPwm4Regs.CMPCTL. bit .SHDWAMODE = CCSHADOW; // Load registers every ZERO
364 EPwm4Regs.CMPCTL. bit .SHDWBMODE = CCSHADOW;
365 EPwm4Regs.CMPCTL. bit .LOADAMODE = CC CTR ZERO;
366 EPwm4Regs.CMPCTL. bit .LOADBMODE = CC CTR ZERO;
367
368 EALLOW;
369 EPwm4Regs.HRCNFG. all = 0x0;
370 EPwm4Regs.HRCNFG. bit .EDGMODE = HR FEP; //Falling Edge Position
371 EPwm4Regs.HRCNFG. bit .CTLMODE = HRCMP; //CMPAHR controls value .
372 EPwm4Regs.HRCNFG. bit .HRLOAD = HR CTR ZERO; //Shadow load on CTR=0
96
373 // Setup compare
374 EPwm4Regs.CMPA. half .CMPA = 45;
375 EPwm4Regs.CMPA. half .CMPAHR = 0x0000 ;
376 // EPwm4Regs.CMPB = 3000;
377
378 // Set actions
379 EPwm4Regs.AQCTLA. bit .ZRO = AQ SET;
380 EPwm4Regs.AQCTLA. bit .CAU = AQ CLEAR; // Set PWM1A on Zero
381 // EPwm4Regs.AQCTLA. bit .CAD = AQ CLEAR;
382
383 EPwm4Regs.AQCTLB. bit .ZRO = AQ SET;
384 EPwm4Regs.AQCTLB. bit .CAU = AQ CLEAR; // Set PWM1A on Zero
385 // EPwm4Regs.AQCTLB. bit .CAD = AQ SET;
386
387 // Active Low PWMs ? Setup Deadband
388 EPwm4Regs.DBCTL. bit .OUTMODE = DB FULL ENABLE;
389 //EPwm4Regs.DBCTL. bit .POLSEL = DB ACTV LO;
390 EPwm4Regs.DBCTL. bit .POLSEL = DB ACTV HIC;
391 EPwm4Regs.DBCTL. bit .IN MODE = DBA ALL;
392 EPwm4Regs.DBRED = EPWMMINDB;
393 EPwm4Regs.DBFED = EPWMMINDB;
394
395 // Setup Trip?Zone for ePWM1:
396 EALLOW;
397 EPwm4Regs.TZSEL. bit .OSHT1 = TZ ENABLE; //TZ1 is a one?shot killer
398 EPwm4Regs.TZCTL. bit .TZA = TZ FORCE LO;
399 EPwm4Regs.TZCTL. bit .TZB = TZ FORCE LO;
400 EPwm4Regs.TZEINT. bit .OST = TZ ENABLE;
401 // EDIS;
402
403 EPwm4Regs.ETSEL. bit .INTEN = 0; // disable INT
404 }
405
406 void EPwm5Init()
407 {
408
409 EPwm5Regs.TBPRD = 374; // Set timer period
410 EPwm5Regs.TBPHS. half .TBPHS = 0x0000 ; // Phase is 0
411 EPwm5Regs.TBCTR = 0x0000 ; // Clear counter
412
413 // Setup TBCLK
414 EPwm5Regs.TBCTL. bit .CTRMODE = TB COUNT UP; // Count up
415 EPwm5Regs.TBCTL. bit .PHSEN = TB DISABLE; // Disable phase loading
416 // EPwm5Regs.TBCTL. bit .HSPCLKDIV = TB DIV4; // Clock ratio to
SYSCLKOUT
417 // EPwm5Regs.TBCTL. bit .CLKDIV = TB DIV4;
418 EPwm5Regs.TBCTL. bit .HSPCLKDIV = TB DIV1; // Clock ratio to SYSCLKOUT
419 EPwm5Regs.TBCTL. bit .CLKDIV = TB DIV1;
420 EPwm5Regs.TBCTL. bit .SYNCOSEL = TB CTR ZERO;
421
422 EPwm5Regs.CMPCTL. bit .SHDWAMODE = CCSHADOW; // Load registers every ZERO
423 EPwm5Regs.CMPCTL. bit .SHDWBMODE = CCSHADOW;
424 EPwm5Regs.CMPCTL. bit .LOADAMODE = CC CTR ZERO;
425 EPwm5Regs.CMPCTL. bit .LOADBMODE = CC CTR ZERO;
97
426
427 EALLOW;
428 EPwm5Regs.HRCNFG. all = 0x0;
429 EPwm5Regs.HRCNFG. bit .EDGMODE = HR FEP; //Falling Edge Position
430 EPwm5Regs.HRCNFG. bit .CTLMODE = HRCMP; //CMPAHR controls value .
431 EPwm5Regs.HRCNFG. bit .HRLOAD = HR CTR ZERO; //Shadow load on CTR=0
432 // Setup compare
433 EPwm5Regs.CMPA. half .CMPA = 45;
434 EPwm5Regs.CMPA. half .CMPAHR = 0x0000 ;
435 // EPwm5Regs.CMPB = 3000;
436
437 // Set actions
438 EPwm5Regs.AQCTLA. bit .ZRO = AQ SET;
439 EPwm5Regs.AQCTLA. bit .CAU = AQ CLEAR; // Set PWM5A on Zero
440 // EPwm5Regs.AQCTLA. bit .CAD = AQ CLEAR;
441
442 EPwm5Regs.AQCTLB. bit .ZRO = AQ SET;
443 EPwm5Regs.AQCTLB. bit .CAU = AQ CLEAR; // Set PWM5A on Zero
444 // EPwm5Regs.AQCTLB. bit .CAD = AQ SET;
445
446 // Active Low PWMs ? Setup Deadband
447 EPwm5Regs.DBCTL. bit .OUTMODE = DB FULL ENABLE;
448 //EPwm5Regs.DBCTL. bit .POLSEL = DB ACTV LO;
449 EPwm5Regs.DBCTL. bit .POLSEL = DB ACTV HIC;
450 EPwm5Regs.DBCTL. bit .IN MODE = DBA ALL;
451 EPwm5Regs.DBRED = EPWMMINDB;
452 EPwm5Regs.DBFED = EPWMMINDB;
453
454 // Setup Trip?Zone for ePWM1:
455 EALLOW;
456 EPwm5Regs.TZSEL. bit .OSHT1 = TZ ENABLE; //TZ1 is a one?shot killer
457 EPwm5Regs.TZCTL. bit .TZA = TZ FORCE LO;
458 EPwm5Regs.TZCTL. bit .TZB = TZ FORCE LO;
459 EPwm5Regs.TZEINT. bit .OST = TZ ENABLE;
460 // EDIS;
461
462 EPwm5Regs.ETSEL. bit .INTEN = 0; // disable INT
463 }
464 void EPwm6Init()
465 {
466
467 // EPwm6Regs.TBPRD = 6000; // Set timer period ?25
kHz
468 EPwm6Regs.TBPRD = 50; // Set timer period ? 3MHz
469 EPwm6Regs.TBPHS. half .TBPHS = 0x0000 ; // Phase is 0
470 EPwm6Regs.TBCTR = 0x0000 ; // Clear counter
471
472
473 // Setup TBCLK
474 EPwm6Regs.TBCTL. bit .CTRMODE = TB COUNT UP; // Count up
475 EPwm6Regs.TBCTL. bit .PHSEN = TB DISABLE; // Disable phase loading
476 EPwm6Regs.TBCTL. bit .HSPCLKDIV = TB DIV1; // Clock ratio to SYSCLKOUT
477 EPwm6Regs.TBCTL. bit .CLKDIV = TB DIV1; // Slow so we can observe on
the scope
98
478
479 // Setup compare
480 EPwm6Regs.CMPA. half .CMPA = 50;
481
482 // Set actions
483 EPwm6Regs.AQCTLA. bit .CAU = AQ SET; // Set PWM6A on Zero
484 EPwm6Regs.AQCTLA. bit .CAD = AQ CLEAR;
485
486 EPwm6Regs.AQCTLB. bit .CAU = AQ CLEAR; // Set PWM6B on Zero
487 EPwm6Regs.AQCTLB. bit .CAD = AQ SET;
488
489 // Active high complementary PWMs ? Setup the deadband
490 EPwm6Regs.DBCTL. bit .OUTMODE = DB DISABLE; //DB FULL ENABLE;
491 EPwm6Regs.DBCTL. bit .POLSEL = DB ACTV HIC;
492 EPwm6Regs.DBCTL. bit .IN MODE = DBA ALL;
493 EPwm6Regs.DBRED = 0;
494 EPwm6Regs.DBFED = 0;
495
496 // Interrupt where we will change the deadband
497 // EPwm6Regs.ETSEL. bit .INTSEL = ET CTR ZERO; // Select INT on Zero
event
498 // EPwm6Regs.ETSEL. bit .INTEN = 1; // Enable INT
499 // EPwm6Regs.ETPS. bit .INTPRD = ET 3RD; // Generate INT on 3rd
event
500 EPwm6Regs.ETSEL. bit .INTEN = 0; // Disable interrupt
generation (EPWMx INT)
501 EPwm6Regs.ETCLR. bit .SOCA = 1; // Clear any existing SOCA flag .
502 EPwm6Regs.ETSEL. bit .SOCAEN = 1; // Enable SOCA pulse
503 EPwm6Regs.ETSEL. bit .SOCASEL = ET CTR PRD; // SOCA when timebase = period
504 EPwm6Regs.ETPS. bit .SOCAPRD = 1; // Every event generates SOCA
505
506
507 }
99
I2CHandler.h
1 #ifndef I2CHANDLER H
2 #define I2CHANDLER H
3
4 #include ?DSP28x Project .h? // Device Headerfile and Examples Include File
5
6 #define I2C PCA0 ADDR 0x60 //0xC0
7 #define I2C PCA1 ADDR 0x61 //0xC1
8 #define I2C PCA2 ADDR 0x62 //0xC2
9 #define I2C PCA3 ADDR 0x63 //0xC3
10
11 #define I2C PCA CTL INPUT 0x00
12 #define I2C PCA CTL PSC0 0x01
13 #define I2C PCA CTL PWM0 0x02
14 #define I2C PCA CTL PSC1 0x03
15 #define I2C PCA CTL PWM1 0x04
16 #define I2C PCA CTL LS0 0x05
17 #define I2C PCA CTL LS1 0x06
18
19 #define I2C PCA CTL AUTO 0x10 ;
20
21 #define LCD OFF 0x00 ;
22 #define LCD ON 0x01 ;
23 #define LCD BLINK1 0x02 ;
24 #define LCD BLINK2 0x03 ;
25
26 #define I2C NUMBYTES 4
27 #define I2C EEPROM HIGH ADDR 0x00
28 #define I2C EEPROM LOW ADDR 0x30
29
30 #define I2C TX 0x00
31 #define I2C RX 0x01
32
33 #define I2CBUFFSIZE 16
34 //extern Uint16 I2CTXFlag;
35 //extern Uint16 I2CRXFlag;
36
37 struct I2C MSG{
38 Uint16 SlaveAddress ;
39 Uint16 CommandByte;
40 Uint16 MsgStatus ;
41 Uint16 NumOfBytes;
42 // void (?CallbackFunc)( struct I2C MSG? msg) ;
43 Uint16 MsgBuffer [8]; //Should not need full buffer size
44 // Uint16 MsgBuffer [I2C MAX BUFFER SIZE];
45 };
46
47 extern struct I2C MSG I2cMsgOut1;
48
49 extern struct I2C MSG I2cMsgIn1 ;
50
51 void I2CA Init () ;
52 //void InitI2CModule(void) ;
100
53 void InitPCAs() ;
54 Uint16 PollButtons () ; //Determine which phases are inserted into the carrier .
55 Uint16 PollPhases () ; //Determine which phases are inserted into the carrier .
56 void SetPCA1Status(Uint16 value) ; //Set PCA1 LED Status . 2 bits per LED:
57 void SetPCA3Status(Uint16 value) ; //Set PCA1 LED Status . 2 bits per LED:
58
59 Uint16 I2CA WriteData(struct I2C MSG ?msg) ;
60 Uint16 I2CA ReadData(struct I2C MSG ?msg) ;
61 Uint16 I2CA ReadDataBlocking(struct I2C MSG ?msg) ;
62 //Uint16 I2CA ReadDataBlocking( struct I2C MSG ?msg) ;
63 interrupt void i2c int1a isr (void) ;
64
65
66 //Uint16 I2CA WriteDataAsync( struct I2C MSG ?msg) ;
67
68 #endif /?I2CHANDLER H ?/
101
I2CHandler.c
1 #include ?I2CHandler .h?
2 #include ?SerialHandler .h?
3 #include ?DSP28x Project .h? // Device Headerfile and Examples Include File
4 //
5 //
6 struct I2C MSG I2cMsgOut1={I2C PCA1 ADDR,
7 I2C PCA CTL LS0,
8 1,
9 0x42};
10
11 struct I2C MSG I2cMsgIn1={ I2C PCA2 ADDR,
12 I2C PCA CTL INPUT,
13 1};
14 //
15 //Uint16 i2cMode = 0;
16 //
17 struct I2C MSG I2CBuffer [I2CBUFFSIZE];
18 struct I2C MSG ?I2CFIFOFront;
19 struct I2C MSG ?I2CFIFOBack;
20 struct I2C MSG ?I2CBufferEnd ;
21 //
22 //
23 ////Uint16 I2CTXFlag;
24 ////Uint16 I2CRXFlag;
25 //
26 //
27 ////void InitI2CModule(void){
28 //// // Initialize I2C
29 //// I2caRegs .I2CSAR = I2C PCA0 ADDR; // Slave address ? EEPROM control
code
30 ////
31 //// #if (CPU FRQ 150MHZ) // Default ? For 150MHz SYSCLKOUT
32 //// I2caRegs .I2CPSC. all = 14; // Prescaler ? need 7?12 Mhz on module
clk (150/15 = 10MHz)
33 //// #endif
34 //// #if (CPU FRQ 100MHZ) // For 100 MHz SYSCLKOUT
35 //// I2caRegs .I2CPSC. all = 9; // Prescaler ? need 7?12 Mhz on module
clk (100/10 = 10MHz)
36 //// #endif
37 ////
38 ////// I2caRegs .I2CCLKL = 10; // NOTE: must be non zero
39 ////// I2caRegs .I2CCLKH = 5; // NOTE: must be non zero
40 //// I2caRegs .I2CCLKL = 100; // NOTE: must be non zero
41 //// I2caRegs .I2CCLKH = 100; // NOTE: must be non zero
42 //// I2caRegs .I2CIER. all = 0x24 ; // Enable SCD & ARDY interrupts
43 ////
44 //// I2caRegs .I2CFFTX. all = 0x6000 ; // Enable FIFO mode and TXFIFO
45 //// I2caRegs .I2CFFRX. all = 0x2040 ; // Enable RXFIFO, clear RXFFINT,
46 ////
47 //// I2caRegs .I2CMDR. all = 0x0020 ; // Take I2C out of reset
48 //// // Stop I2C when suspended
49 //// i2cMode = I2C TX;
102
50 //// return ;
51 ////}
52 //
53 void InitPCAs(){
54 Uint16 result ;
55 I2cMsgOut1. SlaveAddress = I2C PCA1 ADDR;
56 I2cMsgOut1.CommandByte = I2C PCA CTL PSC0 | I2C PCA CTL AUTO;
57 I2cMsgOut1. MsgBuffer [0] = 0x03 ; //PCS0 ? 40Hz
58 I2cMsgOut1. MsgBuffer [1] = 0x30 ; //PWM0
59 I2cMsgOut1. MsgBuffer [2] = 0x97 ; //PCS1 ?half a second
60 I2cMsgOut1. MsgBuffer [3] = 0x80 ; //PWM1
61 I2cMsgOut1. MsgBuffer [4] = 0x00 ; //LS0
62 I2cMsgOut1. MsgBuffer [5] = 0x00 ; //LS1
63 I2cMsgOut1.NumOfBytes = 6;
64 do{
65 result = I2CA WriteData(&I2cMsgOut1) ;
66 }while( result != I2C SUCCESS) ;
67 I2cMsgOut1. SlaveAddress = I2C PCA3 ADDR;
68 do{
69 result = I2CA WriteData(&I2cMsgOut1) ;
70 }while( result != I2C SUCCESS) ;
71 }
72
73
74 Uint16 PollPhases (){
75 Uint16 result ;
76 I2cMsgIn1 . SlaveAddress = I2C PCA0 ADDR;
77 I2cMsgIn1 .CommandByte = I2C PCA CTL INPUT;
78 I2cMsgIn1 .NumOfBytes = 1;
79 do{
80 result = I2CA ReadDataBlocking(&I2cMsgIn1) ;
81 }while( result != I2C SUCCESS) ;
82 return I2cMsgIn1 . MsgBuffer [1];
83 }
84
85 Uint16 PollButtons (){
86 Uint16 result ;
87 I2cMsgIn1 . SlaveAddress = I2C PCA2 ADDR;
88 I2cMsgIn1 .CommandByte = I2C PCA CTL INPUT;
89 I2cMsgIn1 .NumOfBytes = 1;
90 do{
91 result = I2CA ReadDataBlocking(&I2cMsgIn1) ;
92 }while( result != I2C SUCCESS) ;
93 return I2cMsgIn1 . MsgBuffer [1];
94 }
95
96 void SetPCA1Status(Uint16 value){
97 Uint16 retval = 0;
98 I2cMsgOut1. SlaveAddress = I2C PCA1 ADDR;
99 I2cMsgOut1.CommandByte = I2C PCA CTL LS0 | I2C PCA CTL AUTO;
100 I2cMsgOut1. MsgBuffer [0] = value & 0x00FF;
101 I2cMsgOut1. MsgBuffer [1] = (value>>8) & 0x00FF;
102 I2cMsgOut1.NumOfBytes = 2;
103 do{
103
104 retval = I2CA WriteData(&I2cMsgOut1) ;
105 }
106 while ( retval != I2C SUCCESS) ;
107 if ( retval != I2C SUCCESS){
108 char? msg;
109 msg = ?Error in Writing I2C SetPCA1\0?;
110 scia msg async (msg) ;
111 }
112 }
113 void SetPCA3Status(Uint16 value){
114 Uint16 retval = 0;
115 I2cMsgOut1. SlaveAddress = I2C PCA3 ADDR;
116 I2cMsgOut1.CommandByte = I2C PCA CTL LS0 | I2C PCA CTL AUTO;
117 I2cMsgOut1. MsgBuffer [0] = value & 0x00FF;
118 I2cMsgOut1. MsgBuffer [1] = (value>>8) & 0x00FF;
119 I2cMsgOut1.NumOfBytes = 2;
120 do{
121 retval = I2CA WriteData(&I2cMsgOut1) ;
122 }
123 while ( retval != I2C SUCCESS) ;
124 if ( retval != I2C SUCCESS){
125 char? msg;
126 msg = ?Error in Writing I2C SetPCA1\0?;
127 scia msg async (msg) ;
128 }
129 }
130
131 void I2CA Init(void)
132 {
133 // Initialize I2C
134 I2caRegs .I2CSAR = I2C PCA0 ADDR; // Slave address ? EEPROM control code
135
136 #if (CPU FRQ 150MHZ) // Default ? For 150MHz SYSCLKOUT
137 I2caRegs .I2CPSC. all = 14; // Prescaler ? need 7?12 Mhz on module clk
(150/15 = 10MHz)
138 #endif
139 #if (CPU FRQ 100MHZ) // For 100 MHz SYSCLKOUT
140 I2caRegs .I2CPSC. all = 9; // Prescaler ? need 7?12 Mhz on module clk
(100/10 = 10MHz)
141 #endif
142
143 // I2caRegs .I2CCLKL = 10; // NOTE: must be non zero
144 // I2caRegs .I2CCLKH = 5; // NOTE: must be non zero
145 I2caRegs .I2CCLKL = 50; // NOTE: must be non zero
146 I2caRegs .I2CCLKH = 50; // NOTE: must be non zero
147 I2caRegs .I2CIER. all = 0x24 ; // Enable SCD & ARDY interrupts
148
149 I2caRegs .I2CFFTX. all = 0x6000 ; // Enable FIFO mode and TXFIFO
150 I2caRegs .I2CFFRX. all = 0x2040 ; // Enable RXFIFO, clear RXFFINT,
151
152 I2caRegs .I2CMDR. all = 0x0020 ; // Take I2C out of reset
153 // Stop I2C when suspended
154
155 //// I2CBuffer [I2CBUFFSIZE];
104
156 // I2CFIFOFront = I2CBuffer ;
157 // I2CFIFOBack = I2CBuffer ;
158 //// I2CBufferEnd = I2CBuffer + sizeof ( struct I2C MSG)?(I2CBUFFSIZE?1);
159 // I2CBufferEnd = &(I2CBuffer [I2CBUFFSIZE?1]) ;
160 return;
161 }
162
163 Uint16 I2CA WriteData(struct I2C MSG ?msg)
164 {
165 Uint16 i ;
166
167 // Wait until the STP bit is cleared from any previous master communication
.
168 // Clearing of this bit by the module is delayed until after the SCD bit is
169 // set . If this bit is not checked prior to initiating a new message , the
170 // I2C could get confused .
171 if (I2caRegs .I2CMDR. bit .STP == 1)
172 {
173 return I2C STP NOT READY ERROR;
174 }
175
176 // Setup slave address
177 I2caRegs .I2CSAR = msg?>SlaveAddress ;
178 //I2caRegs .I2CSAR = I2C PCA1 ADDR;
179
180 // Check if bus busy
181 if (I2caRegs .I2CSTR. bit .BB == 1)
182 {
183 return I2C BUS BUSY ERROR;
184 }
185
186 // Setup number of bytes to send
187 // MsgBuffer + Address
188 I2caRegs .I2CCNT = msg?>NumOfBytes+1;
189 //I2caRegs .I2CCNT = 1; //send control byte and data byte .
190
191 // Setup data to send
192 I2caRegs .I2CDXR = msg?>CommandByte;
193 // I2caRegs .I2CDXR = msg?>MemoryLowAddr;
194 //// for ( i=0; i<msg?>NumOfBytes?2; i++)
195 for ( i=0; i<msg?>NumOfBytes; i++)
196 {
197 I2caRegs .I2CDXR = ?(msg?>MsgBuffer+i ) ;
198 }
199 // I2caRegs .I2CDXR = I2C PCA CTL LS0;
200 // I2caRegs .I2CDXR = 0x42 ;
201
202 // Send start as master transmitter
203 I2caRegs .I2CMDR. all = 0x6E20;
204
205 return I2C SUCCESS;
206 }
207
208 Uint16 I2CA ReadData(struct I2C MSG ?msg)
105
209 {
210 // Wait until the STP bit is cleared from any previous master communication
.
211 // Clearing of this bit by the module is delayed until after the SCD bit is
212 // set . If this bit is not checked prior to initiating a new message , the
213 // I2C could get confused .
214 if (I2caRegs .I2CMDR. bit .STP == 1)
215 {
216 return I2C STP NOT READY ERROR;
217 }
218
219 I2caRegs .I2CSAR = msg?>SlaveAddress ;
220
221 // I2caRegs .I2CCNT = 2;
222 // I2caRegs .I2CDXR = msg?>MemoryHighAddr;
223 // I2caRegs .I2CDXR = msg?>MemoryLowAddr;
224
225 // I2caRegs .I2CDXR = msg?>MemoryHighAddr;
226 I2caRegs .I2CMDR. all = 0x2620 ; // Send data to setup EEPROM address
227
228 // else if (msg?>MsgStatus == I2C MSGSTAT RESTART)
229 {
230 I2caRegs .I2CCNT = msg?>NumOfBytes; // Setup how many bytes to expect
231 // I2caRegs .I2CMDR. all = 0x2C20; // Send restart as master receiver
232 I2caRegs .I2CMDR. all = 0xAC20; // Send restart as master receiver ,
enable NACK.
233 }
234
235 return I2C SUCCESS;
236 }
237
238
239 Uint16 I2CA ReadDataBlocking(struct I2C MSG ?msg)
240 {
241 // Wait until the STP bit is cleared from any previous master communication
.
242 // Clearing of this bit by the module is delayed until after the SCD bit is
243 // set . If this bit is not checked prior to initiating a new message , the
244 // I2C could get confused .
245 if (I2caRegs .I2CMDR. bit .STP == 1)
246 {
247 return I2C STP NOT READY ERROR;
248 }
249
250 I2caRegs .I2CSAR = msg?>SlaveAddress ;
251
252 // I2caRegs .I2CCNT = 2;
253 // I2caRegs .I2CDXR = msg?>MemoryHighAddr;
254 // I2caRegs .I2CDXR = msg?>MemoryLowAddr;
255
256 // I2caRegs .I2CDXR = msg?>MemoryHighAddr;
257 I2caRegs .I2CMDR. all = 0x2620 ; // Send data to setup EEPROM address
258
259 // else if (msg?>MsgStatus == I2C MSGSTAT RESTART)
106
260 {
261 I2caRegs .I2CCNT = msg?>NumOfBytes; // Setup how many bytes to expect
262 // I2caRegs .I2CMDR. all = 0x2C20; // Send restart as master receiver
263 I2caRegs .I2CMDR. all = 0xAC20; // Send restart as master receiver ,
enable NACK.
264 }
265 while(I2caRegs .I2CSTR. bit .NACKSNT == 0){
266 ;
267 }
268 I2cMsgIn1 . MsgBuffer [1] = I2caRegs .I2CDRR;
269 I2caRegs .I2CSTR. bit .NACKSNT = 1;
270
271
272 return I2C SUCCESS;
273 }
274
275
276 interrupt void i2c int1a isr (void) // I2C?A
277 {
278 Uint16 IntSource ;
279 // Uint16 res ;
280
281 // Read interrupt source
282 IntSource = I2caRegs .I2CISRC. all ;
283
284 // Interrupt source = stop condition detected
285 switch( IntSource ){
286 case I2C SCD ISRC: // stop condition detected
287 // if (I2CFIFOFront != I2CFIFOBack) // Data in I2CBuffer
288 // { //try to send out data in our queue .
289 // res = I2CA WriteData(I2CFIFOFront) ;
290 // if ( res == I2C SUCCESS){
291 // I2CFIFOFront++;
292 // if (I2CFIFOFront > I2CBufferEnd)
293 // I2CFIFOFront = I2CBuffer ;
294 // }
295 // I2caRegs .I2CFFTX. bit .TXFFINTCLR = 1;
296 // break ;
297 // }
298 //nothing in queue , must be receiving data :
299 case I2C RX ISRC:
300 I2cMsgIn1 . MsgBuffer [0] = I2caRegs .I2CCNT;
301 I2cMsgIn1 . MsgBuffer [1] = I2caRegs .I2CDRR;
302 break;
303 case I2C ARDY ISRC: // register access ready
304 break;
305 case I2C NO ISRC: //No Interrupt source
306 break;
307 case I2C ARB ISRC:
308 break; // Arbitration lost
309 case I2C NACK ISRC: // No?ack condition detected
310 break;
311 case I2C TX ISRC: // Transmit data ready
312 break;
107
313 case I2C AAS ISRC: // Addressed as slave
314 break;
315 default :
316 break;
317 }
318 // Enable future I2C (PIE Group 8) interrupts
319 PieCtrlRegs .PIEACK. all = PIEACK GROUP8;
320 }
321 //
322 //Uint16 I2CA WriteDataAsync( struct I2C MSG ?msg){
323 // ?I2CFIFOBack++ = ?msg; //Possibly very expensive .
324 // if (I2CFIFOBack > I2CBufferEnd)
325 // I2CFIFOBack = I2CBuffer ;
326 // if (I2caRegs .I2CFFTX. bit .TXFFIENA == 0){
327 // I2CA WriteData(I2CFIFOFront) ;
328 // I2caRegs .I2CFFTX. bit .TXFFIENA = 1;
329 // }
330 // return I2C SUCCESS;
331 //}
332 //
108
DSP28x Project.h
1
2 // TI File $Revision : /main/1 $
3 // Checkin $Date: April 22, 2008 14:35:56 $
4 //###########################################################################
5 //
6 // FILE: DSP28x Project .h
7 //
8 // TITLE: DSP28x Project Headerfile and Examples Include File
9 //
10 //###########################################################################
11 // $TI Release : 2833x/2823x Header Files V1.32 $
12 // $Release Date: June 28, 2010 $
13 //###########################################################################
14
15 #ifndef DSP28x PROJECT H
16 #define DSP28x PROJECT H
17
18 #include ?DSP2833x Device .h? // DSP2833x Headerfile Include File
19 #include ?DSP2833x Examples.h? // DSP2833x Examples Include File
20
21 #endif // end of DSP28x PROJECT H definition
109
DSP2833x Device.h
1 // TI File $Revision : /main/5 $
2 // Checkin $Date: January 22, 2008 16:55:35 $
3 //###########################################################################
4 //
5 // FILE: DSP2833x Device .h
6 //
7 // TITLE: DSP2833x Device Definitions .
8 //
9 //###########################################################################
10 // $TI Release : 2833x/2823x Header Files V1.32 $
11 // $Release Date: June 28, 2010 $
12 //###########################################################################
13
14 #ifndef DSP2833x DEVICE H
15 #define DSP2833x DEVICE H
16
17
18 #ifdef cplusplus
19 extern ?C? {
20 #endif
21
22
23 #define TARGET 1
24 //???????????????????????????????????????????????????????????????????????????
25 // User To Select Target Device :
26
27 #define DSP28 28335 TARGET // Selects ?28335/?28235
28 #define DSP28 28334 0 // Selects ?28334/?28234
29 #define DSP28 28332 0 // Selects ?28332/?28232
30
31
32 //???????????????????????????????????????????????????????????????????????????
33 // Common CPU Definitions :
34 //
35
36 extern cregister volatile unsigned int IFR;
37 extern cregister volatile unsigned int IER;
38
39 #define EINT asm(? clrc INTM?)
40 #define DINT asm(? setc INTM?)
41 #define ERTM asm(? clrc DBGM?)
42 #define DRTM asm(? setc DBGM?)
43 #define EALLOW asm(? EALLOW?)
44 #define EDIS asm(? EDIS?)
45 #define ESTOP0 asm(? ESTOP0?)
46
47 #define M INT1 0x0001
48 #define M INT2 0x0002
49 #define M INT3 0x0004
50 #define M INT4 0x0008
51 #define M INT5 0x0010
52 #define M INT6 0x0020
110
53 #define M INT7 0x0040
54 #define M INT8 0x0080
55 #define M INT9 0x0100
56 #define M INT10 0x0200
57 #define M INT11 0x0400
58 #define M INT12 0x0800
59 #define M INT13 0x1000
60 #define M INT14 0x2000
61 #define MDLOG 0x4000
62 #define M RTOS 0x8000
63
64 #define BIT0 0x0001
65 #define BIT1 0x0002
66 #define BIT2 0x0004
67 #define BIT3 0x0008
68 #define BIT4 0x0010
69 #define BIT5 0x0020
70 #define BIT6 0x0040
71 #define BIT7 0x0080
72 #define BIT8 0x0100
73 #define BIT9 0x0200
74 #define BIT10 0x0400
75 #define BIT11 0x0800
76 #define BIT12 0x1000
77 #define BIT13 0x2000
78 #define BIT14 0x4000
79 #define BIT15 0x8000
80
81
82
83 //???????????????????????????????????????????????????????????????????????????
84 // For Portability , User Is Recommended To Use Following Data Type Size
85 // Definitions For 16?bit and 32?Bit Signed/Unsigned Integers :
86 //
87
88 #ifndef DSP28 DATA TYPES
89 #define DSP28 DATA TYPES
90 typedef int int16 ;
91 typedef long int32 ;
92 typedef long long int64 ;
93 typedef unsigned int Uint16 ;
94 typedef unsigned long Uint32 ;
95 typedef unsigned long long Uint64 ;
96 typedef float float32 ;
97 typedef long double float64 ;
98 #endif
99
100
101 //???????????????????????????????????????????????????????????????????????????
102 // Include All Peripheral Header Files :
103 //
104
105 #include ?DSP2833x Adc.h? // ADC Registers
106 #include ?DSP2833x DevEmu.h? // Device Emulation Registers
111
107 #include ?DSP2833x CpuTimers.h? // 32?bit CPU Timers
108 #include ?DSP2833x ECan.h? // Enhanced eCAN Registers
109 #include ?DSP2833x ECap.h? // Enhanced Capture
110 #include ?DSP2833x DMA.h? // DMA Registers
111 #include ?DSP2833x EPwm.h? // Enhanced PWM
112 #include ?DSP2833x EQep.h? // Enhanced QEP
113 #include ?DSP2833x Gpio.h? // General Purpose I/O Registers
114 #include ?DSP2833x I2c .h? // I2C Registers
115 #include ?DSP2833x McBSP.h? // McBSP
116 #include ?DSP2833x PieCtrl .h? // PIE Control Registers
117 #include ?DSP2833x PieVect .h? // PIE Vector Table
118 #include ?DSP2833x Spi .h? // SPI Registers
119 #include ?DSP2833x Sci .h? // SCI Registers
120 #include ?DSP2833x SysCtrl .h? // System Control/Power Modes
121 #include ?DSP2833x XIntrupt .h? // External Interrupts
122 #include ?DSP2833x Xintf .h? // XINTF External Interface
123
124 #if DSP28 28335
125 #define DSP28 EPWM1 1
126 #define DSP28 EPWM2 1
127 #define DSP28 EPWM3 1
128 #define DSP28 EPWM4 1
129 #define DSP28 EPWM5 1
130 #define DSP28 EPWM6 1
131 #define DSP28 ECAP1 1
132 #define DSP28 ECAP2 1
133 #define DSP28 ECAP3 1
134 #define DSP28 ECAP4 1
135 #define DSP28 ECAP5 1
136 #define DSP28 ECAP6 1
137 #define DSP28 EQEP1 1
138 #define DSP28 EQEP2 1
139 #define DSP28 ECANA 1
140 #define DSP28 ECANB 1
141 #define DSP28 MCBSPA 1
142 #define DSP28 MCBSPB 1
143 #define DSP28 SPIA 1
144 #define DSP28 SCIA 1
145 #define DSP28 SCIB 1
146 #define DSP28 SCIC 1
147 #define DSP28 I2CA 1
148 #endif // end DSP28 28335
149
150 #if DSP28 28334
151 #define DSP28 EPWM1 1
152 #define DSP28 EPWM2 1
153 #define DSP28 EPWM3 1
154 #define DSP28 EPWM4 1
155 #define DSP28 EPWM5 1
156 #define DSP28 EPWM6 1
157 #define DSP28 ECAP1 1
158 #define DSP28 ECAP2 1
159 #define DSP28 ECAP3 1
160 #define DSP28 ECAP4 1
112
161 #define DSP28 ECAP5 0
162 #define DSP28 ECAP6 0
163 #define DSP28 EQEP1 1
164 #define DSP28 EQEP2 1
165 #define DSP28 ECANA 1
166 #define DSP28 ECANB 1
167 #define DSP28 MCBSPA 1
168 #define DSP28 MCBSPB 1
169 #define DSP28 SPIA 1
170 #define DSP28 SCIA 1
171 #define DSP28 SCIB 1
172 #define DSP28 SCIC 1
173 #define DSP28 I2CA 1
174 #endif // end DSP28 28334
175
176 #if DSP28 28332
177 #define DSP28 EPWM1 1
178 #define DSP28 EPWM2 1
179 #define DSP28 EPWM3 1
180 #define DSP28 EPWM4 1
181 #define DSP28 EPWM5 1
182 #define DSP28 EPWM6 1
183 #define DSP28 ECAP1 1
184 #define DSP28 ECAP2 1
185 #define DSP28 ECAP3 1
186 #define DSP28 ECAP4 1
187 #define DSP28 ECAP5 0
188 #define DSP28 ECAP6 0
189 #define DSP28 EQEP1 1
190 #define DSP28 EQEP2 1
191 #define DSP28 ECANA 1
192 #define DSP28 ECANB 1
193 #define DSP28 MCBSPA 1
194 #define DSP28 MCBSPB 0
195 #define DSP28 SPIA 1
196 #define DSP28 SCIA 1
197 #define DSP28 SCIB 1
198 #define DSP28 SCIC 0
199 #define DSP28 I2CA 1
200 #endif // end DSP28 28332
201
202 #ifdef cplusplus
203 }
204 #endif /? extern ?C? ?/
205
206 #endif // end of DSP2833x DEVICE H definition
207
208
209 //===========================================================================
210 // End of file .
211 //===========================================================================
113
Appendix B
Source Code for Single Phase Controller:
The single phase controller utilizes the same files as the two phase controller, with only
a different main.c, shown below.
main.c
1 //###########################################################################
2 //
3 // FILE: main.c
4 //
5 // TITLE: For use with Buck Carrier board v1 and buck daughter boards v3+.
6 //
7 // ASSUMPTIONS:
8 //
9 // This program requires the DSP2833x header files .
10 // As supplied , this project is configured for ?boot to SARAM? operation .
11 //
12 // Connect the SCI?A port to a PC via a transciever and cable .
13 // The PC application ? hypterterminal ? can be used to view the data
14 // from the SCI and to send information to the SCI. Characters recieved
15 // by the SCI port are sent back to the host .
16 //
17 // As supplied , this project is configured for ?boot to SARAM?
18 // operation . The 2833x Boot Mode table is shown below .
19 // For information on configuring the boot mode of an eZdsp ,
20 // please refer to the documentation included with the eZdsp ,
21 //
22 // $Boot Table :
23 //
24 // GPIO87 GPIO86 GPIO85 GPIO84
25 // XA15 XA14 XA13 XA12
26 // PU PU PU PU
27 // ==========================================
28 // 1 1 1 1 Jump to Flash
29 // 1 1 1 0 SCI?A boot
30 // 1 1 0 1 SPI?A boot
31 // 1 1 0 0 I2C?A boot
32 // 1 0 1 1 eCAN?A boot
33 // 1 0 1 0 McBSP?A boot
34 // 1 0 0 1 Jump to XINTF x16
35 // 1 0 0 0 Jump to XINTF x32
36 // 0 1 1 1 Jump to OTP
37 // 0 1 1 0 Parallel GPIO I/O boot
114
38 // 0 1 0 1 Parallel XINTF boot
39 // 0 1 0 0 Jump to SARAM <? ?boot to
SARAM?
40 // 0 0 1 1 Branch to check boot mode
41 // 0 0 1 0 Boot to flash , bypass ADC cal
42 // 0 0 0 1 Boot to SARAM, bypass ADC cal
43 // 0 0 0 0 Boot to SCI?A, bypass ADC cal
44 // Boot Table End$
45 //
46 // DESCRIPTION:
47 // Communicates with the computer via serial port 9600 baud , 8 data ,
48 // 1 stop , no parity .
49
50 // As is , the program configures SCI?A for 9600 baud with
51 // SYSCLKOUT = 150MHz and LSPCLK = 37.5 MHz
52 //###########################################################################
53 #include ?SerialHandler .h?
54 #include ?ADCHandler.h?
55 #include ?PWMHandler.h?
56 #include ?TimerHandler .h?
57 #include ?I2CHandler .h?
58 #include ?Globals .h?
59 #include ?controller .h?
60 #include ?DSP28x Project .h? // Device Headerfile and Examples Include File
61
62
63 //Uint16 LoopCount;
64 //Uint16 ErrorCount ;
65 //Uint16 ConversionCount ;
66 //Uint16 XmitFlag ;
67 Uint16 PhaseStatus ;
68 Uint16 PhaseCount ;
69 union LEDS LEDStatus;
70 union LEDS LEDStatus2;
71
72
73 union MAINFLAGS MainFlags ;
74 union BUTTONS ButtonStatus ;
75
76 int32 a1 ,a2 ,a3 ,a4 ,a5 , S, S1old , S2old ,S1 ,S2 ,dS1 ,dS2 , xint ;
77 int32 u1 , u1old1 , u1old2 ;
78 const int32 alpha1 = 10;//100;//?2;
79 const int32 alpha2 = ?2;//4;
80 const int32 alpha3 = 1;//?2;
81 const int32 alpha4 = 0;//10;//10;
82 const int32 alpha5 = 0;//10;//10;//?1;
83 const int32 alpha6 = 0;//1;//1;//?1;
84 const int32 alpha7 = 0;//2;//2;//?1;
85 const int32 alphaC0 = 0;//?200;//?10;
86 const int32 alphaC1 = 0;//?200;//?10;
87 const int16 Vref = 1160;
88 const int32 kappa = 80;
89 const int32 negkappa = ?80;
90 const int32 taud1 = 0;//10;
115
91 const int32 taud2 = 0;//5;
92
93 int32 adcbuffer [32];
94
95 #pragma DATA SECTION(DMABuf1,?DMARAML4?) ;
96 volatile Uint16 DMABuf1[40];
97
98 volatile Uint16 ?DMADest;
99 volatile Uint16 ?DMASource;
100
101 void main(void)
102 {
103 Uint16 i , i2ccounter , idx ;
104 int32 ramp1 ,ramp2;
105 int32 adcV1 ,adcV2 , adcI1 , adcI2 ;
106 int32 x6 ,x7;
107 int32? adcP;
108 Uint32 c0 , c1 ;
109 // Uint16 tmp;
110
111
112 char ?msg;
113
114 EALLOW;
115
116 MainFlags . all = 0;
117
118 // Step 1. Initialize System Control :
119 // PLL, WatchDog, enable Peripheral Clocks
120 // This example function is found in the DSP2833x SysCtrl .c file .
121 InitSysCtrl () ;
122
123 // Step 2. Initalize GPIO:
124 // This example function is found in the DSP2833x Gpio.c file and
125 // illustrates how to set the GPIO to it ?s default state .
126 // InitGpio () ; Skipped for this example
127
128 // For this example , only init the pins for the SCI?A port .
129 // This function is found in the DSP2833x Sci .c file .
130 InitSciaGpio () ;
131 // InitI2CGpio () ;
132
133 // Specific clock setting for this example :
134 EALLOW;
135 SysCtrlRegs .HISPCP. all = ADCMODCLK; // HSPCLK = SYSCLKOUT/ADCMODCLK
136 //ADC clock now = 25MHz.
137 // EDIS;
138
139 // Step 3. Clear all interrupts and initialize PIE vector table :
140 // Disable CPU interrupts
141 DINT;
142
143 // Initialize PIE control registers to their default state .
144 // The default state is all PIE interrupts disabled and flags
116
145 // are cleared .
146 // This function is found in the DSP2833x PieCtrl .c file .
147 InitPieCtrl () ;
148
149 // Disable CPU interrupts and clear all CPU interrupt flags :
150 IER = 0x0000 ;
151 IFR = 0x0000 ;
152
153 // Initialize the PIE vector table with pointers to the shell Interrupt
154 // Service Routines (ISR) .
155 // This will populate the entire table , even if the interrupt
156 // is not used in this example . This is useful for debug purposes .
157 // The shell ISR routines are found in DSP2833x DefaultIsr .c.
158 // This function is found in DSP2833x PieVect .c.
159 InitPieVectTable () ;
160
161
162 // Interrupts that are used in this example are re?mapped to
163 // ISR functions found within this file .
164 EALLOW; // This is needed to write to EALLOW protected register
165 // PieVectTable .ADCINT = &adc isr ;
166 // PieVectTable .SCIRXINTA = &scirxa isr ;
167 // PieVectTable .SCITXINTA = &scitxa isr ;
168 // PieVectTable .TINT0 = &timer0 isr ;
169 // PieVectTable .I2CINT1A = &i2c int1a isr ;
170 // PieVectTable .EPWM1 INT = &epwm1 isr ;
171 // PieVectTable .EPWM2 INT = &epwm2 isr ;
172 // PieVectTable .EPWM3 INT = &epwm3 isr ;
173 // EDIS; // This is needed to disable write to EALLOW protected
registers
174
175 EALLOW;
176 SysCtrlRegs .PCLKCR0. bit .TBCLKSYNC = 0;
177 // EDIS;
178
179 //InitPwmModule() ;
180 // InitTimerModule () ;
181 // InitI2CModule () ;
182 // I2CA Init () ;
183 InitPwmModule() ;
184
185 EALLOW;
186 SysCtrlRegs .PCLKCR0. bit .TBCLKSYNC = 1;
187 // EDIS;
188
189 InitADCModule() ;
190
191 // PieCtrlRegs .PIEIER1. bit .INTx7 = 1; // Timer0 Interrupt
192 // PieCtrlRegs .PIEIER9. bit .INTx1 = 1; // Enable SCIRXINTA in PIE
193 // PieCtrlRegs .PIEIER9. bit .INTx2 = 1; // Enable SCITXINTA in PIE
194 // PieCtrlRegs .PIEIER1. bit .INTx6 = 1; // Enable ADCINT in PIE
195 // PieCtrlRegs .PIEIER3. bit .INTx1 = 1; // Enable EPWM1INT in PIE
196 // PieCtrlRegs .PIEIER3. bit .INTx2 = 1; // Enable EPWM2INT in PIE
197 // PieCtrlRegs .PIEIER3. bit .INTx3 = 1; // Enable EPWM3INT in PIE
117
198 // PieCtrlRegs .PIEIER8. bit .INTx1 = 1; // Enable I2C in PIE
199
200 // IER |= M INT1; // Enable CPU Interrupt block 1 ? ADC, Timer0
201 // IER |= M INT3; // Enable CPU Interrupt block 3 ? EPWM
202 // IER |= M INT8; // Enable CPU Interrupt block 8 ? I2C
203 // IER |= M INT9; // Enable CPU Interrupt block 9 ? SCI
204 EINT; // Enable Global interrupt INTM
205 ERTM; // Enable Global realtime interrupt DBGM
206
207
208 // Step 5. User specific code :
209 // LoopCount = 0;
210 // ErrorCount = 0;
211 // ConversionCount = 0;
212 // XmitFlag = 0;
213 PhaseStatus = 0;
214 PhaseCount = 0;
215 for ( i=0; i<BUF SIZE; i++)
216 {
217 SampleTable [ i ] = 0;
218 }
219
220
221
222 scia fifo init async () ; // Initialize the SCI FIFO
223 scia echoback init () ; // Initalize SCI for echoback
224
225 // Kill all PWMs initially .
226 EALLOW;
227 EPwm1Regs.TZFRC. bit .OST = 1; // Kill PWM1
228 EPwm2Regs.TZFRC. bit .OST = 1; // Kill PWM2
229 EPwm3Regs.TZFRC. bit .OST = 1; // Kill PWM3
230 EPwm4Regs.TZFRC. bit .OST = 1; // Kill PWM3
231 EPwm5Regs.TZFRC. bit .OST = 1; // Kill PWM3
232
233
234 msg = ?\r\nWelcome to PowerControl ! \r\nHopefully this controller will
work!\ r\n\0?;
235 scia msg (msg) ;
236
237 //Configure GPIOs
238 GpioCtrlRegs .GPAPUD. bit .GPIO0 = 0; // Enable pull?up on GPIO0
239 GpioCtrlRegs .GPAPUD. bit .GPIO1 = 0; // Enable pull?up on GPIO1
240 GpioCtrlRegs .GPAPUD. bit .GPIO2 = 0; // Enable pull?up on GPIO2
241 GpioCtrlRegs .GPAPUD. bit .GPIO3 = 0; // Enable pull?up on GPIO3
242 GpioCtrlRegs .GPAPUD. bit .GPIO4 = 0;
243 GpioCtrlRegs .GPAPUD. bit .GPIO6 = 0;
244
245 GpioCtrlRegs .GPADIR. bit .GPIO0 = 1; // Set as output
246 GpioCtrlRegs .GPADIR. bit .GPIO1 = 1; // Set as output
247 GpioCtrlRegs .GPADIR. bit .GPIO2 = 1; // Set as output
248 GpioCtrlRegs .GPADIR. bit .GPIO3 = 1; // Set as output
249 GpioCtrlRegs .GPADIR. bit .GPIO4 = 1; // Set as output
250 GpioCtrlRegs .GPADIR. bit .GPIO6 = 1; // Set as output
118
251
252
253 GpioDataRegs .GPACLEAR. all = 0x0F;
254
255 GpioCtrlRegs .GPAMUX1. bit .GPIO0 = 0; // Configure GPIO0 as GPIO //EPWM1A
256 GpioCtrlRegs .GPAMUX1. bit .GPIO1 = 0; // Configure GPIO1 as GPIO //EPWM1B
257 GpioCtrlRegs .GPAMUX1. bit .GPIO2 = 0; // Configure GPIO2 as GPIO //EPWM1A
258 GpioCtrlRegs .GPAMUX1. bit .GPIO3 = 0; // Configure GPIO3 as GPIO //EPWM1B
259 GpioCtrlRegs .GPAMUX1. bit .GPIO4 = 0;
260 GpioCtrlRegs .GPAMUX1. bit .GPIO6 = 0;
261
262 // Start SEQ1
263 AdcRegs.ADCTRL2. all = 0x2000 ;
264
265
266 idx = 9;
267 xint = 0;
268 S1old = 0;
269 S2old = 0;
270 dS1 = 0;
271 dS2 = 0;
272 u1old1 = 0;
273 u1old2 = 0;
274 S1 = 0;
275 S2 = 0;
276 ramp1 = 0;
277 ramp2 = 100;
278 adcV1 = 0;
279 adcV2 = 0;
280 adcI1 = 0;
281 adcI2 = 0;
282 x6 = 0;
283 x7 = 0;
284 c0 = 0;
285 c1 = 0;
286 while(1) // Infinite Loop
287 {
288 if (idx++ > 7)
289 idx = 0;
290 adcP = &adcbuffer [4? idx ];
291 adcV1 = AdcMirror .ADCRESULT0;
292 adcI1 = AdcMirror .ADCRESULT1;
293 adcV2 = AdcMirror .ADCRESULT2;
294 adcI2 = AdcMirror .ADCRESULT3;
295 //ADC freerunning . Latest sample will be in ADCMirror.ADCRESULTn (Use
mirror for fastest response times)
296 u1 = Vref ? (adcV1 + adcV2) /2;
297 // adcOld = AdcMirror.ADCRESULT0;
298 ?(adcP++) = adcV1;
299 ?(adcP++) = adcI1 ;
300 ?(adcP++) = adcV2;
301 ?(adcP++) = adcI2 ;
302
303 // a5 = alpha5?Sold2 ;
119
304 // a4 = alpha4?Sold1 ;
305 a2 = alpha2?u1old1 ;
306 a3 = alpha3?xint ;
307 xint = xint + (u1 >> 4) ;
308 if ( xint > 0x00004000){
309 xint = 0x00004000 ;
310 }
311 if ( xint < ?0x00004000){
312 xint = ?0x00004000 ;
313 }
314 a1 = alpha1?u1;
315 // idx1++;
316 S = a1+a2+a3 ;//+a4+a5;
317 S1 = S + alpha4?ramp1 + alpha6?x6 + alphaC1?c1 ;
318 u1old1 = u1;
319 if (S1 > kappa){
320 // if (( idx & 1) == 0){
321 GpioDataRegs .GPASET. all = 0x05 ;//0x05 ; //Phase 2 for monitoring
322 EPwm1Regs.TBCTR = 0;
323 c0 = 1;
324 // if (S1old < kappa)
325 ramp1 = 0;
326 }
327 if (S1 < negkappa){
328 // else{
329 // GpioDataRegs.GPACLEAR. all = 0x05 ; //Phase 2 for monitoring
330 GpioDataRegs .GPACLEAR. all = 0x05 ; //Phase 2 for monitoring .
331 // x6 = taud1 ;
332 c0 = 0;
333 }
334 S2 = 0;//S + alpha5?ramp2 + alpha7?x7 + alphaC0?c0 ;
335 if (S2 > kappa){
336 // if (( idx & 1) == 0){
337 GpioDataRegs .GPASET. all = 0x50 ; //Phase 4 for monitoring
338 EPwm1Regs.TBCTR = 0;
339 c1 = 1;
340 // if (S2old < kappa)
341 ramp2 = 0;
342 }
343 if (S2 < negkappa){
344 // else{
345 GpioDataRegs .GPACLEAR. all = 0x50 ; //Phase 4 for monitoring .
346 // x7 = taud2 ;
347 c1 = 0;
348 // ramp2 += 1;
349 }
350 dS1 = S1 ? S1old ;
351 dS2 = S2 ? S2old ;
352 if (dS1 <= 0)
353 x6 ?= 1;
354 else
355 x6 = taud1 ;
356 if (dS2 <= 0)
357 x7 ?= 1;
120
358 else
359 x7 = taud2 ;
360 ramp1++;// = EPwm1Regs.TBCTR;
361 ramp2++;// = EPwm2Regs.TBCTR;
362 if ( x6 < ?0x04000000){
363 x6 = ?0x04000000 ;
364 }
365 if ( x7 < ?0x04000000){
366 x7 = ?0x04000000 ;
367 }
368 S1old = S1;
369 S2old = S2;
370 }
371
372 }
373
374
375
376
377
378
379
380 //===========================================================================
381 // No more.
382 //===========================================================================
121