Dual-Threshold Voltage Design of Sub-Threshold Circuits
by
Jia Yao
A dissertation submitted to the Graduate Faculty of
Auburn University
in partial ful?llment of the
requirements for the Degree of
Doctor of Philosophy
Auburn, Alabama
August 2, 2014
Keywords: Sub-threshold circuits, Dual-threshold voltage, Minimum energy operation
Copyright 2014 by Jia Yao
Approved by
Vishwani D. Agrawal, Chair, James J. Danaher Professor of
Electrical and Computer Engineering
Victor P. Nelson, Professor of Electrical and Computer Engineering
Bogdan M. Wilamowski, Professor of Electrical and Computer Engineering
Abstract
Threshold voltage of MOSFET technology represents the value of the gate-source voltage
when the current in a MOS transistor starts to increase signi?cantly since the conduction
layer just begins to appear. However, a MOSFET transistor can also function correctly
with a supply voltage below its threshold voltage (Vth), which is referred to as sub-threshold
operation or weak-inversion of a transistor. The circuits that works under a supply voltage
in the sub-threshold range are named sub-threshold circuits.
Due to the increasing emergence of energy-constrained electronic devices, it is more
important to suppress energy consumption to achieve a longer battery life. Therefore there
are demands for design methods for less energy consumption. Sub-threshold circuit pro-
vides a potential solution since it can reduce energy per cycle signi?cantly by the scaling of
supply voltage (Vdd) below threshold voltage (Vth). In addition, sub-threshold circuits are ex-
pected to receive increasing attention in the coming years since the minimum energy CMOS
operation typically occurs when supply voltage scales down to the sub-threshold range.
The dual-threshold voltage method bene?ts from the characteristics of low and high
threshold voltages. Higher threshold voltage results in less leakage current, therefore less
leakage power consumption with the sacri?ce of delay. On the contrary, lower threshold
voltage brings more leakage power consumption with faster speed. Dual-threshold voltage
design is a common method for reducing leakage power consumption for above-threshold
circuits. In this thesis, dual-threshold voltage is proven e?ective for reducing energy con-
sumption per cycle (EPC) of sub-threshold circuits. It is demonstrated in this research that
the energy per cycle is independent of threshold voltage in single-Vth designs.
ii
A dual-threshold voltage framework written in PERL language is developed to generate
the optimal dual-threshold voltage design with minimum energy consumption. The pro-
posed framework is built on a gate-slack based dual-threshold voltage algorithm to precisely
?nd out the optimal high threshold voltage and supply voltage (Vddopt), along with accurate
estimation of energy consumption for the generated dual-Vth designs. Meanwhile, the frame-
work conducts static timing analysis (STA) to ensure that the dual-threshold voltage design
is able to run at the fastest possible operating frequency at Vddopt. Experimental results on
32-bit ripple carry adder (RCA), 4-by-4 multiplier and ISCAS85 benchmark circuits show
that minimum EPC is lowered by 10% to 29% by dual-Vth design over its single-Vth version.
The impact of process variations is also discussed. Applying random process variations
on threshold voltage as Gaussian variables can bring variations on both energy consumption
and performance for sub-threshold circuits.
iii
Acknowledgments
First of all, I would like to give my deepest thanks to my advisor, Dr. Vishwani D.
Agrawal. I am sincerely grateful for his patience and guidance during my study. He always
encourages the students to explore for more possibilities not only for research but also for
personal life. Without his encouragements, I would not complete my study. Also, I would
like to thank my committee members, Dr. Victor Nelson, Dr. Bogdan Wilamowski and Dr.
Xiao Qin, for their great help and e?orts. Special thanks go to Dr. Prathima Agrawal and
Auburn University Wireless Engineering Research and Education Center for the generous
support and help. I would like to thank my colleagues, Suraj, Mridula, Farhana, Kim,
Karthik, Vijay, Praveen, Wei and Yu for their valuable help on my research work.
Also, I would like to thank my parents and my husband for their love and support. And
thanks for my friends I met in Auburn - Julia Evans, Elizabeth Wills, Elizabeth Williams,
Jena Robison, Martha Dees, Man Zhang, Yueqin Lin, Binying Tan and Fei Tong. Their
friendship and encouragements give me strength and comforts.
Thank myself for not giving up and I am glad that I did hold on to the end. Life is too
short to waste. I will keep on moving.
iv
Table of Contents
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Contribution of The Dissertation . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Organization of The Dissertation . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 The History of Sub-threshold Circuits . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Logic Operation in Sub-threshold Region . . . . . . . . . . . . . . . . . . . . 15
2.2.1 Sub-threshold Current . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.2 Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3 Dual-Threshold Voltage Techniques . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.1 The History of The Dual-Threshold Voltage Technique . . . . . . . . 19
2.3.2 Slack-Based Dual-Threshold Voltage Technique . . . . . . . . . . . . 20
2.4 The History of Minimum Energy Operation . . . . . . . . . . . . . . . . . . 22
2.5 Alpha-Power Law MOSFET Model . . . . . . . . . . . . . . . . . . . . . . . 23
3 Single-Vth Design of Sub-threshold Circuits . . . . . . . . . . . . . . . . . . . . . 25
3.1 Theoretical Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 Dual-Vth Design of Sub-threshold Circuits . . . . . . . . . . . . . . . . . . . . . 30
v
4.1 The Proposed Dual-Vth Design Framework . . . . . . . . . . . . . . . . . . . 30
4.1.1 The Method of Obtaining Low Vth and High Vth gates . . . . . . . . 31
4.1.2 Library Characterization . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1.3 Gate Slack Based Dual-Vth Algorithm . . . . . . . . . . . . . . . . . . 37
4.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.1 32-Bit Ripple Carry Adder . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2.2 4-by-4 Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.2.3 ISCAS85 Benchmark Circuits . . . . . . . . . . . . . . . . . . . . . . 47
5 Analysis of Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.2 Theoretical Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.2.1 Single-Vth Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.2.2 Dual-Vth Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6 Ultra-Low Voltage Circuit Under Process Variations . . . . . . . . . . . . . . . . 59
6.1 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.2 Impact of Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.2.1 Gate delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.2.2 Circuit Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.2.3 Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7 Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.2.1 Challenge with Scaled Technology . . . . . . . . . . . . . . . . . . . . 68
7.2.2 Variation-Aware Design . . . . . . . . . . . . . . . . . . . . . . . . . 69
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
vi
List of Figures
2.1 Measurment of Id(VGS) of a P-channel MOS transistor (cleaned up plot from
E.Vittoz notebook, CEH, 1967). . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 DIBL e?ects on drain current of NMOS transistor in PTM 32nm Bulk CMOS
technology with Wn = 5L. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3 Voltage Transfer Curve of Inverter at Vdd = 0.2V with varying transistor sizing
ratio (? = Wp/Wn) in PTM 32nm Bulk CMOS technology. . . . . . . . . . . . . 18
2.4 One bit full adder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5 8-bit RCA energy calculated by HSPICE in PTM 32nm Bulk CMOS technology
with Wn = 5L and Wp = 12L. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 32-bit RCA energy calculated by HSPICE using PTM 32nm Bulk CMOS tech-
nology with Wn = 5L and Wp = 12L. . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1 Two-input low Vth NAND gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2 Two-input high Vth NAND gate implemented with reverse bias voltage = 0.1V. 32
4.3 One-bit full adder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.4 HSPICE simulation for energy per cycle (EPC) of 32-bit RCA single Vth designs
in PTM 32nm Bulk CMOS with Wn = 5L and Wp = 12L. . . . . . . . . . . . . 43
4.5 Gate slacks of single low Vth design of a 288-gate 32-bit RCA at Vdd = 0.25V. . 44
vii
4.6 Gate slacks of dual Vth design of 288-gate 32-bit RCA with bias voltage = 0.3V
at Vdd = 0.25V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.7 Energy savings vs. percentage of high Vth gates from HSPICE simulation results
of a 124-gate 32-bit RCA dual Vth designs under varying Vdd values. . . . . . . . 46
4.8 Random-vector HSPICE simulation results vs. estimation results for energy per
cycle (EPC) for 124-gate 32-bit RCA dual-Vth design with reverse body bias
voltage = 0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.9 Gate slacks of single low Vth design of 4-by-4 multiplier at Vdd = 0.21V. . . . . . 48
4.10 Gate slacks of dual Vth design of 4-by-4 multiplier with bias voltage = 0.2V at
Vdd = 0.21V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.1 HSPICE simulation results of dynamic energy vs. leakage energy for 32-bit RCA
single low Vth and dual-Vth design. . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.2 Root mean squared error analysis of polynomial ?t for leakage energy with low
Vth; a third-degree polynomial is selected. . . . . . . . . . . . . . . . . . . . . . 53
5.3 Root mean squared error (RMSE) analysis of polynomial ?t for leakage energy
with high Vth; a third-degree polynomial is selected. . . . . . . . . . . . . . . . . 54
5.4 Regression coe?cent (R-squared) analysis of polynomial ?t for leakage energy
with low Vth; a third-degree polynomial is selected. . . . . . . . . . . . . . . . . 55
5.5 Regression coe?cent (R-squared) analysis of polynomial ?t for leakage energy
with high Vth; a third-degree polynomial is selected. . . . . . . . . . . . . . . . . 56
5.6 HSPICE simulation results vs. theoretical analysis of energy ratio of 32-bit RCA
dual-Vth designs with bias voltage = 0.3V and single-Vth design. . . . . . . . . . 57
viii
6.1 Monte Carlo HSPICE simulations of NAND02 gate delay with three Inverters as
load at Vdd = 0.25V and source-bulk bias voltage = 0.3V in PTM 32nm Bulk
CMOS with Wn = 5L and Wp = 12L. . . . . . . . . . . . . . . . . . . . . . . . . 62
6.2 Monte Carlo HSPICE simulations of circuit delay of 32-bit RCA single low Vth
design under random Vth Gaussian variations at Vdd = 0.25V in PTM 32nm Bulk
CMOS with Wn = 5L and Wp = 12L. . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3 Monte Carlo HSPICE simulations of circuit delay of 32-bit RCA dual Vth design
with bias voltage = 0.3V under random Vth Gaussian variations at Vdd = 0.25V
in PTM 32nm Bulk CMOS with Wn = 5L and Wp = 12L. . . . . . . . . . . . . 64
6.4 Monte Carlo HSPICE simulations of EPC of 32-bit RCA single low Vth design
under randomVth Gaussian variations atVdd = 0.25 V in PTM 32nm Bulk CMOS
with Wn = 5L and Wp = 12L. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.5 Monte Carlo HSPICE simulations of EPC of 32-bit RCA dual Vth design with
bias voltage = 0.3 V under random Vth Gaussian variations at Vdd = 0.25 V in
PTM 32nm Bulk CMOS with Wn = 5L and Wp = 12L. . . . . . . . . . . . . . . 65
ix
List of Tables
3.1 PTM 32nm Bulk CMOS Vth Calculated in HSPICE. . . . . . . . . . . . . . . . 27
4.1 Threshold voltages of NMOS and PMOS in PTM 32nm bulk technology calcu-
lated by HSPICE with Wn = 5L and Wp = 12L . . . . . . . . . . . . . . . . . . 31
4.2 Vth calculated by HSPICE in PTM 32nm bulk CMOS technology with varying
source-bulk voltages with Wn = 5L and Wp = 12L. . . . . . . . . . . . . . . . . 33
4.3 Low Vth NAND02 gate delay calculated by HSPICE in PTM 32nm bulk CMOS
technology with single fan-out to an inverter load under varying input vectors at
Vdd = 0.2V with Wn = 5L and Wp = 12L. . . . . . . . . . . . . . . . . . . . . . 34
4.4 Low Vth NAND02 gate delay calculated by HSPICE in PTM 32nm bulk CMOS
technology with fan-out varying from one inverter to ten inverters at Vdd = 0.2V
and Vdd = 0.4V with Wn = 5L and Wp = 12L. . . . . . . . . . . . . . . . . . . . 35
4.5 NAND02 gate delay calculated by HSPICE in PTM 32nm bulk CMOS technology
with one inverter as load at Vdd = 0.2V with Wn = 5L and Wp = 12L under
varying reverse source-bulk bias voltages. . . . . . . . . . . . . . . . . . . . . . . 35
4.6 Low Vth NAND02 gate leakage power calculated by HSPICE in PTM 32nm bulk
CMOS technology with fan-out as one inverter under varying input vectors at
Vdd = 0.2V with Wn = 5L and Wp = 12L. . . . . . . . . . . . . . . . . . . . . . 36
4.7 NAND02 gate leakage power calculated by HSPICE in PTM 32nm bulk CMOS
technology with varying reverse source-bulk bias voltages with fan-out as one
inverter at Vdd = 0.2V with Wn = 5L and Wp = 12L. . . . . . . . . . . . . . . . 36
4.8 Low Vth NAND02 gate nodal capacitance calculated by HSPICE in PTM 32nm
bulk CMOS technology with fan-out condition from one inverter to 10 inverters
at Vdd = 0.2V and Vdd = 0.4V with Wn = 5L and Wp = 12L. . . . . . . . . . . . 37
4.9 NAND02 gate nodal capacitance calculated by HSPICE in PTM 32nm bulk
CMOS technology with varying Vth with fan-out as one inverter at Vdd = 0.2V
with Wn = 5L and Wp = 12L. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.10 Parameters used in the proposed dual-Vth algorithm. . . . . . . . . . . . . . . . 38
x
4.11 4-by-4 Multiplier single-Vth design vs. dual-Vth minimum EPC saving. . . . . . . 47
4.12 ISCAS85 benchmark circuit HPICE simulation results on energy saving. . . . . 48
4.13 ISCAS85 benchmark circuit HPICE simulation results on Vddopt and optimal bias
voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1 PTM 32nm Vth variation characteristics. . . . . . . . . . . . . . . . . . . . . . . 61
6.2 Low Vth gate vs. high Vth gate delay under Gaussian Vth variations. . . . . . . . 63
xi
Chapter 1
Introduction
Sub-threshold circuit is also named as ultra-low voltage circuit. It refers to the circuit
operating at a supply voltage (Vdd) below transistor?s threshold voltage (Vth). Conventionally,
a transistor is considered as ON when Vdd is greater than Vth and it is considered as OFF
when Vdd is less than Vth. As a result, sub-threshold operation of transistors has been
neglected for a long time. However, since 1960s, much work has been done in this ?eld
and researchers found out that a transistor in sub-threshold region is not completely OFF
since there are ?leaking? currents ?owing through it. Moreover, based on these ?leaking?
currents, transitions of logic levels of a transistor can be successfully completed, in another
word, transistors can function correctly. But it brings the cost of large transition delays.
The most obvious advantage of sub-threshold operation is its low energy consumption.
The energy consumption per cycle (EPC) can be tremendously reduced as Vdd scales down
to sub-threshold region, by an order of magnitude compared to conventional operation.
Therefore, sub-threshold circuits have been very attractive to certain applications which re-
quire ultra-low energy consumption, like wristwatches, implantable medical sensors, wireless
sensor networks and so on. Moreover, due to the increasing emergence of battery-based
portable electronic devices, long battery life becomes a big concern for the circuit designer.
Sub-threshold circuit appears as a potential candidate due to its low energy consumption.
However, sub-threshold circuits are not the ultimate solution for all low power or low
energy applications due to the large circuit delay. For example, they are not suitable for
applications like processors, CPUs and others which demand high circuit performance.
1
1.1 Motivation
Due to the increasing emergence of energy-constrained electronic devices, it is important
to suppress energy consumption to achieve a longer battery life. Therefore, it demands for
design methods for less energy consumption. Among the previously proposed work, minimum
energy operation designs draw researchers? attention [15, 19, 28, 95, 125, 198, 199, 216]. As
the Vdd scales from the above-threshold region to sub-threshold region, the energy per cycle
curve starts to drop signi?cantly, reaching a minimum at optimal supply voltage (Vddopt).
When Vdd decreases further, energy per cycle curve begins to increase. The minimum EPC
point of a circuit typically locates in the sub-threshold region [194]. This is one of the reasons
why sub-threshold circuits have been gaining increasing attentions recently.
For above-threshold circuits, circuit performance is still the key concern therefore dual-
Vth algorithms aim to reduce the power consumption while maintaining the high performance
of the circuit. However, when it comes to circuits with sub-threshold supply voltage, power
consumption is no longer the correct criteria to evaluate whether it is a good design or
not. Because the circuit delay of a sub-threshold circuit is very large, even if the power
consumption is small, the EPC can still be very high since energy is the product of power
and circuit delay. Therefore, for sub-threshold circuits, it is more important to identify
the minimum EPC point and develop algorithms to further reduce the minimum EPC. The
dual-Vth approach has been well applied to reduce power consumption for above-threshold
circuits. But its e?ectiveness on reducing energy per cycle of sub-threshold circuits has not
been investigated. In this work, we perform thorough study towards this issue.
1.2 Problem Statement
The aim of this dissertation is:
1. Investigate the e?ectiveness of the dual-Vth approach in reducing energy per cycle for
CMOS sub-threshold circuits.
2
2. Develop a framework to generate the optimal dual-Vth design for sub-threshold circuits.
The proposed dual-Vth algorithm is able to estimate the optimal highVth, automatically
generate the optimal dual-Vth assignments with maximum energy saving and accurately
estimate the optimal supply voltage.
1.3 Contribution of The Dissertation
The single-Vth design of sub-threshold circuits was ?rst reviewed. Theoretical and
simulation-based proofs are presented to demonstrate that the energy per cycle of single-Vth
sub-threshold circuits is independent of threshold voltage Vth. In fact, Vth increase does
not in?uence dynamic energy, which is only related to switching capacitance of the circuit
and supply voltage. Leakage energy remains unchanged since the increment of Vth not only
reduces the leakage power consumption but also raises the circuit delay.
However, in a dual-Vth design, the energy per cycle depends on both threshold voltage
and supply voltage. A framework written in PERL language is proposed to generate the
optimal dual-Vth design for sub-threshold circuits to achieve maximum energy saving. Given
the circuit gate-level netlist and low Vth level, the framework analyzes the single low Vth
design and ?nd out its minimum EPC point (Emin;singleVth). Then the framework conducts
static timing analysis and energy estimation analysis to accurately ?nd out the optimal the
optimal high Vth level, optimal supply voltage, automatically generate the optimal dual-
Vth assignment and estimates the energy consumption per cycle. The minimum EPC is
e?ectively lowered by dual-Vth over its single-Vth version.
1.4 Organization of The Dissertation
This dissertation is organized as follows. Chapter 2 provides detailed background knowl-
edge on sub-threshold circuits, the dual-Vth approach, and minimum energy operation design.
3
Chapter 3 discusses single-Vth sub-threshold circuits. It is discovered that the energy per
cycle of single-Vth designs is independent of threshold voltage. Theoretical and simulation
proof are presented in this chapter to demonstrate this statement.
In Chapter 4, thorough interpretations of the proposed dual-Vth framework are given.
The gate slack based dual-Vth algorithm is presented as well.
In Chapter 5, experimental results on 32-bit ripple carry adder, 4-by-4 multiplier, and
ISCAS85 benchmark circuits are listed, followed by a section of theoretical analysis.
Chapter 6 discusses the impact of process variations on sub-threshold circuits, along
with a short introduction of variation-aware sub-threshold circuits.
In the end, summary and future work are included in Chapter 7.
4
Chapter 2
Background
This chapter provides background knowledge on sub-threshold circuits, including the
history of sub-threshold circuit research and logic gate operation in the sub-threshold re-
gion. More background knowledge about common low power techniques, especially dual-Vth
technique, are presented in this chapter. Previous research work on minimum energy oper-
ation of sub-threshold circuits are summarized in the end.
2.1 The History of Sub-threshold Circuits
The only dominant current component for a transistor working under a supply voltage
in the sub-threshold range is called sub-threshold current. As we know, in a transistor, there
are two modes by which current can ?ow: di?usion and drift. Di?usion is the natural ?ow
of carriers from higher to lower concentration while drift is the the ?ow of carriers under an
external voltage potential. Sub-threshold current is the result of di?usion. The fact behind
the scene can be summarized as follows. As we apply a small positive gate-source voltage to
an n-type transistor, holes are repelled away from the surface while electrons are the only
mobile charge available at the surface. The density of electrons depends on the di?erence
in the voltage across the two pn junction diodes (Bulk-Source and Bulk-Drain). In other
words, the densities of electrons are di?erent at Drain and Source. As a result, a di?usion
current between Drain and Source is formed.
Because of this weak ?leakage? current, sub-threshold operation is often referred to as
weak inversion operation. The study of this weak current ?rst emerged with the discovery
of parabolic region in 1955 [58], the authors showed that the density of the electrons is
proportional toexp(q sK T),?s being the surface potential of a MOS transistor. Later, research
5
on sub-threshold current and sub-threshold operation appeared in 1960s and early 1970s [12,
61, 91, 92, 108, 129, 174, 177]. In [12], an analytical expression between sub-threshold drain
current and gate voltage was illustrated. In [61], the authors demonstrated that the main
contributions to drain leakage current in sub-threshold region are reverse-bias drain junction
leakage current and surface channel current in weak inversion mode. In [91], the author
presented measurement results of sub-threshold circuit delay on test chips of 2-stage and
6-stage CMOS inverters. In [92], mathematical analysis of MOS transistor behavior in weak
inversion were presented along with analysis of surface mobility of electron and inversion layer
charge. In [108], a CMOS binary counter had been realized to suit low power low voltage
applications. In [174], the authors speci?ed the exponential relation between sub-threshold
current and transistor gate voltage for the ?rst time. Due to revelation of this sub-threshold
current, researchers and designers knows that the transistor is not completely OFF when
gate voltage is below threshold voltage. This also introduces a brand-new understanding
of threshold voltage since it was known as the voltage to turn the transistor from complete
OFF to ON. In addition, authors in [174] also pointed out that the supply voltage must be
at least 3-4 times of KT/q for a digital circuit to function properly. This paper also was
the ?rst discussion on minimum operating voltage of digital CMOS circuits. Later in [177],
analytical model of sub-threshold current for insulated-gate ?eld-e?ect transistors (IGFET)
was developed for both long channel and short channel devices.
The ?rst measurement of drain current characteristics of MOS transistor in both weak
and strong inversion regions was conducted by Eric Vittoz in 1967 [188, 194] as shown in
Figure 2.1.
Since the middle 1970s, it has been well recognized that sub-threshold region exists
in addition to linear and saturation regions. At ?rst, the behavior of MOS transistors
in weak inversion only draws attentions of analog circuit designers. The ?rst discussion
on small-signal model for weak inversion operation was published in 1976 in [11]. The
author proposed the model and pointed out the possibility of applying it to ampli?ers. In
6
Figure 2.1: Measurment of Id(VGS) of a P-channel MOS transistor (cleaned up plot from
E.Vittoz notebook, CEH, 1967).
the same year, Eric Vittoz, a pioneer of sub-threshold circuit research, published his ?rst
paper on possible application of analog circuits utilizing weak-inversion operation [190].
He mentioned several possible analog circuit applications, including voltage reference [180,
193], amplitude detector, low power quartz oscillator [185, 186] and bandpass ampli?er.
Quoted from Vittoz [194], he received serious comments from the audience that circuits
which operate on sub-threshold current of transistors cannot be reliable. Soon afterwards,
a thorough characterization and modelling of MOS transistor behavior in weak inversion
region was presented by Vittoz and Fellrath [191]. The well known sub-threshold drain
current expression was introduced in this paper as shown in Equation (2.1):
7
ID = IDo exp( VGn V
t
) [exp( VSV
t
) exp( VDV
t
)] (2.1)
where IDo is a characteristic current and n is sub-threshold slope factor. More importantly,
the authors built sample circuits of current references, amplitude detector and low-frequency
bandpass ampli?er. The experimental results obtained from these sample circuits demon-
strated the validation of weak inversion operation for CMOS technology.
During the following decade, the application of weak inversion was still limited to analog
circuits, mainly focusing on oscillators and ampli?ers [49, 50, 51, 93, 94, 180, 185, 186, 189,
192]. The most successful production was an electronic wrist watch which ?rst appeared on
the market in 1975 [179]. The following important milestone in the history of weak inversion
was the invention of the EKV model in 1995 [54]. The authors established continuous
expressions for MOS transistor parameters like drain current, small signal and large signal
transconductance, intrinsic capacitance, trans-admittance and thermal noise for all regions
of operation, from weak inversion to saturation. Around 1990s, researchers shifted their
focus onto digital sub-threshold circuit design due to increasing need for portable and low
power circuit designs. The authors in [38] proposed an architectural-based voltage scaling
strategy for parallel and pipelined architectures. The concept of optimal supply voltage was
introduced and the authors demonstrated that reduction of supply voltage can come from
proper structural parallelism. In [187], a discussion of existing low power techniques was
presented and it was mentioned that design methodologies, tool, libraries and models have
to be adapted for low power low voltage designs.
Due to the increasing interest in ultra-low power medical devices that do not need high
performance but require extremely low power consumption, sub-threshold digital circuit
came to researchers? attention since it o?ers potential solutions for these speci?c applica-
tions [8, 59, 119, 135, 170]. A research group at Purdue University did some of the earliest
work on sub-threshold digital CMOS circuits. In 1999, the authors examined both CMOS
and pseudo-NMOS logic operating in the sub-threshold region in power consumption and
8
delay [164, 165]. For a characteristic inverter, sub-threshold pseudo-NMOS logic was shown
to consume less power and have smaller delay than sub-threshold CMOS logic. In [204],
the authors proposed a design technique which provides di?erent threshold voltages within
a logic gate and demonstrated its e?ectiveness on leakage reduction. The authors extended
their work to investigate multiple Vdd and multiple Vth design techniques to achieve high
speed and low power consumption in [146]. In 2000, common low power techniques like
multiple Vdd, multiple Vth and some standby leakage control techniques were investigated for
their impacts on leakage current reduction [206]. In 2000, robust sub-threshold DTMOS logic
was introduced in [167] and its stability to temperature and process variations was discussed.
In [166], the authors presented simulation results on sub-domino logic and demonstrated that
sub-domino logic has lower power consumption and smaller area and faster than sub-CMOS
logic. In 2001, this group built a test chip of 8-by-8 carry save array multiplier and ana-
lyzed it with sub-threshold supply voltage using TSMC 0.35 ?m process technology [132].
A 96% power-delay-product reduction was reported on the test chip operating at 0.47 V
(the threshold voltages for PMOS and NMOS are 0.82 V and 0.67 V, respectively) [132].
Same year, this team presented successful implementation of sub-threshold circuits in the
area of hearing aid instruments [82]. In this paper, an ultra-low-power delayed least mean
square (DLMS) adaptive ?lter was designed and simulated. Sub-threshold pseudo-NMOS
logic was chosen over CMOS logic since it provides lower power-delay-product. The au-
thors also suggested robust sub-threshold circuit design scheme using adaptive body biasing
method to resist process and temperature variations. Experiments on their 8-by-8 carry
save array multiplier test chip showed stable operation with sub-threshold supply voltage.
In 2004, this group also conducted research on double-gated MOSFET sub-threhsold cir-
cuits in [85]. The results showed that devices with longer length instead of minimum gate
length should be used for robust sub-threshold operation. Later, in [142], the authors ex-
plored the feasibility of sub-threshold SRAM design by investigating its stability. The results
9
showed that sub-threshold SRAM design provides signi?cant power reduction in both oper-
ating and standby modes. This team also presented research work on device optimization
for sub-threshold circuits in terms of ?nding the optimum doping pro?le to achieve mini-
mum power consumption [130, 131, 143]. In [130], the authors pointed out that MOSFET
libraries optimized for above-threshold region need extra adjustments to suit sub-threshold
circuit designs. Device optimization method was proposed to migrate the impact on circuit
power-delay product [131, 143]. In 2006, the authors demonstrated that minimum oxide
thickness may not produce minimum energy for sub-threshold circuits and oxide thickness
should be adjusted to resist process variations [133].
In the following few years, a research group in University in Michigan presented work
on energy-constrained designs. Since sensor network typically executes low speed tasks and
only relies on small energy supplies, sub-threshold circuit design provides a potential solu-
tion. In [125], energy optimization of sub-threshold voltage sensor processors was presented
and the authors built a sensor network in 130nm CMOS technology which can operate at
235 mV with low energy consumption of 1.38pJ per instruction. This group also presented
work on statistical analysis of sub-threshold leakage current [141], sub-threshold circuit vari-
ations [65, 175, 213], clock network design optimization for subthreshold circuit [15, 153], etc.
In 2007, the group presented research on subthreshold circuit leakage energy reduction tar-
geted at stand-by mode. The proposed method can reduce energy by 99.2% compared to cir-
cuits with no stand-by mode optimization [155]. This work was further modi?ed to a power
gating switch (PGS) approach to minimize energy consumption in stand-by mode [156].
Known stand-by power reduction techniques were investigated for ultra-low power proces-
sors [104]. In the same year, this team also discussed an energy optimization method which
uses gate sizing and supply voltage scaling [64]. In [63], the authors investigated the relation
between device scaling and sub-threshold circuit operations and found out that the di?er-
ence between on current and o? current of a MOSFET drops rapidly as gate oxide thickness
scales down. This team designed and built a test chip for sub-threshold sensor processor
10
in 0.13?m CMOS process with optimum supply voltage at 0.36mV, consuming 2.6 pJ/Inst
at 833 KHz [66, 216]. Their work also extended to designing subthreshold SRAM [212]
fully functional from 193 mV to 1.2 V, which was the ?rst reported 6T SRAM which can
operate in sub-threshold region. Later, the robust version of 6T sub-threshold SRAM were
presented in [215]. In 2012, this group designed a subthresold Fast Fourier Transform (FFT)
core in 65nm technology. The reported optimal Vdd is 270 mV and energy consumption is
15.8 nJ with a clock frequency of 30 MHz [74]. Besides sub-threshold SRAM design, this
team also presented sub-threshold ROM design in [154]. More recently, their research work
included super cuto? CMOS (SCCMOS) bias generator circuit design with ultra low stand-
by power [105], ultra low power sensor nodes [102, 107, 109], wireless sensor nodes [106]
and energy e?cient interconnects [152]. Moreover, in [14], the authors pointed out some
possible sub-threshold application areas such as medical implantable devices for monitoring
disease, surveillance detection and environmental monitoring. In [101], the authors proposed
a maximum power point tracking (MPPT) circuit for ripple voltage sensor systems. In [10],
the authors presented a power management unit (PMU) design for sub-threshold wireless
sensor nodes. In [73], the authors proposed a VGA full-frame extraction processor design
which operates at 400 mV. In [72], the authors presented a ultra-low power digital multiply-
ing DDL (MDLL) design. In [84], the authors built an ultra low power wake-up receiveer
for wireless sensor nodes. The proposed design consumes only 695 pW in stand-by mode.
In [83], the team attempted to build a sub-threshold 10T SRAM which only consumes 1.85
fW per bit operating at 350 mV. In [103], a multi-stage temperature-compensated timer was
presented for sub-threshold wireless sensor nodes. An improved timer design for ultra low
power sensors were presented in [110]. In [157], the authors implemented an example circuit
of a voltage reference design which operates between 0.5 V and 3.0 V in 130nm and 180nm
technologies and studied the impact of process variations.
Around the same time, Dr. Anantha Chandrakasan, another pioneer of sub-threshold
circuit design, published his ?rst work in this area [33]. This work pointed out that the
11
need of ultra low power circuit for portable devices such as portable real-time digital signal
processor (DSP) [33], portable multimedia product [32, 160] and low power programmable
computation devices [34]. In 1992, the authors pointed out that optimum voltage for low
power purpose should be determined by the circuit architecture, logic style and technology
optimization. This optimum value should be achieved by a balance between area overhead
and power consumption [38].
Later, Chandrakasan?s research group at MIT continued work on ultra low power low
voltage circuit designs. In 1996, the authors ?rst proposed a minimum power consumption
design method for DSP [30]. In [35], this team discussed some key design issues for ultra
low power low voltage circuits, including low-threshold devices, multiple-threshold devices,
and bulk CMOS based variable threshold devices. Since 1997, more work were done on
related topic on low power DSP in this group [7, 8, 9, 31, 62, 118, 158, 159]. In 2001, system
partitioning method was proposed to improve energy e?ciency of DSPs [196].
This team also explored low power low voltage wireless applications such as wireless
camera [36, 37] and wireless sensor networks [163]. In [46, 48], pulse width modulated con-
troller (PWM) for low power low voltage DC-DC conversion circuit design were presented.
Their work on low voltage DC-DC conversion circuit was extended in [47, 60]. In [161], the
authors proposed an ultra low power video encoder for battery-operated portable applica-
tions. In [209, 210], the authors pointed out that supply voltage scaling with associated
threshold voltage scaling is an important method for energy e?cient design. However, the
sub-threshold leakage current increases as the threshold voltage scales down. In order to
deal with this issue, the authors proposed a low voltage design using Silicon-On-Insulator-
with-Active-Substrate (SOIAS) technology to control energy saving. In 2000, this team
explored several dual-threshold voltage methods for stand-by power reduction for combina-
tional logic [75, 76, 78]. The discussions focused multi-threshold CMOS (MTCMOS) sleep
12
transistor sizing. And the authors pointed out it is achievable to design a dual-threshold cir-
cuit which has the same performance as in single low threshold circuit and has low stand-by
power dissipation as in single high threshold circuit.
This group started to build and analyze test chips for sub-threshold circuits since 2000s.
The research was initiated due to the increasing interest on wireless microsensor networks
which normally operate from scavenged energy from the environment or self-powered systems
and therefore have constraints on energy consumption. In 2002, this group built a 175
mV multiply-accumulate test chip with tunable supply voltage and body bias values to
investigate its optimum supply voltage and threshold voltage operating points [79]. In [77],
the authors presented sub-threshold current modeling and pointed out possible improvement
for current CAD tools to ?t sub-threshold circuit design. Sub-threshold leakage modeling
for 32-bit microprocessors in 0.18 ?mm CMOS technology in [123]. In 2003, this group
started to focus on low energy low voltage Fast Fourier Transformer (FFT) designs [197]. In
2004, a sub-threshold fast Fourier transform (FFT) processor which can operate as low as
0.18V was designed and fabricated with 0.18 ?m CMOS process technology [199]. In their
following publication [198], the authors demonstrated that the minimum energy operation
point typically locates in the sub-threshold region. The fabricated 16-bit FFT processor has
its minimum energy point at 0.35V, with energy consumption of 155nJ at a clock frequency
of 10KHz. In the same year, the authors proposed a sub-threshold leakage power prediction
tool for sub-threshold circuits in [124]. In 2005, the authors described some key issues
associated with modeling subthreshold circuits in [27]. In 2005, research on sub-threshold
SRAM was also initiated. The group explored how static noise margin for sub-threshold
SRAM was associated with supply voltage, transistor sizing and process variations [20, 24].
A sub-threshold 100 Mbps ultra-wideband (UWB) baseband processor was proposed in [100,
120, 121, 176, 208]. A summary of sub-threshold circuit design challenges was listed in [29].
More recently, a 256KB SRAM was successfully designed and fabricated in 65nm CMOS
process technology [23, 26, 162, 181, 182]. Challenges and directions for low-voltage SRAM
13
design was presented in [136]. In 2008, this team predicted some promising applications for
sub-threshold circuit design such as toxic gas sensors and portable video gadgets [96, 97]. A
65nm sub-threshold micro-controller was presented in 2009 [99]. Minimum energy operation
of DC-DC converter design was presented with 65nm technology in [139, 140]. Sub-threshold
analog-to-digital converter (ADC) was reported which can operate between 0.2V and 0.9V
in [44, 45]. This team also presented an ultra-low-voltage 32-bit microprocessor which can
operate at 0.4 V [69]. Newest work on signal processing was proposed in [98] for biomedical
purpose. A framework was developed to estimate circuit delay under process variations
for sub-threshold circuits [144]. Their research also focused on technique implementation
and optimization on minimum energy operation for sub-threshold circuits, including device
sizing [21, 28, 95] and dynamic voltage scaling [18, 22, 25, 195].
AresearchgroupinArizonaStateUniversitypresentedsomeapplicationsofsub-threshold
circuits [39, 40, 41]. It was suggested [39] that circuits with high fan-in or fan-out are more
likely prone to logic failure in sub-threshold region due to process variations. The authors
derived a statistical model to evaluate the robustness of a sub-threshold circuit. In [40], the
authors designed and fabricated a sub-threshold memory with 130nm process technology.
The proposed memory can operate at 190mV for read operation and 216mV for write oper-
ation. In [41], the authors designed a radiation-harden by design (RHBD) 3218-bit register
?le operating at 320mV with energy dissipation of 10.3fJ per bit. The proposed design was
proven to have good immunity to single event upset (SEU).
Our research group at Auburn University has presented work on dual-Vdd sub-threshold
circuit design [86, 87, 88, 89, 90]. In [89], the authors developed mixed integer linear pro-
grams (MILP) to optimally assign dual-below threshold supply voltages to sub-threshold
circuits. The optimum dual Vdd assignment was designed to eliminate the requirement of
level converters. In [87], a gate slack based algorithm was proposed for dualVdd sub-threshold
circuit design to achieve maximum energy per cycle saving. Compared to previous MILP
method, the complexity of this new algorithm dropped signi?cantly. Level converter was also
14
eliminated in this work. Except for using proper design method to avoid level converters
between di?erent supply voltages, the authors utilized multiple logic-level gates in dual-Vdd
sub-threshold circuit design in [88]. In [90], the authors pointed out that level converters
are too slow to be used in sub-threshold circuit design. The proposed MILP method to
generate optimum dual-Vdd sub-threshold circuit design can result in 23% and 5% energy
saving fro 16-bit ripple-carry adder and 4-by-4 multiplier, respectively. Experimental results
on ISCAS85 benchmark circuits showed energy saving up to 22.2%, compared to single Vdd
design. The proposed gate-slack based dual-Vdd assignment algorithms were later adopted
for above-threshold circuit design [4, 5, 6]. Simulation results on ISCAS85 benchmark cir-
cuits in 90nm bulk CMOS technology showed up to 60% energy savings. The idea of the
dual-Vdd MILP method was adopted from previous work in our group on glitch minimiza-
tion [2, 3, 67, 137, 138] and dual-Vth assignment for above-threshold circuits under process
variations [112, 113, 115, 116, 117].
2.2 Logic Operation in Sub-threshold Region
Around 1970s, with the discovery of weak inversion region of MOS transistors, re-
searchers have con?rmed that CMOS transistors can function correctly under both normal
and sub-threshold supply voltages.
2.2.1 Sub-threshold Current
The sub-threshold current Isub is the main source of current in the sub-threshold region.
The charge and discharge of load capacitance rely on sub-threshold current. It can be
summarized as follows [194]:
Isub = Ioexp(Vgs VthnV
t
)[1 exp( VdsV
t
)] (2.2)
15
where
Io = ?CoxWL (n 1)V2t (2.3)
where ? is e?ective mobility, which is 0.067m2/Vsec for n-channel device and 0.025m2/Vsec
for p-channel device, Cox is oxide capacitance,W is transistor e?ective width, L is transistor
e?ective length, Vt is the thermal voltage, which is 25.8mV for room temperature, Vgs is
the gate-source voltage, Vds is the drain-source voltage, Vth is threshold voltage and n is
sub-threshold slope, which is a technology determined parameter. n is related to the ratio
of oxide capacitance over depletion capacitance by n = 1 +Cox/Cdepletion. It is in the range
of 1 and 1.5 for modern deep sub-micron technology.
For short channel transistors, Drain Induced Barrier Lowering (DIBL) has signi?cant
e?ect on the threshold voltage. DIBL refers to a reduction of threshold voltage and an
increase of drain current under higher source-drain voltage. Therefore, the drain current is
controlled not only by the gate voltage, but also by the drain voltage. To be noted is that
DIBL e?ect exists in the sub-threshold region. Therefore, if DIBL is taken into account for
modeling Isub, Equation (2.2) can be modi?ed as,
Isub = Ioexp(Vgs Vth +?VdsnV
t
)[1 exp( VdsV
t
)] (2.4)
and ? is called DIBL coe?cient, ? = ?Vth/?Vds. From the HSPICE measurements of ? for
PTM 32nm NMOS transistor with Wn = 5L under sub-threshold supply voltage, typical
value of ? is around 0.05.
Figure 2.2 illustrates the DIBL e?ect on MOS transistors. For an NMOS transistor with
Wn = 5L in PTM 32nm Bulk CMOS technology, the drain current versus Vgs under varying
Vds values are plotted. As Vds increases, the current curve shifts to the left. This horizontal
shift caused by DIBL is translated to a decrease of threshold voltage as Vds increases.
16
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
?24
?22
?20
?18
?16
?14
?12
?10
?8
Vgs(V)
Log of Drain Current
Vds=0.2V
Vds=0.3V
Vds=0.9V
Figure 2.2: DIBL e?ects on drain current of NMOS transistor in PTM 32nm Bulk CMOS
technology with Wn = 5L.
2.2.2 Inverter
Figure 2.3 shows the Voltage Transfer Curve (VTC) of an inverter under a sub-threshold
supply voltage of 0.2V with di?erent transistor sizing ratio (? = Wp/Wn).
The transistor under test has characteristic sizing with Wp = Wn = L. This transistor
was simulated with another inverter with the same sizing as fan-out load. As seen, both
logic 0 level and logic 1 level are reachable.
Although CMOS logic can function properly when supply voltage scales down to the
sub-threshold region, the lower limit for voltage scaling still exists. It occurs when Vdd drops
to 3 or 4 times the thermal voltage VT [150, 174]. As seen in this dissertation, the minimum
17
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.20
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
Input Voltage
Output Voltage
?=0.5
?=1
?=2
?=3
?=4
?=5
Figure 2.3: Voltage Transfer Curve of Inverter at Vdd = 0.2V with varying transistor sizing
ratio (? = Wp/Wn) in PTM 32nm Bulk CMOS technology.
supply voltage for a 32-bit Ripple Carry Adder (RCA) in PTM 32nm Bulk CMOS technology
with Wp/Wn = 12L/5L is 0.12V. Logic operations break down below this voltage.
2.3 Dual-Threshold Voltage Techniques
Threshold voltage of MOSFET technology represents the value of the gate-source voltage
when the current in the MOS transistor starts to increase signi?cantly since the conduction
layer just begins to appear. The threshold voltage changes with application of di?erent
source-bulk bias voltages. The threshold voltage when bias voltage is present can be sum-
marized in the following equation [70],
Vth = Vth0 + ?(
?
j 2?F + VSBj
?
j2?Fj)
18
where Vth0 is the threshold voltage with zero source-bulk bias voltage (V), which means
that the bulk terminal is connected to ground in NMOS transistors and the bulk terminal is
connected to supply voltage in PMOS transistors, VSB is the source-bulk bias voltage (V),
2?F is the surface potential parameter (V), ? is the body e?ect parameter (pV). Applying
a positive VSB to an NMOS transistor or a negative VSB to a PMOS transistor can increase
threshold voltages, which is called reverse body biasing. Applying a negativeVSB to a NMOS
transistor or a positive VSB to a PMOS transistor can decrease threshold voltages, which is
called forward body biasing.
Higher threshold voltage results in less leakage current, therefore less leakage power
consumption, at the cost of larger delay. On the contrary, lower threshold voltage brings more
leakage current, and therefore leakage power consumption with faster speed. By utilizing
dual or multiple threshold voltages in a circuit, designers can suppress leakage current while
meeting certain performance requirements as well.
2.3.1 The History of The Dual-Threshold Voltage Technique
With the reduction of supply voltage in order to lower power consumption in VLSI
circuits, threshold voltage scaling is needed to maintain circuit performance. However, low
threshold voltage brings higher leakage power consumption. In order to solve this problem,
multi-threshold CMOS was recommended to control leakage power [122] in 1995. Since
then it had been acceptable to use low threshold voltage devices for critical paths and
high threshold devices for non-critical paths [42, 81, 173, 201, 202, 203, 205]. The basic
idea is to assign as many gates as possible to a high threshold voltage to reduce leakage
power. In [202, 203, 205], the authors pointed out that not all gates on the o?-critical paths
can be switched to high threshold voltage and only some gates which have su?cient slack
can be switched to high threshold due to certain performance constraints. It was the ?rst
introduction of a slack-based theorem of dual-threshold voltage method. They developed an
algorithm to ?nd an optimum set of gates o? the critical paths which can be switched to
19
high threshold voltage. In addition, the proposed algorithm can select the optimum high
threshold voltage with respect to performance constraints. In [81], the authors presented a
transistor-level dual-Vth assignment algorithm for standby power minimization under area
and timing constraints.
Unlike the heuristic algorithm mentioned above, which can only guarantee a locally
optimal solution, researchers attempted to use linear programming (LP) to ensure a global
optimization of dual Vth assignments [57, 112, 114, 126]. The linear programming method
generally tries to ?nd optimum solutions for target optimization formula(s) under several
constraint formulas. In the linear programming method in [112], the target optimization is
to minimize total power consumption with constraints on gate delays, gate slacks, cell sizes
and circuit speed.
Later, moreworkwasdoneoninvestigatingleakagepowerreductionusingdual-threshold
or multi-threshold voltage methods in a combination with other low power design techniques.
The authors in [81, 128, 207] explored the combination of dual-threshold voltage assignment
along with transistor sizing optimization. Authors in [168] experimented on utilizing simul-
taneous gate sizing, dual-Vdd and dual-Vth approach for power minimization.
2.3.2 Slack-Based Dual-Threshold Voltage Technique
Let?s take a one-bit full adder as an example to illustrate the idea of the slack-base
theorem. Figure 2.4 illustrates the structure of one-bit full adder which consists of nine
NAND02 gates.
The process starts with assigning low Vth to all of the gates in the circuit. Let?s assume
all of the nine gates have one unit time (to) of gate delay. So the critical path delay of this
circuit is equal to 6 to. There are four critical paths - the ?rst one goes through gates 1,
2, 4, 5, 6 and 8; the second one goes through gates 1, 3, 4, 5, 7 and 8; the third one goes
through gates 1, 2, 4, 5, 6 and 8 and the last one goes through gates 1, 2, 4, 5, 7 and 8.
20
Figure 2.4: One bit full adder.
Therefore, gates 1 through 8 are marked as critical-path gates while gate 9 is marked as an
o?-critical-path gate.
The slack of a gate is de?ned as the di?erence between the critical path delay of the
circuit and the longest path delay through this gate. Take gate 9 for example, there are two
longest paths through it - the path goes through gates 1, 2, 4, 5 and 9 and the path goes
through gates 1, 3, 4, 5 and 9. The two paths have the same path delay of 5 to. Therefore,
gate 9 has a slack of to. As for the rest of the gates, they have zero slack since they are all
critical-path gates.
As a result, gate 9 will be potentially considered to be shifted from low Vth to high Vth
to save leakage power consumption. More importantly, gate 9 can only switch to high Vth
if its slack remains positive after the change. Positive slack means the circuit critical path
delay remains unchanged. For example, if the delay of gate 9 increases from to to 4 to, new
critical paths will be created which go through gates 1, 2, 4, 5, 9 and gates 1, 3, 4, 5, 9,
respectively. The critical path delay would then be 9 to. If the critical path delay of the
circuit has to remain as 6 to due to performance constraints, gate 9 cannot be changed to
high Vth.
21
2.4 The History of Minimum Energy Operation
When a circuit operates at its minimum energy operation point (Emin), the circuit con-
sumes less energy than any other point. Less energy consumption means longer battery life
which is essential for typical sub-threshold circuit applications such as implantable medical
devices. Sub-threshold circuits have been used for applications which do not require high cir-
cuit performance but require ultra-low energy dissipation. More attention or interests have
been drawn by sub-threshold circuits since a sub-threshold circuit is more energy-e?cient.
The reason is that the minimum energy point typically occurs when the supply voltage scales
down to sub-threshold range [199, 200].
As Vdd scales down, the dynamic energy drops quickly due to its quadratic relation with
Vdd. At the same time, the leakage energy increases due to the increase of circuit delay.
In the above-threshold region, circuit delay increases according to ?-power law, while in
sub-threshold region, circuit delay increases exponentially since the sub-threshold current
is exponentially related to Vdd. The minimum energy occurs when the dynamic energy is
equal to the leakage energy. Figure 2.5 shows the energy plot for an 8-bit RCA from SPICE
simulations.
As shown in Figure 2.5, the dynamic energy represented by the red curve drops quadrat-
ically as Vdd decreases from above-threshold range to sub-threshold range. While leakage
energy represented by the blue curve increases exponentially which is caused by signi?cant
increase of circuit delay. These two curves intersect when Vdd is around 0.2V, therefore the
optimal supply voltage Vddopt for this 8-bit RCA is 0.2V. Leakage energy dominates when
Vdd is below 0.2V, while dynamic energy plays a more important role when Vdd is greater
than 0.2V. As a result, the total energy represented by the black curve reaches its minimum
when dynamic and leakage energy are equal.
In [19], authors derived a theoretical equation for the optimal supply voltage Vddopt to
solve for minimum energy operation point in sub-threshold circuits. Similar equations can
be found in [194] as well.
22
Figure 2.5: 8-bit RCA energy calculated by HSPICE in PTM 32nm Bulk CMOS technology
with Wn = 5L and Wp = 12L.
2.5 Alpha-Power Law MOSFET Model
Alpha-power law is one of the most well-known MOSFET models and developed by Dr.
Sakurai in 1980s. It describes the behaviour of MOSFET drain current in saturation region
as shown in the following equation [148, 149].
ID = WL Pc (VGS VTH) (2.5)
After it was introduced, some researchers presented work on its physical background [16,
17, 68]. And it was veri?ed that the original alpha-power law is only suitable for MOSFET
under high electric ?eld. Therefore, it requires modi?cations when it comes to sub-threshold
23
region. In 2004, Dr. Sakurai published a short paper and completed the alpha-power law
model which includes MOSFET drain current modelling of sub-threshold current [147].
Ion = I0 (S?)? (VGS VTH)? (2.6)
where ? is a technology-determined physical parameter. For modern sub-micro CMOS tech-
nology, ? is now almost ?xed at about 1.3 [147].
Isub = I0 e? eVGS?VTHS (2.7)
where I0 is determined only by physical parameters of the transistor and S is sub-threshold
slope. As seen in Equation (2.7), exp( ?) only appears as a scaling factor for sub-threshold
current. The drain current is actually exponentially related to gate voltage, which is true as
seen in Equation (2.4). The original alpha-power relation between drain current and gate
voltage in Equation 2.5 is not suitable for MOSFET operating in sub-threshold region.
24
Chapter 3
Single-Vth Design of Sub-threshold Circuits
In this chapter, both theoretical analysis and experimental results are presented to
demonstrate that energy per cycle (EPC) of single-Vth sub-threshold circuits is independent
of threshold voltage. In other words, it does not change EPC by changing the threshold
voltage in single-Vth sub-threshold circuits [211].
3.1 Theoretical Analysis
As mentioned in the previous chapter, the complete expression of sub-threshold current
can be summarized in the following equation,
Isub = Io exp(Vgs Vth +?VdsnV
t
) [1 exp( VdsV
t
)] (3.1)
Transistors in sub-threshold region are considered as ?leaking? all the time. The charg-
ing and discharging of capacitance both rely on the sub-threshold current. However, there
is still a di?erence between on-current and o?-current. Similar to above-threshold region,
on-current refers to the ?dynamic? current when the logic gate is switching while o?-current
refers to the ?static? current leaking from voltage supply to ground all the time. In fact,
based on sub-threshold current in Equation (3.1), on-current can be expressed as the current
when assigning Vgs to Vdd, as shown in Equation (3.2), while o?-current is the current when
assigning Vgs to 0, as shown in Equation (3.3).
Ion = Ioexp(Vdd Vth +?VddnV
t
)[1 exp( VddV
t
)] (3.2)
25
Ioff = Ioexp( Vth +?VddnV
t
)[1 exp( VddV
t
)] (3.3)
The delay of a logic gate is de?ned as its output capacitance (Cout) times Vdd divided
by on-current (Ion). Output capacitance is typically dominated by the gate capacitance of
its fan-out gate(s). Therefore, it can be expressed as,
D = Cout VddI
on
= Cout VddI
o exp(Vdd?Vth+ VddnVt ) [1 exp(?VddVt )]
(3.4)
Therefore, for a given circuit, the critical path delay of a circuit can be de?ned as,
Tc = l CgVddI
on
= Cg VddI
o exp(Vdd?Vth+ VddnVt )[1 exp(?VddVt )]
(3.5)
where Cg is the gate capacitance of a characteristic inverter and l is the length of the critical
path in terms of a characteristic inverter.
Since the leakage energy per cycle is the product of leakage power consumption and
circuit critical path delay, we can summarize its expression based on the above equations.
As expressed by Equations (3.6), (3.7) and (3.8), the Vth term is canceled out in the leakage
energy expression, which means that Vth has no e?ect on leakage energy.
Eleak = Ioff Vdd Tc (3.6)
Eleak = Io exp( Vth +?VddnV
t
) [1 exp( VddV
t
)] Vdd l Cg VddI
o exp(Vdd?Vth+ VddnVt )[1 exp(?VddVt )]
(3.7)
Eleak = l Cg V
2
dd
exp(VddnVt) (3.8)
26
Table 3.1: PTM 32nm Bulk CMOS Vth Calculated in HSPICE.
NMOS PMOS
HS model 0.328 V -0.291 V
LP model 0.549 V -0.486 V
On the other hand, dynamic energy is only dependent on the e?ective switching capac-
itance of the circuit as well as the supply voltage, as shown in Equation (3.9). The e?ective
switching capacitance is calculated as the product of gate output activity and output ca-
pacitance. Gate output activity can be estimated through logic simulations in Modelsim.
The total number of 0 ! 1 transitions at the gate output divided by the number of applied
random vectors is gate output activity.
FromEquations(3.8)and(3.9), wecanseethatthetotaltotalenergypercycle(EPC)for
single-Vth design is independent of Vth. Its complete expression is shown in Equation (3.10).
Edyn = Ceff V2dd (3.9)
E = Edyn +Eleak = Ceff V2dd + l Cg V
2
dd
exp(VddnVt) (3.10)
3.2 Simulation
HPICE simulations are conducted to verify the theory stated above. We utilize 32nm
Predictive Technology Model (PTM) technology developed by Arizona University. It o?ers
two types of NMOS and PMOS models for di?erent purposes ? high speed (HS) model and
low power (LP) model. The HS model o?ers low Vth and the LP model o?er high Vth, their
threshold voltage values calculated at nominalVdd = 0.9V in HSPICE are shown in Table 3.1.
Since PTM 32nm Bulk CMOS technology only o?ers models for NMOS and PMOS
transistors, we construct CMOS logic gates with NMOS transistor width Wn = 5L and
PMOS transistor width Wp = 12L for HSPICE simulations.
27
0.1 0.2 0.3 0.4 0.5 0.6
2
3
4
5
6
7
8 x 10
?14
Vdd (V)
Energy Per Cycle (J)
HP model (Low Vth)
LP model (High Vth)
Figure 3.1: 32-bit RCA energy calculated by HSPICE using PTM 32nm Bulk CMOS tech-
nology with Wn = 5L and Wp = 12L.
For the Vdd range between 0.12V and 0.6V, ?rst we calculate the critical path delay (Tc)
of the RCA by applying critical path vectors to primary inputs. The logic function of RCA
fails, when the Vdd is below 0.12V. Second, ?ve hundred random vectors are applied to the
RCA with time interval of Tc to calculate the total energy consumption per cycle, which
consists of dynamic energy and leakage energy.
The EPC for the two single threshold voltage circuits, as functions of Vdd, computed in
HSPICE simulations with random input vectors are shown in Figure 3.1. The red curve is
for lowVth and the blue curve is for highVth. We notice that EPC for the two designs remain
practically same over the sub-threshold supply voltage range Vdd = 0.12V to Vdd = 0.4V. As
28
Vdd scales down, EPC decreases, reaching a minimum at the same Vddopt just above 300mV.
When Vdd decreases further, EPC increases as leakage energy dominates. Logic operations
break down earlier, at about Vdd = 200mV, for high Vth. The low Vth design continues to
work at lower Vdd.
29
Chapter 4
Dual-Vth Design of Sub-threshold Circuits
In this chapter, we demonstrate that energy per cycle of sub-threshold circuits can be
reduced by the dual-Vth approach. We propose a gate-slack based dual-Vth algorithm for
minimum EPC operation. For a given circuit and low threshold voltage level, the proposed
algorithm is able to ?nd the optimal high threshold voltage level, optimal sub-threshold
supply voltage (Vddopt), generate an optimal dual-Vth design and accurately estimate the
EPC. Experimental results on a dual-Vth 32-bit ripple carry adder show a 29% EPC reduction
at minimum EPC point over its single-Vth version [211].
4.1 The Proposed Dual-Vth Design Framework
The dual-Vth method utilizes the characteristics of two di?erentVth levels. A lowVth gate
has larger gate delay but higher leakage current, while a high Vth gate has smaller gate delay
but less leakage current. In general, gates on critical path(s) use low Vth to maintain circuit
speed and gates on o?-critical paths use high Vth to suppress leakage current. Therefore, the
dual-Vth algorithm generally begins with assigning low Vth to all of the gates in the circuit,
then properly selecting as many gates as possible to switch to high Vth to suppress leakage
power consumption [56]. As a result, critical-path gates are normally assigned lowVth to keep
circuit with fast speed and o?-critical-path gates are normally assigned high Vth to reduce
leakage. However, the tricky part is that it is not appropriate to assign high Vth to every
non-critical path gate since the circuit performance may be degraded signi?cantly. Since
energy per cycle (EPC) is the product of power and circuit performance, energy reduction
should be a more appropriate criteria in dual-Vth algorithm compared to power reduction.
Therefore, we propose a gate slack based dual-Vth algorithm to maximize EPC reduction.
30
Table 4.1: Threshold voltages of NMOS and PMOS in PTM 32nm bulk technology calculated
by HSPICE with Wn = 5L and Wp = 12L
NMOS PMOS
HP model 0.328 V -0.291 V
LP model 0.549 V -0.486 V
For a given circuit and a low Vth level, the proposed dual-Vth algorithm generates the
optimal dual-Vth design, accurately determines an optimal high Vth level, and an optimal
supply voltage Vddopt, as well as estimates the energy saving.
4.1.1 The Method of Obtaining Low Vth and High Vth gates
(A) PTM 32nm Bulk CMOS Technology Models
PTM 32nm Bulk CMOS technology o?ers two types of models for MOSFET transistors
? a High Speed (HS) model and a Low Power (LP) model. The HS model o?ers low Vth, and
thus results in smaller gate delay and more leakage current. On the contrary, the LP model
o?ers high Vth, and thus results in larger gate delay and less leakage current. Table 4.1 lists
the threshold voltage of NMOS and PMOS transistors calculated by HSPICE using the two
models at nominal supply voltage Vdd = 0.9V.
(B) Low Vth Gate and High Vth Gate
For a MOSFET transistor, it is common to adjust its threshold voltage by applying a
source-bulk bias voltage. To be more speci?c, reverse bias voltage is often used to increase
the threshold voltage and forward bias voltage is often used to decrease the threshold voltage.
To construct a low Vth gate, we use the original HS model with zero source-bulk voltage.
AsillustratedinFigure4.1, thelowVth two-inputNANDgateisconstructedbygroundingthe
bulk terminals of NMOS transistors and connecting the bulk terminals of PMOS transistors
to Vdd. On the contrary, to construct a high Vth gate, we use the HS model with non-zero
reverse source-bulk bias voltage. As illustrated in Figure 4.2, high Vth two-input NAND gate
should be constructed by connecting the bulk terminals of NMOS transistors to a voltage
31
Figure 4.1: Two-input low Vth NAND gate.
supply more negative than ground and connecting the bulk terminals of PMOS transistors
to a voltage supply more positive than Vdd.
Figure 4.2: Two-input high Vth NAND gate implemented with reverse bias voltage = 0.1V.
The threshold voltage of a transistor increases as the reverse bias voltage increases.
Multiple levels of high Vth are provided in the proposed framework. The threshold voltage
32
Table 4.2: Vth calculated by HSPICE in PTM 32nm bulk CMOS technology with varying
source-bulk voltages with Wn = 5L and Wp = 12L.
NMOS PMOS
HS model w/ zero bias 0.328 V 0.291 V
HS model w/ bias=0.1V 0.348 V 0.309 V
HS model w/ bias=0.2V 0.367 V 0.327 V
HS model w/ bias=0.3V 0.385 V 0.344 V
HS model w/ bias=0.4V 0.402 V 0.360 V
HS model w/ bias=0.5V 0.419 V 0.375 V
HS model w/ bias=0.6V 0.435 V 0.389 V
HS model w/ bias=0.7V 0.450 V 0.403 V
HS model w/ bias=0.8V 0.465 V 0.417 V
of an NMOS transistor calculated in HPSICE at nominal Vdd = 0.9V under varying reverse
bias voltages are listed in Table 4.2.
4.1.2 Library Characterization
Before proceeding to the interpretations of the proposed dual-Vth algorithm, we need to
characterize libraries for delay, leakage power consumption and nodal capacitance under vary-
ing conditions for basic types of logic gates with characteristic sizing. In the proposed frame-
work, characterizations are included for the following types of logic gate: inverter, bu?er,
two-input NAND (NAND02), three-input NAND (NAND03), two-input NOR (NOR02),
three-input NOR (NOR03), two-input AND (AND02), three-input AND (AND03), two-
input OR (OR02) and three-input OR (OR03). Library characterization is done through
HSPICE simulations in PTM 32nm bulk CMOS technology with the characteristic sizing as
Wn = 5L and Wp = 12L.
(A) Gate Delay
For a single gate, di?erent conditions ofVth, Vdd and the number of fan-out input vectors
would result in di?erent values of gate delay. The Vdd range included in the framework is
between 0.12V and 0.6V. Gate delay with di?erentVth values, which are obtained by applying
33
Table 4.3: Low Vth NAND02 gate delay calculated by HSPICE in PTM 32nm bulk CMOS
technology with single fan-out to an inverter load under varying input vectors at Vdd = 0.2V
with Wn = 5L and Wp = 12L.
Input Vectors Delay
00 ! 11 1.7620E-08 S
01 ! 11 1.4171E-08 S
10 ! 11 1.5190E-08 S
11 ! 00 1.6059E-08 S
11 ! 01 1.3137E-08 S
11 ! 10 1.5424E-08 S
source-bulk bias voltages to the HS model, are calculated in HSPICE simulations as well.
Besides, in order to obtain di?erent fan-out conditions, a single gate drives di?erent numbers
of inverters with characteristic sizing at its output node. As for di?erent input vectors, we
calculate gate delay under all possible combinations of input vectors and take the maximum
of the calculated values. For example, for Vdd from 0.12V to 0.6V, we calculate NAND02
gate delay with fan-out load ranging from one inverter to 10 inverters with the following
input vectors, (00 ! 11), (01 ! 11), (10 ! 11), (11 ! 00), (11 ! 01) and (11 ! 10).
In order to illustrate the in?uence of input vectors on gate delay, Table 4.3 lists the
calculated delay of a low Vth NAND02 gate with one inverter as load under varying input
vectors at Vdd = 0.2V. As shown, vector pair (00 ! 11) generates the largest delay which
will be used in the gate delay library. Table 4.4 shows the impact of supply voltage Vdd on
gate delay. It lists the calculated delay of the NAND02 gate with fan-out condition changing
from one inverter to ten inverters at Vdd = 0.2V and Vdd = 0.4V, respectively. Table 4.5
lists the calculated NAND02 gate delays with one inverter as load with varying Vth levels
at Vdd = 0.2V. The varying Vth levels are obtained by applying a reverse source-bulk bias
voltage to the PTM 32nm HS model.
(B) Leakage Power Consumption
For a single gate, the following parameters a?ect its delay ? Vdd, Vth and input vectors.
Similar to the characterization of gate delay, we calculate leakage power of logic gates under
34
Table 4.4: Low Vth NAND02 gate delay calculated by HSPICE in PTM 32nm bulk CMOS
technology with fan-out varying from one inverter to ten inverters at Vdd = 0.2V and Vdd =
0.4V with Wn = 5L and Wp = 12L.
Vdd = 0.2V Vdd = 0.4V
fo = 1 inv 1.7620E-08 S 3.0194E-10 S
fo = 2 inv 2.2776E-08 S 3.4879E-10 S
fo = 3 inv 2.6689E-08 S 4.0520E-10 S
fo = 4 inv 3.2040E-08 S 4.5757E-10 S
fo = 5 inv 3.8014E-08 S 5.1891E-10 S
fo = 6 inv 4.5034E-08 S 5.8038E-10 S
fo = 7 inv 5.2394E-08 S 6.7758E-10 S
fo = 8 inv 6.0028E-08 S 7.3543E-10 S
fo = 9 inv 6.7673E-08 S 7.8842E-10 S
fo = 10 inv 7.5213E-08 S 8.4028E-10 S
Table 4.5: NAND02 gate delay calculated by HSPICE in PTM 32nm bulk CMOS technology
with one inverter as load at Vdd = 0.2V with Wn = 5L and Wp = 12L under varying reverse
source-bulk bias voltages.
Bias Voltage Delay
Zero Bias 1.7620E-08 S
Bias = 0.1V 3.1674E-08 S
Bias = 0.2V 5.9140E-08 S
Bias = 0.3V 1.0263E-07 S
Bias = 0.4V 1.8353E-07 S
Bias = 0.5V 3.1555E-07 S
Bias = 0.6V 5.1736E-07 S
Bias = 0.7V 8.9194E-07 S
Bias = 0.8V 1.4136E-06 S
di?erent conditions from HSPICE simulations. As for di?erent input vectors, we calculate
the leakage power with all possible input vectors and take the average of the calculated values.
Take the NAND02 gate for example, for a Vdd range from 0.12V to 0.6V, we apply di?erent
source-bulk bias voltages to obtain di?erent high threshold voltage levels and calculate gate
delay with four di?erent input vectors.
35
Table 4.6: Low Vth NAND02 gate leakage power calculated by HSPICE in PTM 32nm bulk
CMOS technology with fan-out as one inverter under varying input vectors at Vdd = 0.2V
with Wn = 5L and Wp = 12L.
Input Vectors Leakage Power
00 1.5831E-11 W
01 4.7944E-11 W
10 3.6800E-11 W
11 2.6519E-11 W
Table 4.7: NAND02 gate leakage power calculated by HSPICE in PTM 32nm bulk CMOS
technology with varying reverse source-bulk bias voltages with fan-out as one inverter at
Vdd = 0.2V with Wn = 5L and Wp = 12L.
Bias Voltage Leakage Power
Zero Bias 6.3439e-011 W
Bias = 0.1V 3.2603e-011 W
Bias = 0.2V 1.7515e-011 W
Bias = 0.3V 1.0133e-011 W
Bias = 0.4V 6.6668e-012 W
Bias = 0.5V 5.2779e-012 W
Bias = 0.6V 5.0516e-012 W
Bias = 0.7V 4.8355e-012 W
Bias = 0.8V 4.7337e-012 W
Table 4.6 lists the calculated leakage power of the NAND02 gate with fan-out as one
inverter with varying input vectors at Vdd = 0.2V. Table 4.7 lists the calculated low Vth
NAND02 leakage power with fan-out as one inverter under varying Vth levels at Vdd = 0.2V.
(C) Output Node Capacitance
Nodal capacitance is needed in the proposed framework because it will be used to
calculate the e?ective switching capacitance of a gate in the calculation of dynamic energy.
It is found out that the nodal capacitance is mainly in?uenced by the threshold voltage of
the driving gate as well as its fan-out condition. To be noted is that the variations on the
threshold voltage of the driven gates or the loads are ignored in this library characterization
since these variations have little e?ect on the nodal capacitance of the driving gate. In
36
Table 4.8: Low Vth NAND02 gate nodal capacitance calculated by HSPICE in PTM 32nm
bulk CMOS technology with fan-out condition from one inverter to 10 inverters atVdd = 0.2V
and Vdd = 0.4V with Wn = 5L and Wp = 12L.
Vdd = 0.2V Vdd = 0.4V
fo = 1 inv 1.2656E-015 F 1.2644E-015 F
fo = 2 inv 1.7040E-015 F 1.6944E-015 F
fo = 3 inv 2.1424E-015 F 2.1244E-015 F
fo = 4 inv 2.5808E-015 F 2.5543E-015 F
fo = 5 inv 3.0192E-015 F 2.9843E-015 F
fo = 6 inv 3.4576E-015 F 3.4143E-015 F
fo = 7 inv 3.8961E-015 F 3.8442E-015 F
fo = 8 inv 4.3345E-015 F 4.2742E-015 F
fo = 9 inv 4.7729E-015 F 4.7041E-015 F
fo = 10 inv 5.2113E-015 F 5.1341E-015 F
addition, supply voltage Vdd has small but noticeable in?uence on gate nodal capacitance.
Therefore, in summary, nodal capacitance of a gate is calculated with varying Vth of the
driving gate and varying fan-out conditions, with Vdd ranging from 0.12V to 0.6V.
Table 4.8 shows how nodal capacitance of a NAND02 gate changes as its fan-out con-
dition and Vdd changes. The NAND02 output node capacitance is calculated in HSPICE
with varying input vectors at Vdd = 0.2V and Vdd = 0.4V, respectively. Table 4.9 shows the
impact of threshold voltage of a NAND02 gate on its nodal capacitance. NAND02 output
node capacitance is calculated in HSPICE at Vdd = 0.2V with varying reverse source-bulk
bias voltages.
4.1.3 Gate Slack Based Dual-Vth Algorithm
Before proceeding to the detailed explanation of the dual-Vth algorithm, let us declare
some important parameters used in this algorithm, as shown in Table 4.10.
The proposed framework ?rst reads in a given combinational circuit gate-level netlist
and analyses the structure of the circuit. It ?nds out the structural information for each
gate i, namely, its gate type, driving gate(s) and fan-out gate(s). Next, levelize all gates.
37
Table4.9: NAND02gatenodalcapacitancecalculatedbyHSPICEinPTM32nmbulkCMOS
technology with varying Vth with fan-out as one inverter at Vdd = 0.2V with Wn = 5L and
Wp = 12L.
Bias Voltage Output Node Capacitance
Zero Bias 1.2656E-015 F
Bias = 0.1V 1.2520E-015 F
Bias = 0.2V 1.2398E-015 F
Bias = 0.3V 1.2289E-015 F
Bias = 0.4V 1.2190E-015 F
Bias = 0.5V 1.2100E-015 F
Bias = 0.6V 1.2018E-015 F
Bias = 0.7V 1.1943E-015 F
Bias = 0.8V 1.1874E-015 F
Table 4.10: Parameters used in the proposed dual-Vth algorithm.
Parameter Name Description
N Total number of gates in the circuit
TPI (i) the longest time for an event to arrive from PI to gate i
TPO (i) the longest time for an event to reach a PO from gate i
DL (i) Gate delay of gate i with low Vth
DH (i) Gate delay of gate i with high Vth
D (i) Gate delay of gate iD (i) = DH (i) or DL (i)
DPi The path delay of the longest path through gate iDP (i) = TPI (i) +TPO (i) +D (i)
T Critical path delay of the circuit with low VthT = Max fDP (i)g where i = 1 N
Thigh Critical path delay of the circuit with high Vth
k k = Thigh/T
S (i) Slack of gate iS (i) = T DP (i)
Delta (i) Delay di?erence of gate iDelta (i) = DH (i) DL (i)
S (i) Upper bound of gate slackS
u =
(k?1)?T
k
Sl Lower bound of gate slackS
l = Min fDelta (i)g where i = 1 N
38
Figure 4.3: One-bit full adder.
Levelizing basically means how far gate i is away from primary inputs or primary outputs.
For example, if the inputs of a gate are primary inputs of the circuit, this gate is levelized
as level 0 from the primary input. Let?s take an one-bit full adder for example. As shown
in Figure 4.3, gate 1 is marked as level 0 from primary inputs since both of its inputs are
primary inputs. As for gate 2, one of its inputs is a primary input and the other input is the
output of gate 1. Gate 2 is marked as level 1 since it is one level after a level 0 gate. When
a gate has multiple inputs with di?erent levels, this gate?s level is determined by the input
with the largest level.
After the circuit structural analysis and levelization, the following steps will be con-
ducted for given a Vdd and low Vth level,
Step (1) Initialize every gate with low Vth
Assigning low Vth to gate i means that its D (i) will be assigned with DL (i) which is
read from the delay library based on its number of fan-outs. The following parameters for
gate i are calculated as well: TPI (i), TPO (i), DP (i) and S (i). At the same time, circuit
delay with low Vth, T, can be calculated.
39
For any given high Vth level, Thigh can be calculated in a similar way, with every gate
assigned with high Vth. As a result, the ratio of Thigh and T, k, can be calculated, as well as
Su and Sl.
Step (2) First round of dual-Vth gate selection
Based on the values of Su and Sl, we conduct analysis on gate slack S (i). The gates
whose gate slack S (i) Delta (i) (4.4)
We ?rst sort them by the value of their gate slack, then switch them one by one from
low Vth to high Vth, starting from the gate with larger gate slack. The reason to begin with
the gates with large slack is that these gates most likely locate on path(s) with short length.
Threshold voltage changes on these gates are less likely to impact on circuit critical path
delay T. On the contrary, the gates with large slack generally locate on near-critical paths.
A slight gate delay increase can result in instant increase of circuit critical path delay.
The important constraint on high Vth selection is that T can not be exceeded. This is
required to ensure that the dual-Vth runs at its fastest possible frequency. In order to ensure
that, after one gate is switched from low Vth to high Vth, we run static timing analysis (STA)
by our framework to re-calculate circuit critical path delay Tnew. If Tnew is greater than T,
this gate can not be switched to high Vth since this switch will cause the appearance of larger
critical path delay therefore degrading the circuit performance.
Step (4) Estimation of energy per cycle (EPC)
At this step, a dual-Vth design is generated in terms of a list of gates that are assigned
with high Vth. Our framework then estimates its energy per cycle by Equation (4.5). Energy
per cycle of the entire circuit is the sum of that of each gate.
41
E =
n?
i=1
E (i) = Ceff (i) V2dd +Pleak (i) T = ? (i) C (i) V2dd +Pleak (i) T (4.5)
where Ceff;i V2dd represents the dynamic energy of gate i. Ceff;i is the e?ective switching
capacitance of the gate, which can be estimated by the product of gate nodal capacitance
and its activity factor. Pleak (i) T represents the leakage energy of gate i. As mentioned
earlier, C (i) and Pleak (i) are obtained from HSPICE simulations on basic logic gates. As
for activity factor ? (i) for each gate, we conduct logic simulation of an example circuit
with a single low Vth design in Modelsim. Five hundred (500) random vectors are applied at
primary inputs with a vector-period of T in Modelsim. Based on the simulated signals, we
count how many 0 ! 1 transitions occur at each gate output during the entire simulation
and then estimate ? (i) as the average number of transition per vector period.
4.2 Experimental Results
The topology of a circuit in?uences how much energy saving can be achieved by the
dual-Vth method.
We investigate our proposed algorithm for a 32-bit ripple carry adder (RCA) and a 4-by-
4 multiplier, as well as for ISCAS85 benchmark circuits. Among these, we believe that RCA
is an upper bound for energy saving since it has large number of short non-critical paths and
the path length di?erence between the critical path and non-critical paths is considerably
large. Therefore, it allows more gates to be switched to high Vth. On the other hand, the
multiplier is close to a lower bound case since its balanced structure allows only a small
portion of non-critical gates to have high Vth. Application to the 32-bit ripple carry adder
and 4-by-4 multiplier show that minimum EPC is reduced 29% and 10.8%, respectively,
at minimum EPC point. Experiments on ISCAS85 benchmark circuits demonstrate energy
saving in the range of 10% and 29%.
42
0.1 0.2 0.3 0.4 0.5 0.61
2
3
4
5
6
7
8 x 10
?14
Vdd (V)
Energy Per Cycle (J)
Single Vth, Low Vth
Dual Vth, Bias=0.1V
Dual Vth, Bias=0.2V
Dual Vth, Bias=0.3V
Dual Vth, Bias=0.4V
Dual Vth, Bias=0.5V
Dual Vth, Bias=0.6V
Dual Vth, Bias=0.7V
Dual Vth, Bias=0.8V
Figure 4.4: HSPICE simulation for energy per cycle (EPC) of 32-bit RCA single Vth designs
in PTM 32nm Bulk CMOS with Wn = 5L and Wp = 12L.
4.2.1 32-Bit Ripple Carry Adder
Figure 4.4 shows experimental results for 32-bit RCA in PTM 32nm bulk CMOS tech-
nology. It shows how EPC is lowered via optimized dual-Vth design. Supply voltage ranges
from 0.12V to 0.6V and we apply reverse body bias voltages to the example circuit in the
range between 0.1V to 0.8V. For any given Vdd, EPC decreases as bias voltage increases
until it reaches a lower bound. Then it starts to increase slowly, ?nally reaching the same
value as the single-Vth design. The lowest minimum energy occurs when the bias voltage
equals 0.3V, therefore the optimal high bias voltage is 0.3V. The minimum EPC in Figure
is 1.610 10?14J at Vddopt = 0.24V. The corresponding critical path delay is T = 1.2134?s,
resulting in a clock frequency of 0.8241MHz.
43
0 1 2 3 4 5
x 10?7
0
10
20
30
40
50
60
70
80
90
Slack time (S)
Number of gates
Figure 4.5: Gate slacks of single low Vth design of a 288-gate 32-bit RCA at Vdd = 0.25V.
Comparing two single-threshold designs in Figure 4.4 we note that the minimum EPC
is 2.268 10?14J at Vddopt = 0.31V. For low Vth circuit, T = 250.11ns or clock frequency
= 3.998MHz, and for high Vth circuit, T = 35.835?s or clock frequency = 27.9kHz. Thus,
EPC for the dual-Vth circuit is 29.1% lower than that for either of the single-Vth circuit. The
speed of the dual-Vth circuit is between the speeds of the two single-Vth circuits.
In order to show the impact of dual-Vth assignments on gate slack distributions for
all of the 288 gates in 32-bit RCA, Figure 4.5 and Figure 4.6 are presented. Since the
optimal supply voltage of single-Vth design are di?erent from that of dual-Vth design, it is
not appropriate to compare the slack di?erence of these two designs. Therefore, a ?xed
Vddopt = 0.25V is chosen and the gate slack data in single low Vth and dual-Vth designs are
compared. As seen, the number of gates with smaller slack increased after the dual-Vth
assignments.
44
0 1 2 3 4 5
x 10?7
0
10
20
30
40
50
60
70
80
90
Slack time (S)
Number of gates
Figure 4.6: Gate slacks of dual Vth design of 288-gate 32-bit RCA with bias voltage = 0.3V
at Vdd = 0.25V.
More high Vth gates will lead to higher leakage power saving. But it is not appropriate
to assume that more high Vth gates will lead to higher energy saving since the reduction of
leakage energy only comes from a balance between reduction of leakage power and increase
of circuit delay. For varying Vdd, Figure 4.7 presents a relation between x (percentage of
high Vth gates) and the EPC of dual-Vth designs normalized to the minimum EPC of single
low Vth design. For a ?xed Vdd, di?erent high Vth levels result in di?erent values of x. On
the other hand, for a ?xed high Vth level, there is a Vddopt which consumes minimum EPC.
Figure 4.8 compares estimated EPC of dual-Vth designs with HSPICE simulation. The
average error between the estimation and simulation is 6.99%. The error may result from
simpli?cations made in the framework. For example, we assume that fan-out gates are
always low Vth gates when calculating output capacitance of the driving gate in HSPICE.
45
0 0.2 0.4 0.6 0.8 10.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
X (percentage of high vth gates)
Normalized Energy Per Cycle (J)
vdd=0.2V
vdd=0.25V
vdd=0.3V
vdd=0.35V
Figure 4.7: Energy savings vs. percentage of high Vth gates from HSPICE simulation results
of a 124-gate 32-bit RCA dual Vth designs under varying Vdd values.
That is, when a gate drives high Vth gates, the di?erence in output capacitance is considered
negligible.
4.2.2 4-by-4 Multiplier
Experimental results on a 4-by-4 multiplier showing a 10.8% reduction of minimum EPC
by the dual-Vth method. The minimum EPC drops from 7.5954E-15 J in single-Vth design at
Vdd = 0.26V with a frequency of 4.29 MHz to 6.77E-15 J in dual-Vth design at Vdd = 0.21V
with a frequency of 1.76 MHz. The optimal high Vth in the above optimal dual-Vth design is
obtained when bias voltage = 0.2V.
46
0.1 0.2 0.3 0.4 0.5 0.61
2
3
4
5
6
7 x 10
?14
Vdd (V)
Energy Per Cycle (J)
HSPICE Simulation
Estimation
Vddopt = 0.25V
Vddopt = 0.24V
Figure 4.8: Random-vector HSPICE simulation results vs. estimation results for energy per
cycle (EPC) for 124-gate 32-bit RCA dual-Vth design with reverse body bias voltage = 0.3V.
Table 4.11: 4-by-4 Multiplier single-Vth design vs. dual-Vth minimum EPC saving.
Circuit Name Single Vth Design Dual Vth Design EnergyEmin Emin Saving
C432 7.5954E-15 J 6.77E-15 J 10.8%
Figure 4.9 shows the gate slacks for all of the 124 gates in single low Vth design of 4-by-4
multiplier at Vdd = 0.21V. Figure 4.10 shows the gate slacks for all of the 124 gates in dual
Vth design of 4-by-4 multiplier with bias voltage = 0.2V at Vdd = 0.21V.
4.2.3 ISCAS85 Benchmark Circuits
Experimental results on ISCAS85 benchmark circuits are listed in the two following
tables. Table 4.12 lists the minimum EPC points in single-Vth design and dual-Vth design of
47
0 1 2 3 4 5
x 10?7
0
10
20
30
40
50
60
70
80
90
Slack time (S)
Number of gates
Figure 4.9: Gate slacks of single low Vth design of 4-by-4 multiplier at Vdd = 0.21V.
benchmark circuits as well as energy saving. Table 4.13 lists the calculated optimal Vddopt as
well as optimal source-bulk voltage.
Table 4.12: ISCAS85 benchmark circuit HPICE simulation results on energy saving.
Circuit Name Single Vth Design Dual Vth Design EnergyEmin Emin Saving
C432 7.21E-15 J 6.32E-15 J 12.4%
C499 2.12900E-014 J 1.8478E-014 J 13.2%
C880 1.4315E-014 J 1.0613E-014 J 25.86%
C1355 1.9784E-014 J 1.7355E-014 J 12.28%
C1980 3.1425E-014 J 2.6862E-014 J 14.52%
C2670 5.09E-014 J 3.71E?14 J 27.1%
48
0 1 2 3 4 5
x 10?7
0
10
20
30
40
50
60
70
80
90
Slack time (S)
Number of gates
Figure 4.10: Gate slacks of dual Vth design of 4-by-4 multiplier with bias voltage = 0.2V at
Vdd = 0.21V.
Table 4.13: ISCAS85 benchmark circuit HPICE simulation results onVddopt and optimal bias
voltage.
Circuit Name Single Vth Design Dual Vth Design Optimal BiasV
ddopt Vddopt
C432 0.28 V 0.26 V 0.2 V
C499 0.27 V 0.26 V 0.2 V
C880 0.25 V 0.22 V 0.3 V
C1355 0.26 V 0.24 V 0.2 V
C1980 0.27 V 0.25 V 0.3 V
C2670 0.22 V 0.19 V 0.2 V
49
Chapter 5
Analysis of Results
5.1 Overview
Dual-Vth design for above-threshold circuits aims to reduce only leakage power but
doesn?t have requirements on circuit performance. Di?erent from above-threshold circuits,
sub-threshold circuits aims at energy per cycle reduction. In general, energy per cycle reaches
its minimum in the sub-threshold region.
It is e?ective to lower the minimum EPC point by the dual-Vth approach. Minimum
EPC only occurs atVddopt where dynamic and leakage energy are equal. In addition, dynamic
energy is only dependent on e?ective switching capacitance and supply voltage. Therefore,
the reduction of minimum EPC only comes from the reduction of Vdd. Figure 5.1 illustrates
how dynamic energy and leakage energy changed as Vdd scales down and how Vddopt drops
from single low Vth design to dual Vth design. In order to calculate dynamic and leakage
energy, the following steps are done. First, leakage power of a 32-bit RCA is calculated in
HSPICE by simulating with ?ve hundred random vectors. Second, the circuit critical path
delay is calculated in HSPICE simulations with a critical path vector. Third, ?ve hundred
random vectors are used in HSPICE simulations to calculate total energy per cycle. From
the ?rst two steps, we can get the leakage energy since it is the product of leakage power and
circuit delay. Then the dynamic energy can be calculated since it is the di?erence between
total energy per cycle and leakage energy.
As shown in Figure 5.1, the black curve represents the total EPC of a single low Vth
design. Total EPC is the sum of dynamic energy, shown as the red curve, and leakage
energy, shown as the blue curve. The green curve represents the leakage energy of the dual-
Vth design. For single Vth design, minimum EPC occurs in Vddopt1, which is the intersect of
50
0.1 0.2 0.3 0.4 0.5 0.60
1
2
3
4
5
6
7
8 x 10
?14
Vdd (V)
Energy Per Cycle (J)
Total E of single low Vth design
Dyn E
Leak E of single low Vth design
Leak E of dual Vth design
Vddopt1Vddopt2
Figure 5.1: HSPICE simulation results of dynamic energy vs. leakage energy for 32-bit RCA
single low Vth and dual-Vth design.
blue and red curves. For dual Vth design, minimum EPC occurs in in Vddopt2 which is the
intersect of the green and red curves. The Vddopt points can only move along the dynamic
energy curve.
5.2 Theoretical Analysis
In this section, a three-step theoretical analysis is conducted to understand the observed
energy saving for a 32-bit RCA in experimental results. For Vdd ranging from 0.12V to 0.4V,
energy and circuit delay of a 32-bit RCA are characterized into an equation to estimateVddopt
and the energy saving at minimum EPC points.
First, we characterize leakage power and circuit delay of the 32-bit RCA. Five hundred
random vectors are used to calculate the leakage power for single-Vth design with low Vth and
51
optimal high Vth, respectively. Circuit delay T is calculated from HSPICE simulation for
single low Vth design by applying a vector pair that activates the critical path. T determines
the fastest possible operating frequency of the circuit.
Second, we characterize leakage energy as a third-order polynomial in Vdd. We multiply
the leakage power and circuit delay from the previous step to get the leakage energy. The
total energy is,
E = Edyn +Eleak
= ? Ci V2dd +Ioff Vdd Tc
= ? Ci V2dd +Ioff Vdd Cg;iVddI
on
(5.1)
The leakage energy is related to Ion and Ioff that have exponential relationships to Vdd.
According to Euler?s formula, an exponential equation can be expanded as a polynomial.
Therefore, leakage energy can be expressed as a polynomial in Vdd. We use a third-order
polynomial in Vdd for accuracy and simplicity. To illustrate the goodness of curve-?tting,
Figure 5.2 and 5.4 show ?tting error for leakage energy with low Vth as root mean squared
error (RMSE) and R-squared (the square of the correlation between original data and ?tted
data), respectively. When polynomial degree increases from one to three, the RMSE drops
by two orders of magnitude then begins to drop much slower, while the R-squared saturates
almost to the best ?t value of 1. For leakage energy with optimal high Vth, we see similar
trends on RMSE and R-squared as shown in Figure 5.3 and 5.5. The ?tted expressions are,
Eleak;LVth = p1 V3dd +p2 V2dd +p3 Vdd +p4 (5.2)
where p1 = 2.916 10?12, p2 = 3.463 10?12, p3 = 1.401 10?12 and p4 = 1.953 10?13.
Eleak;HVth = h1 V3dd +h2 V2dd +h3 Vdd +h4 (5.3)
52
1 2 3 4 5 6 7 8 90
100
200
300
400
500
600
700
800
Polynomial degree
RMSE (E?17 J)
Low Vth
Figure 5.2: Root mean squared error analysis of polynomial ?t for leakage energy with low
Vth; a third-degree polynomial is selected.
where h1 = 3.413 10?13, h2 = 4.19 10?13, h3 = 1.75 10?13 and h4 = 2.54 10?14.
Third, we characterize dynamic energy as a second-order polynomial in Vdd. Since the
di?erence between total energy and leakage energy is the dynamic energy, we run HSPICE
simulations for 32-bit RCA to calculate total energy using the same set of random vectors.
According to Equation (5.1), dynamic energy is the product of e?ective switching capaci-
tance of the circuit and V2dd. Therefore dynamic energy is characterized as a second-order
polynomial in Vdd as,
Edyn = a V2dd +b (5.4)
where a = 1.653 10?13 and b = 2.103 10?16.
53
1 2 3 4 5 6 7 8 90
10
20
30
40
50
60
70
80
90
100
110
Polynomial degree
RMSE (E?17 J)
High Vth
Figure 5.3: Root mean squared error (RMSE) analysis of polynomial ?t for leakage energy
with high Vth; a third-degree polynomial is selected.
5.2.1 Single-Vth Design
The energy of a single low Vth design is,
Esingle = Edyn +Eleak;LVth
= p1 V3dd + (p2 +a) V2dd +p3 Vdd +p4
(5.5)
Setting the derivative of Esingle w.r.t. Vdd to 0, we write
?Esingle
?Vdd = 3p1 V
2
dd + 2(p2 +a) Vdd +p3 = 0 (5.6)
54
1 2 3 4 5 6 7 8 90.7
0.75
0.8
0.85
0.9
0.95
1
1.05
1.1
Polynomial degree
R?Squared
Low Vth
Figure 5.4: Regression coe?cent (R-squared) analysis of polynomial ?t for leakage energy
with low Vth; a third-degree polynomial is selected.
The minimum EPC occurs at Vddopt, which satis?es Equation (5.6). For a single low Vth
design, Vddopt = 0.3058V, which is close to 0.31V obtained from HSPICE simulation results
shown in Figure 3.1.
5.2.2 Dual-Vth Design
Let us de?ne a parameter x as the fraction of high Vth gates in the circuit. Then, 1 x
represents the fraction of low Vth gates in the circuit. The leakage energy for dual-Vth design
is expressed as,
Edual = Edyn +x Eleak;HVth + (1 x) Eleak;LVth
= K1 V3dd +K2 V2dd +K3 Vdd +K4
(5.7)
55
1 2 3 4 5 6 7 8 90.7
0.75
0.8
0.85
0.9
0.95
1
1.05
1.1
Polynomial degree
R?Squared
High Vth
Figure 5.5: Regression coe?cent (R-squared) analysis of polynomial ?t for leakage energy
with high Vth; a third-degree polynomial is selected.
where K1 = x h1 + (1 x) p1, K2 = x h2 + (1 x) p2 +a, K3 = x h3 + (1 x) p3
and K4 = x h4 + (1 x) p4 +b. Setting the derivative of Edual w.r.t. Vdd to 0, we get
?Edual
?Vdd = 3K1 V
2
dd + 2K2 Vdd +K3 = 0 (5.8)
Since our framework pointed out that the minimum EPC for dual-Vth design occurs
when x is equal to 0.6875, with optimal high Vth obtained by applying a bias voltage of 0.3V
to PTM 32nm HS model. Using this value of x, Equation (5.8) gives Vddopt = 0.254V, which
is close to 0.25V from HSPICE simulation results shown in Figure 4.4.
Based on the Vddopt values for single-Vth and dual-Vth design estimated by the above
equations, we found out that the minimum EPC point drops by 33.4%. This result is not
too di?erent from the 29% energy saving.
56
0 0.2 0.4 0.6 0.8 10
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
X (percentage of high vth gates)
Normalized Energy Per Cycle (J)
Single?Vth, PTM HS model
Single?Vth, PTM LP model
Dual?Vth, bias voltage=0.3V
Dual?Vth design energy estimation
Figure 5.6: HSPICE simulation results vs. theoretical analysis of energy ratio of 32-bit RCA
dual-Vth designs with bias voltage = 0.3V and single-Vth design.
Using di?erent values of x from 0 to 1 in Equation (5.8), we get the corresponding Vddopt
values, for which we calculate the minimum EPC for dual-Vth designs from Equation (5.7).
This is normalized with respect to the minimum EPC of a single-Vth design obtained from
Equation (5.5). The normalized energy of dual-Vth designs is shown as the blue curve in
Figure 5.6.
As seen from Figure 5.6, energy saving reaches its maximum of 67% when x equals 1.
However, realizable maximum energy saving is 29% when x equals 0.6875, as shown by the
red star in Figure 5.6. This discrepancy is explainable by the ?rst two steps of Section 5.
Leakage energy of single high Vth design by Equation (5.3) is the product of leakage power
of single high Vth design and circuit delay T obtained from single low Vth design. However,
in practice the circuit delay increases as the Vth in single-Vth design increases. Therefore, the
57
blue curve in Figure 5.6 only expresses a lower bound of energy saving for a 32-bit RCA. In
addition, the red circle in the upper left corner represents the minimum EPC point for single
low Vth design with PTM HS model. The red square in the upper right corner represents
the minimum EPC point for single high Vth design with PTM LP model. Both points are
normalized against the minimum EPC of a single low Vth design.
58
Chapter 6
Ultra-Low Voltage Circuit Under Process Variations
Process variations are unavoidable in modern semiconductor manufacturing processes.
The ?rst common source of variations comes from transistor geometric parameters, for ex-
ample transistor length, width and gate oxide thickness. The random dopant ?uctuations
(RDF) in transistor doping pro?le is another well-known source of variations. In general,
process variations are classi?ed into two types: global variations and local variations. Global
variations, also named as inter-die variations, refer to the systematic variations among dif-
ferent devices on a die. Global variations remain constant among di?erent devices when it
comes to a single die, while the same devices fabricated on di?erent dies would have di?erent
characteristics. On the other hand, local variations known as intra-die variations refer to
the random variations among di?erent devices on a die. Local variations are often portrayed
as random variables, which obey certain distributions. For example, delay variations are
normally considered as Gaussian random variables in the above-threshold regime.
The impact of process variation in sub-threshold regime has become an important con-
cern for sub-threshold circuit design [82, 95, 214]. Due to the exponential relation between
threshold voltage Vth and sub-threshold current Isub, sub-threshold circuits tend to be more
sensitive to process variations [82].
6.1 Previous Work
Much work has been done on studying the characteristic of process variation in the
sub-threshold region. Authors in [214] showed experimental results of sub-threshold circuits
with an industrial 130nm technology and demonstrated that random dopant ?uctuations are
the only dominant source of variations.
59
Researchers in [52] pointed out that RDF primarily brings uncertainties in threshold
voltage. Although correlations of process variation are shown as concerns in some works
[1, 127, 184], random uncorrelated Vth variation resulted from RDF was proved to be the
dominant component for sub-threshold circuit.
Authors in [145] provided the ?rst robust sub-threshold digital circuit in 2008. They
designed and implemented an 8-bit t-tap Finite Impulse Response (FIR) in 130nm IBM
technology. The FIR was reported to work at 280mV with a frequency of 9.8KHz. Later [183,
215], these authors proposed a sub-threshold 6T SRAM design with 130nm The SRAM can
function between 1.2V and 193mV and has good robustness characteristics in sub-threshold
region. This was the ?rst sub-threshold robust 6T SRAM design reported.
A variation-aware device sizing method emerged for minimum energy operation of sub-
threshold circuits in [95]. The authors pointed out the necessity of increasing the device
size in order to achieve a better yield. Authors in [169] suggested a leakage power reduction
method using dual-Vth and sizing under the existence of process variations. Aiming to provide
a higher yield for sub-threshold devices, researchers in [71] demonstrated a transistor-level
yield optimization technique to suppress variability in sub-threshold devices.
Another device sizing method to achieve higher yield was shown in [43]. Under the
constraints on circuit delay and desired yield the proposed method chose proper gate sizes
considering both inter- and intra-die variations. The proposed method can achieve 19%
saving in area.
In [111], authors o?ered a robust sub-threshold library as well as a post-silicon threshold
voltage tuning framework which utilized adjusting body bias voltage to suppress variations
under certain performance constraint. The tuning framework is implemented by a fuzzy
logic controller with input as circuit performance and output as the selected optimal body
bias voltage.
60
Table 6.1: PTM 32nm Vth variation characteristics.
Low Vth High Vth*
NMOS PMOS NMOS PMOS
W/L 160nm/32nm 384nm/32nm 160nm/32nm 384nm/32nm
?vth 0.328 V -0.291 V 0.385 V -0.344 V
?th 12 mV 7.5 mV 16.7 mV 10.1 mV
*achieved by applying 0.3 V reverse source-bulk bias voltage
on PTM HS model
In most previous work mentioned above on process variations in sub-threshold circuits,
random uncorrelated variations of threshold voltage resulted from RDF has been proved to
be the major type of variations for sub-threshold circuits.
In the sub-threshold region, Vth variations are generally characterized as random vari-
ables with Gaussian distribution, as seen in [43, 95, 214, 215].
The standard deviation of Vth variation distribution (?vth) is proportional to 1/pW L,
which is known as Pelgroms Law [134]. This rule has been used in many previous work and
became well recognized [43, 53, 95, 172, 214, 215]. A detailed ?vth expression was developed
targeted for RDF e?ect in MOS transistors in [171], as shown in Equation 6.1.
?vth =
4
?4q3??
2
Tox
?ox
4pN
pW L (6.1)
where ? = 2kTln(N/ni), k is Boltzmann?s constant, T is room temperature 300 K, ni is
intrinsic carrier concentration, N is channel dopant concentration, Tox is oxide thickness,
? is silicon permittivity, ?ox is silicon dioxide permittivity, W is transistor width and L is
transistor length.
The following Table 6.1 lists the mean value and standard deviation of Vth distribution
used in this chapter for NMOS and PMOS transistors.
61
0 0.2 0.4 0.6 0.8 1 1.2 1.4
x 10?7
0
0.5
1
1.5
2
2.5
3
3.5
4 x 10
7
NAND02 Gate Delay (S)
PDF
SPICE Simulation Data
Fitted Lognormal Distribution
Figure 6.1: Monte Carlo HSPICE simulations of NAND02 gate delay with three Inverters as
load at Vdd = 0.25V and source-bulk bias voltage = 0.3V in PTM 32nm Bulk CMOS with
Wn = 5L and Wp = 12L.
6.2 Impact of Variation
6.2.1 Gate delay
First, ?ve hundred Monte Carlo HSPICE simulations are conducted with random Gaus-
sian variations on Vth to learn how gate delay of an NAND02 gate is in?uenced. According
to the de?nition of log-normal distribution, if variable X has a normal (Gaussian) distribu-
tion, then Y = exp(X) has a log-normal distribution. For a MOSFET transistor, since its
sub-threshold current is exponentially related to Vth, its delay is exponentially related to Vth
as well. Therefore, as seen in Figure 6.1, gate delay obeys log-normal distribution when
Gaussian Vth variations are applied with characteristics shown in above Table 6.1. Table 6.2
shows distribution characteristics of a NAND02 gate delay under variations on Vth.
62
Table 6.2: Low Vth gate vs. high Vth gate delay under Gaussian Vth variations.
Mean STD Mean/STD
(Standard Deviation)
Low Vth Gate 9.3963e-009 2.0518e-009 4.5795
High Vth Gate 5.3228e-008 1.1895e-008 4.4749
6.2.2 Circuit Delay
Next, the critical path delay of a 32-bit RCA under variations is investigated by ?ve
hundred Monte Carlo HSPICE simulations with random Gaussian variations on Vth. The
circuit critical path delay is the sum of critical-path gate delays which have log-normal
distributions. Variations on each gate are random and uncorrelated. The sum of independent
log-normal random variables is proved to be a normal variable as in [13, 55, 151]. Therefore,
the circuit delay should obey normal distribution.
Figure 6.2 shows the HSPICE simulation results of the delay of single low Vth design of
a 32-bit RCA under variations. Similarly, Figure 6.3 shows the HSPICE simulation results
of the delay of dual Vth design of a 32-bit RCA under variations. The dual Vth design
investigated in Figure 6.3 is the optimal dual-Vth generated by the proposed framework.
This optimal dual-Vth corresponds to the minimum EPC point at Vdd = 0.25V with optimal
bias voltage = 0.3V. In both ?gures, the red curve represents the simulation data and the
blue curve represents the ?tted normal distribution.
6.2.3 Energy
Energy per cycle under process variations is the sum of many random Gaussian variables,
therefore it should obey normal distribution as well. In order to compare the EPC under
process variations of single low Vth design and dual-Vth design, both designs are simulated at
the same frequency. To ensure correct functionality of both designs, the operating frequency
63
0.85 0.9 0.95 1 1.05 1.1 1.15 1.2
x 10?6
0
2
4
6
8
10
12x 10
6
32?bit RCA Delay (S)
PDF
SPICE Simulation Data
Fitted Normal Distribution
Figure 6.2: Monte Carlo HSPICE simulations of circuit delay of 32-bit RCA single low Vth
design under random Vth Gaussian variations at Vdd = 0.25V in PTM 32nm Bulk CMOS
with Wn = 5L and Wp = 12L.
0.9 0.95 1 1.05 1.1 1.15 1.2
x 10?6
0
5
10
15x 10
6
32?bit RCA Delay (S)
PDF
SPICE Simulation Data
Fitted Normal Distribution
Figure 6.3: Monte Carlo HSPICE simulations of circuit delay of 32-bit RCA dual Vth design
with bias voltage = 0.3V under random Vth Gaussian variations at Vdd = 0.25V in PTM
32nm Bulk CMOS with Wn = 5L and Wp = 12L.
is chosen according to the maximum of ? + 3? points from the delay of both designs in
Figure 6.2 and Figure 6.3. The chosen frequency is 1/(1.1 10?6 second) = 0.91MHz.
64
1.4 1.42 1.44 1.46 1.48 1.5 1.52
x 10?13
0
0.5
1
1.5
2
2.5
3x 10
14
32?bit RCA EPC (J)
PDF
SPICE Simulation Data
Fitted Normal Distribution
Figure 6.4: Monte Carlo HSPICE simulations of EPC of 32-bit RCA single low Vth design
under random Vth Gaussian variations at Vdd = 0.25 V in PTM 32nm Bulk CMOS with
Wn = 5L and Wp = 12L.
8.5 8.6 8.7 8.8 8.9 9 9.1
x 10?14
0
1
2
3
4
5
6
7x 10
14
32?bit RCA EPC (J)
PDF
SPICE Simulation Data
Fitted Normal Distribution
Figure 6.5: Monte Carlo HSPICE simulations of EPC of 32-bit RCA dual Vth design with
bias voltage = 0.3 V under random Vth Gaussian variations at Vdd = 0.25 V in PTM 32nm
Bulk CMOS with Wn = 5L and Wp = 12L.
Figure 6.4 shows the HSPICE simulation results of EPC of single low Vth design of a
32-bit RCA under variations. Similarly, Figure 6.5 shows the HSPICE simulation results of
EPC of dual Vth design of a 32-bit RCA under variations. The dual Vth design investigated
65
in Figure 6.5 is the optimal dual-Vth generated by the proposed framework. This optimal
dual-Vth corresponds to the minimum EPC point at Vdd = 0.25V with optimal bias voltage
= 0.3 V. In both ?gures, the red curve represents the simulation data and the blue curve
represents the ?tted normal distribution.
66
Chapter 7
Conclusion and Future Work
This chapter provides the summary of this dissertation and some suggestions for the
future work.
7.1 Summary
As the density of modern SoC integration grows very fast to the range of billions or tril-
lions of transistors per square millimeter, the energy density per operation is going beyond
bearable limits. Therefore, energy consumption reduction has became a critical consideration
for digital and analog integrated circuits. This dissertation focuses on investigation and opti-
mization of sub-threshold circuits. When the supply voltage scales down to the sub-threshold
range, the energy consumption tremendously reduces. Moreover, sub-threshold circuits are
proven to be energy-e?cient since the minimum energy consumption point typically occurs
when Vdd is in sub-threshold range.
In Chapter 2, detailed background knowledge are provided on CMOS logic behavior
in sub-threshold region. Sub-threshold operation or weak-inversion operation of MOSFET
transistors has been ignored for a long time. Until the 1970s, researchers started to contribute
much work in this ?eld and validate the existence of sub-threshold current. Dependent on
this ?leaking? current, it is su?cient for the transistors to complete logic level transition
under a supply voltage below its threshold voltage. Literature review on the history of
sub-threshold circuit research is also presented. Dual-Vth technique is also reviewed in this
chapter. Since minimum energy operation is one of the highlights for sub-threshold circuits,
it is introduced as well.
67
In Chapter 3, single-Vth sub-threshold circuit design is investigated. It is revealed by
theoretical expression that the energy per cycle is not dependent on Vth. The increment of
Vth in single-Vth design does not reduce energy per cycle since the reduction of leakage power
consumption and the increase of circuit delay cancel each other out. In addition, this theory
is veri?ed by simulating a 32-bit ripple carry adder (RCA) in HSPICE with PTM 32nm Bulk
CMOS technology.
In Chapter 4, detailed interpretations of dual-Vth design framework are presented. The
framework consists of library characterization and dual-Vth assignment procedure which is
built on the gate slack based dual-Vth algorithm. For any given circuit, the framework reads in
a circuit?s gate-level netlist, analyzes the single low Vth design to get its minimum EPC ?rst,
then ?nds out the optimal high Vth level, optimal Vdd and optimal dual-Vth assignments.
The generated dual-Vth design reduces minimum EPC by 10% to 30% over its single-Vth
version. Experimental results on a 32-bit ripple carry adder, 4-by-4 multiplier and ISCAS85
benchmark circuits are shown.
In Chapter 5, theoretical analysis demonstrates the EPC saving from simulation results.
In Chapter 6, the impact of process variation on sub-threshold circuits is discussed, followed
by a brief introduction of the history of variation-aware sub-threshold circuit design.
7.2 Future Work
7.2.1 Challenge with Scaled Technology
As a result of technology scaling, the supply voltage and threshold voltage of MOSFET
transistors need to be reduced. Since dynamic energy is only related to switching capacitance
and supply voltage, it can remain in an acceptable range. However, the reduction of Vth
brings signi?cant increase of leakage energy. It is reported that the leakage has became a
more serious issue as technology goes into smaller scale. However, in [178, 80], the authors
suggested that the e?ectiveness of Body Bias as a leakage reduction method decreases as
68
technology scales down. Therefore, it is worth exploring dual-Vth technique in sub-32nm
technology.
7.2.2 Variation-Aware Design
In the proposed dual-Vth algorithm, we do not take process variations into account.
However, due to the exponential relation between sub-threshold current and threshold volt-
age, gate delay and leakage current are e?ected by Vth variations exponentially. Therefore,
sub-threshold circuits are more sensitive to process variations, compared to above-threshold
circuits. For variation-aware dual-Vth design, the proposed gate slack based algorithm should
update with some modi?cations. For example, during the procedure of library character-
ization stated in Chapter 2, gate delay should not be deterministic values. Instead, they
should be characterized as a random variable which obeys log-normal distribution. Besides,
the constraints in gate slack-based algorithm should be adjusted accordingly.
69
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