RF LINEARITY ANALYSIS IN NANO SCALE CMOS USING
HARMONIC BALANCE DEVICE SIMULATIONS
Except where reference is made to the work of others, the work described in this
thesis is my own or was done in collaboration with my advisory committee. This
thesis does not include proprietary or classifled information.
Deepika Kopalle
Certiflcate of Approval:
Adit Singh
James B. Davis Professor
Electrical and Computer Engineering
Guofu Niu, Chair
Professor
Electrical and Computer Engineering
Fa Foster Dai
Associate Professor
Electrical and Computer engineering
Stephen L. McFarland
Acting Dean, Graduate School
RF LINEARITY ANALYSIS IN NANO SCALE CMOS USING
HARMONIC BALANCE DEVICE SIMULATIONS
Deepika Kopalle
A Thesis
Submitted to
the Graduate Faculty of
Auburn University
in Partial Fulflllment of the
Requirements for the
Degree of
Master of Science
Auburn, Alabama
July 29, 2005
RF LINEARITY ANALYSIS IN NANO SCALE CMOS USING
HARMONIC BALANCE DEVICE SIMULATIONS
Deepika Kopalle
Permission is granted to Auburn University to make copies of this thesis at its
discretion, upon the request of individuals or institutions and at their expense.
The author reserves all publication rights.
Signature of Author
Date
Copy sent to:
Name Date
iii
Vita
Deepika Kopalle, eldest daughter of Panduranga Vittal Kopalle and Purna
Kopalle was born on Aug 7, 1978 in Hyderabad, India. She flnished her high school
from Ratna Junior College, Hyderabad in 1996 and entered Sri Krishnadevaraya
University for her Bachelors in Electronics and Communication Engineering in
1997. She joined Auburn University for her Masters in Electrical and Computer
Engineering in 2002 under the guidance of Dr.Guofu Niu.
iv
Thesis Abstract
RF LINEARITY ANALYSIS IN NANO SCALE CMOS USING
HARMONIC BALANCE DEVICE SIMULATIONS
Deepika Kopalle
Master of Science, July 29, 2005
(B.Tech.,SKDU,India,2001)
93 Typed Pages
Directed by Guofu Niu
In this thesis, Intermodulation Linearity characteristics of CMOS have been
analyzed using power series and Harmonic Balance(HB) Method. Harmonic Bal-
ance method is a frequency domain steady state analysis method used for solving
nonlinear circuits. This method is extended to semiconductor device simulation
using Taurus-Device tool. Third order Input Intermodulation Product (IIP3), a
measure for linearity is characterized as a function of channel length, oxide thick-
ness, drain and gate voltages using 130nm, 100nm and 90nm MOS devices. The
efiect of Polysilicon gate depletion on linearity is studied and analyzed for dif-
ferent doping concentrations. Further, the simulated IIP3 values obtained from
Harmonic Balance method are compared to the theoretical values calculated using
power series.
v
Acknowledgments
I would like to express my deepest gratitude to Dr. Guofu Niu for his con-
stant support and guidance. This thesis would not have been possible without his
motivation and encouragement. I would like to thank my committee members Dr.
Adit Singh and Dr. Foster Dai for their valuable input.
I am grateful to Dr. J.M.Wersinger from the Department of Physics and Dr.
Luke Marzen from Geology and Geography Department for their flnancial support
throughout my Master?s degree.
Thanks are due to Dr. Qingqing Liang from Georgia Tech., and my colleague
Ms. Yan Cui for their help in my research. I would like to extend special thanks to
my friend Ms. Sailaja Chilaka for her constant support and help in my research.
I am deeply indebted to my parents Mr. K.P.R.Vittal and Mrs. Purna Vittal
and my sister Ms. Manasa whose love and support gave me the strength to over-
come the hurdles throughout my career. I am grateful to all my friends at Auburn
for their love, support and encouragement towards achieving this goal.
vi
Style manual or journal used Journal of Approximation Theory (together with
the style known as \aums"). Bibliograpy follows van Leunen?s A Handbook for
Scholars.
Computer software used The document preparation package TEX (speciflcally
LATEX) together with the departmental style-flle aums.sty.
vii
Table of Contents
List of Figures x
1 INTRODUCTION 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Overview and Organization . . . . . . . . . . . . . . . . . . . . . . 3
2 HARMONICS AND INTERMODULATION BASICS 5
2.1 Harmonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Intermodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 HARMONIC BALANCE FUNDAMENTALS 11
3.1 Transient vs Harmonic Analysis . . . . . . . . . . . . . . . . . . . . 11
3.2 Harmonic Balance Method and Example . . . . . . . . . . . . . . . 12
3.2.1 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Application to Device Simulation . . . . . . . . . . . . . . . . . . . 15
3.3.1 Implementation in TAURUS Tool . . . . . . . . . . . . . . . 16
3.3.2 Multi-tone Simulation . . . . . . . . . . . . . . . . . . . . . 18
4 RF CMOS LINEARITY 20
4.1 RF Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2 First Order Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 100nm MOSFET SIMULATION RESULTS 25
5.1 DC Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2 AC Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3 HB Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.4 Characterization of IIP3 . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4.1 Vgs and Vds Dependence . . . . . . . . . . . . . . . . . . . . 31
5.4.2 Channel Length Dependence . . . . . . . . . . . . . . . . . . 35
5.4.3 Oxide Thickness . . . . . . . . . . . . . . . . . . . . . . . . 37
5.5 Simulation and Theoretical Analysis . . . . . . . . . . . . . . . . . 39
viii
6 POLYGATE DEPLETION EFFECT 43
6.1 Background of Polysilicon Gate . . . . . . . . . . . . . . . . . . . . 43
6.2 Scaling of MOS devices . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.3 Poly Depletion Efiect . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3.1 Efiect on Gate Capacitance . . . . . . . . . . . . . . . . . . 47
6.3.2 Efiect on IIP3 . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7 HALO DOPING 53
7.1 MOS 90nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.2 Harmonic Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.3 Discrepancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8 CONCLUSIONS AND FUTURE WORK 58
8.0.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Bibliography 60
A 63
ix
List of Figures
2.1 Harmonics and third order intermodulation products. . . . . . . . . 8
2.2 First and third order output powers vs input power. . . . . . . . . . 9
3.1 A Diode excited by an RF circuit. . . . . . . . . . . . . . . . . . . . 13
3.2 Equivalent Circuit describing the Linear part. . . . . . . . . . . . . 13
3.3 Equivalent Circuit describing the Nonlinear part. . . . . . . . . . . 14
4.1 First and third order output powers vs input power. . . . . . . . . . 21
4.2 I-V characteristics and the corresponding gm;gm2;gm3 vs Vgs. . . 24
5.1 Doping proflles using a cut-line through the channel. . . . . . . . . 25
5.2 MOS 100nm mesh structure. . . . . . . . . . . . . . . . . . . . . . . 26
5.3 Id ?Vg curves for three difierent values of Vds. . . . . . . . . . . . . 27
5.4 Cutofi frequency(fT) vs Drain Current. . . . . . . . . . . . . . . . . 28
5.5 First and third order output powers vs input power. . . . . . . . . . 29
5.6 IIP3 vs Vgs for difierent Vds values. . . . . . . . . . . . . . . . . . . 31
5.7 gm, gm2, gm3, gm3=gm vs Vgs for 100nm MOS, W=1um. . . . . . . 32
5.8 IIP3 vs Ids for difierent Vds values. . . . . . . . . . . . . . . . . . . . 33
5.9 Gain vs Vgs for difierent Vds values. . . . . . . . . . . . . . . . . . . 34
5.10 gm3 vs Vgs for difierent channel lengths. . . . . . . . . . . . . . . . . 35
5.11 IIP3 vs Vgs for difierent channel lengths. . . . . . . . . . . . . . . . 36
5.12 IIP3 vs Ids for difierent channel lengths. . . . . . . . . . . . . . . . 37
x
5.13 IIP3 vs Vgs for difierent oxide thickness. . . . . . . . . . . . . . . . 38
5.14 IIP3 vs Ids for difierent oxide thickness. . . . . . . . . . . . . . . . . 39
5.15 Gain vs Ids for difierent oxide thickness, L=130nm, W=1um. . . . . 40
5.16 Simulated and theoretical values of IIP3 vs gate voltage Vgs. . . . . 41
5.17 Simulated and theoretical values of IIP3 vs drain current Ids. . . . . 42
6.1 gm3 vs gate voltage(Vgs )for two difierent technologies. . . . . . . . . 44
6.2 Band diagram of n+ poly gate MOS structure. . . . . . . . . . . . . 45
6.3 gm3 vs gate voltage(Vgs )with and without poly depletion. . . . . . . 46
6.4 gm3 vs gate voltage(Vgs )for two difierent polydoping concentration. 47
6.5 gm3 versus gate voltage(Vgs )for two difierent for Vds values. . . . . . 48
6.6 Gate capacitance vs gate voltage for difierent poly gate doping con-
centration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.7 IIP3 vs gate voltage for difierent poly gate doping concentrations. . 50
6.8 IIP3 vs drain current for difierent poly gate doping concentrations. 51
6.9 Simulated and theoretical IIP3 values for difierent poly gate doping
concentrations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.1 Doping Proflle of 90nm NMOSFET along the channel. . . . . . . . 53
7.2 Doping proflle of 90nm NMOSFET across the channel. . . . . . . . 54
7.3 First and third order output powers vs input power. . . . . . . . . 55
7.4 gm;gm2;gm3 vs Vgs. . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7.5 IIP3 vs Vgs for three difierent Vds values. . . . . . . . . . . . . . . . 57
7.6 Simulated and theoretical values. . . . . . . . . . . . . . . . . . . . 57
xi
Chapter 1
INTRODUCTION
With rapid growth of wireless communication systems, the use of CMOS tech-
nologies has been extended to RF applications. Many RF flgures of merit like cutofi
frequency and noise flgure have been improved with scaling. Semiconductor de-
vice simulations have proven to play a key role in the design and development of
Analog and RF systems. Thus, there has been an increasing need for analysis and
modelling of RF flgures of merit at semiconductor device level.
In this work, the efiects of technology scaling on linearity and RF distortion
have been analyzed using power series and Harmonic Balance(HB) method using
Taurus, a process and device simulation tool from Synopsys.
1.1 Background
Linearity is one of the key parameters for RFIC design and it refers to the
ability of a device, circuit or a system to amplify the input signal in a linear fashion
[1]. In an ideal system, the output is linearly related to the input. However, in
any real-time device or system the transfer function is more complicated, which
can be due to presence of active or passive devices in the circuit or signal swing
limitation of the power supply rails [1]. While all electronic circuits are mostly
nonlinear, some circuits such as small signal ampliflers are very weakly nonlinear,
hence are used in systems as if they are linear [2].
1
Nonlinearities in circuits have both advantages and disadvantages. Nonlinear-
ityisrequiredtotranslatefrequencyfrombasebandtoRFandviceversadepending
on whether the signal is transmitted or received. Nonlinearity is also necessary to
build an oscillator and to realize frequency multiplication used in frequency synthe-
sis. Inspite of the mentioned advantages, nonlinearity in circuits may also create
distortion in the desired signals. It causes intermodulation of two adjacent strongly
interfering signals at the input of a receiver, which can corrupt the nearby desired
weak signal [1]. Nonlinear circuits usually generate a large number of frequencies
and hence are more complicated to analyze when compared to linear circuits.
Nonlinearcircuitsareoftencharacterizedaseitherstronglynonlinearorweakly
nonlinear [2]. Strongly nonlinear circuits are very complicated and are analyzed
using HB or time domain methods. Weakly nonlinear circuits can be described
by Taylor series expansion of their nonlinear current-voltage(I-V) characteristics.
Most of the transistors and passive components are weakly nonlinear and are an-
alyzed using power series or Volterra series [2].
1.2 Motivation
Traditional time domain approaches though extremely efiective, often fall
short when applied to simulating steady state quantities such as harmonic dis-
tortion, due to long time constants or widely separated spectral components. Har-
monic balance, a nonlinear frequency domain analysis technique has emerged as
a widely accepted solution to many of the shortcomings that conventional time
2
domain simulators have in high frequency analog arena [3]. With the development
of commercial harmonic balance simulator and compact software, nonlinear fre-
quency domain analysis has assumed its current position as the method of choice
for simulating most nonlinear microwave and RF circuits.
HB simulation has been in use for quite some time to simulate harmonic and
intermodulation distortion at device level. In this work, HB method is applied to
the semiconductor device simulation using Taurus process and device simulation
tool.
1.3 Overview and Organization
This thesis is organized into 8 chapters. Chapter 2, discusses the basic con-
cepts of Harmonics, Intermodulation and the flgure of merits for linearity. In
Chapter 3, the advantages of HB over transient analysis are discussed. A brief
description of the solution methods used for HB simulation and its implementa-
tion in Taurus is presented. Chapter 4 gives an overview of RF CMOS linearity.
Transconductance gm and the efiect of third order gm nonlinearity coe?cient gm3
on linearity is described. In chapter 5, 100nm MOS HB simulation results are
presented and parametric analysis of IIP3 with channel length, oxide thickness is
presented. Simulation results are compared to the theoretical values obtained from
the power series. Chapter 6 discusses CMOS scaling and polysilicon gate deple-
tion efiects. Efiect of polydepletion on linearity is analyzed for difierent doping
concentrations of polygate. Chapter 7, extends the analysis for 90nm MOS device
3
with halo doping. Chapter 8, summarizes the work presented in this thesis and
also extends the scope of this work.
4
Chapter 2
HARMONICS AND INTERMODULATION BASICS
One of the important properties of a nonlinear system is its generation of
harmonics of the excitation/fundamental frequency. In narrow band systems, such
harmonics may not be a serious problem as they are far from the signals of interest
and are rejected by fllters [4]. In others, such as transmitters harmonics may
interfere with desired weak signal or other communication systems and must be
reduced using fllters.
Most of the nonlinearity concepts can be brie y analyzed using simple power
series. This technique is relatively simple but requires an unrealistic assumption
that the circuit contains only ideal memoryless transfer nonlinearities. However,
power series approach is useful in some instances and gives a good intuition of a
nonlinear circuit behavior. It is a simple mathematical representation, which gives
direct response of a nonlinear device or system in frequency domain. Hence, can
be easily applied to most analog, RF and microwave applications. For a small
signal input x(t), the output voltage y(t) of memoryless nonlinear circuit can be
expressed using power series as
y(t) = k1x(t)+k2x2(t)+k3x3(t)+??? (2.1)
5
for simplicity, higher order nonlinearity terms are not considered. Using power
series, the concepts of harmonics and intermodulation are discussed brie y in the
following sections. Most of the concepts presented here are directly extracted from
[1], [4], [5] with pertinent changes.
2.1 Harmonics
If a sinusoidal input x(t) = Acos!t is applied to a nonlinear circuit, the
output y(t) is given by
y(t) = k1Acos!t+k2A2 cos2 !t+k3A3 cos3 !t: (2.2)
Equation (2.2) can further be expressed as
y(t) = k2A
2
2 +(k1A+
3k3A3
4 )cos!t+
k2A2
2 cos2!t+
k3A3
4 cos3!t: (2.3)
In equation (2.3), flrst term is the dc shift, second term with the input frequency
is the \fundamental", and other higher order terms are the \Harmonics", which
are integral multiples of the fundamental frequency. For small A, higher powers of
A can be neglected and therefore, the nth harmonic is proportional to An.
6
2.2 Intermodulation
When two signals with difierent frequencies are applied to a nonlinear system,
the output exhibits some components that are harmonics of neither input frequen-
cies. Such frequencies, called Intermodulation (IM) products arise from the mixing
of two signals.
IM products in an amplifler or communication receiver create serious problems
since they represent spurious signals that interfere with and can be mistaken for
desired signals. If a two tone input voltage x(t) = Acos!1t+Acos!2t , is applied
to a nonlinear system then the output y(t) is given by
y(t) = k1(Acos!1t+Acos!2t)+k2(Acos!1t+Acos!2t)2+k3(Acos!1t+Acos!2t)3:
(2.4)
Expanding the above equation
y(t) =
k1A+ 3k3A
3
4 +
3k3A3
2
?
cos!1t+::: fundamental
+ 3k3A
3
4 cos(2!2 ?!1)t+::: intermodulation: (2.5)
It can be observed that the IM products are generally much weaker than the signals
that generate them. However two strong signals outside the passband may generate
an IM product which is within the passband, and which in turn may obscure the
desired weak signal at the same frequency [4].
7
Figure 2.1: Harmonics and third order intermodulation products.
Fig. 2.1 shows the fundamental and harmonics generated for strong two tone
interference. Even order IM products usually occur in frequencies well above or
below the signals that generate them, hence are of little concern. The IM products
of greatest concern are the third order IM products that occur at 2!1 ? !2 and
2!2 ? !1 frequencies. They are the strongest of all odd order products and are
close to the signals that generate them and often cannot be rejected by fllters.
The corruption of signal due to the third order intermodulation has trouble-
some efiects in RF systems and is very critical. Hence, a performance metric has
8
been deflned to characterize this behavior and is called \Third order intercept
point"(IP3) and can be measured by a two tone test. From equation 2.5 it can be
noticed that fundamentals increase proportional to A, whereas the third order IM
products increase proportional to A3. The third order intermodulation distortion
(IM3)is deflned as
IM3 = 3k3A
3
4 =k1A =
3
4
k3
k1A
2: (2.6)
Thus a 1-dB increase in input results in 1-dB increase in fundamental output while
3-dB increase in IM product. Fundamental output and IM3 product are plotted
versus input on a logarithm scale as shown in Fig.2.2.
Figure 2.2: First and third order output powers vs input power.
The third order intercept point is deflned as the intersection of the two lines.
ThehorizontalcoordinateofthispointiscalledtheinputIP3(IIP3)andthevertical
9
coordinate is called the output IP3(OIP3). IIP3 can be obtained by making IM3 =
1, hence
IIP3 =
r4k
1
3k3: (2.7)
IIP3 is more useful since it does not depend on the input signal level and can serve
as a means of comparing linearity of difierent circuits. IIP3 can be expressed in
terms of IM3 as
IIP3 = A
2
IM3: (2.8)
On log scale they can be expressed as
10logIIP3 = 20logA?10logIM3: (2.9)
Equation 2.9 can be rewritten in terms of power as
PIIP3 = Pin + 12(Po1st ?Po3rd): (2.10)
However, in practise if the input is increased to reach the intercept point,
higher order IM products may become signiflcant and in many circuits IP3 is
beyond the allowable input range. Thus, the practical method for obtaining the
IP3 is to measure the characteristics for small input amplitudes and use linear
interpolation on a log scale to flnd the intercept point.
10
Chapter 3
HARMONIC BALANCE FUNDAMENTALS
Harmonic balance analysis is one of the most important techniques used for
analyzing strongly or weakly nonlinear circuits that have single or multi tone ex-
citation. This method is based on balancing currents between the linear and non-
linear sub circuits, hence it is named so. Harmonic balance is used to calculate
steady state response of a circuit in frequency domain. The essential characteristic
of this method is to implement circuit equations in the frequency domain. It can
be summarized as the method where Kirchofi?s current law is formulated in the
frequency domain.
3.1 Transient vs Harmonic Analysis
Traditional time domain approaches often fall short when applied to simu-
lating the steady state response of systems with long time constants or widely
separated spectral components. For many high frequency (RF and microwave)
applications, the solution of the state equations by standard transient methods
can be prohibitively expensive. Harmonic balance solves the state equations in
the frequency domain, and is almost completely insensitive to widely varying time
constants, tone spacings and incommensurate frequencies. Transient analysis uses
standard numeric integration, constructs a solution as a collection of time samples
with an implied interpolating function. This interpolation is usually a polynomial
11
and polynomials flt sinusoids poorly, hence require more points to approximate si-
nusoidal solutions. Harmonic balance on the other hand uses a linear combination
of sinusoids to build the solution. Thus, periodic and quasi periodic signals found
in a steady state response can be approximated more accurately. It requires a
small data set if the steady state response consists of only few dominant sinusoids.
3.2 Harmonic Balance Method and Example
One ofthemajor di?culties with theharmonic balance approachistocompute
the response of the nonlinear device. It is di?cult to compute the coe?cients of
response directly from the coe?cients of the stimulus. Hence the coe?cients of the
stimulus can be converted into a sampled data representation, which implies a fre-
quency to time domain conversion. This can be done using Inverse Fourier Trans-
form. This conversion helps in determining the response of the nonlinear devices
accurately. The results are then back converted into coe?cient form(frequency
domain) using Forward Fourier Transform. The coe?cients of the steady state
response are now an algebraic function of the coe?cients of the stimulus. Thus
the nonlinear integro-difierential equations that describe a circuit are converted
by harmonic balance into a system of algebraic nonlinear equations , which when
solved give the steady state response of the circuit [6]. These equations can be
solved iteratively to get a steady state solution.
The basic implementation of the harmonic balance method has been explained
in [2] using a simple example and is presented here for better understanding.
12
3.2.1 Example
Figure 3.1: A Diode excited by an RF circuit.
Consider a simple circuit consisting of an RF source, a diode and an impedance
Z(!) as shown in Fig. 3.1. The diode when excited with an RF source at a
frequency!p generatesharmonicsofcurrentandvoltage. Also, Z(!)mayvarywith
the harmonic frequency hence, can be written as Z(k!p) where k is the harmonic
number. Assuming that the diode voltage consisting of its complex components at
all harmonic frequencies (k!p) is known, the circuit can be sub-divided into linear
and nonlinear circuits.
Figure 3.2: Equivalent Circuit describing the Linear part.
13
Figure 3.3: Equivalent Circuit describing the Nonlinear part.
The linear sub-circuit as shown in Fig. 3.2 can be analyzed in the frequency
domain as
Ilin(k!p) = V(k!p)?Vs(k!p)Z(k!
p)
(3.1)
where Vs is periodic. Using Fourier theory V(k!p) is converted into time waveform
V(t). Considering the nonlinear sub circuit as shown in Fig. 3.3, diode current
can be represented as
Inl(t) = Isat(exp(? ?V(t))?1) (3.2)
where ? = q?kT .
Using fourier transformations equation(3.2) can be converted to Inl(k!p). To
flnd out if V(k!p) is a solution, Kirchofi?s Current Law is applied at all harmonics
Ilin(k!p)+Inl(k!p) = 0; (3.3)
14
and an error function is deflned as
fk = Ilin(k!p)+Inl(k!p): (3.4)
Equation(3.1)and equation(3.2) are substituted in equation(3.3) at each harmonic.
If equation(3.3) is satisfled, then the solution is found else the assumed diode
voltage is modifled and the process is repeated. Appropriate numerical method is
used till fk becomes negligibly small.
As the number of ports increases, the above equations become complicated.
3.3 Application to Device Simulation
Large memory and CPU requirements have been the major obstacles for ap-
plication of the HB method to semiconductor device simulation. With the recent
use of iterative solution methods for solving large scale HB problems, this method
is applicable to device simulation on modern computer workstations.
HB method which is commonly used in circuit simulation has been imple-
mented into Taurus. This method when implemented in a device simulator has
many advantages:
? Non-quasi static efiects due to the distributed internal potentials and carrier
densities may be observed
? Tradeofis between the fabrication process and the resulting analog behavior
are more readily observed.
15
? Internal properties of the semiconductor device can be visualized.
? Many RF flgures of merit can be simulated e?ciently in the frequency do-
main.
TheHBmethodasimplementedinTaurusisdescribedinthefollowingsection.
Since the work of this thesis concentrates more on the application of this HB
method to device simulation, the detailed description of the solution methods are
not included. Details of this method can be obtained from [2], [6], [3].
3.3.1 Implementation in TAURUS Tool
In Taurus, the frequency domain solution of the periodically varying poten-
tial and carrier densities known as periodic steady state can be solved using HB
method.The details presented in the following sections have been extracted from
the Taurus manual [7]. If a periodic signal is applied to a semiconductor device at
a frequency f1, the nonlinear relationship between the applied potential and ter-
minal currents will result in harmonics at integer multiples of f1. The HB method
solves the periodic steady state at each of these frequencies simultaneously.
The total ux into the device at each node in a semiconductor device for each
carier type is zero. Thus at each node the sum of the current densities i(t)and the
accumulated number of carriers q(t) must be zero. This is represented as
i(t)+ @q(t)@t = 0: (3.5)
16
HB method ensures that this law is observed at each frequency, which implies
I(f)+j2?fQ(f) = 0 (3.6)
where I(f) and Q(f) are the frequency components of current and charge at fre-
quency f and j2?f represents the frequency domain equivalent of the time deriva-
tive operation. This equation needs to be solved for all frequencies simultaneously.
Using fourier analysis, we have
b = I +?Q = ?
2
66
66
66
66
4
i(0)
i(1)
:::
i(s?1)
3
77
77
77
77
5
+??
2
66
66
66
66
4
q(0)
q(1)
:::
q(s?1)
3
77
77
77
77
5
(3.7)
where ? is the fourier transform operator and ? is a diagonal matrix containing
the time derivative entries. i and q are evaluated over s time samples for each
node in the device. I and Q are the resulting current and charge vectors in the
frequency domain. When b = 0 HB solution is found.
To flnd such solution in frequency domain, an iterative technique such as
Newton?s method is used. To use this method a Jacobian matrix which relates the
changes in ux to the changes in the solution variables is required. The solution
variable is referred to as ?v? although there are atleast three solution variables per
17
node in the semiconductor device simulation. Once the Jacobian is known, the
solution can be found.
3.3.2 Multi-tone Simulation
Taurus supports upto three simultaneous tones using the multi dimension
fast fourier transform. Since the response at higher intermodulation orders is less
signiflcant,the simulator reduces the number of solution variables by removing any
frequencies that have a intermodulation order greater than that specifled for the
simulation.
The HB simulation is carried out as described above though the solution
method for multi tone simulation may difier. As the magnitude of input signal in-
creases, the number of frequencies to be solved also increases thus making Newton?s
method impractical.
A complex variant of a GMRES(Generalized Minimum residual) linear solver
is used in the HB simulation [3]. The problem to be solved for each nonlinear
iteration is then
r = AP?1X ?b (3.8)
where r is residual, P is the preconditioner matrix and X is solution update vector.
Linear solver tries to minimize r. The new HB solution for nonlinear iteration k
at the end of the linear solve is then
vk = vk?1 +P?1X: (3.9)
18
Preconditioner is deflned as
P = ?
2
66
66
66
66
4
?g
?g
:::
?g
3
77
77
77
77
5
+?
2
66
66
66
66
4
?c
?c
:::
?c
3
77
77
77
77
5
where
?g = 1S
s?1X
s=0
g(s)
?c is deflned similar to ?g and S is the number of time samples required. Precondi-
tioner is equivalent to the HB Jacobian except for entries relating coupling between
the frequencies is neglected. Further information about the solution methods can
be obtained in [2] [7].
19
Chapter 4
RF CMOS LINEARITY
With the growth of digital mobile communications, many RF ampliflers such
as low-noise ampliflers (LNA) operate in a region of weak linearity at RF front-end
[8]. Linearity is one of the important issues in RFIC design as it limits system?s
dynamic range. Since scaling of CMOS has resulted in a strong improvement in
the RF performance of MOS devices, various performance metrics like noise flgure,
linearity have been widely studied [9]. As the channel length is decreased, thin gate
oxide is needed to maintain electrostatic integrity. RF distortion is shown to be
worse with decreasing oxide thickness [9]. Devices with high linearity can minimize
signal distortion. Hence, analysis and simulation of linearity helps to understand
limiting factors for a given technology and to optimize transistor structure and
circuit topology [8]. For linearity, flgure of merit IP3 is used as a flrst order
parameter. Larger IP3 is required for higher linearity [9].
Fig. 4.1 shows flrst and third order powers vs input power and the extrapo-
lated IP3 point obtained using taurus simulations.
4.1 RF Distortion
IP3 of CMOS devices has been studied recently using either measured or
simulated I-V data [8], [9], [10]. Experimental characterization of linearity has
also been reported recently [11]. In analog MOS circuits, a purely sinusoidal input
20
?40 ?30 ?20 ?10 0 10?150
?100
?50
0
pin in dbm
pout in dbm
Two tone with order 5 and Vds=1V,Vgs=1.2V
Po1
Po3
1;1
3:1
Figure 4.1: First and third order output powers vs input power.
can produce a distorted output signal with higher-order harmonics due to the
nonlinearity of MOS transistors. These harmonics are mainly induced due to
higer order derivatives of the current-voltage(I-V)characteristics [12]. Of particular
interest is the third order derivative of the drain current Ids with respect to the
gate voltage Vgs, which needs to be minimized for low distortion application.
21
4.2 First Order Analysis
At flrst order, the drain current is simply a function of gate voltage and is
represented as
Ids = f(Vgs): (4.1)
Hence the intermodulation is a function of ac Vgs. The transconductance gm at a
flxed Vds can be deflned as
gm = @Ids@V
gs
: (4.2)
Increase of gm in the weak inversion is faster because of the exponential nature of
the I-V characteristics, and is slower in the strong inversion region. The second
order derivative and third order derivatives of transconductance gm at a flxed Vds
are given by
gm2 = @
2Ids
@2Vgs (4.3)
and
gm3 = @
3Ids
@3Vgs: (4.4)
Since the rate of increase of gm is highest in the moderate inversion region, gm2
has it peak near the threshold voltage during the transition from sub-threshold to
strong inversion. Also, the third order derivative gm3 is zero at this point. Since
the third order derivative is zero, intermodulation product (IM3)is zero. Thus, IP3
22
has a peak value at this point. Once gm;gm3 are known, IIP3 can be calculated as
IIP3 =
r4k
1
3k3: (4.5)
k1;k3 are deflned using power series
Ids = gm ?Vgs +k2 ?V 2gs +k3 ?V 3gs +??? (4.6)
where k1 = gm and
k3 = 13! @
3Ids
@3Vgs: (4.7)
IIP3 is usually expressed in dBm as 10log(103IIP3).
It is usually believed that IP3 has it peak value at the threshold point at
which gm3 is zero. But recent studies have shown that the peak value may not
be at the threshold point [11]. Further, IP3 value is observed to be higher in the
strong inversion region for higher Vgs [11].
Fig. 4.2 shows the simulated gm;gm2;gm3 when plotted vs Vgs and the corre-
sponding I-V characteristics for a 100nm MOSFET. It can be seen that the gm2
peak occurs at 0.33V. Hence, the IIP3 peak occurs at 0.33V. It can also be seen
that gm;gm3 are almost at in the strong inversion region. Thus, from flrst order
theory, the well known linearity sweet spot of gate bias can be easily found using
the simulated or measured I-V data.
23
0 0.5 1 1.5?1
?0.5
0
0.5
1
1.5
gm,gm2,gm3
vgs(v)
0 0.5 1 1.50
0.5
1x 10
?3
vgs
ids
?20
?10
0
log
gm3gm2
gm
Figure 4.2: I-V characteristics and the corresponding gm;gm2;gm3 vs Vgs.
IIP3 at this sweet spot need not necessarily be the highest, since higher Vgs in
strong inversion can lead to even higher IIP3 [11]. It is important to further analyze
this deviation because it has signiflcant implications in RFIC design. Further, the
efiect of CMOS scaling on RF distortion needs to be analyzed.
24
Chapter 5
100nm MOSFET SIMULATION RESULTS
In this chapter, parametric characterization of intermodulation linearity is
presented using 100nm technology. The impact of technology scaling on linearity
is analyzed by varying the channel length and oxide thickness of a 100nm MOS
device. IIP3 is also characterized as a function of drain and gate voltages.
nopoly.tif:line0
0.00 2.00 4.00 6.00 8.00
X (microns) *10-2
14
16
18
log(Ntype) ,log(ptype)(cm-3)
1
Ntype
Ptype
Total Doping
Log |x|
16
16.5
17
17.5
18
18.5
19
19.5
20
20.31
-0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
-0.1
0
0.1
0.2
0.3
nopoly.tif:line0
0.00 1.00 2.00 3.00 4.00
Y (microns) *10-2
-20
0
log(ntype),log(ptype) (cm-3)
npoly GateDi 1
Acceptors
Ntype
Ptype
Total Doping
Log |x|
16
16.5
17
17.5
18
18.5
19
19.5
20
20.31
-0.6 -0.4 -0.2 0 0.2 0.4 0.6
-0.4
-0.2
0
0.2
0.4
Figure 5.1: Doping proflles using a cut-line through the channel.
A simple 2-D MOS device with 100nm channel length, 1nm oxide thickness
and uniform channel doping is used for linearity analysis.
25
Ntype
Log |x|
0
4
8
12
16
2020.3
Figure 5.2: MOS 100nm mesh structure.
The device is built using Medici Device simulation tool and is visualized using
Taurus. Input code for the device in Medici is included in Appendix A. Fig. 5.1
shows the typical doping proflle when a cut-line is made through the channel.
5.1 DC Simulation
The device built in Medici is imported into Taurus and is further analyzed
as described in the following sections. 100nm MOS structure is divided into 3135
grid points and the mesh structure is shown in Fig. 5.2.
At each of these grid points Taurus simulator solves Drift-Difiusion equations
given by
26
r?(??r?) = q(p?n+N+D +N?A) (5.1)
@n
@t =
1
qrJn +(Gn ?Rn) (5.2)
@p
@t = ?
1
qrJp +(Gp ?Rp) (5.3)
where Jn = q(n?n"+Dnrn) and Jp = q(p?p"?Dprp).
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10
1
2
3
4
5
6x 10
?4
vgs
ids
vds=1v
vds=0.8v
vds=0.6v
Figure 5.3: Id ?Vg curves for three difierent values of Vds.
Terminal currents are the most important characteristics of the device simu-
lation and can be easily obtained by applying a simple DC bias. Current -Voltage
output characteristics are always sought since they give an intuition about the
device performance.
27
For a flxed drain voltage, the variation of drain current with gate voltage can
be obtained from DC simulation. The Id ?Vg curves for three difierent Vds values
are as shown in Fig. 5.3.
5.2 AC Simulation
1 2 3 4 5 6 7 8 9
x 10?4
50
55
60
65
70
75
80
Id (A/um)
ft(GHz)
Figure 5.4: Cutofi frequency(fT) vs Drain Current.
Cutofi frequency fT, one of the important considerations in RFIC design can
be obtained from AC simulation data. For a flxed drain voltage, AC analysis is
applied keeping the frequency constant at 1MHZ and sweeping the gate voltage
from 0.5 V to 1.2V. Cutofi frequency vs drain current is plotted and is as shown
in Fig. 5.4. Peak fT is found to be 75 GHz using drift-difiusion equations.
28
5.3 HB Simulation
?40 ?30 ?20 ?10 0 10?150
?100
?50
0
pin in dbm
pout in dbm
Two tone with order 5 and Vds=1V,Vgs=1.2V
Po1
Po3
1;1
3:1
Figure 5.5: First and third order output powers vs input power.
HB analysis is done by applying a periodic signal to the 100nm MOS device
at a flxed dc bias point of Vds = 1V and Vgs = 1:2V. Source voltage is swept from
10mV to 60mV and the corresponding output power for the harmonic balance
simulation is plotted. Since a two-tone test is used for IIP3 calculations, two tones
at frequencies 5.8 GHz and 5.9 GHz with a tone spacing of 1MHz are used. Source
and load resistances are assumed to be 50 ohms. Truncation order for each tone
is specifled as flve.
29
Input power is obtained as
Pin = V
2
in
8Rs: (5.4)
First and third order powers are calculated as
PO1 = I
2
w1Rl
2 (5.5)
PO3 = I
2
2w2?w1Rl
2 (5.6)
where Vin is the source voltage, Rs and Rl are the source load resistances, Iw1 and
I2w2?w1 are the flrst and third order output currents. First and third order output
powers obtained from the above equations are expressed in dBm and are plotted
against input power as shown in Fig. 5.5. For higher input powers the simulation
does not converge hence, the values are extrapolated. From Fig. 5.5, IIP3 value is
found to be 8 dBm.
5.4 Characterization of IIP3
Characterization of IIP3 with respect to Vgs, Vds, channel length and oxide
thickness is presented in this section. 100nm MOS device with 1nm oxide thickness
is used for the analysis, unless specifled.
30
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1?20
?15
?10
?5
0
5
10
15
Vgs(V)
IIP3(dbm)
vin=10m,two tone 5 order
vds=1v
vds=0.8v
vds=0.6v
Figure 5.6: IIP3 vs Vgs for difierent Vds values.
5.4.1 Vgs and Vds Dependence
IIP3 values are plotted vs Vgs for three difierent values of Vds as shown in
Fig. 5.6. It can be seen that IIP3 has a sharp peak near threshold, during the
transition between sub-threshold to strong inversion. At this point the second
order gm nonlinearity coe?cient gm2 is highest, thus the third order nonlinearity
coe?cient gm3 is zero, leading to IM3 = 0. IIP3 value at this point was considered
to be the highest but, recent studies have indicated that IIP3 values in the strong
inversion may be much higher [11].
From Fig. 5.6, it can be observed that IIP3 peak does not change much in the
weak inversion region as Vds increases from 0:6V to 1:0V, while it varies strongly
31
0 0.5 1 1.5?0.5
0
0.5
1
1.5
vgs(v)
gm,gm2,gm3
gm3
gm2
gm
gm3/gm
Figure 5.7: gm, gm2, gm3, gm3=gm vs Vgs for 100nm MOS, W=1um.
with Vds in strong inversion. Fig. 5.7 shows gm;gm2 and gm3 plotted vs Vgs for a
flxed Vds = 1V. It can be seen that as Vgs increases from saturation to linear region,
the ratio of gm3=gm remains constant. Hence, IIP3 remains constant at higher Vgs.
IIP3 is also plotted versus drain current for difierent Vds values as shown in Fig.
5.8. For same drain current, IIP3 increases with Vds in strong inversion.
Fig. 5.9 shows Gain versus Vgs for 100nm MOS device with 1?m width. Gain
also improves with Vds but the increase is very weak. This weak increase in gain
is due to increase in gm with vds at higher Vgs. The negative gain values as seen
from Fig. 5.9 are mainly because the device width is equal to 1?m. As the width
32
10?7 10?6 10?5 10?4 10?3?20
?15
?10
?5
0
5
10
15
Ids
IIP3(dbm)
vds=1v
vds=0.8v
vds=0.6v
Figure 5.8: IIP3 vs Ids for difierent Vds values.
of the device increases, drain current increases and is given by
Ids = I0ds ?W: (5.7)
First and third order output powers can then be expressed as
Po3 = I0ds3 ?W2 (5.8)
and
Po1 = I0ds1 ?W2 (5.9)
33
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1?70
?60
?50
?40
?30
?20
?10
0
10
20
Vgs(V)
Gain(dB)
vds=1v
vds=0.8v
vds=0.6v
W=40um
W=1um
Figure 5.9: Gain vs Vgs for difierent Vds values.
whereI0ds;I0ds3;I0ds1 arethedraincurrentsobtainedfromtheDCandHBsimulations
using Taurus and W is the width of the device.
Gain and IIP3 can be calculated as
G = Po1P
in
?W2 (5.10)
IIP3 = Pin ? 12(Po1 ?Po3) (5.11)
where Pin is the input power. Fig. 5.9 shows the increase in gain as the device
width is scaled by 40. Thus, scaling the device width improves gain but does not
34
afiect IIP3 since both flrst and third order powers are scaled by the same number.
All the results presented in this chapter have 1?m device width.
5.4.2 Channel Length Dependence
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.810
?8
10?7
10?6
10?5
Vgs(V)
gm3
100nm
120nm
130nm
Figure 5.10: gm3 vs Vgs for difierent channel lengths.
Channel length is one of the important considerations for RFIC design. Scal-
ing channel length though improves fT, trades other performance metrics. Longer
channel length reduces output conductance gd and its nonlinearities in both weak
and strong inversion. This is due to reduced drain-induced-barrier-lowering (DIBL)
and weaker channel length modulation efiects. In short channel devices, both these
efiects are signiflcant and hence it is di?cult to describe how channel length afiects
35
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1?4
?2
0
2
4
6
8
10
12
Vgs
IIP3
IIP3 vs Vgs,for vds=1v
120nm, 1nm
130nm, 1nm
100nm,1nm
Figure 5.11: IIP3 vs Vgs for difierent channel lengths.
IIP3. However, gm3 can be used to explain the channel length dependence. Fig.
5.10 shows gm3 versus Vgs for difierent channel lengths. It can be clearly seen that
RF distortion increases with scaling which in turn decreases IIP3.
Fig. 5.11 shows simulated IIP3 versus Vgs at 5.8 GHz frequency for three
channel lengths 100nm, 120nm, 130nm. IIP3 is almost same for the devices in
strong inversion.
As channel length decreases, threshold voltage reduces. Hence, IIP3 peak
shifts to lower Vgs values. Since devices with difierent channel lengths have difierent
Ids values, it is important to analyze the efiect of channel length on IIP3 at the
same Ids value. Fig. 5.12 shows IIP3 vs Ids for difierent channel lengths. It can be
36
10?6 10?5 10?4 10?3?4
?2
0
2
4
6
8
10
12
Ids
IIP3
IIP3 vs Ids,for vds=1v
120nm, 1nm
130nm, 1nm
100nm,1nm
Figure 5.12: IIP3 vs Ids for difierent channel lengths.
seen that IIP3 peak occurs at a higher current in a small channel device. However,
at higher Vgs, IIP3 is higher for a longer channel device in strong inversion. Thus,
longer channel length improves linearity provided gain requirement is satisfled.
5.4.3 Oxide Thickness
In scaled CMOS processes, multiple oxide thickness devices are provided to
facilitate circuit designs requiring a higher voltage swing [8]. Linearity dependance
on oxide thickness needs to be analyzed, since oxide scaling may be traded if gm
requirements are not high. The efiect of oxide scaling on IIP3 is analyzed in this
section by varying the oxide thickness of a 130nm MOS device. Fig. 5.13 shows
37
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1?15
?10
?5
0
5
10
15
vgs
IIP3 dbm
IIP3 vs vgs ,for vds=1v and channel length=130nm
1nm
1.2nm
1.3nm
1.5nm
Figure 5.13: IIP3 vs Vgs for difierent oxide thickness.
IIP3 vs Vgs for oxide thicknesses 1nm, 1.2nm, 1.3nm and 1.5nm. All the devices
are biased at same Vgs and have Vds = 1V. A shift in threshold voltage is observed
as the oxide thickness is increased. It can be seen that the IIP3 peak occurs at
higher Vgs as the oxide thickness is increased. Thus, devices with thin oxide have
smaller threshold values.
Fig. 5.14 shows IIP3 vs Ids for difierent oxide thicknesses. For the same drain
current, IIP3 is found to be higher for thicker gate oxide. Thus, oxide scaling
trades linearity and hence increases RF distortion.
From Fig. 5.15, it can be seen that Gain improves with oxide scaling. Thus,
short channel devices trade linearity to gain and threshold voltage.
38
10?7 10?6 10?5 10?4 10?3?15
?10
?5
0
5
10
15
Ids
IIP3 dbm
IIP3 vs Ids ,for vds=1v and channel length=130nm
1nm
1.2nm
1.3nm
1.5nm
Figure 5.14: IIP3 vs Ids for difierent oxide thickness.
5.5 Simulation and Theoretical Analysis
In this section, the simulation results obtained from Harmonic Balance are
analyzed using power series. Power series is a simple mathematical representation
used to obtain the direct response of a nonlinear system in frequency domain.
This series when restricted to be Taylor?s series around a predetermined quiescent
point(usually the dc bias point), inherently represents the device?s small signal be-
havior [6]. Thus, it can be used to predict a circuits weakly nonlinear behavior [13].
The nonlinear relation between drain current and gate potential can be expressed
using power series by deflning a number of nonlinear coe?cients as described in
39
0 0.5 1 1.5 2 2.5 3 3.5
x 10?4
?70
?65
?60
?55
?50
?45
?40
?35
?30
?25
?20
Ids(A/um)
Gain(dB)
Gain vs Ids ,for vds=1v and channel length=130nm
1nm
1.2nm
1.3nm
1.5nm
Figure 5.15: Gain vs Ids for difierent oxide thickness, L=130nm, W=1um.
chapter 4. These coe?cients help to characterize I-V nonlinearity. From DC sim-
ulation, gm;gm2;gm3 can be calculated and IIP3 as described in chapter 5 can be
calculated theoretically as
IIP3 =
r4k
1
3k3 (5.12)
wherek1 = gm andk3 = 13! @3Ids@3Vgs. IIP3isusuallyexpressedindBmas10log(103IIP3).
Simulated values obtained from Harmonic Balance and theoretical values com-
putedusingpowerseries, forthreedevices withdifierentchannellengthsareplotted
vs gate voltage as shown in Fig. 5.16. Fig. 5.17 shows the results when plotted
versus the drain current on log scale. It can be seen that the values are in well
40
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9?20
0
20
Vgs(V)
IIP3(dbm)
mos 130nm channel length,1nm tox
simulated
theoretical
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9?20
0
20
Vgs(V)
IIP3(dbm)
mos 120nm channel length,1nm tox
simulated
theoretical
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1?20
0
20
Vgs(V)
IIP3(dbm)
mos 100nm channel length,1nm tox
simulated
theoretical
Figure 5.16: Simulated and theoretical values of IIP3 vs gate voltage Vgs.
agreement hence, the third order gm nonlinearity can be used for analyzing linearity
at the flrst order level.
41
10?6 10?5 10?4 10?3
?20
0
20
Ids(A/um)
IIP3(dbm)
mos 130nm channel length,1nm tox
simulated
theoretical
10?6 10?5 10?4 10?3
?20
0
20
Ids(A/um)
IIP3(dbm)
mos 120nm channel length,1nm tox
simulated
theoretical
10?6 10?5 10?4 10?3
?20
0
20
Ids(A/um)
IIP3(dbm)
mos 100nm channel length,1nm tox
simulated
theoretical
Figure 5.17: Simulated and theoretical values of IIP3 vs drain current Ids.
42
Chapter 6
POLYGATE DEPLETION EFFECT
In this chapter, polysilicon technology and the efiect of polysilicon gate de-
pletion on RF distortion is analyzed using a 100nm MOS device with 1nm oxide
thickness, at bias conditions relevant for RF design (i.e., saturation conditions and
gate bias near threshold). Linearity dependence on the doping concentration of
polysilicon gate is also presented.
6.1 Background of Polysilicon Gate
The use of polysilicon gate is a key advance in modern CMOS technology
[17]. Polysilicon gate is used as a mask during the ion implantation so that the
source and drain regions are self-aligned with respect to the gate. This self-aligned
structure reduces the device size and also eliminates the large overlap capacitances
between gate and drain while maintaining a continuous inversion layer between
source and drain. Scaling of MOS devices results in depletion of polysilicon gate
at higher gate bias. This efiect is further analyzed in the following sections.
6.2 Scaling of MOS devices
Scaling of MOS devices requires thinner gate oxide to maintain electrostatic
integrity [14]. Oxide scaling results in poly depletion efiect which in turn afiects
RF distortion [15]. Thus, the impact of poly depletion efiects on RF distortion
43
0.2 0.4 0.6 0.8 1 1.2 1.4 1.610
?7
10?6
10?5
10?4
10?3
10?2
10?1
vgs
gm3
130nm,2.2nm100nm,1nm
Figure 6.1: gm3 vs gate voltage(Vgs )for two difierent technologies.
needs to be studied in order to project the gate oxide scaling in MOS RF circuits.
Fig. 6.1 shows gm3 at Vds = 1V for two difierent technologies, 130nm gate length
device with 2.2nm oxide thickness and 100nm gate length device with 1nm oxide
thickness. It can been seen that the linearity can be worse for scaled devices with
thin gate oxide.
6.3 Poly Depletion Efiect
If the polysilicon gate is not heavily doped, depletion of the n+ poly gate may
occur at higher gate bias. In scaled devices, where tox is less then 5nm, thickness of
this depletion layer cannot be neglected. The depletion layer acts as an extension
44
Figure 6.2: Band diagram of n+ poly gate MOS structure.
of the gate oxide insulator thus, increasing the efiective gate oxide thickness and
decreasing the efiective gate oxide capacitance.
This can be further explained using a band diagram of an n+ polysilicon gated
n-channel MOS structure from [17]. From Fig. 6.2 it can seen that as the gate
bias is increased, the oxide fleld is in the direction of accelerating a negative charge
towards the gate. Thus, the bands in the n+ polysilicon bend slightly upward
towards the oxide interface. This depletes the surface of electrons and forms a thin
space-charge region in the polysilicon layer which lowers the total gate capacitance.
Poly depletion has a signiflcant impact on RF distortion and can be analyzed
using gm3 values. Fig. 6.3 shows the simulated gm3 curves in the presence of
polydoping efiects for dopant concentration Np = 2:5?1019cm?3. The solid line
represents gm3 curve when the poly depletion efiect is not taken into account and
hence, gate electrode is deflned by using a work function. As Vgs increases it can
45
0 0.5 1 1.510
?6
10?5
10?4
10?3
10?2
10?1
Vgs(V)
gm3
Vds=1V
nopoly dpeletionpolydoping 2.5e19
RF biasrange
Figure 6.3: gm3 vs gate voltage(Vgs )with and without poly depletion.
be seen that in the RF bias range, gm3 increases in the absence of poly depletion.
Thus, at higher Vgs RF distortion increases due to poly depletion. This depletion
efiect can be decreased by increasing the dopant concentration in the polysilicon
gate which in turn decreases the depletion layer thickness.
Fig. 6.4 shows gm3 values for difierent dopant concentrations of poly-gate for
Vds = 1V. Thus, as the doping concentration in poly-gate increases, RF distortion
is reduced. Further gm3 is also plotted for difierent Vds values. It can be seen from
Fig. 6.5 that as Vds increases the device is in saturation for higher Vgs values.
46
0 0.5 1 1.510
?4
10?3
10?2
10?1
100
Vgs(V)
gm3
Vds=1V
nopoly
2.5e19
5e19
Figure 6.4: gm3 vs gate voltage(Vgs )for two difierent polydoping concentration.
6.3.1 Efiect on Gate Capacitance
Drain current in MOSFET can be expressed as
Ids = WQv (6.1)
where Q is the channel charge density along the current direction, W is the width
of the device, v is the velocity of the carriers. For su?ciently high flelds, the carrier
velocity approaches saturation value vsat. Hence, equation 6.1 can be written as
Ids ? WQvsat: (6.2)
47
0 0.5 1 1.510
?6
10?5
10?4
10?3
10?2
10?1
vgs
gm3
2.5e19nopolydoping
Vds=1V
Vds=2
Figure 6.5: gm3 versus gate voltage(Vgs )for two difierent for Vds values.
First order derivative of drain current with respect to gate bias, gm is given by [15]
gm ? @Ids@V
gs
= WC(Vgs)vsat: (6.3)
An ideal gate capacitance in strong inversion must be equal to the total oxide
capacitance and is given by
Cox = ?oxt
ox
: (6.4)
However, the real gate capacitance in strong inversion depends on gate bias when
poly efiects are taken into efiect and can be expressed as [15].
C(Vgs) = ?oxt
ox +tdp(Vgs)
(6.5)
48
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8x 10
?15
vgs
cgs
cgs Vs Vgs
nopoly
2.5e19
5e19
1e20
Figure 6.6: Gate capacitance vs gate voltage for difierent poly gate doping con-
centration.
where tdp represents the depleted thickness of poly-gate. Thus, decrease in gate
capacitance adversely efiects gm.
Fig. 6.6 shows C-V plots at 1MHz frequency. It can be seen that gate capac-
itance decreases with the decrease in dopant concentration of polysilicon gate and
then remains constant at higher Vgs values. This is because, as Vgs increases, the
depletion layer thickness increases and reaches a saturation point beyond which
the surface gets inverted. Since there is no p-type semiconductor available to sup-
ply holes, inversion holes cannot be generated fast enough to follow the ac signal
(assuming there is no Generation/Recombination process). Thus, at higher Vgs
the gate capacitance remains constant since the depletion layer thickness remains
constant.
49
6.3.2 Efiect on IIP3
0.4 0.5 0.6 0.7 0.8 0.9 1?15
?10
?5
0
5
10
15
20
Vgs(V)
IIP3(dbm)
no polydoping
5e19
2.5e19
Figure 6.7: IIP3 vs gate voltage for difierent poly gate doping concentrations.
The efiect of poly depletion on linearity is presented in this section. Harmonic
Balance simulations are done using Taurus, by changing the dopant concentration
in the polysilicon gate. Fig. 6.7 shows variation of IIP3 with the dopant concen-
tration in polysilicon gate, as the gate voltage is increased. It can be seen that
as the polydoping is decreased, the IIP3 decreases because of the poly depletion
efiect in the strong inversion region. Fig. 6.8 shows the IIP3 vs drain current for
difierent doping concentration. It can be seen that linearity decreases with drain
current in the strong inversion region.
The simulated values of the IIP3 for difierent poly-gate concentrations are
compared to the theoretical values obtained using the power series and are in good
50
10?6 10?5 10?4 10?3?15
?10
?5
0
5
10
15
20
no polydoping
5e19
2.5e19
Figure 6.8: IIP3 vs drain current for difierent poly gate doping concentrations.
agreement as shown in Fig. 6.9. Thus, from the simulation results it can be stated
that the RF distortion increases with scaling.
The only way to overcome polysilicon gate depletion efiect is to go back to the
use of metal gate. As the critical MOS dimensions shrink, conventional polysilicon
gates are being replaced by the metal gates. Research is being done to introduce
new gate materials which can suppress the poly depletion efiect.
51
10?6 10?5 10?4 10?3?20
0
20
Ids
IIP3(dbm)
polydoping =5e19cm?3
simulatedcalculated
10?6 10?5 10?4?20
0
20
Ids
IIP3(dbm)
polydoping=2.5e19cm?3
simulatedcalculated
10?6 10?5 10?4 10?3?20
0
20
Ids
IIP3(dbm)
without polydoping
simulatedcalculated
Figure 6.9: Simulated and theoretical IIP3 values for difierent poly gate doping
concentrations.
52
Chapter 7
HALO DOPING
In this chapter, linearity analysis is extended to 90nm technology. With scal-
ing of CMOS, uniform channel doping has been slowly replaced by super retrograde
doping and source/drain halo. Halo design is a critical element in CMOS scaling.
Super Halo doping consists of highly nonuniform proflle in both vertical and lat-
eral directions. These high doping regions are self-aligned to the gate and source-
drain, which help shield the gate controlled depletion region from penetration of
the source and drain flelds [20].
regrid90.tif:line0
-5.00 0.00 5.00X (microns) *10-2-30
-20
-10
0
10
20
log(Ntype) (cm-3)
5
Ntype Ptype
Ntype
Log |x|
9.927
12
14
16
18
2020.29
-0.3 -0.2 -0.1 0 0.1 0.2 0.3
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Figure 7.1: Doping Proflle of 90nm NMOSFET along the channel.
53
7.1 MOS 90nm
A hypothetical NMOSFET device with 90nm Leff, 4:5nm oxide thickness and
super retrograde channel doping and source/drain halo has been used to extend the
linearity characterization to short channel devices. The input code in Medici for
this device is obtained from [16]. The detailed description of the device topology
is described in [16]. This structure is imported into Taurus and Harmonic Balance
analysis is performed.
regrid90.tif:line2
0.000 0.100 0.200Y (microns)-30
-20
-10
0
10
log(Ntype) (cm-3)
1 4 5
Ntype Ptype
Total_Doping
Ptype
Log |x|
15.5415.75
1616.25
16.516.75
1717.25
17.517.75
18.21
-0.3 -0.2 -0.1 0 0.1 0.2 0.3
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Figure 7.2: Doping proflle of 90nm NMOSFET across the channel.
The doping proflles through the channel are shown in Fig. 7.1 and Fig. 7.2.
54
?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15?140
?120
?100
?80
?60
?40
?20
0
pin in dbm
pout in dbm
90nm mos,Two tone with order 5 and Vds=1V,Vgs=1V
Po1
Po3
1;1
3:1
Figure 7.3: First and third order output powers vs input power.
7.2 Harmonic Analysis
Applying HBsimulationforthe90nm NMOS device, theimpact ofhalo doping
on linearity is analyzed. First and third order output powers are plotted against
the input power and the extrapolated IP3 point is as shown in the Fig. 7.3. Fig.
7.4 shows gm;gm2;gm3 vs Vgs for Vds = 1V. Further, IP3 dependence on Vds and
Vgs is analyzed using an input drive of 10mV and is plotted as shown in Fig. 7.4.
It can be seen that the IIP3 peak as seen for the 100nm MOS device is not very
pronounced in this device, which may be attributed to the halo doping. It can also
be observed that the IP3 value at threshold point where gm3 = 0 may not be a
peak value and its value is higher in strong inversion.
55
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8?0.5
0
0.5
1
vgs
gm,gm2,gm3
gmgm2
gm3
Figure 7.4: gm;gm2;gm3 vs Vgs.
7.3 Discrepancy
Unlike previous results, there is a discrepancy between simulated and cal-
culated results when plotted versus Vgs and is shown in Fig.7.6. This deviation
may be attributed to the presence of halo doping or the way halo doping is han-
dled in the simulator. The efiect of halo doping on linearity could not be clearly
established and hence requires further research.
56
0.4 0.5 0.6 0.7 0.8 0.9 1?10
?8
?6
?4
?2
0
2
4
Vgs(V)
IIP3(dbm)
vds=1v
vds=0.8v
vds=0.6v
Figure 7.5: IIP3 vs Vgs for three difierent Vds values.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9?20
?15
?10
?5
0
5
10
Vgs(V)
IIP3(dbm)
mos 90nm halo doping
simulated
theoretical
Figure 7.6: Simulated and theoretical values.
57
Chapter 8
CONCLUSIONS AND FUTURE WORK
In this thesis, Intermodulation Linearity characteristics of CMOS devices is
analyzed using hypothetical 130nm, 100nm, 90nm NMOS devices. The efiect of
technology scaling on linearity is examined by varying the channel length and
oxide thickness of the NMOS devices. Polysilicon gate depletion and its impact on
linearity is also presented for various doping concentrations of the poly-gate.
HB Method is used to analyze harmonic distortion at semiconductor device
level using Taurus simulation tool. The IIP3 values obtained from HB simulation
are compared using power series.
Although it is not possible to represent any dynamic system by power series,
it can still be used in cases where the system can be represented by several non-
interacting subsystems, and where nonlinearities are memoryless [13].
It can be concluded from this work that devices with longer channel and
thicker gate oxide can be used to achieve improved linearity. Further, it can also
be concluded that RF distortion increases with scaling. In short channel devices,
linearity can be improved by increasing the dopant concentration of the poly-gate.
Thus, CMOS scaling trades linearity to cutofi frequency and gain.
58
8.0.1 Future Work
It is observed that the IIP3 does not have a sharp peak at the threshold
point for the 90nm MOS device, which may be attributed to the presence of Halo
doping. The efiects of Halo doping on linearity are yet to be analyzed. The impact
of polysilicon depletion on gate capacitance need to be further analyzed.
59
Bibliography
[1] Guofu Niu, John D. Cressler, SiGe Heterojunction Bipolar Transistor, Artech
House Publishers Jan. 2003
[2] Stephen Mass, RF and microwave steady state analysis,Artech House publish-
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[3] Boris Troyanovsky \Frequency domain algorithms for simulating large sig-
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[4] Behzad Razavi, RF Microelectronics, Prentice Hall PTR, 1st edition,
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[5] John Rodgers, Calvin Plett, RF Integrated circuit design, Artech House Pub-
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[6] kenneth S. kundert, Jacob K. White, Alberto De Sangiovanni-Vincentelli,
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[7] Taurus manual from Synopsys
[8] Guofu Niu, Qingqing Liang, John D. Cressler, Charles S.Webster, David
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[9] Pierre H.Woerlee, Mathijis J. Knitel, Ronald van Langevelde, Dirk B. M.
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Duijnhoven,\RF-CMOS performance trends", IEEE Transactions on Electron
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[10] Sanghoon Kang, Byounggi Choi, Bumman Kim,\Linearity Analysis of CMOS
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[11] Guofu Niu, Jun Pan, Xiaoyun Wei, Stewart S.Taylor and David Sheridan \In-
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process" RFIC Conference, 2005
60
[12] R.Van Langevelde, L.Tiemeijer, R.Havens, M.Knitel, R.Ores, P.Woerlee,and
D.Klaassen,\RF-distortion in deep-submicron CMOS technologies," IEDM
Technical Digest, p807-810, Dec.2000
[13] Jose Carlos Pedro, Nuno Borges Carvalho, Intermodulation distortion in Mi-
crowave and Wireless Circuits, Artech House Publishers, Dec.2002
[14] Yannis Tsividis Operation and Modeling of The Mos Transistor Oxford Uni-
versity press, 2nd edition, May 2003
[15] Chang-Hoon Choi, Zhiping Yu, Robert W.Dutton \Impact of Poly-Gate De-
pletion on MOS RF Linearity" IEEE Electron Device Letters, Vol.24, No.5,
May 2003
[16] http://www-mtl.mit.edu/researchgroups/Well/device1/topology1.html
[17] Yuan Taur, Tak H.Ning Fundamentals of Modern VLSI Devices, Cambridge
University Press, 1998
[18] Ulrich L.Rohde, David P.Newkirk RF/Microwave circuit design for wireless
applications, Wiley-Interscience, 1 edition ,March 2000
[19] Y.Taur and E.J.Nowak,\CMOS Devices below 0.1um:How will performance
Go?" IEDM Technical Digest,p.215(1997)
[20] Y.Taur, C.H.Wann and D.J.Frank,\25nm CMOS Design Considerations"
IEDM Technical Digest, p.789, 1998
[21] Hang Hu, Jarvis B.Jacobs, Lisa T.Su, Dimitri A.Antoniadis,\A study of Deep-
SubMicron MOSFET scaling based on Experiment and simulation", IEEE
Transactions on Electron Devices, Vol.42,No., April 1995
[22] Bart Van Zeghbroeck, Principles of Semiconductor Devices
[23] Boris Troyanovsky et al.,\E?cient Multi-Tone Harmonic balance Simula-
tion of Semiconductor Devices in the presence of Linear High-Q Circuitry"
Proc.SASIMI, Dec.1997
[24] Boris Troyanovsky et al.,\Large signal analysis of RF/microwave devices with
parasitics using harmonic balance device simulation, Proc.SASIMI, Nov.1996
[25] Peng Li, Lawrence T.Pileggi,\E?cient Per-Nonlinearity Distortion Analysis
for Analog and RF Circuits", IEEE Transactions on computer-Aided design
of intergrated circuits and systems Vol.22,No.10,Oct.2003
61
[26] F Yuan and A.Opal,\An e?cient transient analysis algorithm for midly mon-
linear circuits", IEEE Transactions on Computer Aided design of Integrated
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[27] P. Feldmann, R. C. Melville, and D. Long, E?cient frequency domain analysis
of large nonlinear analog circuits, Proc.IEEE CICC, pp 461464, May 1996
[28] Medici manual, Synopsys
[29] P.L.Heron and M.B Steer,\Jacobian calculation using the multidimensional
Fast Fourier Transform in the harmonic balance analysis of nolinear circuits,"
IEEE Transactions on Microwave Theory and Techniques, Vol.38, pp 429-431,
April 1990
[30] V. Rizzoli, C. Cecchetti, A. Lipparini and F.Mastru,\General-purpose har-
monic balance analysis of nonlinear microwave circuits under multitone exci-
tation," IEEE Transactions on Microwave Theory and Techniques, pp 1650-
1659, Dec.1988
[31] Paulo J. C. Rodrigues, Computer-aided analysis of nonlinear microwave cir-
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[32] Ulrich L. Rohde, David P. Newkirk,RF/Microwave Circuit Design for wireless
Applications A Wiley-Interscience Publication
[33] http://www.intel4004.com/sgate.htm
[34] http://en.wikipedia.org/wiki/MOSFET
62
Appendix A
Input code for 100nm MOS structure in Medici
1... $input code for 100nm mos device
2... mesh smooth=1
3... $ X-COORDINATES
4... $ -------------
5... x.mesh n=1 l=-0.56
6... x.mesh n=9 l=-0.06 r=0.9
7... x.mesh n=20 l=0 r=0.9
8... x.mesh n=37 l=0.02 r=0.9
9... x.mesh n=48 l=0.05 r=1.2
10... x.mesh n=59 l=0.08 r=0.8
11... x.mesh n=76 l=0.10 r=1.1
12... x.mesh n=87 l=0.16 r=1.1
13... x.mesh n=95 l=0.66 r=1.1
14... $ Y-COORDINATES
15... $ ------------
16... y.mesh n=1 l=-0.0110
17... y.mesh n=2 l=-0.0010 r=1
18... y.mesh n=4 l=0.0000 r=1
19... y.mesh n=5 l=0.0002 r=1
63
20... y.mesh n=8 l=0.0015 r=1
21... y.mesh n=9 l=0.0025 r=1
22... y.mesh n=10 l=0.0035 r=1
23... y.mesh n=11 l=0.0050 r=1
24... y.mesh n=12 l=0.0070 r=1
25... y.mesh n=13 l=0.0090 r=1
26... y.mesh n=14 l=0.0120 r=1
27... y.mesh n=15 l=0.0150 r=1
28... y.mesh n=16 l=0.0160 r=1
29... y.mesh n=17 l=0.0270 r=1
30... y.mesh n=18 l=0.0300 r=1
31... y.mesh n=21 l=0.0500 r=1
32... y.mesh n=23 l=0.1000 r=1
33... y.mesh n=26 l=0.1500 r=1
34... y.mesh n=29 l=0.1800 r=1
35... y.mesh n=30 l=0.2200 r=1
36... y.mesh n=31 l=0.2600 r=1
37... y.mesh n=32 l=0.3500 r=1
38... y.mesh n=33 l=1.5000
39... $ REGION AND ELECTROD
40... $ -------------------
41... region num=1 silicon ix.min=1 ix.max=95 iy.min=4 iy.max=33
64
42... region num=2 oxide ix.min=1 ix.max=95 iy.min=1 iy.max=4
43... region name="GateDi" oxide ix.min=9 ix.max=87 iy.min=1 iy.max=4
44... region num=5 oxide ix.min=1 ix.max=20 iy.min=1 iy.max=2
45... region num=4 oxide ix.min=76 ix.max=95 iy.min=1 iy.max=2
46... $polysilicon gate
47... region name="npoly" silicon ix.min=20 ix.max=76 iy.min=1 iy.max=2
48... electrod name=Gate ix.min=20 ix.max=76 iy.min=1 iy.max=2
49... electrod name=Substr ix.min=1 ix.max=95 iy.min=33 iy.max=33
50... electrod name=Source ix.min=1 ix.max=9 iy.min=4 iy.max=4
51... electrod name=Drain ix.min=87 ix.max=95 iy.min=4 iy.max=4
52... $ DOPING
53... $ ------
54... $poly doping
55... $profile n-type unif n.peak=1e20 region=npoly out.file=profile.dop
56... profile unif conc=1e16 p.type x.right=10 x.left=-10 y.t=-10 y.b=10
57... profile p.type conc=4e18 x.right=10 x.left=-10 char=0.019 y.min=0.0130 depth=
58... profile p.type conc=6e17 x.right=10 x.left=-10 char=0.050 y.min=0.0550 depth=
59... $D/S:
60... profile conc=1e20 n.type x.left=-10 x.right=-0.01 junc=0.03 erfc.lat
... + x.char=0.0103
61... profile conc=1e20 n.type x.left=-10 x.right=-0.06 junc=0.10 erfc.lat
... + x.char=0.03
65
62... profile conc=1e20 n.type x.left=0.11 x.right=10 junc=0.03 erfc.lat
... + x.char=0.0103
63... profile conc=1e20 n.type x.left=0.16 x.right=10 junc=0.10 erfc.lat
... + x.char=0.03
64... $ SAVE MESH
65... $ ---------
66... save mesh out.file=nopoly.tif tif
67... end.
This structure is imported into Taurus device and the following
code describes DC, AC and HB analysis in Taurus device.
1: taurus{device}
2:
3: DefineDevice (name=mos,meshfile=regrid.tif)
4:#models
5: physics
6: (
7: Silicon
8: (
9: Electroncontinuity
10: (
66
11: Mobility
12: (
13: Lowfieldmobility
14: (
15: SurfModelActive=True
16: ,SurfModel=LombardiSurfaceModel
17: )
18 highfieldmobility
19 (
20 highefieldmodel=caugheythomas
21 )
22: ),
23:
24: )
25: HoleContinuity
26: (
27: Mobility
28: (
29: Lowfieldmobility
30: (
31: SurfModelActive=True
32: ,SurfModel=LombardiSurfaceModel
67
33: )
34: ),
35:
36: )
37: )
38: )
39 Contact definitions
40: contact(name=gate,workfunction=4.17)
41: setbias(value=-0.5){contact(name=Gate, type=contactvoltage){mos}}
42: setbias(value=0.0){contact(name=back, type=contactvoltage){mos}}
43: setbias(value=0.0){contact(name=Source, type=contactvoltage){mos}}
44: setbias(value=0.0){contact(name=Drain, type=contactvoltage){mos}}
45:
46:
47:
48:
49: symbolic(carriers=0,newton,direct)
50: solve{}
51: symbolic(newton, carriers=2, direct)
#-------------DC Bias------------------------------
52: solve{
68
53: ramp(logfile=mosfet100nm_dc.data,
54: RampSpecification(endValue=1.0, nsteps=20)
55: {BiasObject(name=drain,type=contactVoltage)}
56: )
57:
58: }
59:#---------- AC analysis-----------------------------
60
61: solve
62: {
63: acanalysis
64: (
65: logfile=ac_mos100nm.data,acxfile=mosfet100nm_ac,frequency=2e9,
66: terminal(gate)
67: rampspecification(endvalue=1.2,nsteps=20)
68: {biasobject(name=gate,type=contactvoltage)}
69: extract(cutofffrequency(basecontact=gate,collectorcontact=drain))
70: )
71: }
72: save(meshfile=mos100nm_Ac.tdf)
73:
69
74: # -------------- harmonic balance--------------------------------------------
75: # one tone HB simulation
frequency= 5.8GHZ frequency,
truncation order=5 and is specified by nharm,
periodic source specified using hb_src has 10mV amplitude
76: harmonicbalance(
77: hb_numerics(iterations=20 maxiiter=100 maxbackvector=10)
78: tone1=5.8e9 nharm1=5 hb_src(name=gate m1=0.010)
79: logfile=mos100nm_5o_hb_010.data
80: display_solution=false
81: )
82: #two tone test used to find IIP3,
f1=5.8GHz and f2=5.9GHz are the two frequencies applied
Input voltage is sweeped from 20mV to 40mv
83: harmonicbalance(
84: tone1=5.8e9 nharm1=5
85: tone2=5.9e9 nharm2=3
86: hb_src(name=gate m1=0.020 m2=0.020)
87: logfile=mos100nm_5o_hb_020_020.data
70
88: display_solution=false
89: hb_continue=false
90: )
91:
92: harmonicbalance(
93: tone1=5.8e9 nharm1=5
94: tone2=5.9e9 nharm2=3
95: hb_src(name=gate m1=0.030 m2=0.030)
96: logfile=mos100_5o_hb_030_030.data
97: display_solution=false
98: hb_continue=false
99: )
100:
101: harmonicbalance(
102: tone1=5.8e9 nharm1=5
103: tone2=5.9e9 nharm2=3
104: hb_src(name=gate m1=0.040 m2=0.040)
105: logfile=mos100nm_5o_hb_040_040.data
106: display_solution=false
107: hb_continue=false
108: )
109:
71
110: save(meshfile=mos100_hb.tdf)
# The logfiles give the first and third order terminal currents
and hence first and third order powers can be calculated.
------------------------------------------------------------------------------
#Input code for plotting IIP3 dependence on Vgs and Vds,
#At a fixed drain voltage(1V), HB analysis is applied at
different gate voltages.
1: taurus{device}
2:
3: DefineDevice (name=mos,meshfile=nopoly.tif)
4:
5:
6: physics
7: (
8: Silicon
72
9: (
10: Global
11: (
12: fermistatisticsActive=true
13: )
14: Electroncontinuity
15: (
16: Mobility
17: (
18: Lowfieldmobility
19: (
20: SurfModelActive=True
21: ,SurfModel=LombardiSurfaceModel
22: )
23: Highfieldmobility(
24: highfieldmodel=caugheythomasmodel
25: )
26: ),
27: )
28: HoleContinuity
29: (
30: Mobility
73
31: (
32: Lowfieldmobility
33: (
34: SurfModelActive=True
35: ,SurfModel=LombardiSurfaceModel
36: )
37: Highfieldmobility(
38: highfieldmodel=caugheythomasmodel
39: )
40:
41: ),
42: )
43: )
44: )
45: contact(name=gate,workfunction=4.17)
46: setbias(value=0.0){contact(name=Gate, type=contactvoltage){mos}}
47: setbias(value=0.0){contact(name=substr, type=contactvoltage){mos}}
48: setbias(value=0.0){contact(name=Source, type=contactvoltage){mos}}
49: setbias(value=0.0){contact(name=Drain, type=contactvoltage){mos}}
50:
51: symbolic(carriers=0,newton,direct)
74
52: solve{}
53: symbolic(newton, carriers=1,electron, direct)
# drain voltage is ramped to 1V
54: solve{
55: ramp(logfile=poly_vds_1p0.data,
56:
57: RampSpecification(endValue=1.0, nsteps=20)
58: {BiasObject(name=drain,type=contactVoltage)}
59: )
60:
61: }
62:
63: solve{
64: ramp(logfile=poly_vds_1p0_vgs_p40.data,
65: RampSpecification(endValue=0.40 nsteps=20)
66: {BiasObject(name=gate,type=contactVoltage)}
67: )
68:
69: }
70:#harmonic balance analysis at gate voltage=0.4v
#f1=5.8GHz,f2=5.9GHz are the two fundamental frequencies with
1MHZ tone spacing, trucation order is 5, input voltage=10mV
75
71: harmonicbalance(
72: hb_numerics(iterations=20 maxiiter=100 maxbackvector=10)
73: tone1=5.8e9 nharm1=5
74: tone2=5.9e9 nharm2=3
75: hb_src(name=gate m1=0.010 m2=0.010)
76: logfile=hb_vds_1p0_vgs_p40_010_010_1carrier.data
77: display_solution=false
78: hb_continue=false
79: )
80:
81:
82: solve{
83: ramp(logfile=poly_vds_1p0_vgs_p45.data,
84: RampSpecification(endValue=0.45, nsteps=20)
85: {BiasObject(name=gate,type=contactVoltage)}
86: )
87:
88: }
89:#HB at Vgs=0.45V
90: harmonicbalance(
91: tone1=5.8e9 nharm1=5
92: tone2=5.9e9 nharm2=3
76
93: hb_src(name=gate m1=0.010 m2=0.010)
94: logfile=hb_vds_1p0_vgs_p45_010_010_1carrier.data
95: display_solution=false
96: hb_continue=false
97: )
98: solve{
99: ramp(logfile=poly_vds_1p0_vgs_p5.data,
100: RampSpecification(endValue=0.5, nsteps=20)
101: {BiasObject(name=gate,type=contactVoltage)}
102: )
103:
104: }
105:
106:#HB at vgs=0.5V
107: harmonicbalance(
108: tone1=5.8e9 nharm1=5
109: tone2=5.9e9 nharm2=3
110: hb_src(name=gate m1=0.010 m2=0.010)
111: logfile=hb_vds_1p0_vgs_p5_010_010_1carrier.data
112: display_solution=false
113: hb_continue=false
77
114: )
115:
116: solve{
117: ramp(logfile=poly_vds_1p0_vgs_p55.data,
118: RampSpecification(endValue=0.55, nsteps=20)
119: {BiasObject(name=gate,type=contactVoltage)}
120: )
121:
122: }
123:
124:#HB at Vgs=0.55V
125: harmonicbalance(
127: tone1=5.8e9 nharm1=5
128: tone2=5.9e9 nharm2=3
129: hb_src(name=gate m1=0.010 m2=0.010)
130: logfile=hb_vds_1p0_vgs_p55_010_010_1carrier.data
131: display_solution=false
132: hb_continue=false
133: )
134: solve{
135: ramp(logfile=poly_vds_1p0_vgs_p6.data,
78
136: RampSpecification(endValue=0.6, nsteps=20)
137: {BiasObject(name=gate,type=contactVoltage)}
138: )
139:
140: }
141:
142:#HB at Vgs=0.6V
143: harmonicbalance(
144: tone1=5.8e9 nharm1=5
145: tone2=5.9e9 nharm2=3
146: hb_src(name=gate m1=0.010 m2=0.010)
147: logfile=hb_vds_1p0_vgs_p6_010_010_1carrier.data
148: display_solution=false
149: hb_continue=false
150: )
151:
152:
153: solve{
154: ramp(logfile=poly_vds_1p0_vgs_p65.data,
155: RampSpecification(endValue=0.65, nsteps=20)
156: {BiasObject(name=gate,type=contactVoltage)}
157: )
79
158:
159: }
160:
161:#HB at Vgs=0.65V
162: harmonicbalance(
163: tone1=5.8e9 nharm1=5
164: tone2=5.9e9 nharm2=3
165: hb_src(name=gate m1=0.010 m2=0.010)
166: logfile=hb_vds_1p0_vgs_p65_010_010_1carrier.data
167: display_solution=false
168: hb_continue=false
169: )
170:
171:
172: solve{
173: ramp(logfile=poly_vds_1p0_vgs_p7.data,
174: RampSpecification(endValue=0.7, nsteps=20)
175: {BiasObject(name=gate,type=contactVoltage)}
176: )
177:
178: }
179:
80
200:#HB at Vgs=0.7V
201: harmonicbalance(
202: tone1=5.8e9 nharm1=5
203: tone2=5.9e9 nharm2=3
204: hb_src(name=gate m1=0.010 m2=0.010)
205: logfile=hb_vds_1p0_vgs_p7_010_010_1carrier.data
206: display_solution=false
207: hb_continue=false
208: )
209:
210: solve{
211: ramp(logfile=poly_vds_1p0_vgs_p75.data,
212: RampSpecification(endValue=0.75, nsteps=20)
213: {BiasObject(name=gate,type=contactVoltage)}
214: )
215:
216: }
217:
218:#HB at vgs=0.75V
219: harmonicbalance(
220: tone1=5.8e9 nharm1=5
221: tone2=5.9e9 nharm2=3
81
222: hb_src(name=gate m1=0.010 m2=0.010)
223: logfile=hb_vds_1p0_vgs_p75_010_010_1carrier.data
224: display_solution=false
225: hb_continue=false
226: )
227:save(meshfile=hb.tdf)
#first and third order terminal currents can be obtained from the
logfiles and hence IIP3 value for each bias can be calculated.
82