AN ACCURATE CMOS FOUR-QUADRANT ANALOG MULTIPLIER Except where reference is made to the work of others, the work described in this thesis is my own or was done in collaboration with my advisory committee. This thesis does not include proprietary or classified information. _________________________________________ Ramraj Gottiparthy Certificate of Approval: ______________________________ ______________________________ Richard C. Jaeger Bogdan M. Wilamowski, Chair Distinguished University Professor Professor Electrical and Computer Engineering Electrical and Computer Engineering ______________________________ ______________________________ Fa Foster Dai Stephen L. McFarland Associate Professor Dean Electrical and Computer Engineering Graduate School AN ACCURATE CMOS FOUR-QUADRANT ANALOG MULTIPLIER Ramraj Gottiparthy A Thesis Submitted to the Graduate Faculty of Auburn University in Partial Fulfillment of the Requirements for the Degree of Master of Science Auburn, Alabama May 11, 2006 iii AN ACCURATE CMOS FOUR-QUADRANT ANALOG MULTIPLIER Ramraj Gottiparthy Permission is granted to Auburn University to make copies of this thesis at its discretion, upon the request of individuals or institutions and at their expense. The author reserves all publication rights. _______________________ Signature of Author _______________________ Date of Graduation iv VITA Ramraj Gottiparthy, son of Rajaiah G, and Bharathi G, was born on May 29, 1981 in Hanamkonda, India. After finishing high school from Nalanda Jr. College in 1998, he attended National Institute of Technology Warangal, India where he received his Bachelor of Technology (Electrical and Electronics) degree in 2002. He entered graduate school at Auburn University in Fall of 2003 as a graduate research assistant, and later went on to accept a fellowship through Auburn University. v THESIS ABSTRACT AN ACCURATE CMOS FOUR-QUADRANT ANALOG MULTIPLIER Ramraj Gottiparthy Master of Science, May 11, 2006 (B. Tech., National Institute of Technology Warangal, 2002) 63 Typed Pages Directed by Bogdan M Wilamowski Analog multipliers are used in communication circuits, neural networks as well as frequency doublers, RMS circuits and phase detectors. High linearity is the prime issue for multipliers in conventional applications like modulation circuits. Power consumption is the criteria in case of massive parallel processing based neural networks. This thesis details the design process of four-quadrant multiplier designed using AMIS C5F CMOS process which could able to address the challenges mentioned above. Initially, different multiplier architectures are reviewed. A MOS resistor based multiplier and divider circuits are designed and simulated. Eliminating the limitations of this configuration, final four-quadrant multiplier is designed. In addition to these, input signal range, bandwidth, mismatching of transistors and active area of the chip are also optimized. The final design of multiplier has ?2.2V input range, 73MHz bandwidth, 0.242mW power consumption with 10?A bias current and -63db total harmonic distortion at 100 KHz 1Vp-p input signal. Special layout techniques like interdigitation and common centriod methods are used to reduce mismatches between transistors and effects of process variations are minimized. vii ACKNOWLEDGEMENTS My deepest respect and appreciation goes to my advisor, Dr. Bogdan M. Wilamowski for his guidance, support and encouragement provided in my journey towards the Master?s Degree in Engineering. I will forever be grateful for his endless advice, incredible patience, generosity and friendship. I am also grateful to my committee members Dr.Richard C. Jaeger and Dr. Fa Foster Dai for their guidance and support. I take the opportunity to thank Mr. Charles Ellis for his support and help. I would like to thank my father and mother, my sister Sandhya Rani and my brother Rajkumar for their enduring love, immense moral support and encouragement throughout my life. viii Style manual of journal used Graduate School: Guide to preparation and submission of theses and dissertations_________________________________________ Computer software used Microsoft Office XP_____________________________ ix TABLE OF CONTENTS LIST OF FIGURES ........................................................................................................... ix LIST OF TABLES............................................................................................................. ix Chapter 1 INTRODUCTION 1.1 Motivation................................................................................................................. 1 1.2 Architecture of Phase locked loop and neural network ............................................ 2 1.3 Research Goal ........................................................................................................... 4 1.4 Thesis outline............................................................................................................ 5 CHAPTER 2 BACKGROUND .......................................................................................... 6 2.1 Introduction............................................................................................................... 6 2.2 Multiplier Classification ........................................................................................... 8 2.2.1 BJT Gilbert multiplier........................................................................................ 8 2.2.2 MOS multiplier operating in voltage saturation region ................................... 10 2.2.3 MOS multiplier operating in current saturation region.................................... 11 2.2.4 MOS multiplier working in weak inversion region ......................................... 12 2.2.5 MOS multiplier based on translinear principle................................................ 14 2.2.6 MOS Resistors ................................................................................................. 17 2.2.7 MOS Divider Circuits...................................................................................... 18 CHAPTER 3 DESIGN AND SIMULATION OF MOS RESISTOR/DIVIDER............. 21 3.1 Introduction............................................................................................................. 21 3.2 MOS resistor/divider design ................................................................................... 21 3.3 Four quadrant multiplier using MOS resistor ......................................................... 23 3.4 Simulations ............................................................................................................. 24 3.5 Summary of Simulation Results ............................................................................. 29 CHAPTER 4 DESIGN AND SIMULATION OF MULTIPLIER ................................... 31 4.1 Introduction............................................................................................................. 31 4.2 Differential multiplier design.................................................................................. 32 4.2.1 Principle of operation....................................................................................... 32 4.2.2 Design of current subtraction circuit................................................................ 35 4.3 Simulations ............................................................................................................. 38 4.4 Summary of Simulation Results ............................................................................. 42 x CHAPTER 5 LAYOUT OF MULTIPLIER..................................................................... 43 5.1 Introduction............................................................................................................. 43 5.2 Layout considerations ............................................................................................. 43 CHAPTER 6 CONCLUSION........................................................................................... 46 BIBLIOGRAPHY............................................................................................................. 47 xi LIST OF FIGURES Figure 1.1 Block diagram of phased locked loop ............................................................... 2 Figure 1.2 Architecture of Neural Network [5] .................................................................. 3 Figure 2.1 Nonlinearity cancellations in four quadrant multiplier (a) using four single quadrant multipliers (b) using square devices .................................................................... 6 Figure 2.2 (a) BJT Gilbert multiplier (b) Gilbert multiplier with predistortion circuit [12]........................................................................................................................... 9 Figure 2.3 MOS multiplier with transistors M1-M4 operating in triode region............... 10 Figure 2.4 MOS version of Gilbert multiplier working in weak inversion region ........... 13 Figure 2.5 Voltage-translinear loop based (a) stacked topology (b) multiplier [20] ........ 14 Figure 2.6 Voltage translinear loop with floating voltage sources ................................... 16 Figure 2.7 Floating MOS resistor circuit. ......................................................................... 17 Figure 2.8 BJT Translinear divider configuration ............................................................ 18 Figure 2.9 Ideal voltage divider characteristics Vo=V1/V2 ............................................. 19 Figure 3.1 (a) Current controlled MOS resistor synthesis (b) block diagram representation.................................................................................................................... 22 Figure 3.2 Small signal equivalent circuit of MOS resistor.............................................. 22 Figure 3.3 (a) Four-quadrant multiplier using MOS resistors (b) Signal divider ............. 23 Figure 3.4 Transfer characteristics of MOS resistor......................................................... 26 Figure 3.5 Synthesized resistance of MOS resistor .......................................................... 26 Figure 3.6 Transfer characteristics of MOS resistor based four-quadrant multiplier....... 27 Figure 3.7 Normalized frequency response of four quadrant multiplier .......................... 27 Figure 3.8 Output voltage (Vo) of divider with input current (I1) as parameter (Vo=I1/I2)........................................................................................................................... 28 Figure 3.9 Output voltage (Vo) of divider with Input current (I2) as parameter (Vo=I1/I2)........................................................................................................................... 28 Figure 3.10 Simulated transient response of MOS divider............................................... 29 Figure 4.1 Simplified schematic of four quadrant differential multiplier......................... 32 Figure 4.2 small signal schematic of differential multiplier............................................. 34 xii Figure 4.3 CMOS current subtraction circuit ................................................................... 35 Figure 4.4 Complete schematic diagram of four quadrant multiplier............................... 37 Figure 4.5 Simulated transfer characteristics of CMOS multiplier .................................. 40 Figure 4.6 Total harmonic distortion of CMOS multiplier as a function of input current ............................................................................................................................... 40 Figure 4.7 Normalized frequency response of CMOS four quadrant multiplier .............. 41 Figure 4.8 Modulated output waveform of multiplier with sine and triangular wave inputs................................................................................................................................. 41 Figure 4.9 Average output current of multiplier as a function of phase difference of inputs................................................................................................................................. 42 Figure 5.1 (a) Two MOS transistor layout with L1=2? and L2=6 ? (b) equivalent circuit ................................................................................................................................ 44 Figure 5.2 (a) Current mirror transistors layout with L=2? (M1 and M2) (b) equivalent circuit......................................................................................................... 44 Figure 5.3 1k? high resistance poly based resistor layout ............................................... 45 Figure 5.4 Four quadrant multiplier layout....................................................................... 45 xiii LIST OF TABLES Table 3.1 Summary of simulation results of MOS resistor, multiplier and divider.......... 29 Table 4.1 Parameter summary of CMOS four quadrant multiplier .................................. 38 Table 4.2 Summary of simulation results of Multiplier.................................................... 42 1 CHAPTER 1 INTRODUCTION 1.1 Motivation Out surrounding world is analog in nature. Digital systems require analog to digital conversion at the front of the system and digital to analog conversion at its end. Analog computation and signal processing makes it simpler and faster [1]. Analog signal processing represents the signals as physical quantities like e.g. charge, current, voltage or frequency. These signals are continuous in value and continuous in time. Analog signal processing is most effective when precision is not the major criteria and when massive parallel collective processing of large number of signals that are continuous in time and amplitude is required [2]. Multiplication and division of analog signals are difficult operations in analog signal processing. Analog multipliers and dividers are used in communication circuits as well as in neural networks and fuzzy logic applications. Phase detector, adaptive filter, function generators, frequency doubling and amplitude modulation are some applications of analog multipliers in communications industry. Voltage gain amplifier, signal squarer, RMS signal estimator and weight-input multiplication in neural networks are some application in signal processing. Phase detector is an essential element in phase locked loops. PLLs are widely used in frequency synthesizers, demodulators, clock generation circuits, clock recovery circuits and spread spectrum PLLs. Analog multipliers as part of automatic gain control circuits used in AM radio receivers and radar systems. 2 Communication systems, low power portable applications and low power massive signal processing circuits like neural and fuzzy logic circuits have lot of demand in this century. Low power and high performance hardware implementation of these circuits is a challenging task. In addition to these, the cost of circuits must be lowered as well. All these challenges of analog multiplier and divider circuits are addressed in this thesis. 1.2 Architecture of Phase locked loop and neural network Phased locked loop is a universal building block used in both analog and digital applications. The basic structure of Phase locked loop is shown in the Figure 1.1. Phase detector finds the phase difference between input and output signals of the controlled oscillator and locks the PLL on zero phase difference. Analog multiplier is most widely used as phase detector in PLLs with sine wave inputs and sine wave outputs [3]. Multiplier with two inputs having a phase difference of ? (inputs sinxv t? and sin( )yv t? ?+ ) gives output outv . Phase Detector Loop Filter Voltage Contrlled Oscillator Frequency Reference Input FIN Frequency Reference Output FOUT Figure 1.1 Block diagram of phased locked loop }{/ 2 (2 ) [1.1]out x yv v v cos cos t? ? ?= ? + 3 The output of multiplier has DC term and double frequency term. Either by filtering the output or taking average of the output gives phase detection or phase error of the input signals. Analog VLSI implementation of artificial neural networks represents one of approaches to enhance the computational capabilities in real-time information processing. Character recognition, retrieval of data/image from fragments, pattern recognition and speech synthesis are some applications of artificial neural networks [4]. These neural networks consist of massive parallel layers of neurons interconnected with synapses as shown in Figure 1.2. The main function of the synapse cell is to achieve linear multiplication of input and a weight. These synaptic connections are implemented using Analog multipliers. Applications like multi layer feed forward networks require large number of interconnected neurons and synaptic connections (multipliers). Therefore careful design of multiplier is crucial in achieving compact silicon area, minimizing power consumption and improving input range. ? ? ? ? ? . . . . . . . . . . . . . . . . Layer m-1 Layer m Neuron SynapsemW1 mW 1 m nW 1 1 +mW 1 1 +mW 1+m nW Figure 1.2 Architecture of Neural Network [5] 4 1.3 Research Goal Our goal is to design CMOS analog multiplier and dividers with profound application to frequency doublers, phase locked loops, neural and fuzzy networks. Most of CMOS implementation of analog neural networks uses sub-threshold characteristics of MOS operation. Sub-threshold region of operation gives very limited range of operation (-100mV> Since output resistance of MOS transistor is more than transresistance, output current is controlled by output resistance of source connected transistors (ro5-ro8). Using equation (4.5), the small signal currents are given by 1 5( / 2) / [4.6]c x oi v v r= + ? 2 6( / 2) / [4.7]c x oi v v r= ? ? 34 vc+vx vc+vx vc-vx i+iy gmvgs1 gmvgs2 gmvgs4gmvgs3 ro1 ro4ro3r o2 vg1 vg4 vg2 vg3 vs1 v s4vs3 vs2 ro5 ro8ro7ro6 i1 i2 i 3 i4 i-iy Figure 4.2 small signal schematic of differential multiplier 3 6( / 2) / [4.8]c x oi v v r= ? ? 4 8( / 2) / [4.9]c x oi v v r= + ? Using equations (4.6)-(4.9) output current io is given by 1 3 2 4( ) ( ) [4.10]oi i i i i= + ? + 5 7 6 8( / 2) / ( / 2) / ( / 2) / ( / 2) / [4.11]o c x o c x o x o x oi v v r v v r vc v r vc v r= + ? + ? ? ? ? ? ? + ? Assuming matching of transistors M5, M6, M7 and M8 and equation (4.3) {( / 2)( / 2) ( / 2)( / 2) ( / 2)( / 2) ( / 2)( / 2)} [4.12] o c x y c x y x y x y i v v i i v v i i vc v i i vc v i i ?= + ? + ? + ? ? ? ? ? ? ? + ? ? + ? ? ? [4.13]o x yi K v i= ? ? K is a constant whose value is equal to ?. Thus for any given input voltage and input current, the output voltage is proportional to the product of differential input voltage and differential input current. Output current is obtained by subtracting output currents of differential pairs. This current subtractor is explained in the next section. 35 4.2.2 Design of current subtraction circuit M1 M12 M7 M8 M10M6 M9M5 M3M4 M2 M11 i2i1 i2-i1 Vcc Vdd vb M11 Iref Iref 1/4 1/4 Figure 4.3 CMOS current subtraction circuit Although, a simple current mirror can be used for current subtraction, the drain voltages of input transistors need to be kept at same value. The simple current mirror drain voltages differ by threshold voltage. So a special subtraction circuit is designed with high output resistance current mirrors. Figure 4.3 shows current subtraction circuit, which uses three identical current mirrors i.e. M1-M4, M5-M8 and M9-M11. These are high swing and high output resistance current mirrors. All these transistors have same W/L ratio and no mismatching is assumed for threshold voltages and transconductance parameters of PMOS and NMOS transistors. In this current mode implementation of 36 subtractor, the input current i1 is mirrored by M5-M8 and current i2 is mirrored by M9- M12. By principle of KCL at the output node of M1-M4 current mirror pair, i1-i2 is obtained. Current gain is excellent because of same Vds for lower pair of transistors in each mirror. To reduce channel length modulation effect, length of channels is kept high. This current subtraction circuit is connected to output of differential multiplier. The important characteristic of multiplier is to obtain large input signal ranges. Stacking less number of transistors between the power supply lines allows larger signal swings. In addition to the threshold voltages of input transistors, the current mirrors in current subtraction circuits prevents the input voltage swings from reaching the supply rails. The minimum input voltage (Vt+?) required for current mirrors decides the input swing of differential multiplier. 2 [4.14] '( / ) I K W L? = I is input current and Vt is threshold voltage of transistor. In order to improve the input signal range, ? is kept small by using lower values of bias currents. The smaller supply currents also guarantee lower power dissipation. 37 Figure 4.4 Complete schematic diagram of four quadrant multiplier 38 4.3 Simulations The simulations of this differential multiplier were done using SPECTRE circuit simulator, in Cadence Analog Artist with AMIS C5F 0.5?m technology parameters. The simulated CMOS multiplier schematic is shown in Figure 4.4. Important parameters of NMOS and PMOS like transconductance parameter (K?) and channel length modulation parameter (?) are extracted from device characteristics [36]. The extracted parameters are listed in the Table 4.1. Mismatches are avoided between NMOS and PMOS transistors by proper selection of W/L ratios as shown in table 4.1. A higher value of bias current gives better bandwidth to multiplier but at the expense of power consumption. Therefore an optimum value of bias current (10?A) is chosen to give good bandwidth as well as low power consumption. Table 4.1 Parameter summary of CMOS four quadrant multiplier Parameters Values K?n, K?p (extracted parameter) 72.96?A/V2, 6.41?A/V2 ? (extracted parameter) 0.0217V-1 Bias current IB 10?A Loading resistor RL 1k? (W/L)0-(W/L)3 20?m/0.6?m (W/L)4-(W/L)7 20?m/1.8?m (W/L)8, (W/L)28 25?m/2.4?m (W/L)23, (W/L)15-(W/L)22 75?m/2.4?m, (W/L)9-(W/L)14, (W/L)24-(W/L)27 100?m/2.4?m 39 Fig. 4.5 illustrates the simulated DC transfer characteristics of multiplier obtained for input voltage ranging from -2.2V to 2.2V in 7 steps and input current swept form - 10?A to 10?A. These transfer characteristics are simulated with 1K? load resistor. Figure 4.6 shows variation of Total Harmonic Distortion (THD) with input signal amplitude. THD simulations performed with 1V @ 100 KHz sine wave input. THD is as low as -20dB (0.1%) for full range of input current. The variation in THD is from 0.07% to 0.1% for full swing of input current. These characteristics show superior performance in terms of linearity. The output frequency response is shown in fig. 4.7. It shows that the output 3-dB bandwidth is 73MHz with 1K? resistive loading. With change in bias current the highest bandwidth that was obtained for multiplier is 192MHz for bias current of 100?A. Fig. 4.8 and Fig. 4.9 show the applications of multiplier as amplitude modulator and phase detector. Fig. 4.8 illustrates an amplitude modulator with 100 KHz carrier sinusoid (upper waveform), 5 KHz triangular periodic modulating signal (lower waveform) inputs to the multiplier and AC modulated output (middle waveform). Two input sinusoid signals ( 1 1sin(2 10 ) and sin(2 10 )V Kt I Ktpi pi ?+ ) with phase difference are applied to the multiplier and the average output current (DC component) is plotted against phase as shown in Fig.4.9. The average output current is proportional to the cosine of phase difference ( cos? ) between input signals. As shown in Fig. 4.2 MOS transistors connected at source terminals of input transistors acts as variable resistors with resistance controlled by bias current. This provides programmable multiplier cell. The worst case power consumption for multiplier is estimated to be 0.242mW. 40 Figure 4.5 Simulated transfer characteristics of CMOS multiplier Figure 4.6 Total harmonic distortion of CMOS multiplier as a function of input current 41 Figure 4.7 Normalized frequency response of CMOS four quadrant multiplier Figure 4.8 Modulated output waveform of multiplier with sine and triangular wave inputs 42 Figure 4.9 Average output current of multiplier as a function of phase difference of inputs 4.4 Summary of Simulation Results Table 4.2 Summary of simulation results of Multiplier Multiplier Characteristics Values Input voltage ?2.2V Input current range ?10?A THD @ 100KHz 0.07% Input BW 73MHz Bias current 10?A Power consumption 0.242mW Some crucial parameters that affect the performance of multiplier are provided in Table 4.2. For same supply voltage, some of parameters like power consumption, linearity and bandwidth are much better in this design compared to current-mode multiplier[37]. 43 CHAPTER 5 LAYOUT OF MULTIPLIER 5.1 Introduction The successfully simulated four-quadrant multiplier layout is made in this chapter. Some special layout techniques used in four-quadrant multiplier layout are presented in this chapter. The techniques are very important in analog circuit design in order to avoid mismatching problems in the multiplier. Some tradeoffs are made to optimize the effects. In the end, post-layout simulation results are presented using multiplier circuit extracted from layout. Layout of the multiplier is done using Cadence Virtuoso layout editor using AMIS C5F technology libraries. Assura is used for design rule check (DRC) and layout versus schematic (LVS) checking. The area is occupied by the large current mirrors of subtraction circuit with higher values of (W/L) ratios. 5.2 Layout considerations A customized transistor layout [38] is used for cascode input transistors as shown in Figure 5.1. In this configuration channel length of M2 transistor is three times longer than channel length of M1. This gives higher output resistance to M2 transistor and satisfies the condition (4.5). In this customized layout the source of M1 transistor and drain of M2 transistor are shared. Since this layout eliminates the need of metal contact between source and drain and reduces diffusion area, the effective capacitance also reduces. Further, this configuration reduces any mismatches between the two transistors. 44 Figure 5.2 shows layout of current mirror MOS transistors. To reduce current mismatches between input and output, very high width (W=100?m) transistors are used. M1 M2 G1 G2 D S (a) (b) Figure 5.1 (a) Two MOS transistor layout with L1=2? and L2=6 ? (b) equivalent circuit M1 M2 M4M3 (a) (b) Figure 5.2 (a) Current mirror transistors layout with L=2? (M1 and M2) (b) equivalent circuit 45 Long channel transistors are made by using series of 3 short channel devise with gates shorted. Process gradient-induced mismatches are minimized by reducing the distance between centriods of matched devices [39]. This interdigitated MOS transistors configuration gives common centriod to the two transistors M1 and M2. Figure 5.3 also shows common centriod based 1k? high resistance poly based resistor. HIRES mask layer is used for resistor layout. This layer blocks poly2 doping, giving very high resistance [40]. Figure 5.4 shows final four quadrant multiplier layout. Figure 5.3 1k? high resistance poly based resistor layout Figure 5.4 Four quadrant multiplier layout 46 CHAPTER 6 CONCLUSION In this work, a MOS resistor is designed and simulated. This work attempted to design four-quadrant multiplier and divider using this MOS resistor. The limited input range, low linearity and higher power dissipation of these multipliers are analyzed by means of simulation results. A better approach for differential input four-quadrant multiplier is designed and verified by means simulations to provide better results. This multiplier as phase detector can detect phase difference between input signals over 360 degree range is illustrated by simulation. The design is able achieve ?2.2V input range with 0.07% THD @ 100 KHz with 1V p-p input signal. For bias current of 10?A, the power consumption was 0.242mW. The design layout was done using AMIS C5F 0.5?m technology using Cadence Virtuoso environment. The layout of final design is verified by means of Assura (Verification tool) without any design kit. The design is cleared with respect to Design Rule Check (DRC) and Layout Versus Schematic (LVS) check. Because of setup problems with extraction tool, a post layout extraction and post layout simulations were not performed. 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