DESIGN AND OPTIMIZATION OF NANOSCALED
SILICONGERMANIUM HETEROJUNCTION BIPOLAR TRANSISTORS
Except where reference is made to the work of others, the work described in this
dissertation is my own or was done in collaboration with my advisory committee. This
dissertation does not include proprietary or classified information.
Yun Shi
Certificate of Approval:
Foster Dai
Associate Professor
Electrical and Computer Engineering
Guofu Niu, Chair
Professor
Electrical and Computer Engineering
Victor P. Nelson
Professor
Electrical and Computer Engineering
Stephen L. McFarland
Acting Dean
Graduate School
DESIGN AND OPTIMIZATION OF NANOSCALED
SILICONGERMANIUM HETEROJUNCTION BIPOLAR TRANSISTORS
Yun Shi
A Dissertation
Submitted to
the Graduate Faculty of
Auburn University
in Partial Fulfillment of the
Requirements for the
Degree of
Doctor of Philosophy
Auburn, Alabama
August 2005
DESIGN AND OPTIMIZATION OF NANOSCALED
SILICONGERMANIUM HETEROJUNCTION BIPOLAR TRANSISTORS
Yun Shi
Permission is granted to Auburn University to make copies of this thesis at its discretion,
upon the request of individuals or institutions and at their expense. The author reserves
all publication rights.
Signature of Author
Date
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Name Date
iii
VITA
Yun Shi was born on February 19, 1977, in Beijing, P. R. China. She earned the
Bachelor?s degree in 1999 from Beijing University of Posts and Telecommunications,
majoring in wireless communications. After graduation, she joined Great Dragon Tele
com and worked on the development of internet management protocol (SNMP) using
embedded operating system. In August 2001, she started her master program and joined
the Alabama Microelectronics and Science Technology Center at Auburn University.
Ever since then, she has been working on semiconductor device physics/modeling and
TCAD. She earned the Master of Science degree in July 2003, and continued on the Ph.
D program.
iv
DISSERTATION ABSTRACT
DESIGN AND OPTIMIZATION OF NANOSCALED
SILICONGERMANIUM HETEROJUNCTION BIPOLAR TRANSISTORS
Yun Shi
Doctor of Philosophy, August 2005
(M. S., Auburn University, Auburn, Al, USA. July 2003)
(B.E.E., Beijing University of Posts and Telecommunications, Beijing, P. R. China,
July, 1999)
133 Typed Pages
Directed by Prof. Guofu Niu
In this work, we explore the design and optimization of nanoscaled SiGe HBTs.
The cuto frequency fT and the maximum oscillation frequency fmax are optimized
towards Terahertz. We first start with intrinsic device designs to obtain the initial one
dimensional doping profile, which features a 7 nm base width, a high base doping of
8?1019/cm3, and a 25 nm collector width. Using this profile, the impacts of Ge designs
on device performance, including ?, regional transit time, fT, and fT?BVCEO product,
are examined at the same film stability. After comprehensive comparisons, we conclude
that graded Ge profile wins over box Ge profile in device performance metrics.
Then we focus on the 2D device scaling for the purpose of minimizing device
parasitic e ects and maintaining the high performance achieved by the highly scaled
1D design. The raised extrinsic base 2D structure is used, which is widely used in 200
GHz ? 350 GHz SiGe HBT technologies. To better understand 2D parasitic e ects,
v
the transit time analysis is extended to 2D, which provides a method to analyze the
distributive capacitance. Two lateral scaling schemes, fixed total base width (wBase) and
fixed extrinsic base width (wex;B), are examined. When emitter window is scaled to 60
nm, fmax can be optimized to 1090 GHz for both scaling. However, fixed wex;B scaling
features less extrinsic base transit time ?B;ex, and hence the higher fT. Therefore, fixed
wex;B lateral scaling is favored for those highlyscaled SiGe HBT designs.
vi
ACKNOWLEDGMENTS
I am so grateful that there are so many people in my life who support and encourage
me to finish this work. Without any of them, it is hard to imagine how I can stay focused
and motivated through. First of all, I want to acknowledge my parents ? for years, their
unconditional love and continuous support has given me strength to grow and overcome
di culties. This dissertation is dedicated to them. Secondly, I want to thank my advisor
Prof. Guofu Niu for giving me the opportunity to start my graduate studies in semi
conductor physics/TCAD and providing me a strong base to undertake this work. I also
thank my advisory committee, Dr. Foster Dai, Dr. Adit D. Singh, Dr. Victor Nelson, and
Dr. John Williams for their interests and comments. Additional thanks to Tongan Wang,
Rui Yan, Hua Yang, Weidong Tang for their long time encouragement. Thanks to Kejun
Xia for his fruitful discussions and friendship. I am thankful for the financial assistance
provided by the National Science Foundation under ECS0119623 and ECS0112923,
the Semiconductor Research Corporation under SRC #2001NJ937, an IBM Faculty
Partner Award, and the Alabama Microelectronics Science and Technology Center. Fi
nally, I want to acknowledge the Lord Jesus Christ for making the race worth running
and the prize worth living for.
vii
Style manual or journal used IEEE Transactions on Electron Devices (together
with the style known as ?auphd?). Bibliography follows van Leunen?s A Handbook for
Scholars.
Computer software used The document preparation package TEX (specifically
LATEX) together with the departmental stylefile auphd.sty. The plots were generated
using MICROSOFT VISIO R?, MATLAB R?.
viii
TABLE OF CONTENTS
LIST OF FIGURES xi
LIST OF TABLES xv
1 MODERN SIGE HBT OVERVIEW 1
1.1 SiGe HBT Operations with Device Scaling . . . . . . . . . . . . . . . 3
1.1.1 fT and Device Scaling . . . . . . . . . . . . . . . . . . . . . . 5
1.1.2 JC;peak and Device Scaling . . . . . . . . . . . . . . . . . . . . 7
1.1.3 Avalanche and Device Scaling . . . . . . . . . . . . . . . . . . 8
1.1.4 RB and Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1.5 fmax and Device Scaling . . . . . . . . . . . . . . . . . . . . . 12
1.2 SiGe HBT Design Examples . . . . . . . . . . . . . . . . . . . . . . . 13
1.2.1 200 GHz SiGe HBTs . . . . . . . . . . . . . . . . . . . . . . . 13
1.2.2 Fabrication Process . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3 Dissertation Contributions . . . . . . . . . . . . . . . . . . . . . . . . 16
2 1D PROFILE OPTIMIZATION 20
2.1 Physical Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2 Intrinsic Design for THz fT . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.1 Emitter Design . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.2 Base Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.3 Collector Design . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3 1D Parasitic Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3.1 1D Transit Time . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3.2 Distributive Capacitance . . . . . . . . . . . . . . . . . . . . . 42
2.4 Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.4.1 Impact of Ge . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.4.2 Impact of Collector Design . . . . . . . . . . . . . . . . . . . . 49
2.4.3 Base Profile Optimization . . . . . . . . . . . . . . . . . . . . 54
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3 2D DEVICE DESIGNS 57
3.1 2D Device Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.2 2D Parasitic Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.2.1 RB and CCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
ix
3.2.2 2D Transit Time Analysis . . . . . . . . . . . . . . . . . . . . 64
3.2.3 2D Distributive Capacitance . . . . . . . . . . . . . . . . . . . 68
3.3 Lateral Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.3.1 2D versus 1D Intrinsic . . . . . . . . . . . . . . . . . . . . . . 73
3.3.2 2D versus 2D Intrinsic . . . . . . . . . . . . . . . . . . . . . . 76
3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4 CONCLUSION 79
BIBLIOGRAPHY 80
APPENDICES 86
A MEDICI INPUT FILE 88
A.1 2D MESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
A.2 DC Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
A.3 ac Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
B MATLAB SCRIPTS 97
B.1 Transit Time Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
B.1.1 ?n and ?p Extraction . . . . . . . . . . . . . . . . . . . . . . 97
B.1.2 1D ?n and ?p Extraction . . . . . . . . . . . . . . . . . . . . . . 99
B.1.3 2D ? Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . 102
B.2 Distributive Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . 109
B.3 M 1 Postprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . 111
x
LIST OF FIGURES
1.1 The growth of SiGe HBT technology. . . . . . . . . . . . . . . . . . . 2
1.2 JC;peak versus fT;peak with SiGe HBT scaling technology [25]. . . . . . 8
1.3 Increase of junction temperature with VCE=1 V. LE is scaled that all
device have 2 mA peak fT current [25]. . . . . . . . . . . . . . . . . . 9
1.4 M1 versus fT;peak at IE=10 5A and VCB = 1.5 V [25]. . . . . . . . . . 10
1.5 Base resistance (RB) normalized by emitter stripe length and area versus
lithography node [30]. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.6 2D schematic of device structure. (a) shared base and (b) raised base. . 12
1.7 NC impact on JC;peak and fT;peak for a 200 GHz SiGe HBT design with
wB = 10 nm [35]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.8 2D schematic of a device structure used for 200  300 GHz SiGe HBTs
[26]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.9 Selective SiGe epitaxial deposition [36]. . . . . . . . . . . . . . . . . . 17
1.10 SEM picture of a 220/230 GHz fT=fmax SiGe HBT [24]. . . . . . . . . 18
2.1 Simulation of a 120 GHz SiGe HBT using tuned physical model coe 
cients. (a) Gummel, (b) fT JC, and (c) M 1 versus VCB. . . . . . . 22
2.2 NanoScaled doping and Ge profile for Terahertz fT. A lowdoped emit
ter is used. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3 fT  JC curves for Si BJT, box Ge and Graded Ge designs. VCB = 0 V.
Total Ge are kept the same. . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4 Comparisons of tunneling for two emitter designs. Box Ge profile is used. 26
2.5 Comparisons of ? for two emitter structures, with and without low
doped emitter. (a) Box Ge profile and (b) Graded Ge profile. . . . . . . 27
xi
2.6 Comparisons of the Boron outdi usion e ects between SiGe and SiGe:C. 28
2.7 Output curves of the nanoscale SiGe HBT with a xpeakmole=5% graded Ge
profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.8 The ?n and ?p distributions for a 50 GHz SiGe HBT design [48]. . . 32
2.9 The ?n and ?p distributions for Si BJT design. . . . . . . . . . . . . 33
2.10 ?E, ?EB, ?B, and ?C definitions . . . . . . . . . . . . . . . . . . . . . . 34
2.11 The ?n and ?p distributions for (a) box Ge design and (b) graded Ge. 36
2.12 (a) Comparisons of ? components versus JC characteristics between Si
BJT and graded SiGe HBT designs. (b) Comparisons of ? components
versus JC characteristics between graded Ge and box Ge designs. . . . . 37
2.13 Barrier e ect for Box Ge profile. (a) Electron concentration with in
creasing JC and (b) Hole concentration with increasing JC. . . . . . . . 38
2.14 Barrier e ect for Box Ge profile. (a) n distribution with increasing JC
and (b) ?n distribution with increasing JC. . . . . . . . . . . . . . . . 39
2.15 Barrier e ect for Graded Ge profile. (a) Electron concentration with
increasing JC and (b) Hole concentration with increasing JC. . . . . . . 40
2.16 Barrier e ect for Graded Ge profile. (a) n distribution with increasing
JC and (b) ?n distribution with increasing JC. . . . . . . . . . . . . . 41
2.17 Cte, Ctc, CdE, CdB and CdC versus JC at VCB = 0.5 V. . . . . . . . . . . 43
2.18 Comparisons of the fT;peak and ? versus total Ge for box and graded Ge
profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.19 fT;peak versus ? for box and graded Ge profiles . . . . . . . . . . . . . . 46
2.20 Comparison of fT ?BVCEO versus total Ge between box and graded Ge
profiles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.21 ?E, ?te, ?B, ?C and fT versus total Ge for (a) box Ge and (b) graded Ge. 48
2.22 wC impact on transit times components. . . . . . . . . . . . . . . . . . 50
xii
2.23 fTJC curves for wC = 200 nm, 150 nm, 100 nm, 50 nm, and 30 nm.
VCB = 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.24 Comparisons of (a) electron velocity profile, and (b) n/p distributions
inside CB SCR between wC = 200 nm and 30 nm designs. JC = 40
mA/?m2, VCB = 0.5 V. A base pushout is observed for wC = 200 nm. . 52
2.25 Electric field distribution for five subcollector designs. . . . . . . . . . 53
2.26 ?C  JC for five subcollector designs. . . . . . . . . . . . . . . . . . . 53
2.27 Optimized base profile for lower RB? . . . . . . . . . . . . . . . . . . 55
3.1 Schematic of device cross section using a raised base structure.
wE=120 nm, tEB=140 nm, tsp=40 nm, wSTI=0.4 ?m, dSTI=0.25 ?m,
wST ST=0.38 ?m, and wDT DT=1.7 ?m. . . . . . . . . . . . . . . . . . 58
3.2 Comparisons of fT/fmax  JC curves obtained between 2D DD and EB
simulations. Also shown is the 1D EB fT result. . . . . . . . . . . . . 59
3.3 Comparisons of simulation details between DD and EB on (a) elec
tron distribution, (b) electron velocity, and (c) ? distribution. JC = 30
mA/?m2, VCB = 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.4 Simulated M 1 versus VCB curves for 200 GHz and THz SiGe HBTs.
Also shown is the measured data for 200 GHz design. . . . . . . . . . . 63
3.5 Definition of 2D ? components and related capacitance. Y?EE, Y?EB and
Y?CB correspond to XEE, XEB and XCB in Figure 3. . . . . . . . . . . . 66
3.6 Simulated 2D n distribution near peak fT, VCB=0.5 V . . . . . . . . . 66
3.7 ?E, ?Ef, ?EB, ?B;in, ?B;ex, ?CSCR;in, ?CSCR;ex, ?tc;in and ?tc;ex versus JC at
VCB=0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.8 Comparison of ? contribution from each region. VCB=0.5 V. . . . . . . 68
3.9 Capacitance versus JC curves. VCB=0.5 V. . . . . . . . . . . . . . . . . 69
3.10 Illustration of lateral scaling. (a) wBase is fixed. (b) wB;ex is fixed. . . . . 71
xiii
3.11 Comparisons of intrinsic and extrinsic ?E, ?B and ?C at peak fT between
two lateral scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.12 Comparisons of (a) Ctc;in and Ctc;ex, and (b) CCSCR;in and CCSCR;ex for
fixed wBase and fixed wB;ex scalings. . . . . . . . . . . . . . . . . . . . 75
3.13 Comparisons of intrinsic and extrinsic ? contributions at peak fT. . . . . 76
3.14 Illustration of the internal 2D intrinsic device. . . . . . . . . . . . . . . 77
3.15 Comparisons of 2D intrinsic and extrinsic fT=fmax between two scalings. 77
xiv
LIST OF TABLES
1.1 SiGe HBT device scaling [25]. . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Comparison of key performance parameters for di erent SiGe growth
technologies [26]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Characteristics of manufacturable 200 GHz SiGe HBT Technology. . . 14
2.1 Physical Models at T=300K . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 2D Distributive Capacitance . . . . . . . . . . . . . . . . . . . . . . . 69
3.2 Device performance for fixed wBase lateral scaling. . . . . . . . . . . . . 70
3.3 Device performance for fixed wB;ex lateral scaling. . . . . . . . . . . . . 72
xv
CHAPTER 1
MODERN SIGE HBT OVERVIEW
The SiliconGermanium heterojunction bipolar transistor (SiGe HBT) has gained
worldwide attention, ever since the first high performance SiGe HBT with a cuto fre
quency (fT ) of 75 GHz was grown using ultrahigh vacuum/chemical vapor deposition
(UHV/CVD) [1, 2] in 1990. Compared with Si BJT and Si CMOS, SiGe HBT fea
tures high speed, low noise, and high linearity, which make SiGe HBT technology more
suitable and attractive to IC designs. After the first SiGe BiCMOS technology was in
vented in 1992 [3], single systemonchip (SoC) integration became reality by growing
the highperformance RF SiGe HBTs and the lowpower, highdensity Si CMOS on the
same substrate. BiCMOS technology provides a broad market for SiGe HBT technol
ogy, from wired to wireless applications. In recent years, the explosion of telecommu
nications, such as 3G wireless and fiber communication, has been driving SiGe HBT
technology growth from one generation to the next. Figure 1.1 shows the growth trend
of SiGe HBTs. The cuto frequency (fT ), which represents the device scaling and
hence the technology generation, has been improved over 300 GHz [8], and a 600 GHz
fT SiGe HBT design [9] has been proposed.
Terahertz band applications have become interesting research areas in recent years.
These applications cover medical and biological imaging [10], radio astronomy [11],
upper atmosphere study [12], plasma diagnostics [13], and ultrawide band communica
tion systems that would benefit from the virtually infinite bandwidth with THz spectrum.
1
1990 1995 2000 2005
0
100
200
300
400
500
600
Year
f
T,peak
(GHz)
[1,2]
[4]
[5]
[6]
[7]
[8]
[9]
Figure 1.1: The growth of SiGe HBT technology.
Currently, GaAs Schottky barrier diodes and Gunn diodes have been used as key com
ponents in THz applications, such as mixers, power generators and oscillators [14?16].
However, they do not provide the ability to integrate the signal processing function with
switching and amplification functions. Being a potential candidate, the operation fre
quency of SiGe HBT needs to be further improved through scaling.
In this work, we explore the SiGe HBT scaling issues for THz applications. First,
the vertical profile scaling for an intrinsic device was examined. A nanometerscale
design was obtained, which can achieve over 1000 GHz fT [17]. When the base width
is scaled below 10 nm, the collector design becomes the bottleneck for speed. Higher
doping (NC) and smaller thickness (wC) are proved to improve fT at high injection, and
hence achieve THz fT. The Ge design issues for such highly scaled SiGe HBTs are also
examined at the same film stability. The results show that a graded Ge profile surpasses
the box Ge profile in all device performance metrics.
2
For THz SiGe HBTs, the emitter?collector transit time, which is ?EC = 1=2?fT, is
on the order of 0.1 ps. Therefore, the delay from extrinsic parasitic e ects can degrade
the ultrahigh speed of the highly scaled intrinsic design. Besides fT, the maximum
oscillation frequency fmax is also relevant to circuit designs, and sensitive to extrinsic
parasitic e ects. A simplified expression is
fmax ?
r f
T
8?RBCtc; (1.1)
where RB is the base resistance, and Ctc is the CB junction depletion capacitance. In or
der to reduce parasitic e ects, device structures have been improved through many inno
vations, such as shallowtrenchisolation (STI) [18], doublepolysilicon technology (for
selfaligned emitter structure) [19, 20], selectively ionized collector (SIC) [21], SiGe:C
base [22], raised extrinsic base [23], and selectivelyepitaxial grown (SEG) base [24].
These design innovations have been implemented in this work. Another method of re
ducing parasitic e ects is lateral scaling. As we will see later, as fT increases from 50
GHz to 300 GHz, the emitter window wE decreases from 0.5 ?m to 0.12 ?m to achieve
high fmax. The impact of lateral scaling on THz SiGe HBTs is examined, and 1000 GHz
fmax is achieved when wE is reduced to 60 nm.
1.1 SiGe HBT Operations with Device Scaling
The essential benefit of a SiGe HBT over Si BJT is that we can reduce the bandgap
Eg by introducing Ge in the base. The result is an exponential increase of the e ective
3
intrinsic carrier concentration, and hence the minority carrier density. By controlling
the Ge profile, an accelerating electric field can be established in the base, which favors
minority electron transport for an npn transistor, and thus helps reduce base transit time
?B. Another advantage of using a SiGe base is that the low base sheet resistance RB;?,
high ? and low ?B can be achieved simultaneously.
Much e ort has been made for SiGe HBT scaling in order to improve device per
formance. A brief summary of the structure scaling trend and its impact on electrical
performance are listed in Table 1.1. For the emitter design, phosphorus is preferred due
Table 1.1: SiGe HBT device scaling [25].
Emitter Base Collector
Structure Arsenic to Narrow base Increase doping
Phosphorus Improve extrinsic design Improve
Reduce emitter Higher Ge ramp extrinsic design
window Add Carbon
Electrical Lower RE Lower RB Higher avalanche
Reduced thermal budget Lower ?B Higher JC;peak
for dopants drivein Higher CCB
to its low resistivity, which helps reduce emitter resistance RE. For the base design,
besides the aggressive base width wB reduction, a higher Ge ramp is also used to help
reduce base transit time ?B. Additionally, base doping is increased, and the extrinsic
base design is improved to reduce RB. For the collector design, a higher doping and a
narrow thickness design are used to reduce collector transit time ?C. Inevitably, the Kirk
e ect is surpassed, but the breakdown voltage is reduced due to the higher CB space
charge region (SCR) electric field. The impacts on device performance through grow
ing technologies are compared in Table 1.2 for five generations of SiGe HBTs [26]. As
4
Table 1.2: Comparison of key performance parameters for di erent SiGe growth tech
nologies [26].
Generation Index 1 2 3 4 5
wE (?m) 0.5 0.25 0.18 0.13 0.12
fT (GHZ) 47 47 120 210 375
fmax (GHz) 65 65 100 285 210
? 100 100 350 300 3500
BVCEO (V) 3.4 3.4 1.8 1.7 1.4
BVCBO (V) 10.5 10.5 6.5 5.5 5.0
JC;peak (mA/?m2) 1.5 1.5 8 12 23
discussed, the emitter window wE is reduced from 0.5 to 0.12 ?m, fT/fmax is improved
to 375/210 GHz, and the Kirk e ect is delayed, which is indicated by the increase of
JC;peak. However breakdown performance is sacrificed. BVCEO is reduced from 3.4 V
to 1.4 V. Next, we will briefly discuss how the performance of each device is impacted
through vertical scaling.
1.1.1 fT and Device Scaling
The cuto frequency fT, a figureofmerit for device speed, can be generally ex
pressed as
1
2?fT = ?f +?t; (1.2)
?f = ?E +?B +?CSCR (1.3)
?t = VthJ
C
(Cte +Ctc): (1.4)
5
?f is the forward transit time due to electron di usion for an npn SiGe HBT. ?t is the
depletion capacitance charging time associated with EB junction (Cte) and CB junction
(Ctc). Vth is the thermal voltage and JC is the collector current density. ?f includes the
emitter transit time ?E, the base transit time ?B, and the collector space charge region
transit time ?CSCR. For an npn bipolar transistor with constant base doping and Ge
profile, ?E and ?B can be expressed as
?E = 1? w
2
E
2Dp; (1.5)
?B = w
2
B
2Dn: (1.6)
wE and wB are the quasineutral emitter and base width, ? is the current gain, Dp is the
minority hole di usivity in the emitter and Dn is the minority electron di usivity in the
base. ?E can be reduced significantly through increasing ?. Depending on the emitter
and base design, a su cient ? is required to make ?E negligible. A main feature of
scaled SiGe HBT is the significantly reduced base width wB, which has decreased from
100 to 5 nm, accompanied by increased base doping NB. Once the emitter and base
are scaled down to the nanoscale, ?CSCR becomes the bottleneck for speed. Generally,
?CSCR can be expressed as [27]
?CSCR = 1X
CSCR
ZXCSCR
0
XCSCR x
v(x) dx; (1.7)
where XCSCR is the space charge region width, and v(x) is the local carrier velocity. For
equilibrium transport, where the electron velocity saturates at Vsat in the collector SCR,
6
the right side of (1.7) equals ?XCSCR=2Vsat?. Using firstorder approximations [28]
XCSCR / 1p
NC
(1.8)
Therefore, to fully benefit from base scaling, the collector doping NC needs to be in
creased to reduce ?CSCR.
1.1.2 JC;peak and Device Scaling
Observing (1.2)  (1.4), at the same JC, fT can be improved through the ?f and
junction capacitance reduction. Interestingly, however, when NC is increased to reduce
collector transit time ?CSCR, the Kirk e ect is delayed simultaneously. The reason is
that the current density JC;peak at which base push out occurs [29] is proportional to NC.
As a result, not only does the peak fT value increase, but also it happens at higher JC.
fT rolls o when JC > JC;peak. JC;peak has increased from 3 mA/?m2 to 23 mA/?m2 as
technology increases from 50 GHz to 375 GHz [25], as shown in Figure 1.2.
The concerns with the higher JC are the potential device degradations associated
with electromigration and selfheating, both of which are addressed by spreading current
and power over an increasingly narrow emitter. Copperinterconnection and appropriate
emitter layout can eliminate the electromigration. For device selfheating, it has been
demonstrated in [25] that when the emitter width is scaled down proportionally to the
increased JC;peak, and the device perimeter is maintained constant, selfheating can be
controlled to guarantee reliable device operation. Figure 1.3 shows one such example
[25]. As JC;peak increases with device scaling, wE is scaled proportional to 1/JC;peak, and
7
0 50 100 150 200 250 300 350 400
0
5
10
15
20
25
Peak f
T
(GHz)
J
C,f
T,peak
(mA/
m
m
2
)
Figure 1.2: JC;peak versus fT;peak with SiGe HBT scaling technology [25].
emitter length lE is chosen that fT peaks at the same collector current IC = 2 mA for
each technology. As a result, the selfheating induced junction temperature increase can
be maintained below 20 K. For the THz designs proposed in this work, JC;peak is as high
as 40 mA/?m2. A much more careful layout is required to maintain the device reliability
with such high values of JC;peak.
1.1.3 Avalanche and Device Scaling
The higher NC also increases the CB SCR electric field. As we know, a higher field
leads to a higher impact ionization rate, and thus a more severe avalanche e ect. The
8
0 5 10 15 20 25
0
5
10
15
20
25
30
J
C,peak
(mA/mm
2
)
D
T
J
(K)
w
E
scaled with 1/J
C
l
E
scaled to keep all devices
have 2 mA peak f
T
current
Figure 1.3: Increase of junction temperature with VCE=1 V. LE is scaled that all device
have 2 mA peak fT current [25].
avalanche e ect can be measured using the M1 factor as
M 1 = In;outI
n;in
1; (1.9)
= IC(VCB)I
E IB(VBE)jVCB=0
1; (1.10)
where In;out is the electron current flowing out of the collector SCR, and In;in is the
electron current flowing into the collector SCR. This trend is shown in Figure 1.4 [25].
A higher M 1 indicates the more severe avalanche e ect.
The breakdown voltage BVCEO equals the VCE at which M 1 = 1=?. With
increasing ?, the threshold M 1 decreases. Therefore the BVCEO decreases as well
9
0 50 100 150 200 250 300 350 400
0
0.005
0.01
0.015
0.02
f
T
(GHz)
M?1
V
CB
= 1.5 V
I
E
= ?10
?5
A
Figure 1.4: M1 versus fT;peak at IE=10 5A and VCB = 1.5 V [25].
with technology growth. As shown in Table 1.2, BVCEO is reduced from 3.4 to 1.4 V
when fT increases from 47 to 375 GHz.
1.1.4 RB and Scaling
Base resistance RB impacts both RF noise performance and fmax. RB reduction can
be achieved through the lateral scaling as well as structural improvements, such as the
doublepoly process and the raised polysilicon base structure. Figure 1.5 shows the RB
improvement versus lithography node [30]. The data are normalized by emitter stripe
length and emitter area, respectively. As shown, a 15?18% per generation decrease in
lengthnormalized RB is observed when wE is reduced from 0.5 ?m to 0.18 ?m. The
reason is the intrinsic base resistance RB;in reduction, which is inversely proportional to
10
wE as
RB;in = 112 wEl
E
RB;?; (1.11)
where lE is the emitter length, and RB;? is the base sheet resistance.
0 0.1 0.2 0.3 0.4 0.5 0.6
0
50
100
150
200
250
300
350
400
450
Lithography Node (mm)
Norm R
B
(
W
?
m
m &
W
?
m
m
2
)
Normalized by L
E
(unit: W?mm)
Normalized by A
E
(unit: W?mm
2
)
raised
base
Figure 1.5: Base resistance (RB) normalized by emitter stripe length and area versus
lithography node [30].
For these early technologies, a ?sharedbase? design is used to form the extrinsic
base. Figure 1.6 (a) shows the 2D cross section of a sharedbase structure. The dis
advantage is that the p+ extrinsic base leads to a high extrinsic Ctc. The implantation
process also damages the collector epilayer and induces traps, which further increases
Ctc. Starting from 0.13 ?m node, a ?raisedbase? design is used to form the extrinsic
base on top of the SiGe base, as shown in Figure 1.6 (b). Because the extrinsic Ctc is not
related to the p+ base, a higher doping can be used, which helps reduce RB. As a result,
a much larger 68% drop in RB is observed for the lengthnormalized RB.
11
X49X6EX74X72X69X6EX73X69X63
X42 X61X73X65
X45 X78X74X72X69X6EX73X69X63
X42X61X73X65
X43 X6FX6CX6CX65X63X74X6FX72
X70X65X64X65X73X74X61X6C
X43 X63X62X2CX65X78
X49X6DX70X61X63X74
X53 X54 X49
(a)
X49X6EX74X72X69X6EX73X69X63
X42X61X73X65
X45 X78X74X72X69X6EX73X69X63
X42X61X73X65 X70X6FX6CX79
X53 X54X49
X43 X6FX6CX6CX65X63X74X6FX72
X70X65X64X65X73X74X61X6C
X43 X63X62X2CX65X78
X69X6DX70X61X63X74
X72X65X64X75X63X65X64
(b)
Figure 1.6: 2D schematic of device structure. (a) shared base and (b) raised base.
1.1.5 fmax and Device Scaling
As discussed above, through vertical scaling, fT can be improved dramatically.
RB and Ctc can be reduced by lateral scaling and device structure innovations as well.
Additionally, the shallowtrenchisolation (STI) and selectiveimplantedcollector (SIC)
structures can also help reduce extrinsic CB capacitance. Recall (1.1) that a reduction
12
of Ctc is desired to improve fmax. Overall, fmax has been increased from 65 GHz to 300
GHz for modern SiGe HBTs.
1.2 SiGe HBT Design Examples
From a design point of view, we devide the real device into intrinsic and extrinsic
parts. Generally, the intrinsic device, which performs the main device functions, deter
mines the device performance to first order. The extrinsic device, which is essential to
link the current flow to electrodes, introduces parasitic e ects and hence degrades over
all performance. Therefore, the goal is to achieve high performance through intrinsic
designs and minimize the parasitic e ects through extrinsic designs.
1.2.1 200 GHz SiGe HBTs
Many research groups have contributed to the optimization of SiGe HBTs and have
published the designs for 200 GHz devices. Table 1.3 shows the characteristics of four
examples. As discussed previously, the thin base width wB is for the purpose of reducing
?B. Correspondingly, peak NB is increased to the 1019/cm3 ? 1020/cm3 to keep the low
base sheet resistance RB;?.
The high collector doping NC is required to achieve higher fT, and as discussed,
JC;peak increases as well. Figure 1.7 shows the impact of NC on fT;peak and JC;peak for a
200 GHz SiGe HBT design with wB = 10 nm. When NC increases from 5?1016/cm3 to
1018/cm3, peak fT is improved from 110 GHz to 240 GHz, and JC;peak increases from 1
mA/?m2 to 4.5 mA/?m2 [35].
13
Table 1.3: Characteristics of manufacturable 200 GHz SiGe HBT Technology.
Reference [31] [32] [33] [34]
Lithographic node (?m) 0.15 0.18 0.2 0.12
fT/fmax (GHZ) 190/100 206/184 166/210 207/285
? ? 450 2000 400
BVCEO (V) 1.7 1.8 1.7 1.7
JC;peak (mA/?m2) 6.6 8 8 8.3
Peak NB (/cm3) 2?1020 4?1019 3.5?1020 4?1019
wB (nm) 2.5 25 1.2 20
Gepeak 10% 25% 22% 25%
RB;? (k /?) 2.5 3.0 2.0 2.5
10
17
10
18
1
1.5
2
2.5
3
3.5
4
4.5
5
N
C
(/cm
3
)
J
C,f
T,peak
(mA/
m
m
2
)
100
120
140
160
180
200
220
240
260
f
T,peak
(GHz)
J
C,f
T,peak
f
T,peak
Figure 1.7: NC impact on JC;peak and fT;peak for a 200 GHz SiGe HBT design with wB
= 10 nm [35].
14
Figure 1.8: 2D schematic of a device structure used for 200  300 GHz SiGe HBTs [26].
1.2.2 Fabrication Process
The challenge of extrinsic device design is to minimize the parasitic e ects and
guarantee the high performance given by intrinsic designs. Figure 1.8 shows a 2D
schematic of the device structure used for 200 ? 300 GHz SiGe HBTs [26]. As shown,
the doublepolysilicon structure is used to make the emitter selfaligned to the extrinsic
base. The SiGe base is grown nonselectively. A doublebase contact structure is used,
which reduces the base resistance by 1/4 compared to the single base contact structure.
The extrinsic base is raised to the top of the intrinsic SiGe base. As a result, the CB
15
junction traps induced by ptype extrinsic base implantation are reduced. The base re
sistance is reduced as well, since the new structure allows a higher extrinsic base doping.
The SIC is also used in order to reduce the extrinsic CB capacitance Ctc.
The structure shown in Figure 1.8 can be improved by using a selectivelygrown
epitaxial SiGe base. Figure 1.9 illustrates the process sequence. First, the polysilicon
base is deposited and p+ implantation is conducted. The pad oxide under the extrin
sic base prevents the p+ extrinsic base di usion during the epitaxial base prebake and
restricts the area so that the CB capacitance can be reduced. Another advantage is
that the rapidthermalannealing (RTA) after implantation, which is a high tempera
ture process, happens before base formation. This helps to maintain a heavily doped
thin base. Figure 1.10 shows an SEM crosssection of a SiGe HBT with 220/230 GHz
fT=fmax [24], where the base was grown using selective SiGe epitaxy. In this work, we
design the 2D structure based on those advanced features and fabrication capabilities.
1.3 Dissertation Contributions
The design and optimization of SiGe HBTs for high speed has been explored exten
sively in recent years. When the intrinsic vertical design is scaled down to the nanometer
regime, there are new concerns and design issues. Especially for the extrinsic design,
since now the intrinsic delay has now been reduced to 0.1 ps range, any comparable
delay due to parasitic e ects will sacrifice the ultrahigh speed given by intrinsic design.
Motivated by this challenge, we explore both the intrinsic 1D and extrinsic 2D design
issues using MEDICI [37].
16
Figure 1.9: Selective SiGe epitaxial deposition [36].
17
Figure 1.10: SEM picture of a 220/230 GHz fT=fmax SiGe HBT [24].
In Chapter 2, we first run 1D device simulations to achieve the initial designs
e ciently. A nanoscaled SiGe HBT profile is obtained, which can achieve terahertz
fT. The spatial distribution of the total transit time is shown to be di erent from that in
conventional devices. Extensive comparisons of the box and graded Ge profiles show
that the graded profile leads to higher fT, higher ? and higher BVCEO for the same
total amount of Ge for nanoscale SiGe HBTs. A gradual ncollector to n+ subcollector
transition is shown to give higher fT, BVCEO and slower fT rollo .
The 2D design and parasitic e ects are examined in Chapter 3. The delay contri
bution from each extrinsic device region is examined by using 2D regional transit time
analysis. The device parasitic rB and Ctc are extracted, and the dependence on lateral
scaling is examined as well. 1.09 THz fmax is achieved when wE is 60 nm. The overall
18
results would provide the guidelines for designing ultra fast SiGe HBTs with Terahertz
fT/fmax.
19
CHAPTER 2
1D PROFILE OPTIMIZATION
Device vertical scaling has been driven by the purpose of increasing cuto fre
quency fT. For the early technology, base transit time ?B is the limitation of the speed.
By reducing base width wB, ?B has been reduced significantly. Therefore, the collector
space charge region (SCR) transit time, ?CSCR, becomes the bottleneck, which makes
the scaled SiGe HBT design more a collector design issue. A high collector doping NC
and a narrow collector epitexial layer wC are desired to reduce ?CSCR. When device
dimension is reduced to nanometer scale, the nonequilibrium transport becomes signif
icant due to both high electric field and rapid field change. Because of nonequilibrium
transport, velocity overshoot occurs, and collector doping does not have to increase dra
matically to achieve THz design. Hence, the device breakdown performance can be
suitable for application requirements.
We first tune the physics models used in MEDICI, which can obtain reasonable
device simulation results. Then, the design details for the vertical profile of THz fT are
addressed. The impact of Ge profile (box vs. graded) on THz device performance is
compared at the same film stability. Since the collector design is more important for the
THz design, we examine the impact of collector width wC and n=n+ transition on fT and
BVCEO.
20
2.1 Physical Models
Before addressing design details and device characteristics analysis, we tune the
physical models and their coe cients for device simulations. The validity is demon
strated by the simulations of a 120 GHz SiGe HBT.
With device scaling, not only the high electric field, but also the rapid change of
electric field over a short distance are present for scaled SiGe HBTs. As a result, the
nonequilibrium carrier transport leads to high order phenomena, such as velocity over
shoot. In order to model device function correctly, the energy balance (EB) equations
are solved together with Poison?s equation, and electron and hole continuity equations.
Table 2.1 lists the physical models and their Ge dependence. The e ective density
of states in SiGe is adjusted by fitting experimental IV data of a 120 GHz HBT, as
shown in Figure 2.1 (a). The a nity for SiGe is the same as for Si, meaning the Ge
induced bandgap reduction is on the valence band completely. Slotboom BGN model is
used to model the heavy doping induced bandgap narrowing [38,39]. Due to the lack of
experimental BGN data for SiGe, we assume here that the apparent BGN for SiGe is the
same as for Si. Boltzmann statistics, as opposed to Fermidirac statistics, is used in order
to ensure physically consistent modeling of minority carrier concentration, as discussed
in [40]. The Philip?s unified mobility model is used to be consistent with Slotboom?s
BGN model [41]. An electron relaxation time ?n = 0.3 ps is used. The simulated fT can
fit the measured fT (2D), as shown in Figure 2.1 (b).
The calibration of avalanche multiplication factor M1 over VCB at fixed JE = 1
mA/?m2 is shown in Figure 2.1 (c). The model works well in the VCB range of 0.9
21
0.6 0.65 0.7 0.75 0.8
10
?6
10
?5
10
?4
10
?3
10
?2
10
?1
10
0
V
BE
(V)
J
C
, J
B
(mA/
m
m
2
)
120 GHz SiGe HBT (V
CB
=0 V)
Meas.
Calibration
(a)
10
?1
10
0
10
1
0
20
40
60
80
100
120
J
C
(mA/mm
2
)
f
T
(GHz)
Meas.
Calibration
120 GHz SiGe HBT
V
CB
=1 V
(b)
0.5 0.9 1 1.5 1.7 2 2.5
10
?5
10
?4
10
?3
10
?2
10
?1
10
0
V
CB
(V)
M?1
Meas.
Calibration
120 GHz SiGe HBT
J
e
= 1 mA/mm
2
0.9 ?? 1.7
Avalanche (BV)
overestimated by
calibration
(c)
Figure 2.1: Simulation of a 120 GHz SiGe HBT using tuned physical model coe cients.
(a) Gummel, (b) fT JC, and (c) M 1 versus VCB.
22
Table 2.1: Physical Models at T=300K
Model Ge Dependence (x)
Density of States NC;Si=2.89?1019/cm3 NC;SiGe = NC;Si
NV;Si=1.04?1019/cm3 NV;SiGe = 0.4 ?NV;Si
Bandgap Eg;Si=1.12 eV Eg;SiGe = Eg;Si 0.74x
A nity ?Si=4.17 eV ?SiGe = ?Si
BGN Slotboom BGN Same as Si
Statistics Boltzmann Statistics ?
G/R SRH and Auger ?
Mobility Philips Unified Mobility model Same as Si
Relaxation Time ?n=0.3 ps Same as Si
V ? 1.7 V, after which the avalanche e ect is overestimated by simulations, and hence
indicates that the simulated breakdown voltage is lower than measured. To the first order,
we expect the simulated breakdown voltage to be reasonable for terahertz designs. Self
heating is more dependent on the 2D layout, and therefore is not included in the intrinsic
device performance.
2.2 Intrinsic Design for THz fT
Using the tuned physical models, we obtained a highly scaled 1D profile as shown
in Figure 2.2 [42]. The metallurgical base width is 7 nm. the peak base doping is
8?1019/cm3. The base sheet resistance R? is 8 k =?. A retrograding collector profile
is used for optimum high injection performance and breakdown voltage tradeo . A 20
nm thick lowdoped collector is used to reduce ?C. Using this doping profile, both box
23
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
10
16
10
18
10
20
10
22
Depth (mm)
Doping (/cm
3
)
High?low
Emitter
Ge profile ?
Graded
vs. Box
n
+
n
p n n
+
x
mole
peak
x
mole
box
Figure 2.2: NanoScaled doping and Ge profile for Terahertz fT. A lowdoped emitter
is used.
and graded Ge profile designs are examined at the same film stability. For the box Ge,
xboxmole=18%. For the graded Ge, xpeakmole=27%.
Figure 2.3 shows the simulated fT JC curves. The Sibase design has 500 GHz
peak fT, the box and graded SiGe designs show 1.2 and 1.5 terahertz (THz) peak fT,
respectively. Next, we will address in detail the emitter, base and collector designs.
2.2.1 Emitter Design
In order to reduce emitter resistance RE, a high emitter doping concentration of NE
= 1021/cm3 is used. A lightly doped emitter EL, with NEl = 3?1018/cm3, is sandwiched
between the heavily doped emitter and base, as shown in Figure 2.2. The purpose is
to reduce tunneling current and G/R current as well. To see the improvement, the base
current density JB is simulated for the EB profile with and without lowdoped emitter,
24
10
0
10
1
10
2
0
200
400
600
800
1000
1200
1400
1600
1800
J
C
(mA/mm
2
)
f
T
(GHz)
Box Ge (x
mole
box
=18%)
Graded Ge (x
mole
peak
=27%)
Si Only
V
CB
= 0 V
Figure 2.3: fT  JC curves for Si BJT, box Ge and Graded Ge designs. VCB = 0 V. Total
Ge are kept the same.
respectively. The box Ge profile is used in both. The results are compared in Figure 2.4.
When the tunneling model is turned o , shown as the solid lines, the JB for the high
low emitter design is more ideal at the low VBE range of 0.3  0.5 V. The reason is that
the doping concentration at EB junction is smaller when a lowdoped emitter is used,
which leads to a longer carrier lifetime and hence a less G/R current. When tunneling is
included, shown as the dash lines, both JB values are increased due to the EB junction
tunneling currents. For the design without the highlow emitter, the tunneling is much
more severe due to the heavier doping concentration at the junction.
Another advantage is that the lowdoped emitter is depleted, and the EB SCR is
located at this region. Therefore, the base width modulation due to the change of VBE is
less. Figure 2.5 (a) and (b) compare the ? between two emitter structures for both box
25
0.3 0.4 0.5 0.6 0.7 0.8 0.9
10
?10
10
?8
10
?6
10
?4
10
?2
10
0
V
BE
(V)
J
B
(mA/
m
m
2
)
nEL + Tunneling
nEL
EL + Tunneling
EL
Band?to?band
Tunneling
Figure 2.4: Comparisons of tunneling for two emitter designs. Box Ge profile is used.
and graded Ge profiles. The lowemitter structure has a more linear ? curve. The box
Ge profile is better than the graded Ge profile, due to less Ge ramp e ect. However, the
process of forming a thin layer of lowdoped emitter using insitu growth is di cult and
expensive. Usually, phosphorus is used, which features a low resistivity compared with
arsenic.
2.2.2 Base Design
To mimic the profile after fabrication, a nonuniformly doped base profile is used,
with the peak base doping as high as 8?1019/cm3. In order to reduce the base transit
time ?B dramatically, the base width is scaled as narrow as 7 nm. The fabrication inno
vations, such as ?HCIfree LPCVD?, have made it possible to grow a high quality thin
Boron layer with doping level in the 1020/cm3 range [31]. The base sheet resistance,
26
10
?2
10
?1
10
0
10
1
10
2
0
200
400
600
800
J
C
(mA/mm
2
)
b
with E
l
no E
l
(a)
10
?2
10
?1
10
0
10
1
10
2
0
500
1000
1500
J
C
(mA/mm
2
)
b
with E
l
no E
l
(b)
Figure 2.5: Comparisons of ? for two emitter structures, with and without lowdoped
emitter. (a) Box Ge profile and (b) Graded Ge profile.
27
0 0.2 0.4
10
16
10
17
10
18
10
19
10
20
Depth (mm)
Boron (/cm
3
)
SiGe:C
0 0.2 0.4
10
16
10
17
10
18
10
19
10
20
Depth (mm)
Boron (/cm
3
)
No C
Boron
OutDiff
as
grown
After
RTA
Figure 2.6: Comparisons of the Boron outdi usion e ects between SiGe and SiGe:C.
R?, is 8 k =?, which is higher than the R? of 2.5 ? 3 k =? for 200 GHz technology.
A main challenge of maintaining such a heavily doped thin base is the so called base
outdi usion during the following high temperature process. Benefitting from the fabri
cation technology improvement, Carbon has been added into the SiGe layer to eliminate
the base outdi usion and guarantee that the nanoscaled base design will be manufac
turable [43, 44]. Figure 2.6 illustrates the benefit of using SiGe:C. As discussed in [44],
usually a Carbon concentration of 1020/cm3 is required to achieve substantial suppres
sion of the Boron outdi usion, while the active Boron concentration is not impacted.
28
2.2.3 Collector Design
The collector design is very involved, which determines collector transit time ?C,
the onset of Kirk e ect and hence JC at peak fT (JC;peak), and the breakdown voltage.
Collector doping NC impact on transit time ?C has been examined extensively [35] [45].
Using first order approximation, as addressed in [28],
?C = ?CSCR +?tc (2.1)
/ 1N
C
;
where ?CSCR is the collector SCR transit time and ?tc is the CB depletion capacitance
charging time. Intuitively, NC should be increased with scaling to reduce ?C. In this
work, a retrograding collector profile is used for optimum high injection performance
and breakdown voltage tradeo . A 20 nm thick moderately doped collector is used to
reduce ?C [46]. The narrow collector is fully depleted, and thus the n=n+ transition has
impacts on fT and BVCEO, as will be addressed later.
For the nanoscale base design, the base must be designed to avoid base punch
through. Besides, the breakdown voltage BVCEO should be practical. To examine these
issues, a simple 2D simulation is performed. Figure 2.7 shows the simulated output
curves for a graded Ge profile design with xpeakmole = 5%, and IB = 50 ?A to 200 ?A, in
50 ?A step. The device shows no base punchthrough, and a 1.65 V BVCEO is observed.
The measured BVCEO for a 350 GHz fT SiGe HBT is 1.4 V [47]. A higher BVCEO in
this design is due to the lower ?. In this design ? is 720, while in [47], ? is 3500.
29
0 0.5 1 1.5 2 2.5 3
0
5
10
15
20
25
V
CE
(V)
I
C
(mA/
m
m)
Graded Ge (x
mole
peak
=15%)
Total Ge: 0.75 ?10nm 10%Ge
f
T,peak
=1210 GHz
w
E
= 0.12 mm
I
B
= 50 ? 200 mA
BV
CEO
=1.65 V
Figure 2.7: Output curves of the nanoscale SiGe HBT with a xpeakmole=5% graded Ge
profile.
2.3 1D Parasitic Analysis
Recall that fT is inversely proportional to the overall transit time as
1
2?fT =
X
?n: (2.2)
To probe device internal delay, a regional analysis of transit time is conducted to sep
arate and extract each ? component. The transit delay can also be modeled using the
distributive capacitance, which can be extracted using
C = ? ?gm: (2.3)
30
gm is the transconductance and can be extracted using the real part of y21 at low fre
quency. The capacitance associated with the junction depletion region is called the de
pletion capacitance. The capacitance associated with the excess minority carrier storage
is called the di usion capacitance.
2.3.1 1D Transit Time
Transit time analysis is widely used in understanding the spatial distribution of
transit time ?n and ?p, which are defined as,
?n = q n= JC; (2.4)
?p = q p= JC: (2.5)
n, p and JC are electron, hole and conduction current density changes for a small
ac excitation at the base, when VCE is fixed [48]. For traditional designs with wider wB,
there is always a region in the base where ?n= ?p, as can be seen in Figure 2.8 for a
50 GHz fT SiGe HBT [48]. However, for the nanoscale base design, such a region of
?n= ?p does not exist, and ?n? ?p in the whole base, as shown in Figure 2.9 for
the Si design. Due to charge conservation, the total electron and hole charge changes
must be the same, meaning Rl0 ?ndx=Rl0 ?pdx. Therefore, as shown in Figure 2.8, the
?p integration area A in the base must be equal to the shaded area B in the collector.
With scaling, the integration of ?n in the ptype base is much smaller than in the n
type collector. As a result, ?p, which is related to area A, must be much larger than
31
0.15 0.2 0.25 0.3 0.35 0.4
?10
0
10
20
30
40
50
60
70
80
Depth (mm)
D
t
n
,
D
t
p
(ps/
m
m)
Dt
n
Dt
p
Dt
n
=Dt
p
J
C
= 1mA/mm
2
V
CB
= 0 V
near peak f
T
f
T,peak
=50 GHz
A
B
A = B
Base Collector
Figure 2.8: The ?n and ?p distributions for a 50 GHz SiGe HBT design [48].
?n in the base to balance the greater ?n distribution in the collector, and hence the
?n= ?p region disappears at nanoscale base width. Figure 2.9 also shows clearly that
the emitter transit time severely limits fT in the Si design. An EB junction high injection
barrier due to heavy base doping induced BGN is observed.
Consequently, the boundaries used for traditional regional transit time analysis [49]
cannot be defined for THz designs. In [50] the electrical junctions x?EB and x?CB, where
?n and ?p are crossed in junctions, are used as the boundaries to define each transit
time components . The base transit time is
??B =
Zx?
CB
x?EB
?njVCBdx: (2.6)
32
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
?5
0
5
10
15
20
25
30
35
40
Depth (mm)
D
t
n
,
D
t
p
(ps/
m
m)
Dt
p
Dt
n
n
+
n p
n
t
B
t
C
Si Base
V
CB
= 0 V
near f
T,peak
n
+
t
E
Figure 2.9: The ?n and ?p distributions for Si BJT design.
The ??B consists of neutral base transit time ?B and part of neutral EB SCR transit time.
Since ?B is very small for THz SiGe HBT designs, the neutral transit time may take
an appreciable amount in ??B. Therefore, in this work, we use the peak ?n and ?p
positions as the depletion boundary to distinguish emitter, EB SCR, base and collector
region, as shown in Figure 2.10.
xEE, xEB and xCB are defined to distinguish each transit time components, where
1. xEE is the peak ?n position at the high?low emitter interface;
2. xEB is the peak ?p position at the emitter side of the base;
3. xCB is the peak ?p position at the collector side of the base.
33
0.02 0.03 0.04 0.05 0.06 0.07 0.08
?10
0
10
20
30
40
50
60
D
t
n
,
D
t
p
(ps/
m
m)
10
16
10
18
10
20
Depth (mm)
Doping (/cm
3
)
J
C
=20 mA/mm
2
V
CB
=0.5 V
t
C
=
x
CB
x
C Dt
n
dx
=t
CSCL
+C
tc
/g
m
x
CB
x
EE
x
EB
t
B
t
te
t
E
x
EB
*
x
CB
*
Figure 2.10: ?E, ?EB, ?B, and ?C definitions
Consequently, we divide emitter?collector transit time ?EC into emitter transit time ?E,
EB SCR transit time ?te, base transit time ?B and collector transit time ?C.
?E =
ZxEE
0
?njVCEdx; (2.7)
?te =
ZxEB
xEE
?njVCEdx; (2.8)
?B =
ZxCB
xEB
?njVCEdx; (2.9)
?C =
ZxC
xCB
?njVCEdx = ?CSCR +?tc: (2.10)
Figure 2.11 (a) and (b) show the ?n, ?p distribution near peak fT for the box
and graded SiGe HBTs. Compared with Si, ?E is reduced dramatically, due to high ?,
which is responsible for more than 500 GHz fT increase over Si. However, because of
34
the higher barrier for holes in the base of the SiGe HBTs, ?n> ?p in the low doped
emitter, while ?n= ?p for Si.
The JC dependence of each ? component for Si BJT is shown in Figure 2.12 (a), in
comparison with a xpeakmole = 27% graded SiGe HBT. For Si BJT, ?E and ?C dominate. The
advantage of a SiGe base is primarily more than 20? ?E reduction. However, both EB
and CB junction high injection barrier e ects are more severe in the SiGe HBT, which
leads to the ?B increase at high JC. No clear ?B increase is observed for Si design.
Figure 2.12 (b) compares JC dependence of ? components between the graded and box
profiles. ?B is two times larger in the box profile. ?C is dominant in both and hence the
?EC curves follow the ?C curves. When Kirk e ect occurs at high JC, ?C increases more
dramatically than ?B, and is the main reason for fT rollo .
To examine the high injection barrier e ect for box and graded Ge profiles, we
simulate the electron, hole, n and ?n distributions with increasing JC. Figure 2.13
(a) and (b) show the electron and hole distributions, together with doping for box Ge
profile. When JC increases from 14 mA/?m2 to 100 mA/?m2, the electron storage in the
base increase. The hole concentration at the EB junction side of the base is higher than
the background ptype doping, which is due to the Ge induced band barrier. Figure 2.14
(a) shows the n distributions. Most n occurs at the EB side of the ptype base and
the CB junction barrier e ect gets more severe with increasing JC. The ?n curves are
compared in Figure 2.14 (b), which shows clearly that for the box Ge profile, most ?B
increase is due to the EB junction barrier induced electron storage increase.
35
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
0
5
10
20
30
40
Depth (mm)
D
t
n
,
D
t
p
(ps)
Dt
p
Dt
n
Box Ge
V
CB
= 0 V
J
C
= 40 mA/mm
2
near f
T,peak
n
+
n p n n
+
t
E
t
te
t
B
t
C
High Injection
barrier effect
(a)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
0
5
20
40
60
Depth (mm)
D
t
n
,
D
t
p
(ps)
Dt
p
Dt
n
n
+
n p
n n
+
Graded Ge
V
CB
= 0 V
J
C
= 40 mA/mm
2
near f
T,peak
t
E
t
te
t
B
t
C
(b)
Figure 2.11: The ?n and ?p distributions for (a) box Ge design and (b) graded Ge.
36
10
0
10
1
10
2
10
?3
10
?2
10
?1
10
0
J
C
(mA/mm
2
)
t
(ps)
Si
Graded
t
E
t
B
t
C
t
te
t
EC
(a)
10
0
10
1
10
2
10
?2
10
?1
10
0
J
C
(mA/mm
2
)
t
(ps)
graded
box
t
C
t
B
t
te
t
E
t
EC
(b)
Figure 2.12: (a) Comparisons of ? components versus JC characteristics between Si
BJT and graded SiGe HBT designs. (b) Comparisons of ? components versus JC char
acteristics between graded Ge and box Ge designs.
37
0.02 0.03 0.04 0.05 0.06
10
17
10
18
10
19
10
20
Depth (mm)
n (/cm
3
)
10
17
10
18
10
19
10
20
Doping (/cm
3
)
J
C
= 14, 18, 25,
40, 58 and
100 mA/mm
2
(a)
0.02 0.025 0.03 0.035 0.04
10
17
10
18
10
19
10
20
p (/cm
3
)
10
17
10
18
10
19
10
20
Depth (mm)
Doping (/cm
3
)
J
C
= 14, 18, 25,
40, 58 and
100 mA/mm
2
(b)
Figure 2.13: Barrier e ect for Box Ge profile. (a) Electron concentration with increasing
JC and (b) Hole concentration with increasing JC.
38
0.03 0.04 0.05 0.06
?1
0
1
2
3
x 10
17
Depth (mm)
D
n (/cm
3
)
p
+
n
n
+
J
C
= 14, 18, 25, 40,
58 and 100 mA/mm
2
(a)
0.03 0.04 0.05 0.06
0
5
10
15
20
25
30
35
Depth (mm)
D
t
n
(ps/
m
m)
J
C
= 14, 18, 25, 40,
58 and 100 mA/mm
2
(b)
Figure 2.14: Barrier e ect for Box Ge profile. (a) n distribution with increasing JC
and (b) ?n distribution with increasing JC.
39
0.02 0.03 0.04 0.05 0.06
10
17
10
18
10
19
10
20
n (/cm
3
)
10
17
10
18
10
19
10
20
Depth (mm)
Doping (/cm
3
)
J
C
= 14, 18,
25, 40, 58
and 100 mA/mm
2
(a)
0.02 0.025 0.03 0.035 0.04
10
16
10
17
10
18
10
19
10
20
p (/cm
3
)
10
16
10
17
10
18
10
19
10
20
Depth (mm)
Doping (/cm
3
)
J
C
= 14, 18,
25, 40, 58
and 100 mA/mm
2
(b)
Figure 2.15: Barrier e ect for Graded Ge profile. (a) Electron concentration with in
creasing JC and (b) Hole concentration with increasing JC.
40
0.03 0.04 0.05 0.06
?1.5
?1
?0.5
0
0.5
1
1.5
2
x 10
17
Depth (mm)
D
n (/cm
3
)
p
+
n n
+
J
C
= 14, 18, 25, 40
58 and 100 mA/mm
2
(a)
0.03 0.04 0.05 0.06
0
10
20
30
40
50
Depth (mm)
D
t
n
(ps)
p
+
n n
+
J
C
= 14, 18, 25, 40
58 and 100 mA/mm
2
(b)
Figure 2.16: Barrier e ect for Graded Ge profile. (a) n distribution with increasing JC
and (b) ?n distribution with increasing JC.
41
Figure 2.15 (a) and (b) compare the electron and hole concentrations with increas
ing JC for the graded Ge profile. Because the Ge at the EB and CB junction for the
graded profile is much smaller than for the box profile, the barrier for holes is smaller.
Therefore, the hole concentration near junctions are smaller for graded Ge. Figure 2.16
(a) and (b) compare the n and ?n distributions for graded Ge. With increasing JC,
CB junction high injection barrier is much more severe, which leads to an increase of n
and ?n at the CB side of the base. We conclude that while the EB junction high injec
tion barrier e ect is responsible for the ?B increase for the box profile, the CB junction
high injection barrier e ect is responsible for the ?B increase for the graded profile.
2.3.2 Distributive Capacitance
Recall (2.3), an alternative way to analyze di erent delay times is to calculate the
capacitance corresponding to each transit time as C = gm?. This helps to associate
distributive analysis with traditional lumped element equivalent circuit analysis. For 1D
intrinsic design, we have EB depletion capacitance Cte, CB depletion capacitance Ctc,
emitter di usion capacitance CdE, base di usion capacitance CdB, and collector SCR
42
10
0
10
1
10
?2
10
?1
10
0
10
1
J
C
(mA/mm
2
)
C=g
m
t
(fF/
m
m)
V
CB
=0.5 V
C
te
C
tc
C
dC
C
dB
C
dE
Figure 2.17: Cte, Ctc, CdE, CdB and CdC versus JC at VCB = 0.5 V.
di usion capacitance CdC.
Cte = gm ??te; (depletion capacitance) (2.11)
Ctc = gm ??tc; (depletion capacitance) (2.12)
CdE = gm ??E; (di usion capacitance) (2.13)
CdB = gm ??B; (di usion capacitance) (2.14)
CdC = gm ??CSCR; (di usion capacitance) (2.15)
At each JC, the transconductance gm of a SiGe HBT is extracted using the real
part of y21 at low frequency f [51]. Figure 2.17 compares capacitance versus JC curves
for each C defined above for the THz design. The junction depletion capacitance is
43
equivalent to a parallelplate capacitor of separation wd,
Ct = flsiw
d
; (2.16)
where wd is the depletion width. Ct is independent of JC. Ctc is the CB junction depletion
capacitance. Notice that the Cte extracted in this work actually includes the EB junction
neutral transit time ?n [9]. However, since the junction depletion capacitance dominates,
as shown, we did not extract ?n. The di usion capacitance is defined as
Cd = dQexcessdV
BE
= dI?dV
BE
(2.17)
= IV
th
?
For emitter, the ?I? is the base current, which can be expressed as ?IC=??. For base and
collector SCR, ?I? is the collector current. ? is the ?E, ?B and ?CSCR respectively. Since
as shown in Figure 2.12, ?E, ?B and ?CSCR are constant from low to medium injection,
the di usion capacitance CdE, CdB and CdC should be a linear function of JC, which is
correctly shown in Figure 2.17.
2.4 Design Issues
Next, we examine how Ge profile impacts device performance. Since the collector
design primarily determines the ?C, the collector width and the collectorsubcollector
44
transition impact on transistor performance are also examined. Finally, the base op
timization issue is addressed for the purpose of reducing base sheet resistance RB;?,
which impacts both RF noise performance and fmax.
2.4.1 Impact of Ge
Discussions on the choice between the box and graded profiles have been addressed
in many works, often using first order theories assuming uniform doping and drift
di usion transport [52] [54]. We revisit this issue here for nanoscale designs. To make
a meaningful comparison, we compare the box and graded profiles at the same total Ge,
so that the SiGe film stability is kept the same. We use the unit of ?10nm?10%Ge? to
specify the amount of total Ge.
At the SiGe film thickness of 7 nm, the maximum Ge that can be used to maintain
the strainedlayer is 2.5 ?10nm?10%Ge? [48]. In this work, we examined the device
performance up to the total Ge of 1.5 ?10nm?10%Ge?, where the film is under ther
modynamic stability. Figure 2.18 compares fT and ? between the graded and box Ge
profiles. For our doping profile design, the graded Ge profile shows a higher ? than the
box profile, which is the opposite of the prediction by first order analytical theories. An
inspection of simulation details and additional simulations with di erent options show
that this is related to the nonuniform base doping as well as the very thin base thickness.
Figure 2.19 shows fT;peak versus ? for the graded and box Ge profile. For the same ?,
the graded profile gives higher fT;peak. Besides, as indicated in Figure 2.18, for the same
performance, the graded profile uses less Ge and thus is more stable. For the same peak
45
0 0.5 1 1.5
600
800
1000
1200
1400
1600
f
T,peak
(GHz)
0
200
400
600
800
1000
Total Ge (10nm 10%Ge)
bf
T,peak
b
Solid Line ?? Graded Ge
Dash Line ?? Box Ge
V
CB
= 0 V
Figure 2.18: Comparisons of the fT;peak and ? versus total Ge for box and graded Ge
profiles
10
1
10
2
400
600
800
1000
1200
1400
1600
b
f
T,peak
(GHz)
Graded Ge
Box Ge
V
CB
= 0 V
Figure 2.19: fT;peak versus ? for box and graded Ge profiles
46
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
1400
1500
1600
1700
1800
1900
2000
2100
Total Ge (10nm 10%Ge)
f
T
?
BV
CEO
(GHz
V)
Graded Ge
Box Ge
Figure 2.20: Comparison of fT ? BVCEO versus total Ge between box and graded Ge
profiles.
fT, the graded profile has lower ?, indicating a higher BVCEO. Therefore, the graded Ge
profile is preferred for higher device performance, as well as better stability. Figure 2.20
shows the fT ?BVCEO product as a function of total Ge. The graded profile has a higher
fT ?BVCEO than the box profile, particularly at higher total Ge (and hence higher fT ).
A 2000 GHz?V fT ? BVCEO is achieved using the graded profile. The results are the
opposite of the prediction by first order analytical theories. The reason is related to the
nonuniform base doping as well as the very thin base thickness.
The Ge content dependence of ? components and peak fT are shown in Figure 2.21
(a) for the box profile, and in Figure 2.21 (b) for the graded profile. ?C is the same for
both box and graded Ge profile, regardless of Ge content. ?E is reduced dramatically
with increasing Ge, which corresponds to a rapid fT;peak improvement. However ?E be
comes the smallest component when total Ge is above 10nm?10%Ge. Further increasing
47
0 0.5 1 1.5
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
Total Ge (10nm 10%Ge)
t
(ps)
400
600
800
1000
1200
1400
f
T,peak
(GHz)
Box Ge
t
E
t
C
f
T,peak
t
B
t
te
(a)
0 0.5 1 1.5
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
Total Ge (10nm 10%Ge)
t
(ps)
600
800
1000
1200
1400
1600
f
T,peak
(GHz)
Graded Ge
f
T,peak
t
E
t
C
t
B
t
te
(b)
Figure 2.21: ?E, ?te, ?B, ?C and fT versus total Ge for (a) box Ge and (b) graded Ge.
48
Ge has no dramatic impact on reducing ?EC. A major di erence between the box and
graded profiles is the base transit time ?B. When total Ge is increased from 0 to 1.5
?10nm?10%Ge, ?B is increased by 0.007 ps in box profile design due to increasing EB
barrier height, and ?B is reduced by 0.015 ps in graded profile design due to increasing
base accelerating field.
2.4.2 Impact of Collector Design
To examine the wC impact, we fix emitter, base and, particularly, CB junction pro
files, and reduce wC from 200 to 150, 100, 50, and 30 nm, while the same n=n+ transition
is kept. Using the 1D transit time analysis, the ?n and ?p are extracted again to dis
tinguish ?CSCR and ?Ctc. But v is at the emitter electrode, while VCB is fixed. Because
now the electron change in collector SCR is only due to injection, CB junction depletion
capacitance Ctc charging time is not included in the collector ?n integration. Therefore
?CSCR = ?CjVCB (2.18)
?tc = ?CjVCE ?CjVCB: (2.19)
Applying the 1D transit time analysis mentioned above, ?CSCR and ?tc are calcu
lated for each wC at the same JC of 20 mA/?m2. Besides, ?E, ?B and ?te are also ex
tracted. Figure 2.22 compares the results. ?EC is dominated by ?CSCR, which decreases
with decreasing wC. Figure 2.23 compares fT JC curves. Mainly because of ?CSCR
reduction, a higher fT is achieved at the same JC for the design with smaller wC.
49
50 100 150 200
0
0.05
0.1
0.15
0.2
0.25
W
C
(mm)
t
(ps)
t
CSCR
t
tc
t
E
t
B
t
te
t
CSCR
V
CB
= 0.5 V
J
C
=20 mA/mm
2
Figure 2.22: wC impact on transit times components.
10
0
10
1
10
2
0
200
400
600
800
1000
1200
J
C
(mA/mm
2
)
f
T
(GHz)
w
C
=30nm, 50nm,100nm,
150nm and 200nm
V
CB
=0.5 V
Same Base and
CB junction profiles
Figure 2.23: fTJC curves for wC = 200 nm, 150 nm, 100 nm, 50 nm, and 30 nm. VCB
= 0.5 V.
50
Interestingly, the onset of Kirk e ect is delayed with decreasing wC, as indicated
by a higher JC;peak for smaller wC. This is a result of higher electric field in the CB SCR
for smaller wC, which leads to a higher electron velocity. Figure 2.24 (a) compares the
electron velocity vn profiles in the collector for wC = 200 and 30 nm designs. JC =
40 mA/?m2, VCB = 0.5 V. Because of the nonequilibrium transport, velocity overshoot
occurs. The smaller the wC, the higher the vn. Consequently, electron concentration n
is higher for larger wC. p is also higher for larger wC, and hence base pushout (Kirk
e ect) is easier to happen. A wC smaller than 30 nm is required to delay the onset of
Kirk e ect, and hence to achieve THz intrinsic design.
For the design with narrow collector width, the n=n+ transition gradient directly
impacts the e ective lowdoped collector thickness, and thus should have an impact
on fT and BVCEO. Figure 2.25 compares the electric field distribution in the collector
for five n=n+ transitions with increasing gradient, for a xpeakmole=27% graded Ge profile.
Since a rapid charge distribution change is associated with an abrupt transition, a higher
electric field is presented at the n=n+ junction. BVCEO is thus degraded from 1.55 V for
coll1 to 1.36 V for coll5. Figure 2.26 compares ?CJC for each design. Increasing n=n+
gradient e ectively increases wC, and hence decreases fT. Meanwhile, a more rapid fT
rollo is observed for an abrupt n=n+ transition. Therefore, a gradual n=n+ transition
is desired for high fT, high BVCEO and weaker fT rollo .
51
0.03 0.035 0.04 0.045 0.05
0.5
1
1.5
2
2.5
3
x 10
7
Depth (mm)
v
n
(cm/s)
V
sat
w
C
= 200 nm
w
C
= 30 nm
(a)
0.03 0.035 0.04 0.045 0.05
10
17
10
18
10
19
10
20
Depth (mm)
n, p and Doping (/cm
3
)
w
C
= 200 nm
w
C
= 30 nm
Base push out
for w
C
= 200nm
n
p
(b)
Figure 2.24: Comparisons of (a) electron velocity profile, and (b) n/p distributions inside
CB SCR between wC = 200 nm and 30 nm designs. JC = 40 mA/?m2, VCB = 0.5 V. A
base pushout is observed for wC = 200 nm.
52
0.04 0.045 0.05 0.055 0.06 0.065 0.07
10
18
10
19
10
20
10
21
Doping (/cm
3
)
?500
?400
?300
?200
?100
0
Depth (mm)
E
field
(kV/cm)
J
C
= 15 mA/mm
2
V
CB
= 0 V
E
Coll1
E
Coll2
E
Coll3
E
Coll4
E
Coll5
coll1 coll2 coll3 coll4 coll5
Figure 2.25: Electric field distribution for five subcollector designs.
10
1
10
?1
J
C
(mA/mm
2
)
t
C
(ps)
coll1
coll2
coll3
coll4
coll5
V
CB
= 0 V
Figure 2.26: ?C  JC for five subcollector designs.
53
2.4.3 Base Profile Optimization
Compared with 200 GHz SiGe HBT designs, we notice that the base sheet resis
tance RB? for THz design is much higher, primarily because of the narrow base width.
RB?j200G ?2.5 k =?, and RB?jTHz ?8 k =?.
The base sheet resistance for an npn transistor is extracted as
RB? = 1qRwB
0 NB(x)?p(x)dx
; (2.20)
where wB is the base width and ?p is the hole mobility. Since RB? is inversely pro
portional to base doping NB and base width wB, we can increase either NB or wB to
optimize RB?. Because it is more challenging to form a very thin layer of heavily doped
base, in this work, we increase wB instead, which compromises ?B and hence fT. Fig
ure 2.27 compares the optimized base profile with original design. The peak base doping
is the same, and the base width is increased. RB? is reduced to 3.5 k =?, which is close
to the value for 200 GHz designs. However, peak fT is reduced also to 1.1 THz.
The reason to have a low RB? is to reduce intrinsic base resistance and hence the
total base resistance. For a double base contact structure, the intrinsic base resistance is
RB;in = 112
?w
E
lE
?
RB?: (2.21)
The lateral scaling of wE can also reduce RB;in. With reducing RB;in, the extrinsic base
resistance RB;ex can become appreciable, which is related to the base current flowing
through the extrinsic base region. In order to reduce RB;ex, device structure innovation
54
0.02 0.025 0.03 0.035 0.04
10
16
10
17
10
18
10
19
10
20
10
21
Depth (mm)
Doping (/cm
3
)
N
B2
: R
s
= 3.5 KW/s
N
B1
: R
s
= 8 KW/s
Figure 2.27: Optimized base profile for lower RB?
such as the raised extrinsic base and the lateral scaling of the extrinsic base are imple
mented.
2.5 Summary
In this chapter, the intrinsic profile design for THz SiGe has been discussed. The
highlow emitter structure is shown to provide the advantage of reducing tunneling and
G/R current, as well as reducing the VBE modulations on base width. As a result, more
linear JB and JC can be obtained, which gives better ?. When emitter and base tran
sit time is reduced dramatically with scaling, the collector SCR transit time becomes
the limit to speed. In order to achieve THz fT intrinsic design, collector width has to
be reduced below 30 nm. The subcollector transition also impacts ?C and BVCEO. A
55
gradual nn+ transition is favored, which results in smaller ?C and higher BVCEO. Com
prehensive comparisons between graded and box Ge profile designs are examined. We
conclude that the graded Ge profile wins in all aspects of the device performance ma
trix for THz designs. Next, we will extend the design to 2D to examine the impact of
parasitic e ects on device performance.
56
CHAPTER 3
2D DEVICE DESIGNS
The 2D device structure must be optimized and improved with intrinsic vertical
scaling. For the THz intrinsic design, the total transit time ?EC is on the order of 0.1
ps. The delay from extrinsic parasitic e ects can be appreciable, and hence degrades
device performance significantly. Many research groups have been devoted to device
optimization and have proposed innovative 2D device structures [55, 57]. In this work,
the design with optimized base profile is used, which has lower base sheet resistance
RB?, and hence lower RB;in.
Then the 2D structure parasitic e ects are studied using MEDICI. The 1D transit
time analysis is extended to 2D. The distributive capacitance is revisited for the 2D
structure. The intrinsic and extrinsic base resistance, RB;in and RB;ex, and CB junction
capacitance Ctc are extracted. The raised extrinsic base structure has been chosen, which
can reduce RB;ex. RB;in and Ctc can be reduced through lateral scaling. Two lateral
scaling schemes are examined. When wE is scaled to 60 nm, fmax can be improved to
1090 GHz.
3.1 2D Device Simulations
Figure 3.1 shows the MEDICI 2D input device structure [59]. As discussed, with
device optimization, the intrinsic base resistance RB;in is reduced, so that the extrinsic
base resistance RB;ex can be appreciable and dominate the total base resistance. As
57
DTDT
w

DI DI
Emitter
STI
Base Poly Base Poly
STI
Fringing
Capacitance
E
w
STST
w

SIC
w
BE
t
sp
t
STI
w
STI
d
Figure 3.1: Schematic of device cross section using a raised base structure. wE=120
nm, tEB=140 nm, tsp=40 nm, wSTI=0.4 ?m, dSTI=0.25 ?m, wST ST=0.38 ?m, and
wDT DT=1.7 ?m.
shown in [58], the extrinsic basepoly resistance RB;poly, which is underneath the base
contact and emitter spacer, can be reduced by reducing the spacing distance tBE. As a
result, RB can be reduced and hence fmax can be improved. In this work, a tEB of 140
nm is used. The STI design impacts the extrinsic CB capacitance. A smaller STI area is
desired to reduce the capacitance. The STI thickness is 0.25 ?m and the STI width is 0.4
?m. A smaller spacing between two STIs can help reduce the extrinsic device induced
parasitic delays. However, the associated stress hurts the mobility and hence degrades
the high speed. Currently, the spacing between the STI edges is 0.38 ?m. The emitter
window wE is 0.12 ?m. The yparameters are simulated as a function of frequency, from
which h21 and Mason?s unilateral gain U are calculated. fT and fmax are then obtained
from the extrapolation of h21 and U.
In some reports, driftdi usion (DD) simulations were found to be accurate for
SiGe HBTs with peak fT above 200 GHz [60]. Our experience, however, shows that
58
0 10 20 30 40 50 60 70
0
200
400
600
800
1000
1200
J
C
(mA/mm
2
)
f
T
and f
max
(GHz)
f
max,EB
f
T,EB
f
max,DD
f
T,DD
f
T,EB
V
CB
=0.5 V
300 GHz
D(f
T,1D
?f
T,2D
)
Figure 3.2: Comparisons of fT/fmax  JC curves obtained between 2D DD and EB
simulations. Also shown is the 1D EB fT result.
nonequilibrium transport is significant. Figure 3.2 compares the 2D fT/fmax JC curves
from energy balance (EB) and driftdi usion (DD) simulations. Peak fT is 800 GHz
and peak fmax is 745 GHz for EB simulations. The 1D fT from EB simulation is also
shown. A 200 GHz peak fT reduction is observed due to extrinsic parasitic e ects.
Observe that the fT and fmax roll o at lower JC in DD simulation, because for DD
simulations, nDD > NC in CB SCR as shown in Figure 3.3 (a), and base push out occurs.
The SCR boundary of DD simulation, xm;DD, moves towards n+ buried layer and n+ is
depleted. xm;EB < xm;DD. Figure 3.3 (b) compares the electron velocity between DD
and EB simulations. Nonequilibrium transport leads to velocity overshoot, therefore
Vn;EB is greater than Vn;sat in SCR for EB simulations. While for DD simulations, Vn;DD
is lower than Vn;sat near CB junction because of the greater nDD accumulated in the push
59
0.03 0.04 0.05 0.06 0.07 0.08
10
17
10
18
10
19
10
20
Depth (mm)
Doping & n (/cm
3
)
Base
Collector
n
DD
>N
C
push out
n
EB
J
C
= 30 mA/mm
2
f
T,DD
= 200 GHz
f
T,EB
= 750 GHz
n
+
depleted
for DD
x
0
x
m,EB
x
m,DD
(a)
0.03 0.04 0.05 0.06 0.07 0.08
0
0.5
1
1.5
2
2.5
x 10
7
Electron Velocity (cm/s)
10
16
10
18
10
20
Depth (mm)
Doping (/cm
3
)
Base
Collector
V
n,EB
V
n,DD
push out
x
0
x
m,EB
x
m,DD
(b)
0.02 0.04 0.06 0.08 0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
t
(ps)
10
16
10
18
10
20
Depth (mm)
Doping (/cm
3
)
t
ec,EB
E B
C
J
C
=30 mA/mm
2
V
CB
=0.5 V
t
ec,DD
Push out
(c)
Figure 3.3: Comparisons of simulation details between DD and EB on (a) electron
distribution, (b) electron velocity, and (c) ? distribution. JC = 30 mA/?m2, VCB = 0.5
V. 60
out region. Generally, collector SCR transit time ?CSCR is related to Vn as [27]
?CSCR =
Zxm
x0
1
Vn(x)
?
1 xx
m x0
?
dx; (3.1)
where x0 and xm indicate the collector SCR boundaries. At equilibrium, Vn(x) = Vn;sat
and ?CSCR = (xm x0)=2Vn;sat. (3.1) indicates that the velocity close to x0 has more
weight. As Vn;EB ? Vn;DD at the start, ?CSCR is lower for EB simulations. Figure 3.3 (c)
compares ?EC profiles between DD and EB. For DD simulations, a dramatic increase of
? is observed at the push out region, and a large ? decrease at the n+ is observed. The
reason is that xm;DD is pushed to the buried layer, the n=n+ transition layer is depleted,
and a negative ?n appears at the end of CB SCR [48]. This nonequilibrium transport
delays the onset of Kirk e ect, and is significant for THz HBTs, as the collector doping
does not need to dramatically increase.
Considering impact ionization at the CB junction, the nonlocal e ect due to the
nonequilibrium transport equivalently delays the maximum impact ionization rate [61?
63]. Therefore, a practical device breakdown performance can be maintained in scaled
devices with over 200 GHz peak fT [64]. This is particularly important for applications
where transient current density can significantly go beyond the peak fT current density,
such as in large signal power amplifiers [65].
To include the nonlocal e ect, an e ective electric field Ee , instead of local elec
tric field, is used in the avalanche analysis. The energy of electrons is derived from
61
approximations to the EB equations as [61]
wn = 35q
Zx
0
E(u) exp
?u x
n
?
du; (3.2)
where wn is the average electron energy, E(u) is the local electric field, and n is the
energy relaxation length for electrons. Ee is then calculated as
Ee = 53 wnq
n
: (3.3)
The M1 curves extracted using Ee between THz and a 200 GHz design are compared
in Figure 3.4. M 1 at higher VCB is about the same between THz and 200 GHz HBTs.
Consequently, the CB breakdown voltage of THz HBTs is expected to be similar as the
200 GHz HBTs.
3.2 2D Parasitic Analysis
To better understand how parasitic e ects limit fT/fmax, we extract the base resis
tance, and CB capacitance from MEDICI simulation results. Also, we extend the 1D
transit time analysis into 2D. Similarly, the 2D distributive capacitance is extracted.
3.2.1 RB and CCB
Given the increasing di culty of base resistance extraction using impedance circle
methods in scaled HBTs, we extract the extrinsic and intrinsic base resistance, RB;ex and
62
0.5 1 1.5 2
10
?5
10
?4
10
?3
10
?2
10
?1
V
CB
(V)
M?1
THz SiGe Simu. (2D)
200 GHz SiGe Simu. (2D)
200 GHz SiGe Meas.
V
BE
=0.65 V
A
E
= 0.12?1.0 mm
2
Figure 3.4: Simulated M 1 versus VCB curves for 200 GHz and THz SiGe HBTs. Also
shown is the measured data for 200 GHz design.
RB;in, as follows
RB;ex = fp=IB; (3.4)
RB;in = 112 ? R?l
E=wE
(3.5)
where fp is the quasihole Fermi potential drop across the extrinsic base, IB is the
base current, R? is the intrinsic base sheet resistance, and lE=1 ?m. The extracted RB;in
is 33.6 ?m, and RB;ex is 70 ?m. The total rb is comparable to the 200 GHz HBT
reported in [55], which has a rb of 110 ?m. An ideal ohmic base contact is assumed
in this work, and the silicide resistance is not included in RB. Therefore, our analysis
represents the best case after we make the perfect contact.
63
In order to extract CCB, ?!Im(Z22Z21)? is plotted versus ?!2?, the yintercept
equals ? 1/CCB? [66]. Using this method, a CCB of 1.14 fF/?m is extracted, slightly
smaller than the 1.7 fF/?m reported in [55], likely due to the smaller spacing between
the STI and the smaller area of the selectively implanted collector (SIC).
3.2.2 2D Transit Time Analysis
Extending the 1D regional transit time analysis into 2D, the total ?EC can be ex
pressed as
?EC = @Q@I
C
= q I
C
Zx2
x1
Zy2
y1
ndxdy; (3.6)
where the n and IC are for a small VBE increase at a given VCE. x1, x2, y1 and y2
are the boundaries for the 2D regions. Vertically, we use Y?EE, Y?EB and Y?CB as bound
aries, which correspond to xEE, xEB and xCB in Figure 2.10, respectively. Laterally,
the emitter window boundaries XE;st and XE;en are used to separate the intrinsic and the
extrinsic device. Then ?EC is divided into seven components as shown in Figure 3.5,
1. ?Ef: the fringing capacitance charging time induced by EB spacers;
2. ?E: the emitter transit time ;
3. ?te: the EB junction capacitance charging time;
4. ?B;in: the intrinsic base transit time;
5. ?B;ex: the extrinsic base transit time;
64
6. ?C;in: the intrinsic collector transit time;
7. ?C;ex: the extrinsic collector transit time.
?Ef is extracted as the integration along the emitter perimeter. ?E equals the integration
above Y?EE for the rest of emitter region. ?te, ?B;in and ?C;in are calculated using
?te = q I
C
ZXE;en
XE;st
ZY?
EB
Y?EE
ndydx; (3.7)
?B;in = q I
C
ZXE;en
XE;st
ZY?
CB
Y?EB
ndydx; (3.8)
?C;in = q I
C
ZXE;en
XE;st
ZY?
C
Y?CB
ndydx: (3.9)
Since SIC width is assumed to be the same as wE in our case, XE;st, XE;en, Y?CB and YC?
define the SIC region. Y?C is the n=n+ interface. ?B;ex is the integral for the extrinsic base,
which is induced by the lateral electron injection through the emitter sidewall. ?C;ex is
the integral for the extrinsic collector, which is outside of the SIC region. Applying (9)
and (10) for 2D ? analysis, we can further distinguish SCR transit time and depletion
capacitance charging time for both ?C;in and ?C;ex, which are denoted as ?CSCR;in, ?tc;in,
?CSCR;ex and ?tc;ex, respectively. An example of n distribution near peak fT is shown
in Figure 3.6, where most of the n occurs in the intrinsic base and collector regions.
Since MEDICI only outputs the n associated with each mesh node in the ?ti ?
format [37], we have to postprocess the raw data in order to extract n and device
geometry informations. Then, based on the 2D regional boundaries defined above, we
run our own Matlab 2D integration script to calculate each 2D ?. Figure 3.7 shows
65
X45 X64X45
X28X43 X29X74
X74X65 X74X65
X28X43 X29X74
X58
X59
X42X2CX69X6E X64X42X2CX69X6E
X28X43 X29X74X42X2CX65X78 X64X42X2CX65X78
X28X43 X29X74
X42X2CX65X78 X64X42X2CX65X78
X28X43 X29X74
X43X53X43X52X2CX69X6E X74X63X2CX69X6E
X64X43X2CX69X6E X74X63X2CX69X6E
X28X43 X2B X43 X29
X74 X74X2B
X43X53X43X52X2CX65X78 X74X63X2CX65X78
X64X43X2CX65X78 X74X63X2CX65X78
X2B
X28X43 X2BX43 X29
X74 X74
X45X66 X45X66
X28X43 X29X74
X2A
X45X45
X59
X2A
X45X42
X59
X2A
X43X42
X59
X45X2CX73X74
X58
X45 X2CX65X6E
X58
X53X54X49 X53X54X49
X42X61X73X65X20X50X6FX6CX79 X42X61X73X65X20X50X6FX6CX79
Figure 3.5: Definition of 2D ? components and related capacitance. Y?EE, Y?EB and Y?CB
correspond to XEE, XEB and XCB in Figure 3.
Figure 3.6: Simulated 2D n distribution near peak fT, VCB=0.5 V
66
10
0
10
1
10
2
10
?3
10
?2
10
?1
J
C
(mA/mm
2
)
t
(ps)
t
te
t
CSCR,in
t
CSCR,ex
t
tc,ex
t
B,in
t
B,ex
t
E
t
Ef
t
tc,in
V
CB
=0.5 V
Figure 3.7: ?E, ?Ef, ?EB, ?B;in, ?B;ex, ?CSCR;in, ?CSCR;ex, ?tc;in and ?tc;ex versus JC at
VCB=0.5 V.
the 2D ? components defined above versus JC at VCB=0.5 V. ?CSCR;in and ?CSCR;ex are
not sensitive to biasing. Both ?te and ?CSCR;in are appreciable from low to high JC. ?te
limits ?EC at lower JC, while ?CSCR;in does at higher JC. ?E, ?B;in and ?B;ex increase
at high JC when high injection occurs. ?Ef, ?te, ?tc;in, and ?tc;ex show the depletion
capacitance charging behavior. ?tc;ex is larger than ?tc;in The contribution from each
region is compared in Figure 3.8 in percentage. The fT JC characteristic is primarily
determined by ?te, ?CSCR;in and ?CSCR;ex. Extrinsic collector design dominates the total
extrinsic delay, and leads to 200 GHz peak fT reduction compared with 1D simulation.
67
10
0
10
1
10
0
10
1
J
C
(mA/mm
2
)
t
/
t
EC
(%)
t
CSCR,in
t
te
t
CSCR,ex
t
B,ex
t
E
t
Ef
t
B,in
t
tc,ex
t
tc,in
Figure 3.8: Comparison of ? contribution from each region. VCB=0.5 V.
3.2.3 2D Distributive Capacitance
Similar to 1D distributive capacitance, 2D distributive capacitance can be extracted.
Table 3.1 lists the definition of each capacitance component. Figure 3.9 shows capaci
tance versus JC curves. In our analysis, Cte includes EB junction depletion capacitance
and neutral capacitance as well. However, the neutral capacitance is very small and
the depletion capacitance dominates. As shown, Cte, CEf, Ctc;in and Ctc;ex are appre
ciable for those highly scaled SiGe HBT designs. Ctc, the sum of Ctc;in and Ctc;ex, is
1.10 fF/?m, which agrees with 1.14 fF/?m extracted using [Z] parameters. Cte>Ctc, and
Ctc;ex>Ctc;in. The di usion capacitance, which is associated with excess carrier injec
tion, increases with JC exponentially. CC;in and CC;ex are dominant. Overall, collector
design is shown to be more important for high speed SiGe HBT designs.
68
Table 3.1: 2D Distributive Capacitance
CdE gm?E Emitter di usion capacitance
CdB gm?B Base di usion capacitance
CdC;in gm?CSCR;in Intrinsic Collector SCR Capacitance
CdC;ex gm?CSCR;ex Extrinsic Collector SCR Capacitance
Cte gm?te EB junction capacitance
Cef gm?Ef EB fringing capacitance
Ctc;in gm?tc;in Intrinsic CB capacitance
Ctc;ex gm?tc;ex Extrinsic CB capacitance
10
0
10
1
10
?1
10
0
10
1
J
C
(mA/mm
2
)
C
dep
(fF/
m
m)
10
0
10
1
10
?2
10
?1
10
0
10
1
J
C
(mA/mm
2
)
C
diff.
(fF/
m
m)
V
CB
=0.5 V
C
te
C
tc,ex
C
tc,in
C
Ef
C
dC,in
C
dC,ex
C
dB,in
C
dB,ex
C
dE
Figure 3.9: Capacitance versus JC curves. VCB=0.5 V.
69
Table 3.2: Device performance for fixed wBase lateral scaling.
wE(nm) 120 100 80 60
RB;in( ?m) 33.6 28 22.4 16.8
RB;ex( ?m) 70 65.6 64 62
CCB (fF/?m) 1.14 1.12 1.09 1.06
fT (GHz) 787 771 750 718
fmax (GHz) 745 871 966 1090
3.3 Lateral Scaling
Lateral scaling is necessary to reduce RB;in and to reduce current crowding. To
examine the impact of lateral scaling, we shrink the emitter window wE from 120 nm to
100 nm, 80 nm and 60 nm, respectively, as illustrated in Figure 3.10. We also assume
that the SIC width is the same as wE. The spacer thickness tsp, and the spacing between
base contact and emitter tEB are both fixed during scaling. The active collector area is
defined by the STI spacing wST ST. We will first consider scaling wE for fixed total
base width, wBase. Besides, wSTI, dSTI, wST ST and wDT DT are all kept the same.
The wST ST of 0.38 ?m is already small. Further shrinking will lead to the device
performance degradation due to stress.
For the fixed wBase scaling, extrinsic base width wB;ex increases with scaling. There
fore, at the same VBE, base current IB is more for the scaled devices, and thus the RB;ex
is smaller as shown in Table 3.2. CCB is extracted from [Z] parameters, and the values
decrease because of the smaller SIC area. Overall, through lateral scaling, a 355 GHz
fmax improvement is obtained. However, fT decreases from 787 GHz to 718 GHz.
70
STI
Base Poly
STI
Base Poly
E
w
BE
t
sp
t
Base
w
,B ex
w
SIC
w
STST
w
Base PolyBase Poly
E
w
BE
t
sp
t
Base
w
SIC
w
STST
w
Base PolyBase Poly
E
w
BE
t
sp
t
SIC
w
STST
w
,B ex
w
(a) fixed
Base
w
,
(b) fixed
B ex
w
STI STI
STI STI
Figure 3.10: Illustration of lateral scaling. (a) wBase is fixed. (b) wB;ex is fixed.
71
Table 3.3: Device performance for fixed wB;ex lateral scaling.
wE (nm) 120 100 80 60
RB;in( ?m) 33.6 28 22.4 16.8
RB;ex( ?m) 70 70 70 70
CCB (fF/?m) 1.14 1.10 1.08 1.05
fT (GHz) 787 785 770 760
fmax(GHz) 745 871 968 1090
Next, we keep wB;ex the same during scaling, as shown in Figure 3.10 (b). The
advantage is a smaller overlap between base and collector through STI, and less peak
fT reduction. The disadvantage is that RB;ex will remain the same (as opposed to de
creasing) with scaling. Table 3.3 compares the device performance for di erent wE.
72
3.3.1 2D versus 1D Intrinsic
To compare the impacts of 1D intrinsic design and 2D design on transit time
through lateral scaling, we define the 1D intrinsic transit time and extrinsic delays as
?E;in = ?E +?te; (Intrinsic emitter transit time) (3.10)
?E;ex = ?Ef; (Extrinsic emitter transit time) (3.11)
?B;in = ?B;in; (Intrinsic base transit time) (3.12)
?B;ex = ?B;ex; (Extrinsic base transit time) (3.13)
?C;in = ?CSCR;in +?tc;in; (Intrinsic collector transit time) (3.14)
?C;ex = ?CSCR;ex +?tc;ex; (Extrinsic collector transit time) (3.15)
Figure 3.11 compares each intrinsic and extrinsic ? for the two scaling methods at wE
= 120, 100, 80, and 60 nm, respectively. Both ?C;ex and ?B;ex increase with reducing wE
for fixed wBase scaling. However, for fixed wB;ex scaling, ?B;ex is the same. Therefore,
the increase of ?EC with lateral scaling is less for fixed wB;ex scaling compared with
fixed wBase scaling. As a result, fT at wE = 60 nm for fixed wB;ex scaling is higher than
fixed wBase scaling. The intrinsic and extrinsic collector depletion capacitance and SCR
capacitance are also extracted using 2D transit time analysis. The results are compared
in Figure 3.12 (a) and (b), respectively. Since wST ST is kept the same for both scalings,
similar collector capacitances are observed. Because of the smaller SIC area, both Ctc;in
and CCSCR;in decrease with reducing wE, However, Ctc;ex increases, which makes the
total collector depletion capacitance CCB not scale with lateral scaling. CCSCR;ex is
73
0
0.05
0.1
0.15
0.2
0.25
w
E
(nm)
t
(ps)
120
100
80 60
t
C,in
t
C,ex
t
B,in
t
B,ex
t
E,in
t
E,ex
left ? fixed w
Base
; right ? fixed w
B,ex
Figure 3.11: Comparisons of intrinsic and extrinsic ?E, ?B and ?C at peak fT between
two lateral scaling.
not sensitive to lateral scaling. In the extrinsic collector, most n happens along SIC
boundaries, which is not impacted by lateral scaling. Overall, the low RB;ex with fixed
wBase scaling is traded o by its higher ?B;ex, and the two scaling schemes lead to the
same fmax of 1090 GHz at wE = 60 nm. A fixed wB;ex scaling has led to a better overall
performance, because of higher fT.
For both scaling schemes, the extrinsic transit time becomes an increasingly larger
portion of the total transit time as wE decreases from 120 to 60 nm, as shown in Fig
ure 3.13. If we do a linear extrapolation, ?in and ?ex curves will meet near wE = 50 nm.
After this point, extrinsic design dominates the total ?EC.
74
0.1
0.2
0.3
0.4
0.5
0.6
0.7
w
E
(nm)
C
c,t
(fF/
m
m)
120 100 80 60
Extrinsic
Intrinsic
Diamond ? fixed w
Base
Square ? fixed w
B,ex
(a)
1
2
3
4
5
6
7
w
E
(nm)
C
cscr
(fF/
m
m)
120 100 80
60
Diamond ? fixed w
Base
Square ? fixed w
B,ex
Extrinsic
Intrinsic
(b)
Figure 3.12: Comparisons of (a) Ctc;in and Ctc;ex, and (b) CCSCR;in and CCSCR;ex for fixed
wBase and fixed wB;ex scalings.
75
0
20
40
60
80
100
w
E
(nm)
t
/
t
EC
(%)
120 100 80 60
t
in
t
ex
Diamond ? fixed w
Base
Square ? fixed w
B,ex
at peak f
T
Figure 3.13: Comparisons of intrinsic and extrinsic ? contributions at peak fT.
3.3.2 2D versus 2D Intrinsic
Another way of examining the parasitic e ects impact is to define the internal 2D
intrinsic device as shown in Figure 3.14, where the width is 20 nm wider than wE in
order to include the spreading e ects. The two lateral scaling schemes are revisited
for the 2D intrinsic device. The peak values of fT and fmax for 2D intrinsic device are
extracted and compared with the data for a full 2D device. The results are shown in
Figure 3.15.
Recall Figure 2.3, the 1D intrinsic fT is 1100 GHz. Due to the spreading e ects,
the 2D intrinsic peak fT is reduced to 980 GHz. The parasitic RC delays lead to more
than 100 GHz peak fT reduction. The solid arrows show the fT reduction for the fixed
wBase lateral scaling and the dash arrows show the fT reduction for the fixed wB;ex lateral
scaling. As shown, the first case leads to more severe fT reduction, which is due to
76
Figure 3.14: Illustration of the internal 2D intrinsic device.
700
750
800
850
900
950
1000
f
T
(GHz)
700
900
1100
1300
f
max
(GHz)
120 100 80 60
w
E
60 80 100 120
w
E
fixed w
Base
fixed w
B,ex
Figure 3.15: Comparisons of 2D intrinsic and extrinsic fT=fmax between two scalings.
77
the higher ?B;ex as discussed above. However, the similar fmax decrease is observed
between two scaling methods. When wE is reduced to 60 nm, while the 2D intrinsic
fmax increases from 880 GHz to 1220 GHz, the full 2D fmax increases from 745 GHz to
1090 GHz.
3.4 Summary
We have examined the impact of extrinsic parasitic e ects on the fT and fmax of
highly scaled SiGe HBTs to explore the structural requirements necessary to further im
prove fmax towards terahertz. A 2D regional transit time analysis shows that the extrinsic
collector parasitics are the most dominant extrinsic transit time contributor, which ac
counts for 20% of ?EC at peak fT. The fixed wBase and the fixed wB;ex lateral scaling
schemes are examined to quantify the extrinsic parasitics geometry reduction needed
to achieve fmax improvement. The nonequilibrium transport is shown to significantly
reduce the electron concentration in the CB SCR, which alleviates Kirk e ect and helps
improving breakdown voltage.
78
CHAPTER 4
CONCLUSION
We have explored in this work the optimization of SiGe HBT towards THzfT=fmax.
The 1D intrinsic design is discussed first. The transit time analysis is used to probe the
internal ?, and find the bottleneck for speed. Both base width wB and collector width wC
have to be reduced to nanometer scale in order to reduce ?B and ?C. The base doping
NB as high as 8?1019/cm3 is used to reduce base sheet resistance RB;?. The Ge design
impacts on device performance are compared between box and graded Ge profile. The
same film stability is used. Graded Ge profile can give higher fT and higher BVCEO.
Next, 2D design of SiGe HBT is addressed. The 1D transit time analysis is ex
tended to 2D, which can quantify transit delay from each intrinsic and extrinsic part.
The base resistance and CB capacitance are both extracted from MEDICI simulation
results. Using those methods, the lateral scaling is examined. The necessary structure is
revealed, which can achieve THz fmax.
In order to improve this work, we would like to propose to explore the 2D device
structure and processing limitation in the future.
79
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86
APPENDICES
87
APPENDIX A
MEDICI INPUT FILE
A.1 2D MESH
assign name=sufix c.val="RaisedBase2_we=120nm"
$ done = 1 > solve INI for tif file
$ done = 0 > Do not
assign name=done n.val=1
assign name=Depthoff n.val=0.095
call file=Layout
assign name=gemax n.val=0.28
mesh out.fil=@sufix".msh"
$ MESH
x.mesh width=0.2 n.space=5 h2=0.02
x.mesh width=0.25 h1=0.02 h2=0.02 h3=0.06
x.mesh width=0.10 n.space=6 h2=0.015
x.mesh width=@ox2x2@conb1x2 h1=0.015 h2=0.005
x.mesh width=@PolySix1@ox2x2 h1=0.008 n.space=8
x.mesh width=0.02 h1=0.005
x.mesh width=0.04 h1=0.005 h2=0.002 h3=0.015
88
x.mesh width=0.12 h1=0.002 h2=0.002 h3=0.02
x.mesh width=0.04 h1=0.002 h2=0.005 h3=0.015
x.mesh width=0.02 h1=0.005
x.mesh width=@PolySix1@ox2x2 h2=0.008 n.space=8
x.mesh width=@ox2x2@conb1x2 h1=0.005 h2=0.015
x.mesh width=0.10 h1=0.015 n.space=6
x.mesh width=0.25 h1=0.02 h2=0.02 h3=0.06
x.mesh width=0.2 n.space=5 h1=0.02
y.mesh depth=0.04 n.space=4 h2=0.005
y.mesh depth=0.05 h1=0.01 h2=0.01 h3=0.02
y.mesh depth=0.025 h1=0.008 h2=0.001 h3=0.004
y.mesh depth=0.005 h1=4e4
y.mesh depth=0.006 h1=5e4
y.mesh depth=0.003 h1=2e4
y.mesh depth=@geX40.129 h1=5e4
y.mesh depth=0.032 h1=5e4 h2=2e3
y.mesh depth=0.215 h1=4e3 h2=0.01 h3=0.03
y.mesh depth=0.98 h1=0.02 h2=0.2
$ REGION
region num=AllINI oxide
region num=Edge PolySi Polygon
89
+x.poly=(@PolySix1,@PolySix2,@PolySix3,@PolySix4,
+ @PolySix5,@PolySix6,@PolySix7,@PolySix8)
+y.poly = (@PolySiy1, @PolySiy2, @PolySiy3, @PolySiy4,
+ @PolySiy5, @PolySiy6, @PolySiy7, @PolySiy8)
region num=Inner PolySi Polygon
+ x.poly = (@PolySix1+0.01, @PolySix20.01, @PolySix30.01, @PolySix40.01,
+ @PolySix50.01, @PolySix6+0.01, @PolySix7+0.01, @PolySix8+0.01)
+ y.poly = (@PolySiy1, @PolySiy2, @PolySiy30.01, @PolySiy40.01, @PolySiy5,
+ @PolySiy6, @PolySiy70.01, @PolySiy80.01)
region num=4a sige y.min=@geX1 y.max=@geX2 x.mol=0 x.end=@gemax
+ y.linear x.min=@sigex1 x.max=@sigex2
region num=4b sige y.min=@geX2 y.max=@geX3 x.mol=@gemax x.end=@gemax
+ y.linear x.min=@sigex1 x.max=@sigex2
region num=4c sige y.min=@geX3 y.max=@geX4 x.mol=@gemax x.end=0
+ y.linear x.min=@sigex1 x.max=@sigex2
region num=Epi1 silicon x.min=@ox2x2 x.max=@PolySix6
+ y.min=@geX4 y.max=0.18
region num=Epi2 silicon x.min=@PolySix5 x.max=@ox6x1
+ y.min=@geX4 y.max=0.18
region num=SIC silicon x.min=@PolySix6 x.max=@PolySix5
+ y.min=@geX4 y.max=0.18
90
region num=3c silicon Polygon
+ x.poly = (@si2x1, @si2x2, @si2x3, @si2x4, @si2x5,
+ @si2x6, @si2x7, @si2x8, @si2x9, @si2x10, @si2x11, @si2x12)
+ y.poly = (@si2y1, @si2y2, @si2y3, @si2y4, 0.18,
+ 0.18, @si2y7, @si2y8, @si2y9, @si2y10, @si2y11, @si2y12)
region num=1a PolySi x.min=@conc1x1 x.max=@conc1x2
+ y.min=@conc1y1 y.max=0.25
region num=1b PolySi x.min=@conc2x1 x.max=@conc2x2
+ y.min=@conc2y1 y.max=0.25
region num=1c PolySi x.min=@conb1x1 x.max=@conb1x2+0.04
+ y.min=@conb1y1 y.max=@conb1y2
region num=1d PolySi x.min=@conb2x10.04 x.max=@conb2x2
+ y.min=@conb2y1 y.max=@conb2y2
region num=1f PolySi x.min=@Poly3x1 x.max=@Poly3x2
+ y.min=@Poly3y1 y.max=@Poly3y2
region num=1g PolySi x.min=@Poly4x1 x.max=@Poly4x2
+ y.min=@Poly4y1 y.max=@Poly4y2
$ ELECTRODE
elec name=emitter x.min=@PolySix1 x.max=@PolySix2 top
elec name=base region=1c
elec name=base region=1d
91
elec name=coll region=1b
elec name=coll region=1a
$ PROFILE
$****** PolySi Emitter ******
profile ntype n.peak=1e21 Polygon
+ x.poly = (@PolySix1, @PolySix2, @PolySix3, @PolySix4,
+ @PolySix5, @PolySix6, @PolySix7, @PolySix8)
+ y.poly = (@PolySiy1, @PolySiy2, @PolySiy3, @PolySiy4,
+ @depthoff, @depthoff, @PolySiy7, @PolySiy8)
+ n.char=1e10
profile 1d.ascii in.fil=asHI_Collopt4.dat y.column=1 n.column=2
+ y.offset=@depthoff
+ y.min=@depthoff x.min=@PolySix6 x.max=@PolySix5 x.char=1e4
profile 1d.ascii in.fil=asLOW_Collopt4.dat y.column=1 n.column=2
+ y.offset=@depthoff y.min=@depthoff
+ x.min=@PolySix6 x.max=@PolySix5 x.char=1e4
$****** PolySi Extrinsic Base
profile ptype n.peak=5e20 x.min=@Poly3x1 x.max=@Poly3x2
+ y.min=@Poly3y1 y.max=@Poly3y2 y.char=5e3 x.char=1e4
profile ptype n.peak=5e20 x.min=@Poly4x1 x.max=@Poly4x2
+ y.min=@Poly4y1 y.max=@Poly4y2 y.char=5e3 x.char=1e4
92
$****** Intrinsic Base
profile 1d.ascii in.fil=boron_Collopt4.dat y.column=1 p.column=2
+ y.offset=@depthoff y.min=@sigey1
+ x.min=@sigex1 x.max=@sigex2 x.char=1e5
$****** Collector
profile ntype n.peak=1e16 x.min=@ox2x2 x.max=@PolySix6
+ y.min=@sigey1 y.max=0.195 x.char=1e3 y.char=1e10
profile ntype n.peak=1e16 x.min=@PolySix5 x.max=@ox6x1
+ y.min=@sigey1 y.max=0.195 x.char=1e3 y.char=1e10
profile 1d.ascii in.fil=phos_Collopt4.dat y.column=1 n.column=2
+ y.offset=@depthoff
+ x.min=@PolySix6 x.max=@PolySix5 x.char=1e4
profile 1d.ascii in.fil=asBuri_Collopt4.dat y.column=1 n.column=2
+ y.offset=@depthoff
+ y.min=@sigey1 y.max=0.195 x.min=@PolySix6 x.max=@PolySix5 x.char=1e4
profile ntype n.peak=5e20 Polygon
+ x.poly = (0, @conc1x2, @ox2x1, @ox2x2, @ox2x2, @PolySix6,
+ @PolySix6, @PolySix5, @PolySix5, @ox6x1, @ox6x1, @ox6x2,
+ @conc2x1, @conc2x2, @conc2x2, 0)
+ y.poly = (@ox2y1, @ox2y1, @ox2y2, @ox2y2, 0.175, 0.175, 0.195,
+ 0.195, 0.175, 0.175, @ox6y2, @ox6y2, @ox6y1, @ox6y1, 1.5, 1.5) n.char=1e6
93
A.2 DC Solution
INI.inp  solve for the initial solutions
assign name=sufix c.val="RaisedBase_1p5THz"
mesh in.fil="../mesh/"@sufix".msh"
models phumob bgn consrh auger et.model tmpmob ef.tmp
call file=newslotboom
material silicon ele.tauw=3e13
symb newton carrier=2 ele.temp
solve v(emitter)=0 v(coll)=0 v(base)=0
solve v(emitter)=0 v(base)=0.1 v(coll)=0.1
save out.fil=@sufix"INIuncoup.sov"
symb newton carr=2 ele.temp coup.ele
load in.fil=@sufix"INIuncoup.sov"
solve v(emitter)=0 v(base)=0.1 v(coll)=0.1
+ out.fil=@sufix"VBE=0p1V_VCB=0V.sov"
loop steps=8
assign name=vb n.val=0.15 delta=0.05
solve v(emitter)=0 v(base)=@vb v(coll)=@vb
l.end
save out.fil=@sufix"VBE=0p5V_VCB=0V.sov"
solve v(emitter)=0 v(base)=0.5 v(coll)=0.5 elec=coll vstep=0.1 nstep=5
solve v(emitter)=0 v(base)=0.5 v(coll)=1.0
94
+ out.fil=@sufix"VBE=0p5V_VCB=0p5V.sov"
DC4YParam.inp  solve and save each DC solutions.
assign name=sufix c.val="RaisedBase_1p5THz"
COMMENT Specify a rectangular mesh
mesh in.fil="../mesh/"@sufix".msh"
symb newton carriers=2 ele.temp coup.ele
models bgn phumob consrh auger tmpmob et.model ef.tmp
call file=newslotboom
material silicon ele.tauw=3e13
load in.fil=@sufix"VBE=0p5V_VCB=0p5V.sov"
assign name=nstep n.val=50
assign name=vstep n.val=0.008
assign name=VCB n.val=0.5
Loop steps=@nstep
assign name=vb n.val=0.55 delta=@vstep
assign name=index n.val=1 delta=1
assign name=zfile c.val=@sufix"_DCsov"@index"_VCB=0p5V"
log out.fil=@zfile".log"
solve v(emitter)=0 v(coll)=@vb+@VCB v(base)=@vb
save out.fil=@zfile
plot.1d x.ax=V(base) y.ax=I(coll) y.log out.fil=@zfile".iv"
L.end
95
A.3 ac Solution
assign name=sufix c.val="RaisedBase_1p5THz"
COMMENT Specify a rectangular mesh
mesh in.fil="../mesh/"@sufix".msh"
symb newton carriers=2 ele.temp coup.ele
models bgn phumob consrh auger tmpmob et.model ef.tmp
call file=newslotboom
material silicon ele.tauw=3e13
assign name=nstep n.val=20
assign name=idxINI n.val=31
Loop steps=@nstep
assign name=index n.val=@idxINI delta=1
assign name=zfile c.val=@sufix@index
log out.fil=@zfile"acVCB=0p5V.log"
Load in.fil=@sufix"_DCsov"@index"_VCB=0p5V"
solve nfstep=30 mult.freq
+ AC.ANAL TERM=(Base,coll) FREQ=10e9 fstep=1.2 Hi.freq
L.end
96
APPENDIX B
MATLAB SCRIPTS
B.1 Transit Time Analysis
B.1.1 ?n and ?p Extraction
clear all;
close all;
sufix = ?../Graded/Graded?;
q=1.6e19;
for i=8:2:16
nacfn = sprintf(?Nac%d.dat?, i);
pacfn = sprintf(?Pac%d.dat?, i);
Jcfn = sprintf(?Jnac%d.dat?, i);
Icfn = sprintf(?Ic%d.dat?, i);
Mnac = load(chf(nacfn));
Mpac = load(chf(pacfn));
Mjc = load(chf(Jcfn));
MIc = load(chf(Icfn));
deln = Mnac(:,4);
97
delp = Mpac(:,4);
Jc = Mjc(:,4);
JCC(i) = MIc(1,2)./0.2.*1000;
dtaun = q.*deln./Jc.*1e4.*1e12; % ps/um
dtaup = q.*delp./Jc.*1e4.*1e12; % ps/um
dist = Mjc(:,3);
figure(1);
plot(dist,deln,?b?);
hold on;
figure(2);
plot(dist, dtaun, ?b?);
hold on;
%plot(dist,delp,?r?);
%legend(?\Delta\tau_p?,?\Delta\tau_n?);
xlabel(?Depth (\mum)?);
ylabel(?\Delta\tau_n, \Delta\tau_p (ps)?);
check = Int_tau_depth(dist, dtaun);
end
98
B.1.2 1D ?n and ?p Extraction
clear all;
close all;
sufix = ?Box?;
q=1.6e19;
for i=1:17
nacfn = sprintf(?Nac%d.dat?, i);
pacfn = sprintf(?Pac%d.dat?, i);
Jcfn = sprintf(?Jnac%d.dat?, i);
Icfn = sprintf(?Ic%d.dat?, i);
Mnac = load(chf(nacfn));
Mpac = load(chf(pacfn));
Mjc = load(chf(Jcfn));
MIc = load(chf(Icfn));
deln = Mnac(:,4);
delp = Mpac(:,4);
Jc = Mjc(:,4);
JCC(i) = MIc(1,2)./0.2.*1000;
dtaun = q.*deln./Jc.*1e4.*1e12; % ps/um
99
dtaup = q.*delp./Jc.*1e4.*1e12; % ps/um
dist = Mjc(:,3);
jx1 = 0.02;
jx2 = 0.025;
jx3 = 0.0325;
Tau_eh=0;
Tau_el=0;
Tau_b=0;
Tau_c=0;
len=length(dist);
for k=1:len1
Taun = (dtaun(k));
if (dist(k)jx1 & dist(k)jx2 & dist(k)<=jx3) % Base Transit time
dTb = Taun*(dist(k+1)dist(k));
Tau_b = Tau_b + dTb;
else
dTc = Taun*(dist(k+1)dist(k)); % Collector charging time
Tau_c = Tau_c + dTc;
end
end
end
TauEH(i) = Tau_eh;
TauEL(i) = Tau_el;
TauB(i) = Tau_b;
TauC(i) = Tau_c;
Total(i) = Tau_eh+Tau_el+Tau_b+Tau_c;
end
figure(1);
subplot(1,2,1);
semilogy(JCC, TauEH);
hold on;
101
semilogy(JCC, TauEL,??);
semilogy(JCC, TauB,?.?);
semilogy(JCC, TauC, ?+?);
figure(2);
loglog(JCC, Total);
B.1.3 2D ? Extraction
clear all;
close all;
%%%%%%%%%%%%%%%%%%%%%%
% Region ID
% (2)  Poly Edge
% (3)  Poly Inner
% (4)  SiGe 4a
% (5)  SiGe 4b
% (6)  SiGe 4c
% (7)  Si Epi1
% (8)  Si Epi2
% (9)  Si SIC
% (10)  Si 3C
% (13)  Poly 1f
% (14)  Poly 1g
102
% (16)  Poly Edge
%%%%%%%%%%%%%%%%%%%%%
Region = [4,5,6, 13,14];
q = 1.6e19;
dir = ?./WE=100nm/E_?;
filename = sprintf(?%sdQ_Base_Jc=30.dat?, dir);
delete(filename);
fid = fopen(filename, ?a+?);
fprintf(fid,?%QEBjx, QBaseEx, QBaseIn, QCollEx, QCollIn, QTotal \n?);
%%%%%%%%%%%%%%%%%%%%%%%%%%
%%% Interation  26:2:48 to get all QE vs. biasing
%%%%%%%%%%%%%%%%%%%%%%%%%%
for Index4Biasing = 1:1
Coorfn = sprintf(?%sVBcoordinate_VCB=0p5V_Jc=30.data?, dir);
Trifn = sprintf(?%sVBtriangle_VCB=0p5V_Jc=30.data?, dir);
Nodefn = sprintf(?%sVBNodeIndex_VCB=0p5V_Jc=30.data?,dir);
Datafn = sprintf(?%sVBData_VCB=0p5V_Jc=30.data?, dir);
103
Coordinate = load(chf(Coorfn, 2));
Tri = load(Trifn);
NodeIndex = load(Nodefn);
Data = load(Datafn);
InteQ = 0;
%%% Triangle "2, TriIndex, RegionID, c1, c2, c3"
%%% The unit of each region is made up of triangles
RegionID = Tri(:,3);
c1 = Tri(:,4);
c2 = Tri(:,5);
c3 = Tri(:,6);
%%% Coordinate "1, CoIndex, X, Y"
CoIndex = Coordinate(:,2);
X = Coordinate(:,3);
Y = Coordinate(:,4);
len = length(RegionID);
for m=1:length(Region) % for each region defined in the input file
104
clear dInteQ;
dQEBjx = 0;
dQBaseEx = 0;
dQBaseIn = 0;
dQBasePoly = 0;
dQCollEx = 0;
dQCollIn = 0;
for i=1:len
if(RegionID(i)~=Region(m))
continue;
else
%%%% get info. of c1 c2 c3
target = [c1(i),c2(i),c3(i)];
lenCoord = length(CoIndex);
for j=1:3
for k=1:lenCoord
if(CoIndex(k)~=target(j))
continue;
else
x_ax(j) = X(k);
y_ax(j) = Y(k);
105
break;
end
end
end
d1 = sqrt((x_ax(1)x_ax(2))^2+(y_ax(1)y_ax(2))^2);
d2 = sqrt((x_ax(1)x_ax(3))^2+(y_ax(1)y_ax(3))^2);
d3 = sqrt((x_ax(3)x_ax(2))^2+(y_ax(3)y_ax(2))^2);
temp = (d1+d2+d3)/2;
ds = sqrt(temp*(tempd1)*(tempd2)*(tempd3)); % unit um^2
ds = ds*1e8; % unit cm^2
%%%% get data
lenData = length(NodeIndex);
for j=1:3
for k=1:lenData
if(NodeIndex(k)~=target(j))
continue;
else
data_nac(j) = Data(k,15);
% Get ac_electron n (unit: /cm^3)
break;
end
106
end
end
avg_nac = (data_nac(1)+data_nac(2)+data_nac(3))/3;
% unit of n  /cm^3
dInteQ(i) = (q*avg_nac)*ds; % unit: Coul/cm
dInteQ(i) = dInteQ(i)/1e4; % unit: Coul
if( Region(m)==13  Region(m)==14 )
dQBasePoly = dInteQ(i);
continue;
else
%%% Extract delta N for each region definition 
%for extrinsic base, EB jx, and intrinsic Base
if(max(x_ax)<=0.73  min(x_ax)>=0.85)
% left/rightside of SiGe Base
if ( max(y_ax) <= 0.1260 )
dQBaseEx(i) = dInteQ(i);
else
dQCollEx(i) = dInteQ(i);
end
continue;
end
107
if (min(x_ax)>0.73 & max(x_ax)<0.85)
% Middle of SiGe Base
if (max(y_ax)<=0.1222)
dQEBjx(i) = dInteQ(i);
else if (min(y_ax)>0.1222 & max(y_ax)<=0.126)
dQBaseIn(i) = dInteQ(i);
else
dQCollIn(i) = dInteQ(i);
end
end
continue;
end
end
end
end
Result(m) = sum(dInteQ);
QEBjx(m) = sum(dQEBjx);
QBaseEx(m) = sum(dQBaseEx);
QBaseIn(m) = sum(dQBaseIn);
QBasePoly(m) = sum(dQBasePoly);
108
QCollEx(m) = sum(dQCollEx);
QCollIn(m) = sum(dQCollIn);
end
DataSave = [sum(QEBjx), sum(QBaseEx)+sum(QBasePoly),
sum(QBaseIn), sum(QCollEx), sum(QCollIn), sum(Result)];
StrSave = num2str(DataSave);
fprintf(fid,?%s\n?, StrSave);
end
fclose(fid);
disp(?FINISH!?);
B.2 Distributive Capacitance
clear all;
close all;
dJc = load(?dJc.txt?);
dIc = dJc.*0.12./1e8;
dQE = load(?dQ_Emitter_Biasing.dat?);
dQB = load(?dQ_Base_Biasing.dat?);
dQC = load(?dQ_Coll_Biasing.dat?);
dQCVe = load(?dQ_Coll_BiasingVe.dat?);
109
dQCVe = 1.*dQCVe;
gm = load(?../../PostProcessing/GmJc.dat?);
gm = gm?;
Taud = load(?../../PostProcessing/TaudJc.dat?);
RB = load(?../../PostProcessing/RBJc.dat?);
Taud = Taud?./gm;
TauEh = dQE(:,1)./dIc.*1e12;
TauEl = ( dQE(:,2) + dQB(:,1) )./dIc.*1e12;
TauEf = dQE(:,3)./dIc.*1e12;
TauBin = dQB(:,3)./dIc.*1e12;
TauBex = dQB(:,2)./dIc.*1e12;
TauCin = (dQCVe(:,1)+dQB(:,5))./dIc.*1e12;
TauCex = (dQCVe(:,2)+dQB(:,4))./dIc.*1e12;
TauCin_dep = (dQC(:,1)  dQCVe(:,1))./dIc.*1e12;
TauCex_dep = (dQC(:,2)  dQCVe(:,2))./dIc.*1e12;
TauEC = TauEh + TauEl + TauEf + TauBin
+ TauBex + TauCin + TauCex + TauCin_dep + TauCex_dep;
j = 1;
for i=26:2:48
fn = sprintf(?../Calibration/RaisedBase2_we=120nm_DCsov%d_VCB=0p5V.iv?, i);
Bias = load(chf(fn, 5));
110
Jc(j)=Bias(1,2)/0.12*1000;
j = j+1;
end
Tau_x = (TauEl+TauBin+TauCin*0.8);
CdE=gm.*TauEh;
Cte = gm.* TauEl;
CEf = gm.*TauEf;
CdBin = gm.*TauBin;
CdBex = gm.* TauBex;
CdCin = gm.* TauCin;
CdCex =gm.* TauCex;
B.3 M 1 Postprocessing
clear all;
close all;
EMedici = load(chf(?VBE=0p65V_VCB=1p8V_vac.ef?));
Xjxn = 0.165; % um
Xjxp = 0.126; % um
VCB4Save=1.8;
% Extract Edata in the CB jx
index = 1;
dist = EMedici(:,1);
111
for k=1:length(dist)
if(dist(k)>= Xjxp & dist(k)<=Xjxn)
xax(index) = EMedici(k,1);
yax(index) = EMedici(k,2);
index = index+1;
else
continue;
end
end
%%%%%%%%%%%%% actual data to work with
Edata = [xax; yax];
Edata = Edata?;
len = length(xax);
xp = xax(1);
xn = xax(len);
%%%%%%%%%%%%%%%%%%%%%%%%%
Eeffdata(1) = 1e4;
alphaN(1) = 0;
alphaP(1) = 0;
for i=2:len
Eeffdata(i) = Eeff(xp, xax(i), Edata); % V/cm
112
alphaNP = IIalpha(Eeffdata(i));
alphaN(i) = alphaNP(1); % 1/cm
alphaP(i) = alphaNP(2); % 1/cm
end
% Calculate innerintegral
expTerm(1) = 0;
func = alphaN  alphaP; % 1/cm
func = func./1e4; % 1/um
func = [xax; func];
func = func?;
for i=2:len
tempRlt = Integral(xp, xax(i), func);
expTerm(i) = exp(tempRlt);
end
% Calculate outerintegral
clear func;
func = alphaN .* expTerm; % 1/cm
func = func./1e4; % 1/um
%Rlt = Integral(Xjxp, Xjxn, func);
for i=1:length(func)1
avg = (func(i)+func(i+1))/2;
113
delx = xax(i+1)xax(i);
area(i) = avg * delx;
end
Rlt = sum(area);
Mn = 1/(1Rlt);
MM1 = Mn  1;
disp(MM1);
if(1)
MM14Save=MM1.*1e6;
outputData = num2str([VCB4Save, MM14Save]);
fname = ?RaisedBase_we=120nmVBE=0p65V.MM1?;
fid = fopen(fname, ?a+?);
fwrite(fid, outputData);
fprintf(fid, ?\n?);
fclose(fid);
end
function result = IIalpha(E)
E = abs(E);
% for electrons
114
an = 7.03e5; %1/cm
bn = 1.231e6; %V/cm
% for holes
if ( E<=4e5)
ap = 1.582e6;
bp = 2.036e6;
else if (E>4e5 & E<= 6e5)
ap = 6.71e5;
bp = 1.693e6;
end
end
alphaN = an * exp(bn/E);
alphaP = ap * exp(bp/E);
result = [alphaN alphaP];
% Calbulate the effective Electric Filed at position x
% Considering the nonlocal effect
function result = Eeff (xp, x, Edata)
Lambdan = 65; % nm
115
Lambdan = 65e3; % um
depthE = Edata(:,1);
lenE = length(depthE);
xaxE(1) = Edata(1,1);
yaxE(1) = Edata(1,2)/1e4;
indexE = 2;
for kE=2:lenE
if(depthE(kE)<=x)
xaxE(indexE) = Edata(kE,1); % um
yaxE(indexE) = Edata(kE,2)/1e4; % V/um
indexE = indexE+1;
else
break;
end
end
nE = length(xaxE)1;
for i=1:nE
V2E = yaxE(i+1)*exp((xaxE(i+1)x)/Lambdan);
V1E = yaxE(i) *exp((xaxE(i) x)/Lambdan);
avgE = (V1E+V2E)/2;
delxE = xaxE(i+1)xaxE(i);
116
areaE(i) = avgE * delxE;
end
result = sum(areaE)/Lambdan; % V/um
result = result/1e4; % V/cm
function result = Integral (st, en, data)
index = 2;
dist = data(:,1);
xaxInt(1) = data(1,1);
yaxInt(1) = data(1,2);
for k=2:length(dist)
if(dist(k)<=en)
xaxInt(index) = data(k,1);
yaxInt(index) = data(k,2);
index = index+1;
else
break;
end
end
n = length(xaxInt)1;
for i=1:n
%clera avg delx;
117
avgInt = (yaxInt(i)+yaxInt(i+1))/2;
delxInt = xaxInt(i+1)xaxInt(i);
areaInt(i) = avgInt * delxInt;
end
result = sum(areaInt);
118