Reconvergent Fanout Analysis of Bounded Gate Delay Faults
Type of DegreeThesis
Electrical and Computer Engineering
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To determine the quality that a set of gate delay tests provides for testing gate delay faults, gate delay fault simulation must determine the minimum size detectable for detected gate delay faults. The minimum size detectable is the minimum faulty gate delay that must be present for the test to detect the fault. Given two tests that detect the same fault, the test that detects the fault with a smaller size is considered a higher quality test for that fault. When bounded gate delays are used, gate delay fault simulation involves bounded delay simulation of the fault-free circuit and an evaluation of the faulty waveforms. Whenever signals in a combinational circuit diverge from a fanout point and reconverge later, the inputs to the reconvergent gate are correlated. In conventional bounded delay simulation and gate delay fault simulation, these correlations are ignored. In this work, we present a method for adding reconvergent fanout analysis to bounded delay simulation and gate delay fault simulation. In bounded delay simulation, considering information about how signals are correlated due to reconvergent fanout provides more accurate evaluation of simulation waveforms than previous approaches that ignore this information. In gate delay fault simulation, this correlation information provides more accurate evaluation of the minimum size detectable for detected gate delay faults. Results for gate delay fault simulation show that ignoring these correlations produces pessimistic calculations for the minimum sizes detectable.