A Novel ROM Compression Technique and a High Speed Sigma-Delta Modulator Design for Direct Digital Synthesizer

Abstract

Traditional designs of high bandwidth frequency synthesizers employ phase locked loops (PLLs). A direct digital frequency synthesizer (DDFS) provides multiple advantages over the frequency synthesizers that use PLLs. A DDFS has fast settling time, high frequency resolution, continuous phase switching response and low phase noise. Traditionally, DDFSs were mainly used in producing narrow bands of closely spaced frequencies. However, recent advancements in integrated circuit (IC) technologies have provided a vast scope for progress in this area. The use of DDFS is still in developmental stages. However, its major bottleneck is the presence of a phase to sine converter ROM look-up-table which restricts speed, occupies large area and has high power consumption. This thesis presents a novel DDFS ROM compression technique that provides high compression ratio without performance degradation. To validate the proposed DDFS ROM compression algorithm, architectures are implemented in a Xilinx Spartan II FPGA and their spurious performances are compared. A theoretical analysis in the first part of the thesis gives an overview of the functionality of DDFSs and sigma-delta modulators with respect to noise and spurs. Other popularly used ROM compression techniques are discussed and compared to the proposed technique. The later part of the thesis deals with the design and implementation of a sigma-delta modulator used to reduce the phase noise at the output of a ROM less DDFS architecture.