Radio Frequency Integrated Circuits for Wireless and Wireline Communications
Type of DegreeDissertation
Electrical and Computer Engineering
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This dissertation presents my studies in design of high frequency circuits for wireless and wireline communication systems. As a part of this effort a seven tap transversal filter has been designed using broadband amplifiers. The use of active devices instead of passive inductors to implement delay stages greatly reduces the required die area and also makes the filter more adaptive in nature. The designed chip is capable of adapting zeros at various frequencies up to 3.5 GHz, implementing various filter characteristics. A detailed study of delay through Current Mode Logic (CML) gate operating at the GHz range has been done and optimal and novel biasing strategies have been investigated to achieve higher operational speeds. --Y΄Keep alive‘ biasing technique has been proposed to reduce delay in CML latches. The optimal biasing strategy for CML circuits is obtained considering the circuit speed and power consumption. Design challenges in the design of high frequency single phase and multiphase oscillators have been investigated followed by prototype designs. A novel Quadrature VCO (QVCO) is implemented in a 47 GHz SiGe technology. The QVCO is a serially coupled LC VCO that utilizes Silicon Germanium (SiGe) Hetero-junction Bipolar Transistors (HBT) for oscillation and Metal Oxide Semiconductor Field Effect Transistors (MOSFET) for coupling, resulting in 14% wide tuning range. Design of high frequency 25 GHz oscillator is also presented. The 25 GHz oscillator achieves phase noise of -82 dBc/Hz @ 500 KHz offset. Design of a 1.2 V, 3.7 mW 8-bit LC tuned Digitally Controlled Oscillator (DCO) implemented in a 120 nm BiCMOS technology is presented. The varactor bank in the oscillator consists of eight binary weighted capacitors controlled by rail-to-rail CMOS logic values. The DCO oscillation frequency can be tuned from 4.2-4.7 GHz with 11.2% tuning range and an average frequency resolution of 2 MHz/bit. The DCO has phase noise of -103 dBc/Hz @ 500 KHz offset and exhibits -177 dBc/Hz figure of merit. Design of 1.5 V second order phase locked loop is presented. The loop exhibits an in-band phase noise of -70 dBc/Hz @ 10 KHz offset and out-band phase noise of -110 dBc/Hz @ 3 MHz offset frequency from a 5 GHz carrier frequency.