|dc.description.abstract||Solder joint failure in electronic devices subject to shock and drop environment is one of the key concerns for the telecommunications industry. The recent trend towards miniaturization and increased functional density has resulted in decreasing the I/O pitch,and thus increasing the chances of failure of the package under shock and vibration
environments. Solder joint failure occurs due to a combination of printed circuit board(PCB) bending and mechanical shock during impact. Consequently, optimization of package design is necessary to minimize the effects of shock during impact on the solder interconnections.
In this present work, the modeling approaches for first-level solder interconnects in shock and drop of electronics assemblies have been developed without any assumptions of geometric or loading symmetry. The problem involves multiple scales
from the macro-scale transient-dynamics of electronic assembly to the micro-structural
damage history of interconnects. Previous modeling approaches include, solid-to-solid sub-modeling [Zhu, et. al. 2001] using a half test PCB board and shell-to-solid submodeling technique using a quarter symmetry model [Ren, et. al. 2003, 2004]. Inclusion of model symmetry saves computational time but targets primarily symmetric mode
shapes. The modeling approach proposed in this paper enables prediction of both symmetric and anti-symmetric modes. Approaches investigated include, smeared property models, Timoshenko-beam element models, explicit sub-models, and
continuum-shell models. Transient dynamic behavior of the board assemblies in free and JEDEC drop has been measured using high-speed strain and displacement measurements.Model predictions have been correlated with experimental data. Two failure prediction models namely the Timoshenko-Beam Failure Model and the Cohesive Zone Failure Model have also been developed to predict the location and mode of failure in the solder interconnections in PCB assemblies subject to drop impact.||en_US