# Simulation Based Power Estimation For Digital CMOS Technologies

## Date

2008-12-15## Type of Degree

Thesis## Department

Electrical and Computer Engineering

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Show full item record## Abstract

The estimation of power in digital CMOS circuits has become a significant problem, especially for present day semiconductor technologies. Finding a balance between opposing factors of estimation accuracy and computation speed makes the estimation procedures more challenging. An area that has been neglected is the breakdown analysis of various components of power. In this thesis, we discuss algorithms and a tool for a ``total'' power estimation tool. This tool does an event-driven simulation of vectors, either supplied or randomly generated at user's option. All components of power, namely, dynamic (separate logic and glitch components), leakage, short-circuit and clock power are estimated. Peak, minimum and average values for the given vector set are also determined. For simulation, first delay, node capacitance, and input state specific leakage are determined for each gate in the given technology, temperature and supply voltage, using a circuit-level simulator (Spice) and saved. This gives us the necessary accuracy and speed to the power estimation. To demonstrate applications of the tool, we examine leakage variation with temperature, variation of short-circuit power with rise time and output load capacitance, and the quadratic reduction in logic transition power. Glitch power is shown to reduce faster than the quadratic function of voltage because the increased gate inertia suppresses many glitches. Since in any design technique to reduce one component of power, in general, affects other components, such a tool is useful. We analyze the effect of process variation in estimation of dynamic power dissipation. Taking a novel approach, we model gates with given lower and upper bounds on delays. For given input vectors, we first find logic transitions using zero-delay simulation. Our algorithms then determine the ambiguity (transient) interval during which transitions occur, and the maximum and minimum number of possible transitions. Computation of these for all gates requires a linear-time analysis of each vector-pair. Weighting with node capacitances estimates lower and upper bounds on dynamic power. Results compare favorably with power analysis using Mont Carlo simulation, which requires significantly more computing resources. Monte Carlo simulation of ISCAS benchmark circuit c880 for 1000 random vectors (999 vector-pairs) demonstrates the advantages of the bounded delay power analysis. Each vector-pair was simulated for 1000 sample circuits. Sample circuits had gate delays varying $\pm 20\%$ about the nominal values for the TSMC025 2.5V CMOS process~\cite{Mosis}. For a vector period of 1000 ps minimum power was 1.424 mW and maximum power was 11.598 mW. Monte Carlo simulation runs took 262.75 CPU s on a Sun Sparc Ultra 10 with 4GB shared memory system. Using the same $\pm 20\%$ variability and the same 1000 vectors, the bounded delay analysis obtained a bound (1.35 mW, 11.89 mW) for power in just 0.3 CPU s. Considering that c880 is a small circuit and the impact of process variation on power continues to assume greater importance, this computational efficiency is a strong motivation for using the method developed in this research.