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dc.contributor.advisorDai, Fa Foster
dc.contributor.advisorNiu, Guofuen_US
dc.contributor.advisorRoppel, Thaddeusen_US
dc.contributor.authorRatcliff, Marcusen_US
dc.date.accessioned2009-02-23T15:54:49Z
dc.date.available2009-02-23T15:54:49Z
dc.date.issued2008-12-15en_US
dc.identifier.urihttp://hdl.handle.net/10415/1452
dc.description.abstractThe components of the phase locked loop (PLL) circuit discussed in this thesis are designed for use in a transmit receive (TR) module contracted out to Auburn University by United States Space and Missile Defense (USSMDC) based in Huntsville, AL. IBMs SiGe 8hp technology is considered to be on the cutting edge of the radio-frequency integrated circuit design world, and was needed to meet the constraints set forth by the objectives of the TR module. There will be a brief introduction to PLLs, followed by a more in-depth look at architectures chosen for use. This will be followed by simulations and comparisons of the architecture blocks used and how they interact with other blocks.en_US
dc.language.isoen_USen_US
dc.rightsEMBARGO_NOT_AUBURNen_US
dc.subjectElectrical and Computer Engineeringen_US
dc.titlePhase Locked Loop Analysis and Designen_US
dc.typeThesisen_US
dc.embargo.lengthMONTHS_WITHHELD:6en_US
dc.embargo.statusEMBARGOEDen_US
dc.embargo.enddate2009-08-23en_US


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