Soft Error Rate Determination For Nanometer CMOS VLSI Circuits

Abstract

Nanometer CMOS VLSI circuits are highly sensitive to soft errors due to envi- ronmental causes such as cosmic radiation and high-energy particles. These errors are random and not related to permanent hardware faults. Their causes may be internal (e.g., interconnect coupling) or external (e.g., cosmic radiation). Nowadays, the term soft errors, also known as Single Event Upsets (SEU), speci¯cally de¯nes radiation errors caused in microelectronic circuits when high energy particles strike at sensitive regions of the silicon devices. The soft error rate (SER) estimation analytically predicts the effects of cosmic radiation and high-energy particle strikes in integrated circuit chips by build- ing SER models. An accurate analysis requires simulation using circuit netlist, device characteristics, manufacturing process and technology parameters, and measurement data on environmental radiation. Experimental SER testing is expensive and analytical approaches are, therefore, bene¯cial. We model neutron-induced soft errors using two parameters, namely, occurrence rate and intensity. Our new soft error rate (SER) estimation analysis propagates occurrence rate and intensity as the width of single event transient (SET) pulses, expressed as a probability and a probability density function, respectively, through the circuit. We consider the entire linear energy transfer (LET) range of the background radiation which is available from measurement data speci¯c to the environment and device material. Soft error rates are calculated for ISCAS85 benchmark circuits in the standard units, failure in time (FIT, i.e., failures in 109 hours). In comparison to the reported SER analysis results in the literature, our method considers several more relevant factors including sensitive regions, circuit technology, etc., which may in°uence the SER. Our simulation results for ISCAS85 benchmark circuits show similar trend as other reported work. For example, our soft error rate results for C432 and C499 considering ground-level environment are 1.18E3 FIT and 1.41E3 FIT, respectively. Although no measured data are available for logic circuits, SER for 0.25mu and 0.13mu 1M-bit SRAMs have been reported in the range E4 to E5 FIT, and for 0.25mu 1G-bit SRAM around 4.2E3 FIT. We also discuss the factors that may cause several orders of magnitude difference in our results and certain other logic analysis methods. The CPU time of our analysis is acceptably low. For example, for C1908 circuit with 880 gates, the analysis takes only 1.14 second. The fact that we propagate the error pulse width density information to primary outputs of the logic circuit would allow evaluation of SER reduction schemes such as time or space redundancy. This thesis also proposes a possible soft error reduction technique by hardware redesign involving circuit board reorientation. The basic idea is that the particles with LET smaller than the critical LET will not be able to cause an error if the angle of incidence is smaller than some critical angle. A proper orientation of hardware circuit boards will possibly reduce the soft error rate.