A Hardware-Software Processor Architecture using Pipeline Stalls for Leakage Power Management
Type of DegreeThesis
Electrical and Computer Engineering
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In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this truer than for portable, battery-operated applications, where power consumption has perhaps superseded speed and area as the overriding implementation constraint. But since last few years as the greater emphasis is put on miniaturization, in future technologies, the problem of subthreshold leakage power in CMOS circuits will grow in significance. The leakage current is exponentially dependent on the value of the threshold voltage such that if the threshold voltage is reduced (as it will be in the future technologies), the leakage current registers an exponential increase. Responding to this challenge, several low power techniques at levels ranging from technology to architecture have been proposed to reduce both dynamic and static power for processors and make them more energy-efficient. Some of these techniques can be applied to hardware whereas others are software based techniques. In this thesis, we propose a combined hardware-software technique which will potentially show considerable leakage energy reduction when power-performance trade-offs are made in higher-leakage technologies. A simple method to reduce the power consumption in a processor is to slow down the clock frequency. The dynamic power reduces in proportion to the frequeny reduction. However, the leakage power remains the same. Because a computing task will require the same number of clock cycles it will now take more time. The leakage energy will therefore increase, although the dynamic energy will remain the same. It is the reduction of leakage power and energy that is targeted in the present work. The main idea introduced and investigated is that the power-performance trade-off is accomplished by inserting empty(no-op) cycles while the clock rate is kept unchanged. The hardware units are especially designed to save leakage power while processing a no-op instruction. As an illustration, the hardware of a five-stage pipeline RISC processor is redesigned to reduce power consumption of the no-op cycles using sleep modes. This largely eliminates the leakage in those cycles. The expected result is that as more empty cycles are inserted, the performance would drop similar to the conventional clock frequency reduction. However, the computing task that now takes more cycles has only a marginal increase in the leakage energy. In addition, the empty cycles may eliminate many of the pipeline hazards and thus reduce the performance penalty. In this work, power supply for the active(i.e., non-empty)cycles is not changed and that aspect is left for the future investigation. The control unit of the processor has been designed to interpret an external power management signal. Based on the power and performance requirements, this signal specifies a performance slow down factor. The power block has been added in the processor architecture that inserts no-ops in proportion to the slow down factor in the instruction stream. The normal clock rate is maintained. The control also generates the power signals for different blocks of the processor along with the other control signals. These power signals are applied to various hardware blocks (register file, ALU, and instruction and data caches) of the processor, which on the basis of the required activity are put into one of the low power modes such as drowsy or sleep mode. These modes are chosen for the best leakage power reduction. We have simulated a modified 32-bit MIPS pipelined processor for 22nm and 65nm technologies using the Berkeley Predictive Technology Models.