Output Hazard-Free Test Generation Methodology
Type of Degreethesis
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Architectural restrictions of scan greatly limit the effectiveness of traditional scan based delay tests. It has been recently shown that additional testing for delays on short paths using fast clocks can significantly lower DPM. However, accurately obtaining the needed timing information for such tests from simulation is extremely difficult. The simulations must not only accurately account for the effects of process parameter variations, but also power supply noise and crosstalk from the excessive switching activity of scan tests. Scan based timing comparison tests offer a potential solution to the problem of small delay detection in aggressive nanometer technologies. These tests require that circuit delays be unambiguously captured in the scan chains using multiple fast clocks. To ensure this, only those signals that are known to be hazard-free at captured are analyzed for timing information from the scan-out data. In this work we present the first systematic ATPG driven approach for generating high coverage Output Hazard-Free (OHF) TDF tests for scan delay testing. We have analyzed the effect of variations in process on test coverage using our approach. Results indicate that acceptable coverage can be achieved, no worse than about 10% below the unconstrained TDF coverage for both LOS and LOC tests, even in the presence of significant process variations. The ATPG effort needed for the test set generation is modest as compared to using SPICE or other similar full circuit simulator for obtaining the OHF TDF vectors.