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dc.contributor.advisorStroud, Charles
dc.contributor.authorYao, Jia
dc.date.accessioned2009-05-05T18:26:03Z
dc.date.available2009-05-05T18:26:03Z
dc.date.issued2009-05-05T18:26:03Z
dc.identifier.urihttp://hdl.handle.net/10415/1723
dc.description.abstractIt is important to test programmable routing resources in Field Programmable Gate Arrays (FPGAs) because they take up the largest portion of configuration memory bits. In Virtex-4 FPGAs, routing resources account for over 80% of the configuration memory. Built-In Self-Test (BIST) is adopted to test the routing resources in FPGAs and overcomes issues residing in previously developed test approaches. The cross-coupled parity BIST approach has proven to be the most effective method for testing FPGA routing resource architectures with high fault coverage. BIST configurations are developed in this thesis to test global routing resources using cross-coupled parity approach in Virtex-4 FPGAs, focusing on hex lines and long lines. The total number of BIST configurations for LX devices is 34. This number increases to 42 for SX25 and SX35 devices and to 66 for SX55 devices. Analysis and evaluations of developed BIST configurations are provided as well. All BIST configurations are downloaded and verified on LX60 and SX35 devices.en
dc.rightsEMBARGO_NOT_AUBURNen
dc.subjectElectrical Engineeringen
dc.titleBuilt-In Self-Test of Global Routing Resources in Virtex-4 FPGAsen
dc.typethesisen
dc.embargo.lengthNO_RESTRICTIONen_US
dc.embargo.statusNOT_EMBARGOEDen_US


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