Spectral Methods for Testing of Digital Circuits
Type of Degreedissertation
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Due to increasing design complexities of digital circuits in recent years, a growing problem in Very Large Scale Integrated (VLSI) digital circuit testing is the exponential rise in the test generation complexity and an increasing need for high quality test vectors. For Built-In Self-Test (BIST) of digital circuit, the in-built pattern generator shows increased area overhead, as larger number and more specific patterns need to be generated. In this thesis we address these issues of digital circuit testing. We propose a novel test generation algorithm for sequential circuits using spectral methods. We generate test vectors for faults defined at Register-Transfer Level (RTL) and analyze them for spectral properties. New test vectors are generated using these properties to detect all faults of the circuit. Our proposed algorithm shows equal or improved test coverage and reduced test generation time as compared to a commercial sequential test generation tool, FlexTest, for various benchmark circuits. For an experimental processor PARWAN, FlexTest achieved a test coverage of 93.40% requiring 1403 test vectors in 26430 CPU seconds. The proposed spectral method achieved a coverage of 98.23% requiring 2327 vectors in 2442 CPU seconds. We also propose a Design-For-Testability (DFT) method at RTL which enables improved test coverage and reduced test generation time. We define N-model tests that target faults belonging to N specified fault models of choice. We propose a method for minimizing these tests using Integer Linear Programming (ILP) without reducing the individual fault model coverage. Stuck-at, transition, and pseudo stuck-at IDDQ faults are used as illustrations. The proposed method shows a noticeable reduction in test set size as compared to conventional minimization. For ISCAS’89 benchmark circuit s1488, the initial test set consisted of 557 test vectors (with 57 IDDQ vectors) (represented as 557(57)). Conventional single fault model minimization achieved 451(45) test vectors while our multiple fault model minimization achieved 175(39) test vectors. We also propose an ILP model to offer a trade-off between the total number of test vectors and the cost of test application (number of IDDQ vectors in our example). For s1488, depending on the cost of application, our method offers a choice anywhere from 175(39) to 187(33) test vectors. Since solving ILP problems has an exponential time complexity, we also propose a reduced complexity ILP approximation. We propose a method for designing a Test Pattern Generator (TPG) for BIST using spectral techniques, which replicates the efficacy of a given set of test patterns generated for a digital circuit. Spectral properties extracted from the test patterns are regenerated in hardware using a novel spectral TPG architecture. For combinational circuits, a test vector reshuffling algorithm is proposed to enhance the extraction of spectral properties. In six out of eight sequential benchmark circuits considered, our method achieved at least as much fault coverage as the ATPG vectors. For the circuit s38417, our proposed method detected 17020 faults as compared to 15472 faults detected by ATPG vectors. Our proposed BIST method detects equal or greater number of faults in six out of eight circuits than random, weighted random and an earlier published work. In case of combinational circuits, for circuit c7552, our method attained a test coverage of 99.82%, while random and weighted random attained 97.41% and 97.86% respectively for the same test vector length. We also show the benefits of reseeding of our proposed spectral TPG in terms of test compression on two combinational benchmark circuits. In the considered circuits, our proposed architecture provides a maximum test data compression exceeding 90%.