High Speed ROM-Less Direct Digital Frequency Synthesizer
Type of Degreedissertation
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This dissertation presents a complete flow for design and evaluation of high speed direct digital frequency synthesizer (DDS). Though some ultra high speed DDSs have already been reported in the literature, to satisfy the demand of keeping good balance between the power consumption and the high performance of DDS is still quite challenging for the analog designer and is worth to be explored from different perspectives. As a digital method to direct generating sine or cosine waveforms with specific frequency, DDS does have many merits. DDS has fine frequency tuning step, fast frequency switching speed, precisely controlled output phases. Since there is no feedback loop in a DDS structure, the DDS doesn't suffer the internal loop delay like that in the phase-locked-loop (PLL) synthesizer. One major benefit that makes DDS stand out is that DDS can be directly modulated in the digital domain. It can be incorporated with various kinds modulation schemes to generate modulated signals. By this way, DDS can be served as an important component to build flexible and reconfigurable transmitter in the communication systems. DDS can also generate quadrature phases and multiple phases with ease. Other than sine and cosine waveforms, DDS can be utilized to synthesize arbitrary waveforms. Taking the advantage of well developed Silicon-Germanium (SiGe) process, it is possible to push the envelope of the DDS speed performance as well as keep the moderate budget of power consumption. The standard CMOS technology has also been investigated. Several DDSs have been implemented with the non-linear digital to analog converters (DAC). The non-linear DAC can directly map the linear phase word into sine or cosine analog output without the assistance of the ROM. By eliminating the ROM, the speed of DDS can be dramatically improved. Due to the code dependent and frequency dependent non-ideal effects from the non-linear DAC, the unwanted harmonics and spurs of the DDS outputs have more significant impacts on the whole systems. In this dissertation, the spurs and harmonics from different sources such as truncation errors, limited DAC amplitude resolutions and non-ideal effects of DAC will be discussed. During the design, a couple of issues such as clock feed through, clock skew, device matching properties will be addressed. In the layout period, an method that can automatically synthesize the layout of current source matrix block has been developed, which can alleviate the transistor matching problem coming from the fabrication. The unique structure of a compact periodical waveform generator has also been investigated. In the waveform generator, a ring oscillator has been combined with a weighted non-linear DAC, thus the external clock and internal clock distributing circuits are no longer need. This will provide some benefits for certain on-chip test applications.