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Strategies for Efficient and Effective Scan Delay Testing
Aggressive timing requirements in today’s high-speed designs have introduced the need to test for small delay defects and distributed timing faults caused by statistical process variations. Faster-than-rated clock delay ...
Testing and Diagnosis of CMOS Open Defects in the Presence of Common Hazards
CMOS open defects are breaks in wires or defective transistors within some library cell causing pull up or pull down failure of the defective gates. Traditionally, TSOF (transistor stuck-open fault) is used to model such ...