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Implementation of High Speed SAR ADC with Proposed Efficient DAC Architecture
A novel, high performance SAR ADC architecture is designed and fabricated in 130nm SiGe technology and 45nm soi technology. In the beginning fundamentals of ADC (Analog-to-Digital Convertor) are introduced and several ...
High Speed Low Power Pipelined SAR ADC with Time Domain Based Fine Quantizer
(2022-12-05) ETD File Embargoed
Due to the demanding requirements of speed, bandwidth, and power consumption of the latest-generation communication systems, designing analog integrated circuits serving the communication systems has become increasingly ...