A Novel Three Dimensional Wafer Level Chip Scale Packaging Technology-Manufacturing Process Development and Reliability Characterizations
Type of Degreedissertation
DepartmentIndustrial and Systems Engineering
MetadataShow full item record
Three Dimensional (3D) packaging has moved to the forefront in the electronic packaging industry, as the trend toward higher performance, smaller form factor and lower cost continues. The development of the manufacturing technology for a novel Three Dimensional Wafer Level Chip Scale Packaging (3D-WLCSP), that leverages the existing infrastructures of high throughput wafer level packaging and low cost flip chip assembly process, is conducted in this research. Two levels of device packaging integration are involved in this novel 3D packaging architecture. The first-level integration is realized by the face-to-face bonding of a thin profile, fine-pitch, flip chip die to a wafer formatted Wafer Level CSP substrate. The second-level integration features the assembly of the first-level packaged component to an FR4 organic substrate (PCB). The 3D-WLCSP packaging technology developed in this research utilizes a 3D die to wafer integration methodology that provides a cost effective, rapid time to market 3D packaging solution. Research efforts were focused on the high-density flip chip wafer level assembly techniques for the packaging of 3D-WLCSP, as well as the challenges, innovations and solutions associated with this type of packaging technology. In this work, the flip chip pitch and bump size are varied as well as the key assembly materials (including fluxes and underfills) used to attach the flip chip to the WLCSP. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; impacts of reflow profile parameters and effects of reflow ambient gas environment toward silicon on silicon flip chip assembly yield, solder joint quality and reliability; wafer level flip chip assembly program setup and yield improvements; and the CSP solder joint voiding issues for the second-level assembly. Various aspects of the die-to-wafer assembly process are explored including scaling issues with high volume wafer level assembly, utilization of low cost underfill approaches such as no-flow underfills, and underfilling a solder balled WLCSP wafer with chip components in close proximity. Different reliability testing methods were utilized to evaluate the reliability performance of the packaged first-level and second-level assemblies. This research has demonstrated that the 3D-WLCSP can be processed with high yield and can successfully undertake harsh environments with long-term, high reliability performance. The 3D-WLCSP is a qualified packaging architecture for the Pb-free 3D die-to-wafer integration.