This Is AuburnElectronic Theses and Dissertations

Test time optimization in scan circuits




Shanmugasundaram, Priyadharshini

Type of Degree



Electrical Engineering


As circuit sizes increase with scale down in technology, the time required to test the circuits also increases. Expensive automatic test equipment (ATE) is used to test these circuits and the cost of testing becomes a significant fraction of the total cost of the chip. Testing cost of a chip is directly related to the time its testing takes. However, test time cannot be reduced by simply applying the tests at a faster speed because if the test clock frequency is increased, the power consumed during test increases. If this power were to exceed the power consumption the chip can withstand, the circuit might perform slower or might malfunction~\cite{v_droop}. This research aims at reducing the time required for test without increasing the power dissipated during test. Full scan design is a popular design for testability (DFT) method~\cite{dft} in which the flip-flops of the circuit are chained together to function as a shift register during test. Test vectors are scanned in and the responses are scanned out bit by bit. The power consumption during test can exceed the power consumption in the functional mode of operation~\cite{high_test_pow_2,high_test_pow} due to high activity required to achieve high test coverage for the circuit under test. Therefore, the scan-in and scan-out of vectors are normally carried out at frequencies much lower than functional frequencies. However, all vectors do not create the same amount of activity in the circuit. The vectors that cause low activity in the circuit can be scanned in at higher frequencies without exceeding the power limit. A scheme to reduce test application time by dynamically increasing the scan clock frequency is proposed. The test power is held below the allowed power limit by controlling the activity per unit time. The per cycle scan activity is monitored dynamically to speed up the scan clock for low activity cycles without exceeding the specified peak power budget. The implementation of the dynamic control of scan frequency in circuits tested by both built-in self-test (BIST) and ATE are discussed. In the newly proposed techniques, on-chip activity monitors are installed at the front end of every scan chain in the circuit. These activity monitors continuously keep track of the number of transitions in the circuit. The power dissipated in a circuit has a direct relationship with the activity per unit time in the circuit~\cite{alpha_f}. Thus, if the number of transitions in the scan chain falls below the peak value allowed, the frequency of scan-in of vectors can be increased without exceeding the power limit the circuit can withstand. A frequency divider circuit was implemented on the circuit. The fastest clock at which scan-in is to be performed is fed to the frequency divider. Based on the number of transitions in the scan chain, the frequency divider block modifies the frequency of clock supplied to the scan chain. Thus, the time required to scan in vectors is reduced by dynamic control of scan clock frequency without exceeding the power limit the circuit can withstand. In the case of circuits tested with ATE, a handshake protocol may control the rate of test data flow between the ATE and device under test (DUT)\nomenclature{DUT}{Device Under Test}. The use of ATE allows information about the activity factor of the vectors in the scan chain to be utilized during test. The activity factor of the test vectors can be used to determine the frequency at which scan-in should be carried out. This information is stored on the ATE and used for dynamic control of scan clock frequency. The dynamic clock control method was implemented on ISCAS89\nomenclature{ISCAS}{International Symposium on Circuits and Systems} benchmark circuits. The test-per-scan BIST model \cite{bist_model} and one scan chain per circuit were used for simulation purposes. Test time reductions of up to 19\% with a 2-3\% increase in area were achieved in large benchmark circuits. All circuits showed test time reduction without increase in test power. It was found that a test time reduction of 19\% can be achieved with fully specified test vectors on the s38584 circuit and that a test time reduction of 43\% is achievable when don't care bits are present in the test vectors. An accurate mathematical analysis on ITC02 benchmark circuits showed test time reductions of up to 50\% for test sets with low activity and up to 25\% for test sets with moderate activity. A reduction of up to 49.9\% was achieved in t512505 circuit when the peak activity factor of test vectors was lower than 1. Significant reduction in test time was achieved in t512505 circuit when information about scan chain activity was pre-simulated and the frequency of scan clock was stored on ATE. It was observed that the proposed method performed better on large circuits. It shows larger reduction in test time when the test vectors have low activity factors. Thus, this method would perform very well on circuits for which vectors are optimized to have minimal activity factors. With the emphasis on power prevalent today, it is common to see vector sets being optimized for power. This indirectly leads to low transition densities in vectors because of the direct relationship between activity factor and power. Hence, the dynamic control of clock frequency method is bound to produce good results on today`s industrial circuits.