Path Delay Tuning for Performance Gain in the face of Random Manufacturing Variations

Abstract

Moore's laws predictions of transistor densities doubling every two years in an integrated circuit has held true for the past fifty years, and is predicted to hold true in the coming few years. But as technologies shrink to smaller dimensions and scaling becomes more aggressive, a number of factors are beginning to hinder the urge towards miniaturization. Process variability, that introduces parametric variations in a device, is one such factor that is today seriously limiting clock rates in large synchronous designs. These variations are predicted to increase significantly with device scaling as silicon technology approaches the end of roadmap. Prior research work on process variability shows that factors contributing to process variations affect the threshold voltage (Vth) of transistors. Varying Vth corresponds to varying path delays in a circuit, a few of which are significant outliers, with path delays much larger than the nominal delays the circuits were designed to have. These variations make it hard to make any pre-fabrication predictions on the slowest paths in designs that would make room for a speeding methodology because of the random way in which they are distributed in a chip. With circuits today including several hundred million transistors, virtually every design will have a dozen of these outlier transistors that would limit the maximum clock frequency at which the chip can be correctly operated. This thesis studies a new design architecture that allows for tuning and speedup of exceptionally slow paths in a chip to recover the lost performance and significantly increase the average clock speed attainable by the manufactured parts.