Energy Efficiency and Process Variation Tolerance of 45 nm Bulk and High-k CMOS Devices

Abstract

With transistor sizes being reduced to sub 45nm ranges, we have seen an improvement in speed, better performance, and deeper integration of digital circuits. However, there has been a corresponding increase in power consumption, along with greater energy dissipation. The reason is because of increased leakage current in the channel. A proposed solution is a shift towards high-k materials and metal gate from poly-silicon gate of yesteryear. Reduced feature sizes also suffer from greater parametric process variations during lithography and cause identical circuits to behave differently.

With high-k technology overshadowing bulk technology ever since transistor sizes hit 45nm, a greater understanding of how the properties of high-k technology will affect digital devices especially their speed, power consumption, and energy dissipated upon voltage scaling is needed. Also, a better estimation of effects of parametric variations on circuits designed in high-k technology can provide valuable information which can be used to improve current designs.