Strategies for Efficient and Effective Scan Delay Testing

Abstract

Aggressive timing requirements in today’s high-speed designs have introduced the need to test for small delay defects and distributed timing faults caused by statistical process variations. Faster-than-rated clock delay tests aimed at targeting small delay defects can generate a large number of unknown X values because the test response for all paths longer than the (over clocked) test clock period must be marked X. Unknown output values prevent the use of efficient test compression techniques. We propose and evaluate a simple multiplexing scheme for output test data compression which avoids any compaction of the test response. In addition, high delay fault coverage is required to ensure that the design meets the desired performance specifications, and the architectural limitations of traditional scan structure restrict the two pattern delay tests that can be applied to a design, resulting in degraded delay test coverage. The use of enhanced scan flip-flops can alleviate this problem by supporting arbitrary delay test vector pairs, but at very high area overhead. We present a new, computationally efficient method for selecting the enhanced scan flip-flops which have most benefits of full enhanced scan at the cost of only 10-20% enhanced scan flip-flops. Thus the proposed techniques contribute to improving the efficiency and effectiveness of scan delay testing.