Enhancing Flash Lifetime in Secondary Storage

Abstract

This research addresses the limited usable life of NAND flash-based storage systems. Unlike a magnetic disk drive, a NAND flash suffers from limited number of write cycles ranging from 10-100K depending on the specific type of flash. As flash memory densities increase and cell sizes shrink, further decrease in write endurance is expected. Although substantial research has been conducted to solve or mitigate the problem by wear leveling, write endurance remains a concern for write intensive applications. We have proposed to use a DRAM cache to filter write traffic to flash memory. Intuition tells us that DRAM cache can filter writes to flash by coalescing and merging overwrites. However, the effectiveness of such a mechanism is not obvious considering that a large file system cache already exists which also merges overwrites. Since DRAM is volatile, to handle integrity of data upon power failure, we propose to use a supercapacitor backup which can provide short duration power during which the DRAM data can be retired to flash memory. The use of supercapacitor is superior to traditional use of battery-backed DRAMs as batteries, unlike super capacitors, suffer from limited number of charge/discharge cycles as well as slow charge times. We studied the effectiveness of DRAM cache in reducing write traffic to flash and the resulting response time and throughput changes. We investigated the use of a DRAM cache under two settings: a) when flash is used as a disk cache within a magnetic disk controller and b) when flash is used as a full secondary storage. Under the first setting, we used two levels of disk cache: DRAM disk cache and flash disk cache. Under the second setting, we used a single DRAM cache to filter the traffic to the full flash secondary storage. For both settings, we compared two policies to retire data from DRAM to flash memory: early vs. lazy retirement. In early retirement policy, flash is updated at the same time DRAM is updated. In lazy retirement policy, flash is updated only upon data eviction from DRAM cache. Conventionally, early update policy has been used to avoid data loss upon power failure. With early update, write traffic to flash is not reduced via DRAM cache. In contrast, lazy update policy substantially reduces write traffic thereby extending the flash lifetime. Our simulation results show that using a medium-sized DRAM cache, flash lifetime doubles with lazy update policy compared to early update policy. Moreover, miss ratio and average response time decrease as well. With little effort, our technique can be extended to improve the usable life of other emerging non volatile memory systems, such as PCM and MRAM.