|dc.description.abstract||As deep sub-micron technologies are widely adopted in modern VLSI design and fabrication process, the shrinking size and increasing complexity of digital circuits make it more difficult to maintain a high yield. Diagnosis is the procedure used when circuit verification fails. Determining the cause of the failure and finding the possible defect locations are included in diagnosis. In this thesis, a procedure of diagnosing multiple net-faults is proposed.
Many previous studies on fault diagnosis mainly focused on single failures. However, considering the increasing complexity of current devices, multiple fault models may better reflect the real failures. Therefore, this thesis aims at using multiple fault models for diagnosis, though only the single fault simulation information is used. We utilize test patterns that have high diagnostic coverage for single stuck-at and single transition faults. Thus, we can expect a better distinguishablility between faults and hopefully better diagnosis can be achieved.
We propose a candidate filtering system based on probabilistic counting criteria, which is different from previous methods that simply relied on strict matching criteria and simple matching count. The proposed candidate filtering system utilizes information on passing patterns as well as that on both erroneous and error-free primary outputs of failing patterns to construct a balanced ratio-count for each fault that could potentially exist in the faulty circuit. By using such ratio-count for each fault, we hope to have better chances of discovering those faults that have been reported detected only few times. In reality this would be the case with hard to detect faults. Fault candidates are then filtered by dropping those with counts lower than an empirically determined threshold.
After candidate filtering, we use a candidate ranking system to rank the remaining fault candidates. We define a structure called erroneous primary output tree (EPO-Tree), which for a failing pattern represents both the observed failing information from the circuit under diagnosis (CUD) and the simulation information of fault candidates. Our ranking procedure is performed within each EPO-Tree. A novel feature of this ranking system is that we do not rank the fault candidates only based on the overall matching performance, but we also consider their potential within each branch of the EPO-Tree. Any fault that has a chance to be the top candidate in any branch of certain EPO-Tree will be selected as the final candidates. By using this method, we can have a better chance to discover the fault candidates that may have a worse overall ranking from first stage but are unique enough in certain branch of EPO-Tree. What's more our candidate ranking system does not require the single-location-at-a-time (SLAT) ability of test pattern to activate single fault among multiple faults as previous works do.
After the fault ranking, we expand the collapsed fault candidates by uncollapsing faults. Each fault candidate in the final ranked list represents a net that it belongs to. According to the ranks of faults on a net we rank the net candidates. All nets derived from the final fault list are put into a net pool. The final net candidate list includes two parts: the first part includes the nets that have more than two members in the net pool, and the second part includes those nets that have only one member in the net pool. The further ranking of the net depends on the top ranked fault's rank.
We use a commercial fault simulation tool for experiments on ISCAS85 benchmark circuits. When simulated faulty responses of benchmark circuit c7552 with multiple faults on a single net were diagnosed, in 90\% cases a set of one to three nets could be found such that this set contained the actual faulty net. Similarly, when responses for two faulty nets were diagnosed, up to six nets were identified containing the two real ones in 90\% cases. We thus assessed the diagnosis algorithms to have 90\% diagnosability with a resolution of three.||en_US