|dc.description.abstract||In this work, we propose a technique to use dual supply voltages in digital designs in
order to get a reduction in energy consumption. Three new algorithms are proposed for nd-
ing and assigning low voltage in dual voltage designs. Given a circuit and a supply voltage,
the rst algorithm nds an optimal lower supply voltage and the other two algorithms assign
that lower voltage to individual gates. A linear time algorithm described in the literature is
used for computing slacks for all gates in a circuit for a given supply voltage.
For the computed gate slacks and the lower supply voltage, the gates in the circuit
are divided into three groups. No gate in the rst group can be assigned the lower supply.
All gates in the second group can be simultaneously set to lower supply while maintaining
positive slack for all gates. The gates in the third group are assigned low voltage in small
subgroups. The gate slacks are recalculated after each such voltage assignment. Thus, the
overall complexity of this reduced power dual voltage assignment procedure is O(n2). But
in practice, it is observed that the computation time is close to linear in the circuit size.
SPICE simulations of ISCAS'85 benchmark circuits using the PTM model for 90-nm bulk
CMOS technology results show up to 60% energy savings.||en_US