This Is AuburnElectronic Theses and Dissertations

Vernier Ring Time-to-Digital Converter Based Digital Phase Locked Loop




Yu, Jianjun

Type of Degree



Electrical Engineering


Digital phase-locked loops (DPLLs) recently are widely explored for wireless communication applications. Time-to-digital converter(TDC)-based DPLLs feature a high degree of integration, easy calibration and high programmability, and the DPLL can be easily scaled down to the deep-submicron CMOS process with less area and improved performance. Replacing the function of a phase detector and charge pump used in a conventional PLL, the TDC measures the phase error between the reference signal and the feedback signal in the time domain and directly outputs the phase errors in a digital format that can be processed by an on-chip digital loop filter. Due to the use of a programmable digital loop filter, the loop dynamics of a DPLL can be programmed on the fly and thus can achieve fast settling time and low phase noise simultaneously. The on-chip digital loop filter can provide accurate loop dynamics that are less sensitive to process, voltage and temperature (PVT) variations and more immune to the supply and substrate noise. In addition, the area of the DPLL can be reduced by eliminating large capacitors used in analog loop filters. TDC is a critical building block of the DPLL. Similar to other sampling circuits, a TDC inevitably generates quantization noise while digitizing the input phase error or time interval. This quantization noise associated with the finite TDC resolution limits the in-band noise of a TDC-based DPLL. On the other hand, it’s desired for a TDC to have a large detectable range in order to be able to respond to large phase error during the pull-in of a phase locking process, especially in the low output frequency DPLL. In this research, a novel 8-ps resolution Vernier ring TDC and a 16-ps resolution 3-D Vernier ring TDC were invented and designed to achieve both the fine resolution and large detectable range. The state-of-art TDC design was also used in the on-chip jitter measurement. The 3.6GHz digital phase locked loop based on the Vernier ring TDC was designed and analyzed. The detailed circuit design and performance analysis are extensively discussed in the dissertation. The simulation and measured results of these circuits are also presented to verify the proposed designs.