Architecture Analysis and Block Design in Modern Communication Radio Transceivers

Abstract

With the rapid growth of consumer electronics market and the increasing demand for low power, wide bandwidth communication devices, the RF transceiver on chip implemented utilizing modern CMOS or SiGe BiCMOS technology achieves wide applications. Therefore it has been attracting attention in academia. This dissertation will present the research on transceiver architecture, and the design implementations of independent building blocks. First the performance degradation of Multiple-Input-Multiple-Output (MIMO) communication systems is analyzed which is due to MIMO wireless transceiver radio frequency integrated circuits (RFIC) imperfections. The effects of signal coupling in RF front-end, frequency synthesizer phase noise and the gain imbalance between different radio paths are investigated. These issues are explored by analytical derivations and results are verified by Monte-Carlo simulations. The analytical model achieves good agreement with the simulation results. The conclusion can serve as a useful reference for MIMO RFIC designers. Then a comprehensive radar transceiver architecture with stretch processing is presented. The radar system on chip (RoC) is a promising topic. RoC with stretch processing was rarely implemented before. The dissertation demonstrates the detail of a practical transceiver. In additional, a power amplifier (PA) driver operating at 10GHz is designed and introduced as a critical block to the whole system. The PA driver delivers +5dBm power and 10dB power gain. A power-saving RF front-end is indispensible to the radio receiver. This dissertation presents a novel RF receiver front-end using only one shared tail current for low power application. The 5GHz receiver front-end RFIC includes a voltage controlled oscillator (VCO), a double balanced mixer and a low noise amplifier (LNA) in a cascoded topology. The receiver RFIC was implemented in a 0.5um SiGe BiCMOS technology. The VCO phase noise was measured around -105dBc/Hz at 1MHz frequency offset. Intermediate frequency (IF) output is centered at frequency of 600MHz using a low-IF architecture and the conversion gain is measured more than 15dB. The front-end core consumes 3.3mA current from a 3.3V power supply and occupies 1.4mm2 area. Harmonic rejection is an important characteristic for the systems in strong interference environment. Due to the time-variant property of mixers, the out-of-band interference will be folded back to in-band by the virtue of high order harmonics. This dissertation presents a novel mixer architecture suppressing 3rd and 5th order harmonics more than 30dB lower. Meanwhile it achieves higher dynamic range with affordable noise figure (NF). Finally a wideband digitally controlled oscillator (DCO) for all digital phase-locked loop (ADPLL) application is presented in this dissertation. The DCO has an 8th order resonator composed of coupled inductors and MOS varactors. By the inductor coupling, the tuning range contains four bands and is extended from 1.4GHz to 3.86GHz. The power consumption for the DCO core is 6.5mW with a 1.5V power supply. The measured phase noise at 1MHz frequency offset from 3GHz output is around −110dBc/Hz.