This Is AuburnElectronic Theses and Dissertations

Enhanced Polymer Passivation Layer for Wafer Level Chip Scale Package




Shu, Huihua

Type of Degree



Electrical Engineering


Wafer level chip scale package (WLCSP) have been used in many consumer products, and thus they are competitive in cost, size, yield, and technology. For advanced WLCSP, solder joint reliability is a major concern. Underfilling is a common solution to addressing WLCSP reliability concerns. Typical stress-relieving methods such as molding compounds and capillary underfills have proven successful in CSP protection, but their added cost to the assembly process is generally prohibited. Instead, successful low cost reliability solutions have generally been the adaptation of wafer level back-end packaging processes such as modification of the redistribution layer materials, solder selection, or metal pad thickness. However, the increased performance is limited. In this research, a new approach is presented to reexamine the final passivation layer as more than a dielectric, but also a partial underfill. The new material, branded as "SolderBrace" as an alternative to underfill, is a photo-imagable molding compound with a low CTE. This layer of SolderBrace coating adds a mechanical buffer to the front side of the WLCSP and delivers improved reliability with conventional tools, short process times and lower costs. SolderBrace coated WLCSPs and standard non-coated WLCSPs, were designed and fabricated with known standard fabrication procedures. The processing of the SolderBrace coatings was achieved by two methods. The first is similar to that of standard polyimide processing: spin coat,bake, photo-image, solvent develop, and ball drop. The second application process involves printing the material on the already-balled wafers followed by solder cleaning and cure. These SolderBrace coatings were low temperature cured and generated minimal wafer bow. The test WLCSPs were assembled to the circuit boards after the wafer singulation. The standard thermal cycling test was used for reliability testing. A finite element based approach was also used to gain a deeper understanding of the solder joint failure mechanism caused by the repeated thermal stress. According to the test results, the SolderBrace coated dies had much higher lifetime than the non-coated dies. SolderBrace technology may offer a unique method to package low cost high performance WLCSPs. The simulation results also give insight on the stress generation and can provide guidance to appropriate design adjustment.