Controlled Transition Density Based Power Constrained Scan-BIST with Reduced Test Time
Type of Degreethesis
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Controlling power dissipation in large circuits during test sessions is one of the major concerns in VLSI testing. The reason behind the high power dissipation during test is because unlike normal mode operation of the system correlation between consecutive test patterns does not exist in test mode. To increase the correlation between consecutive vectors during testing, several techniques have been proposed for creating low transition density in the pattern sets and thus control the power dissipation. However, this in turn increases the test application time as the test has to run for longer test sessions to reach sufficient fault coverage. Increase in test time is also undesirable. This research aims to provide a common way to deal with both the problems by optimizing test lengths for power constraint scan BIST circuits and reduce required test application time. It has been shown that a specific weight or transition density results in producing effective test with shortest test length for a given fault coverage. Thus the test length is optimized to reduce test application time. .Test time is further reduced by adapting the scan clock dynamically based on the transition density of the pattern set staying within power budget. A new pattern generator has been proposed to produce the test patterns of desired properties. Finally we propose a greedy algorithm for mixing various transition densities to reduce the test application time further without sacrificing the fault coverage. Time saving up to 43% has been seen in this proposed method in ISCAS89 circuits.