This Is AuburnElectronic Theses and Dissertations

Diagnostic Test Pattern Generation and Fault Simulation for Stuck-at and Transition Faults




Zhang, Yu

Type of Degree



Electrical Engineering


In VLSI testing we need Automatic Test Pattern Generator (ATPG) to get input test vectors for Circuit Under Test (CUT). Generated test sets are usually compacted to save test time which is not good for failure diagnosis. Physical defects in circuits are modeled by different Fault Models to facilitate test generation. Stuck-at and transition fault models are widely used because of their practicality. In this work a Diagnostic Automatic Test Pattern Generation (DATPG) system is constructed by adding new algorithmic capabilities to conventional ATPG and fault simulation programs. The DATPG aims to generate tests to distinguish stuck-at fault pairs, i.e., two faults must have different output responses. This will help diagnosis to pin point the failure by narrowing down the fault candidates which may be the reason for this particular failure. Given a fault pair, by modifying circuit netlist a new single fault is modeled. Then we use a conventional ATPG to target that fault. If a test is generated, it is guaranteed to distinguish the fault pair in the original circuit. A fast diagnostic fault simulation algorithm is implemented to find undistinguished fault pairs from a fault list for a given test vector set. To determine the quality of the test vector set generated by DATPG, we use a proposed Diagnostic Coverage (DC) metric, which is similar to Fault Coverage (FC). The diagnostic ATPG system starts by first generating conventional fault coverage vectors. Those vectors are then simulated to determine the DC, followed by repeated applications of diagnostic test generation and simulation. We observe improved DC in all ISCAS'85 benchmark circuits. To distinguish between a pair of transition faults, we need to find a test vector pair (LOC or LOS type) that produces different output responses for the two faults. By adding a few logic gates and one modeling flip-flop to the circuit under test (CUT), we extend the ability of the previous DATPG system to target transition faults. Given a transition fault pair, this ATPG model either finds a distinguishing test or proves the faults to be equivalent. The number of fault pairs that needs to be targeted by the ATPG is greatly reduced after diagnostic fault simulation. Experimental results show improved DC and shorter CPU time compared to a previous work. Although not demonstrated in this thesis, the proposed DATPG system can be used for multiple or mixed fault models as long as there is an ATPG and fault simulator for targeted faults. This work thus allows any conventional fault detection ATPG tools to be enhanced for diagnosis purposes without significantly increasing their complexity.