Modeling and Scaling Limitations of SiGe HBT Low-Frequency Noise and Oscillator Phase Noise

Abstract

This dissertation presents modeling of SiGe HBT low-frequency noise and oscillator phase noise, and examines their limitations posed by technology scaling. A new method of extracting low-frequency noise, inverse circuit simulation based low-frequency noise extraction, is proposed to enable noise measurement of devices operating under high current density and voltage, which are typical for modern SiGe HBTs. Traps physically located at collector-base junction are found to not only generate recombination current, but also contribute significant 1/f noise when high-injection occurs. The 1/f noises that originated from the emitter-base and collector-base junctions are separated, and shown to be two distinct processes. The noise dependence on total base current, however, is still approximately the same before and after high-injection occurs. This is good news for compact modeling, since no extra effort is needed to model 1/f noise generated by collector-base junction traps as long as the recombination current in the collector-base junction is correctly modeled. The 1/f noise at a given base current increases with technology scaling from 50 to 120 GHz, but decreases with scaling from 50 to 210 GHz. However, because of the increased current gain, scaling to 120 GHz does not necessarily increase the 1/f noise for a given collector current, which is more relevant for circuit operation.

Using frequency sensitivity method in ADS and impulse sensitivity function method, we examine the upconversion of individual transistor noise source to phase noise as a function transistor sizing, biasing, technology scaling and oscillation frequency. In ADS, 1/f noise in an oscillating transistor depends on the dc component of the oscillating noise generating current only. While in impulse sensitivity method, we consider 1/f noise as modulated stationary noise as supported by the experimental data. Comparison is made with the results in ADS. Phase noise from the modulated stationary model is usually more than 10 dB higher. Optimal phase noise is found in a medium sized transistor with a maximum oscillating collector current below the severe high-injection region. With technology scaling, the phase noise due to base current shot noise is reduced as a result of higher speed and the ability to operate at higher current density without inducing severe high-injection and quasi-saturation. The fundamental limit is set by the collector current shot noise. Technology scaling leads to an improvement of the far-off phase noise which is dominated by white noise contributions. The 1/f noise increase in the 120 GHz HBT is found to degrade only the close-in phase noise. All of the technologies investigated are excellent choices for low phase noise oscillators provided that transistor size and bias are optimized. With increasing oscillation frequency, 1/f noise becomes less important, and the dominant phase noise source is the collector current shot noise.

The results show that corner offset frequency defined by the intersect of the 1/f^3 and 1/f^2 phase noises has little to do with the traditional 1/f noise corner frequency. 1/f noise corner frequency should not be used alone to evaluate the capability of a certain technology in low phase noise oscillator application. A methodology to identify the maximum tolerable 1/f noise K factor for frequency synthesizers, the threshold K, is established and demonstrated for the HBTs used. Using the model that relates 1/f noise to the dc component of the noise generating current only, the actual K is lower than the respective threshold K. While the actual K is higher than the threshold K if the modulated stationary noise model is applied to 1/f noise.