Built-In Self-Test of Logic Resources in Field Programmable Gate Arrays Using Partial Reconfiguration

Abstract

Field Programmable Gate Arrays (FPGAs) are programmable logic devices that can be used to implement virtually any digital circuit design. Built-In Self-Test (BIST) is a testing approach that enables the device to test itself without any external test equipment. The re-programmability feature of the FPGAs makes BIST a very attractive approach for testing FPGAs because it eliminates any area or performance degradation associated with BIST.

Traditional BIST for FPGAs suffers from long test times and large memory storage requirements due to the slow configuration download speeds and the large number of test configurations required to test the FPGAs. The work presented in this thesis implements testing of logic resources of Xilinx Virtex/Spartan-II and Virtex-4 FPGAs with focus on reduction of test time and memory storage requirements using techniques like dynamic partial reconfiguration and partial configuration memory readback. The total number of configurations required to completely test the logic resources are 28 for Virtex/Spartan-II FPGAs and 24 for Virtex-4 FPGAs. A speed-up of 5.1 times and 12.9 times in test time was achieved for Logic BIST for Virtex/Spartan-II and Virtex-4 FPGAs respectively, using dynamic partial reconfiguration and partial configuration memory readback. A reduction in configuration memory storage requirements was also achieved using partial reconfiguration; this reduction was 3.2 times and 5.3 times for Virtex/Spartan-II and Virtex-4 FPGAs respectively.