This Is AuburnElectronic Theses and Dissertations

Modeling and Reliability Characterization of Area-Array Electronics Subjected to High-G Mechanical Shock Up To 50,000G and Finite Element Analysis of Package on Package (PoP) Components for Warpage During Reflow




Patel, Kewal

Type of Degree



Mechanical Engineering


Electronics in aerospace applications may be subjected to very high g-loads during normal operation. A novel micro-coil array interconnect has been studied for increased reliability during extended duration aerospace missions in presence of high-g loads. Ceramic area-array components have been populated with micro-coil interconnects. The micro-coil spring (MCS) is fabricated using a beryllium copper wire post plated with 100 µin of Sn63Pb37, 50 mils in height with a diameter of 20 mils. Board assemblies have been subjected to high g-loads in the 0°, horizontal orientation. The board assemblies are daisy chained. Damage initiation and progression in the interconnects has been measured using in-situ monitoring with high speed data acquisition systems. Transient deformation of the board assemblies has been measured using high-speed cameras with digital image correlation. Multiple board assemblies have been subjected to shock tests till failure. Peak shock pulse magnitudes range from 1,500g typical of JEDEC standard, to very high g-levels of 50,000g. Board assemblies have been tested at different orientations. The MCS interconnects are daisy chained and failures are measured using electrical continuity. A finite element model using explicit global to local models has been used to study interconnect reliability under shock loads. Models have been correlated with experimental data. The reliability performance of micro-coil interconnects has been compared to column interconnects. Results have shown that the micro-coil spring array has a higher reliability than the ceramic column grid array (CCGA). Failure modes have been determined for both interconnect types. Additionally, this study investigates the area of package warpage. Package-on-Package (PoP) assemblies may experience warpage during package fabrication and later during surface mount assembly. Excessive warpage may result in loss-of-coplanarity, open connections, misshaped joints, and reduction in package board-level reliability (BLR) under environmental stresses of thermal cycling, shock and vibration. Previous researchers have shown that warpage may be influenced by a number of design and process factors including underfill properties, mold properties, package geometry, package architecture, board configuration, underfill and mold dispense and cure parameters, and package location in the molding panel. In this study, warpage has been measured using shadow moiré interferometery and an optical full-field measurement technique called DIC or digital image correlation. Finite element models have been created and correlated with experimental data to create a baseline model. Investigation on the effects of materials selection, package dimensions, and material properties has been conducted by altering the baseline finite element model. The material properties (CTE1, CTE2, E1 and E2) have all been varied for each material found in the PoP package including the epoxy molding compound, the substrate core, and the die. The effects of die thickness and geometry have also been investigated. A sensitivity analysis has been performed to determine the relative influences each parameter has on package warpage.