Digital Phase Accumulation for Direct Digital Frequency Synthesis

Abstract

This work explores direct digital frequency synthesis (DDFS) theory and design and its application in radar systems. Though there is nothing particularly novel about DDFS in general, recent designs have been revolutionized with the advancements in CMOS processes and SiGe BiCMOS integration from 2000 to the current day. Many of the performance limitations highlighted in early literature, such as the area and power of the sinusoidal read-only memory (ROM), no longer apply to designs in modern integrated circuit (IC) processes. The digitally-controlled digital oscillator (DCDO) of the DDFS can now produce signals with spectral purity far beyond the capabilities of the digital to analog converter (DAC). CMOS miniaturization allows for high dynamic range sinusoids to be generated with CORDICs instead of lossy compressed sine and cosine ROMs. Parallelization in the accumulator and modulation paths eliminate the need for power hungry, current mode logic (CML) pipeline accumulators. Noise shaping is better understood than at any point prior to this moment, which allows us to mitigate quantization noise that arises from phase or amplitude truncation.

However, alarmingly few DDFS designs published in the past five years have taken note of the radical shift in the design landscape. Of equal importance are the new challenges that have arisen in small feature size geometries. In a way, this document is an attempt to consolidate the state of the art in DDFS design and propose improvements from the study. To this end, the dissertation is organized into two distinct sections, the DCDO and the DAC. Digital phase accumulation and sinusoid generation are approached from number theory and real analysis respectively. An exact computation of the spurs generated through phase truncation is developed that results in closed form expressions for the DCDO spectrum. Current switches and architectures for improved DAC performance is presented qualitatively.