A High-Voltage On-Chip Power Distribution Network
Type of Degreethesis
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With high performance mobile computing devices like tablets and smart-phones virtually swiping the VLSI chip market, the industry is facing the perpetual challenge of optimizing between power and performance, more than ever before. Although, existing Power Distribution Network (PDN) designs take into consideration issues like IR drop and crosstalk noise, they practically ignore the actual power loss in the network. In this work we try to bridge that gap, and propose a scheme for delivering power to different parts of a large integrated circuit, such as modules on a System on Chip(SoC), at a higher than the regular voltage. This increase in voltage lowers the current on the grid, and thereby reduces the I^2R loss in the on-chip power distribution network. The idea, though novel for VLSI devices, is inspired from the distribution system of commercial long distance power supply networks. We propose to use on-chip DC-DC converters to downscale voltage close to the delivery points, much like what is done in commercial power networks using transformers. This scheme can increase the efficiency of power delivery significantly over the current designs. Theoretical estimates, confirmed through SPICE simulations, show that when distributed at 3V(a voltage close to the nominal output of a Li-ion battery), and then down-converted to VDD of 1V, instead of distributing at 1V, the efficiency of the circuit can go up from a mere 60% to more than 90%.